dpt_pci.c revision 65151
1/*- 2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net> 3 * All rights reserved. 4 * 5 * Copyright (c) 1997 Simon Shapiro 6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/dev/dpt/dpt_pci.c 65120 2000-08-26 22:19:53Z peter $ 30 */ 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/bus.h> 37 38#include <machine/bus_memio.h> 39#include <machine/bus_pio.h> 40#include <machine/bus.h> 41#include <machine/resource.h> 42#include <sys/rman.h> 43 44#include <pci/pcireg.h> 45#include <pci/pcivar.h> 46 47#include <cam/scsi/scsi_all.h> 48 49#include <dev/dpt/dpt.h> 50 51#define DPT_VENDOR_ID 0x1044 52#define DPT_DEVICE_ID 0xa400 53 54#define DPT_PCI_IOADDR PCIR_MAPS /* I/O Address */ 55#define DPT_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 56 57#define ISA_PRIMARY_WD_ADDRESS 0x1f8 58 59static int dpt_pci_probe (device_t); 60static int dpt_pci_attach (device_t); 61 62static int 63dpt_pci_probe (device_t dev) 64{ 65 if ((pci_get_vendor(dev) == DPT_VENDOR_ID) && 66 (pci_get_device(dev) == DPT_DEVICE_ID)) { 67 device_set_desc(dev, "DPT Caching SCSI RAID Controller"); 68 return (0); 69 } 70 return (ENXIO); 71} 72 73static int 74dpt_pci_attach (device_t dev) 75{ 76 dpt_softc_t * dpt; 77 struct resource *io = 0; 78 struct resource *irq = 0; 79 int s; 80 int rid; 81 void * ih; 82 int error = 0; 83 84 int iotype = 0; 85 u_int32_t command; 86 87 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 88 89#ifdef DPT_ALLOW_MMIO 90 if ((command & PCIM_CMD_MEMEN) != 0) { 91 rid = DPT_PCI_MEMADDR; 92 iotype = SYS_RES_MEMORY; 93 io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE); 94 } 95#endif 96 if (io == NULL && (command & PCIM_CMD_PORTEN) != 0) { 97 rid = DPT_PCI_IOADDR; 98 iotype = SYS_RES_IOPORT; 99 io = bus_alloc_resource(dev, iotype, &rid, 0, ~0, 1, RF_ACTIVE); 100 } 101 102 if (io == NULL) { 103 device_printf(dev, "can't allocate register resources\n"); 104 error = ENOMEM; 105 goto bad; 106 } 107 108 rid = 0; 109 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 110 RF_ACTIVE | RF_SHAREABLE); 111 if (!irq) { 112 device_printf(dev, "No irq?!\n"); 113 error = ENOMEM; 114 goto bad; 115 } 116 117 /* Ensure busmastering is enabled */ 118 command |= PCIM_CMD_BUSMASTEREN; 119 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 120 121 if (rman_get_start(io) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) { 122#ifdef DPT_DEBUG_WARN 123 device_printf(dev, "Mapped as an IDE controller. " 124 "Disabling SCSI setup\n"); 125#endif 126 error = ENXIO; 127 goto bad; 128 } 129 130 /* Device registers are offset 0x10 into the register window. FEH */ 131 dpt = dpt_alloc(dev, rman_get_bustag(io), rman_get_bushandle(io) + 0x10); 132 if (dpt == NULL) { 133 error = ENXIO; 134 goto bad; 135 } 136 137 /* Allocate a dmatag representing the capabilities of this attachment */ 138 /* XXX Should be a child of the PCI bus dma tag */ 139 if (bus_dma_tag_create( /* parent */ NULL, 140 /* alignemnt */ 1, 141 /* boundary */ 0, 142 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 143 /* highaddr */ BUS_SPACE_MAXADDR, 144 /* filter */ NULL, 145 /* filterarg */ NULL, 146 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 147 /* nsegments */ BUS_SPACE_UNRESTRICTED, 148 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 149 /* flags */ 0, 150 &dpt->parent_dmat) != 0) { 151 dpt_free(dpt); 152 error = ENXIO; 153 goto bad; 154 } 155 156 s = splcam(); 157 158 if (dpt_init(dpt) != 0) { 159 dpt_free(dpt); 160 error = ENXIO; 161 goto bad; 162 } 163 164 /* Register with the XPT */ 165 dpt_attach(dpt); 166 167 splx(s); 168 169 if (bus_setup_intr(dev, irq, INTR_TYPE_CAM, dpt_intr, dpt, &ih)) { 170 device_printf(dev, "Unable to register interrupt handler\n"); 171 error = ENXIO; 172 goto bad; 173 } 174 175 return (error); 176 177bad: 178 if (io) 179 bus_release_resource(dev, iotype, 0, io); 180 if (irq) 181 bus_release_resource(dev, SYS_RES_IRQ, 0, irq); 182 183 return (error); 184} 185 186static device_method_t dpt_pci_methods[] = { 187 /* Device interface */ 188 DEVMETHOD(device_probe, dpt_pci_probe), 189 DEVMETHOD(device_attach, dpt_pci_attach), 190 191 { 0, 0 } 192}; 193 194static driver_t dpt_pci_driver = { 195 "dpt", 196 dpt_pci_methods, 197 sizeof(dpt_softc_t), 198}; 199 200static devclass_t dpt_devclass; 201 202DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0); 203