dpt_pci.c revision 50477
1/* 2 * Copyright (c) 1997 by Simon Shapiro 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31/* 32 * dptpci.c: PCI Bus Attachment for DPT SCSI HBAs 33 */ 34 35#ident "$FreeBSD: head/sys/dev/dpt/dpt_pci.c 50477 1999-08-28 01:08:13Z peter $" 36 37#include "opt_dpt.h" 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/buf.h> 43#include <sys/kernel.h> 44 45#include <pci/pcireg.h> 46#include <pci/pcivar.h> 47 48#include <machine/bus_memio.h> 49#include <machine/bus_pio.h> 50#include <machine/bus.h> 51 52#include <cam/scsi/scsi_all.h> 53 54#include <dev/dpt/dpt.h> 55#include <pci/dpt_pci.h> 56 57#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */ 58#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */ 59 60#define ISA_PRIMARY_WD_ADDRESS 0x1f8 61 62/* Global variables */ 63 64/* Function Prototypes */ 65 66static const char *dpt_pci_probe(pcici_t tag, pcidi_t type); 67static void dpt_pci_attach(pcici_t config_id, int unit); 68 69extern struct cdevsw dpt_cdevsw; 70 71static struct pci_device dpt_pci_driver = 72{ 73 "dpt", 74 dpt_pci_probe, 75 dpt_pci_attach, 76 &dpt_unit, 77 NULL 78}; 79 80COMPAT_PCI_DRIVER(dpt_pci, dpt_pci_driver); 81 82/* 83 * Probe the PCI device. 84 * Some of this work will have to be duplicated in _attach 85 * because we do not know for sure how the two relate. 86 */ 87 88static const char * 89dpt_pci_probe(pcici_t tag, pcidi_t type) 90{ 91 u_int32_t class; 92 93#ifndef PCI_COMMAND_MASTER_ENABLE 94#define PCI_COMMAND_MASTER_ENABLE 0x00000004 95#endif 96 97#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI 98#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000 99#endif 100 101 class = pci_conf_read(tag, PCI_CLASS_REG); 102 if (((type & 0xffff0000) >> 16) == DPT_DEVICE_ID 103 && (class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE 104 && (class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI) 105 return ("DPT Caching SCSI RAID Controller"); 106 return (NULL); 107} 108 109static void 110dpt_pci_attach(pcici_t config_id, int unit) 111{ 112 dpt_softc_t *dpt; 113 vm_offset_t vaddr; 114#ifdef DPT_ALLOW_MEMIO 115 vm_offset_t paddr; 116#endif 117 u_int16_t io_base; 118 bus_space_tag_t tag; 119 bus_space_handle_t bsh; 120 u_int32_t command; 121 int s; 122 123 vaddr = NULL; 124 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 125#ifdef DPT_ALLOW_MEMIO 126 if ((command & PCI_COMMAND_MEM_ENABLE) == 0 127 || (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0) 128#endif 129 if ((command & PCI_COMMAND_IO_ENABLE) == 0 130 || (pci_map_port(config_id, PCI_BASEADR0, &io_base)) == 0) 131 return; 132 133 /* 134 * If the DPT is mapped as an IDE controller, 135 * let it be IDE controller 136 */ 137 if (io_base == ISA_PRIMARY_WD_ADDRESS - 0x10) { 138#ifdef DPT_DEBUG_WARN 139 printf("dpt%d: Mapped as an IDE controller. " 140 "Disabling SCSI setup\n", unit); 141#endif 142 return; 143 } 144 145 /* XXX Should be passed in by parent bus */ 146 /* XXX Why isn't the 0x10 offset incorporated into the reg defs? */ 147 if (vaddr != 0) { 148 tag = I386_BUS_SPACE_MEM; 149 bsh = vaddr + 0x10; 150 } else { 151 tag = I386_BUS_SPACE_IO; 152 bsh = io_base + 0x10; 153 } 154 155 if ((dpt = dpt_alloc(unit, tag, bsh)) == NULL) 156 return; /* XXX PCI code should take return status */ 157 158 /* Allocate a dmatag representing the capabilities of this attachment */ 159 /* XXX Should be a child of the PCI bus dma tag */ 160 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 161 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 162 /*highaddr*/BUS_SPACE_MAXADDR, 163 /*filter*/NULL, /*filterarg*/NULL, 164 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 165 /*nsegments*/BUS_SPACE_UNRESTRICTED, 166 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 167 /*flags*/0, &dpt->parent_dmat) != 0) { 168 dpt_free(dpt); 169 return; 170 } 171 172 if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) { 173 dpt_free(dpt); 174 return; 175 } 176 177 s = splcam(); 178 if (dpt_init(dpt) != 0) { 179 dpt_free(dpt); 180 return; 181 } 182 183 /* Register with the XPT */ 184 dpt_attach(dpt); 185 splx(s); 186} 187