dpt_pci.c revision 41591
1/* 2 * Copyright (c) 1997 by Simon Shapiro 3 * All Rights Reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31/* 32 * dptpci.c: PCI Bus Attachment for DPT SCSI HBAs 33 */ 34 35#ident "$Id: dpt_pci.c,v 1.9 1998/10/07 03:40:51 gibbs Exp $" 36 37#include "opt_devfs.h" 38#include "opt_dpt.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> 43#include <sys/buf.h> 44#include <sys/kernel.h> 45 46#include <pci/pcireg.h> 47#include <pci/pcivar.h> 48 49#include <machine/bus_memio.h> 50#include <machine/bus_pio.h> 51#include <machine/bus.h> 52 53#include <cam/scsi/scsi_all.h> 54 55#include <dev/dpt/dpt.h> 56#include <pci/dpt_pci.h> 57 58#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */ 59#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */ 60 61#define ISA_PRIMARY_WD_ADDRESS 0x1f8 62 63/* Global variables */ 64 65/* Function Prototypes */ 66 67static char *dpt_pci_probe(pcici_t tag, pcidi_t type); 68static void dpt_pci_attach(pcici_t config_id, int unit); 69 70extern struct cdevsw dpt_cdevsw; 71 72static struct pci_device dpt_pci_driver = 73{ 74 "dpt", 75 dpt_pci_probe, 76 dpt_pci_attach, 77 &dpt_unit, 78 NULL 79}; 80 81DATA_SET(pcidevice_set, dpt_pci_driver); 82 83/* 84 * Probe the PCI device. 85 * Some of this work will have to be duplicated in _attach 86 * because we do not know for sure how the two relate. 87 */ 88 89static char * 90dpt_pci_probe(pcici_t tag, pcidi_t type) 91{ 92 u_int32_t class; 93 94#ifndef PCI_COMMAND_MASTER_ENABLE 95#define PCI_COMMAND_MASTER_ENABLE 0x00000004 96#endif 97 98#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI 99#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000 100#endif 101 102 class = pci_conf_read(tag, PCI_CLASS_REG); 103 if (((type & 0xffff0000) >> 16) == DPT_DEVICE_ID 104 && (class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE 105 && (class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI) 106 return ("DPT Caching SCSI RAID Controller"); 107 return (NULL); 108} 109 110static void 111dpt_pci_attach(pcici_t config_id, int unit) 112{ 113 dpt_softc_t *dpt; 114 vm_offset_t vaddr; 115#ifdef DPT_ALLOW_MEMIO 116 vm_offset_t paddr; 117#endif 118 u_int16_t io_base; 119 bus_space_tag_t tag; 120 bus_space_handle_t bsh; 121 u_int32_t command; 122 int s; 123 124 vaddr = NULL; 125 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 126#ifdef DPT_ALLOW_MEMIO 127 if ((command & PCI_COMMAND_MEM_ENABLE) == 0 128 || (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0) 129#endif 130 if ((command & PCI_COMMAND_IO_ENABLE) == 0 131 || (pci_map_port(config_id, PCI_BASEADR0, &io_base)) == 0) 132 return; 133 134 /* 135 * If the DPT is mapped as an IDE controller, 136 * let it be IDE controller 137 */ 138 if (io_base == ISA_PRIMARY_WD_ADDRESS - 0x10) { 139#ifdef DPT_DEBUG_WARN 140 printf("dpt%d: Mapped as an IDE controller. " 141 "Disabling SCSI setup\n", unit); 142#endif 143 return; 144 } 145 146 /* XXX Should be passed in by parent bus */ 147 /* XXX Why isn't the 0x10 offset incorporated into the reg defs? */ 148 if (vaddr != 0) { 149 tag = I386_BUS_SPACE_MEM; 150 bsh = vaddr + 0x10; 151 } else { 152 tag = I386_BUS_SPACE_IO; 153 bsh = io_base + 0x10; 154 } 155 156 if ((dpt = dpt_alloc(unit, tag, bsh)) == NULL) 157 return; /* XXX PCI code should take return status */ 158 159 /* Allocate a dmatag representing the capabilities of this attachment */ 160 /* XXX Should be a child of the PCI bus dma tag */ 161 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/0, /*boundary*/0, 162 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 163 /*highaddr*/BUS_SPACE_MAXADDR, 164 /*filter*/NULL, /*filterarg*/NULL, 165 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 166 /*nsegments*/BUS_SPACE_UNRESTRICTED, 167 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 168 /*flags*/0, &dpt->parent_dmat) != 0) { 169 dpt_free(dpt); 170 return; 171 } 172 173 if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) { 174 dpt_free(dpt); 175 return; 176 } 177 178 s = splcam(); 179 if (dpt_init(dpt) != 0) { 180 dpt_free(dpt); 181 return; 182 } 183 184 /* Register with the XPT */ 185 dpt_attach(dpt); 186 splx(s); 187} 188