dpt_pci.c revision 39234 
1/*
2 *       Copyright (c) 1997 by Simon Shapiro
3 *       All Rights Reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions, and the following disclaimer,
10 *    without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 *    derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31/*
32 *  dptpci.c:  PCI Bus Attachment for DPT SCSI HBAs
33 */
34
35#ident "$Id: dpt_pci.c,v 1.7 1998/08/05 00:54:37 eivind Exp $"
36
37#include "opt_devfs.h"
38#include "opt_dpt.h"
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/malloc.h>
43#include <sys/buf.h>
44#include <sys/kernel.h>
45
46#include <pci/pcireg.h>
47#include <pci/pcivar.h>
48
49#include <machine/bus_memio.h>
50#include <machine/bus_pio.h>
51#include <machine/bus.h>
52
53#include <cam/scsi/scsi_all.h>
54
55#include <dev/dpt/dpt.h>
56#include <pci/dpt_pci.h>
57
58#define PCI_BASEADR0  PCI_MAP_REG_START      /* I/O Address */
59#define PCI_BASEADR1  PCI_MAP_REG_START + 4  /* Mem I/O Address */
60
61#define ISA_PRIMARY_WD_ADDRESS    0x1f8
62
63/* Global variables */
64
65/* Function Prototypes */
66
67static char    *dpt_pci_probe(pcici_t tag, pcidi_t type);
68static void     dpt_pci_attach(pcici_t config_id, int unit);
69
70extern struct cdevsw dpt_cdevsw;
71
72static  struct pci_device dpt_pci_driver =
73{
74	"dpt",
75	dpt_pci_probe,
76	dpt_pci_attach,
77	&dpt_unit,
78	NULL
79};
80
81DATA_SET(pcidevice_set, dpt_pci_driver);
82
83/*
84 * Probe the PCI device.
85 * Some of this work will have to be duplicated in _attach
86 * because we do not know for sure how the two relate.
87 */
88
89static char *
90dpt_pci_probe(pcici_t tag, pcidi_t type)
91{
92	u_int32_t  class;
93
94#ifndef PCI_COMMAND_MASTER_ENABLE
95#define PCI_COMMAND_MASTER_ENABLE 0x00000004
96#endif
97
98#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI
99#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
100#endif
101
102	class = pci_conf_read(tag, PCI_CLASS_REG);
103	if (((type & 0xffff0000) >> 16) == DPT_DEVICE_ID
104	 && (class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE
105	 && (class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI)
106		return ("DPT Caching SCSI RAID Controller");
107	return (NULL);
108}
109
110static void
111dpt_pci_attach(pcici_t config_id, int unit)
112{
113	dpt_softc_t	   *dpt;
114	vm_offset_t	    vaddr;
115	vm_offset_t	    paddr;
116	u_int16_t	    io_base;
117	bus_space_tag_t     tag;
118	bus_space_handle_t  bsh;
119	u_int32_t	    command;
120	u_int32_t	    data;
121	int		    result;
122	int		    ndx;
123	int		    s;
124
125	vaddr = NULL;
126	command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
127#ifdef DPT_ALLOW_MEMIO
128	if ((command & PCI_COMMAND_MEM_ENABLE) == 0
129	 || (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0) {
130#endif
131		if ((command & PCI_COMMAND_IO_ENABLE) == 0
132		 || (pci_map_port(config_id, PCI_BASEADR0, &io_base)) == 0)
133			return;
134
135	/*
136	 * If the DPT is mapped as an IDE controller,
137	 * let it be IDE controller
138	 */
139	if (io_base == ISA_PRIMARY_WD_ADDRESS - 0x10) {
140#ifdef DPT_DEBUG_WARN
141		printf("dpt%d: Mapped as an IDE controller.  "
142		       "Disabling SCSI setup\n", unit);
143#endif
144		return;
145	}
146
147	/* XXX Should be passed in by parent bus */
148	/* XXX Why isn't the 0x10 offset incorporated into the reg defs? */
149	if (vaddr != 0) {
150		tag = I386_BUS_SPACE_MEM;
151		bsh = vaddr + 0x10;
152	} else {
153		tag = I386_BUS_SPACE_IO;
154		bsh = io_base + 0x10;
155	}
156
157	if ((dpt = dpt_alloc(unit, tag, bsh)) == NULL)
158		return;  /* XXX PCI code should take return status */
159
160	/* Allocate a dmatag representing the capabilities of this attachment */
161	/* XXX Should be a child of the PCI bus dma tag */
162	if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/0, /*boundary*/0,
163			       /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
164			       /*highaddr*/BUS_SPACE_MAXADDR,
165			       /*filter*/NULL, /*filterarg*/NULL,
166			       /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
167			       /*nsegments*/BUS_SPACE_UNRESTRICTED,
168			       /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
169			       /*flags*/0, &dpt->parent_dmat) != 0) {
170		dpt_free(dpt);
171		return;
172	}
173
174	if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) {
175		dpt_free(dpt);
176		return;
177	}
178
179	s = splcam();
180	if (dpt_init(dpt) != 0) {
181		dpt_free(dpt);
182		return;
183	}
184
185	/* Register with the XPT */
186	dpt_attach(dpt);
187	splx(s);
188}
189