dpt_pci.c revision 232854 
1/*-
2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Copyright (c) 1997 Simon Shapiro
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/dpt/dpt_pci.c 232854 2012-03-12 08:03:51Z scottl $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/lock.h>
38#include <sys/mutex.h>
39#include <sys/bus.h>
40
41#include <machine/bus.h>
42#include <machine/resource.h>
43#include <sys/rman.h>
44
45#include <dev/pci/pcireg.h>
46#include <dev/pci/pcivar.h>
47
48#include <cam/scsi/scsi_all.h>
49
50#include <dev/dpt/dpt.h>
51
52#define	DPT_VENDOR_ID		0x1044
53#define	DPT_DEVICE_ID		0xa400
54
55#define	DPT_PCI_IOADDR		PCIR_BAR(0)		/* I/O Address */
56#define	DPT_PCI_MEMADDR		PCIR_BAR(1)		/* Mem I/O Address */
57
58#define	ISA_PRIMARY_WD_ADDRESS	0x1f8
59
60static int	dpt_pci_probe	(device_t);
61static int	dpt_pci_attach	(device_t);
62
63static int
64dpt_pci_probe (device_t dev)
65{
66	if ((pci_get_vendor(dev) == DPT_VENDOR_ID) &&
67	    (pci_get_device(dev) == DPT_DEVICE_ID)) {
68		device_set_desc(dev, "DPT Caching SCSI RAID Controller");
69		return (BUS_PROBE_DEFAULT);
70	}
71	return (ENXIO);
72}
73
74static int
75dpt_pci_attach (device_t dev)
76{
77	dpt_softc_t *	dpt;
78	int		s;
79	int		error = 0;
80
81	u_int32_t	command;
82
83	dpt = device_get_softc(dev);
84	dpt->dev = dev;
85
86	command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
87
88#ifdef DPT_ALLOW_MMIO
89	if ((command & PCIM_CMD_MEMEN) != 0) {
90		dpt->io_rid = DPT_PCI_MEMADDR;
91		dpt->io_type = SYS_RES_MEMORY;
92		dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
93						     &dpt->io_rid, RF_ACTIVE);
94	}
95#endif
96	if (dpt->io_res == NULL && (command &  PCIM_CMD_PORTEN) != 0) {
97		dpt->io_rid = DPT_PCI_IOADDR;
98		dpt->io_type = SYS_RES_IOPORT;
99		dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
100						     &dpt->io_rid, RF_ACTIVE);
101	}
102
103	if (dpt->io_res == NULL) {
104		device_printf(dev, "can't allocate register resources\n");
105		error = ENOMEM;
106		goto bad;
107	}
108	dpt->io_offset = 0x10;
109
110	dpt->irq_rid = 0;
111	dpt->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &dpt->irq_rid,
112					      RF_ACTIVE | RF_SHAREABLE);
113	if (dpt->irq_res == NULL) {
114		device_printf(dev, "No irq?!\n");
115		error = ENOMEM;
116		goto bad;
117	}
118
119	/* Ensure busmastering is enabled */
120	command |= PCIM_CMD_BUSMASTEREN;
121	pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
122
123	if (rman_get_start(dpt->io_res) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) {
124#ifdef DPT_DEBUG_WARN
125		device_printf(dev, "Mapped as an IDE controller.  "
126				   "Disabling SCSI setup\n");
127#endif
128		error = ENXIO;
129		goto bad;
130	}
131
132	dpt_alloc(dev);
133
134	/* Allocate a dmatag representing the capabilities of this attachment */
135	/* XXX Should be a child of the PCI bus dma tag */
136	if (bus_dma_tag_create(	/* PCI parent */ bus_get_dma_tag(dev),
137				/* alignemnt */	1,
138				/* boundary  */	0,
139				/* lowaddr   */	BUS_SPACE_MAXADDR_32BIT,
140				/* highaddr  */	BUS_SPACE_MAXADDR,
141				/* filter    */	NULL,
142				/* filterarg */	NULL,
143				/* maxsize   */	BUS_SPACE_MAXSIZE_32BIT,
144				/* nsegments */	~0,
145				/* maxsegsz  */	BUS_SPACE_MAXSIZE_32BIT,
146				/* flags     */	0,
147				/* lockfunc  */ busdma_lock_mutex,
148				/* lockarg   */ &Giant,
149				&dpt->parent_dmat) != 0) {
150		error = ENXIO;
151		goto bad;
152	}
153
154	s = splcam();
155
156	if (dpt_init(dpt) != 0) {
157		error = ENXIO;
158		goto bad;
159	}
160
161	/* Register with the XPT */
162	dpt_attach(dpt);
163
164	splx(s);
165
166	if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY,
167			   NULL, dpt_intr, dpt, &dpt->ih)) {
168		device_printf(dev, "Unable to register interrupt handler\n");
169		error = ENXIO;
170		goto bad;
171	}
172
173	return (error);
174
175bad:
176	dpt_release_resources(dev);
177
178	dpt_free(dpt);
179
180	return (error);
181}
182
183static device_method_t dpt_pci_methods[] = {
184	/* Device interface */
185	DEVMETHOD(device_probe,         dpt_pci_probe),
186	DEVMETHOD(device_attach,        dpt_pci_attach),
187	DEVMETHOD(device_detach,        dpt_detach),
188
189	{ 0, 0 }
190};
191
192static driver_t dpt_pci_driver = {
193	"dpt",
194	dpt_pci_methods,
195	sizeof(dpt_softc_t),
196};
197
198DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0);
199MODULE_DEPEND(dpt, pci, 1, 1, 1);
200MODULE_DEPEND(dpt, cam, 1, 1, 1);
201