dpt_pci.c revision 165102 
1/*-
2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Copyright (c) 1997 Simon Shapiro
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/dpt/dpt_pci.c 165102 2006-12-11 18:28:31Z mjacob $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/lock.h>
38#include <sys/mutex.h>
39#include <sys/bus.h>
40
41#include <machine/bus.h>
42#include <machine/resource.h>
43#include <sys/rman.h>
44
45#include <dev/pci/pcireg.h>
46#include <dev/pci/pcivar.h>
47
48#include <cam/scsi/scsi_all.h>
49
50#include <dev/dpt/dpt.h>
51
52#define	DPT_VENDOR_ID		0x1044
53#define	DPT_DEVICE_ID		0xa400
54
55#define	DPT_PCI_IOADDR		PCIR_BAR(0)		/* I/O Address */
56#define	DPT_PCI_MEMADDR		PCIR_BAR(1)		/* Mem I/O Address */
57
58#define	ISA_PRIMARY_WD_ADDRESS	0x1f8
59
60static int	dpt_pci_probe	(device_t);
61static int	dpt_pci_attach	(device_t);
62
63static int
64dpt_pci_probe (device_t dev)
65{
66	if ((pci_get_vendor(dev) == DPT_VENDOR_ID) &&
67	    (pci_get_device(dev) == DPT_DEVICE_ID)) {
68		device_set_desc(dev, "DPT Caching SCSI RAID Controller");
69		return (BUS_PROBE_DEFAULT);
70	}
71	return (ENXIO);
72}
73
74static int
75dpt_pci_attach (device_t dev)
76{
77	dpt_softc_t *	dpt;
78	int		s;
79	int		error = 0;
80
81	u_int32_t	command;
82
83	dpt = device_get_softc(dev);
84
85	command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
86
87#ifdef DPT_ALLOW_MMIO
88	if ((command & PCIM_CMD_MEMEN) != 0) {
89		dpt->io_rid = DPT_PCI_MEMADDR;
90		dpt->io_type = SYS_RES_MEMORY;
91		dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
92						     &dpt->io_rid, RF_ACTIVE);
93	}
94#endif
95	if (dpt->io_res == NULL && (command &  PCIM_CMD_PORTEN) != 0) {
96		dpt->io_rid = DPT_PCI_IOADDR;
97		dpt->io_type = SYS_RES_IOPORT;
98		dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
99						     &dpt->io_rid, RF_ACTIVE);
100	}
101
102	if (dpt->io_res == NULL) {
103		device_printf(dev, "can't allocate register resources\n");
104		error = ENOMEM;
105		goto bad;
106	}
107	dpt->io_offset = 0x10;
108
109	dpt->irq_rid = 0;
110	dpt->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &dpt->irq_rid,
111					      RF_ACTIVE | RF_SHAREABLE);
112	if (dpt->irq_res == NULL) {
113		device_printf(dev, "No irq?!\n");
114		error = ENOMEM;
115		goto bad;
116	}
117
118	/* Ensure busmastering is enabled */
119	command |= PCIM_CMD_BUSMASTEREN;
120	pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
121
122	if (rman_get_start(dpt->io_res) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) {
123#ifdef DPT_DEBUG_WARN
124		device_printf(dev, "Mapped as an IDE controller.  "
125				   "Disabling SCSI setup\n");
126#endif
127		error = ENXIO;
128		goto bad;
129	}
130
131	dpt_alloc(dev);
132
133	/* Allocate a dmatag representing the capabilities of this attachment */
134	/* XXX Should be a child of the PCI bus dma tag */
135	if (bus_dma_tag_create(	/* parent    */	NULL,
136				/* alignemnt */	1,
137				/* boundary  */	0,
138				/* lowaddr   */	BUS_SPACE_MAXADDR_32BIT,
139				/* highaddr  */	BUS_SPACE_MAXADDR,
140				/* filter    */	NULL,
141				/* filterarg */	NULL,
142				/* maxsize   */	BUS_SPACE_MAXSIZE_32BIT,
143				/* nsegments */	~0,
144				/* maxsegsz  */	BUS_SPACE_MAXSIZE_32BIT,
145				/* flags     */	0,
146				/* lockfunc  */ busdma_lock_mutex,
147				/* lockarg   */ &Giant,
148				&dpt->parent_dmat) != 0) {
149		error = ENXIO;
150		goto bad;
151	}
152
153	s = splcam();
154
155	if (dpt_init(dpt) != 0) {
156		error = ENXIO;
157		goto bad;
158	}
159
160	/* Register with the XPT */
161	dpt_attach(dpt);
162
163	splx(s);
164
165	if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY,
166			   dpt_intr, dpt, &dpt->ih)) {
167		device_printf(dev, "Unable to register interrupt handler\n");
168		error = ENXIO;
169		goto bad;
170	}
171
172	return (error);
173
174bad:
175	dpt_release_resources(dev);
176
177	dpt_free(dpt);
178
179	return (error);
180}
181
182static device_method_t dpt_pci_methods[] = {
183	/* Device interface */
184	DEVMETHOD(device_probe,         dpt_pci_probe),
185	DEVMETHOD(device_attach,        dpt_pci_attach),
186	DEVMETHOD(device_detach,        dpt_detach),
187
188	{ 0, 0 }
189};
190
191static driver_t dpt_pci_driver = {
192	"dpt",
193	dpt_pci_methods,
194	sizeof(dpt_softc_t),
195};
196
197DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0);
198MODULE_DEPEND(dpt, pci, 1, 1, 1);
199MODULE_DEPEND(dpt, cam, 1, 1, 1);
200