dpt_pci.c revision 119690
1/*- 2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net> 3 * All rights reserved. 4 * 5 * Copyright (c) 1997 Simon Shapiro 6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/dpt/dpt_pci.c 119690 2003-09-02 17:30:40Z jhb $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/bus.h> 40 41#include <machine/bus_memio.h> 42#include <machine/bus_pio.h> 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <dev/pci/pcireg.h> 48#include <dev/pci/pcivar.h> 49 50#include <cam/scsi/scsi_all.h> 51 52#include <dev/dpt/dpt.h> 53 54#define DPT_VENDOR_ID 0x1044 55#define DPT_DEVICE_ID 0xa400 56 57#define DPT_PCI_IOADDR PCIR_BAR(0) /* I/O Address */ 58#define DPT_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */ 59 60#define ISA_PRIMARY_WD_ADDRESS 0x1f8 61 62static int dpt_pci_probe (device_t); 63static int dpt_pci_attach (device_t); 64 65static int 66dpt_pci_probe (device_t dev) 67{ 68 if ((pci_get_vendor(dev) == DPT_VENDOR_ID) && 69 (pci_get_device(dev) == DPT_DEVICE_ID)) { 70 device_set_desc(dev, "DPT Caching SCSI RAID Controller"); 71 return (0); 72 } 73 return (ENXIO); 74} 75 76static int 77dpt_pci_attach (device_t dev) 78{ 79 dpt_softc_t * dpt; 80 int s; 81 int error = 0; 82 83 u_int32_t command; 84 85 dpt = device_get_softc(dev); 86 87 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 88 89#ifdef DPT_ALLOW_MMIO 90 if ((command & PCIM_CMD_MEMEN) != 0) { 91 dpt->io_rid = DPT_PCI_MEMADDR; 92 dpt->io_type = SYS_RES_MEMORY; 93 dpt->io_res = bus_alloc_resource(dev, dpt->io_type, 94 &dpt->io_rid, 95 0, ~0, 1, RF_ACTIVE); 96 } 97#endif 98 if (dpt->io_res == NULL && (command & PCIM_CMD_PORTEN) != 0) { 99 dpt->io_rid = DPT_PCI_IOADDR; 100 dpt->io_type = SYS_RES_IOPORT; 101 dpt->io_res = bus_alloc_resource(dev, dpt->io_type, 102 &dpt->io_rid, 103 0, ~0, 1, RF_ACTIVE); 104 } 105 106 if (dpt->io_res == NULL) { 107 device_printf(dev, "can't allocate register resources\n"); 108 error = ENOMEM; 109 goto bad; 110 } 111 dpt->io_offset = 0x10; 112 113 dpt->irq_rid = 0; 114 dpt->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &dpt->irq_rid, 115 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 116 if (dpt->irq_res == NULL) { 117 device_printf(dev, "No irq?!\n"); 118 error = ENOMEM; 119 goto bad; 120 } 121 122 /* Ensure busmastering is enabled */ 123 command |= PCIM_CMD_BUSMASTEREN; 124 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 125 126 if (rman_get_start(dpt->io_res) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) { 127#ifdef DPT_DEBUG_WARN 128 device_printf(dev, "Mapped as an IDE controller. " 129 "Disabling SCSI setup\n"); 130#endif 131 error = ENXIO; 132 goto bad; 133 } 134 135 dpt_alloc(dev); 136 137 /* Allocate a dmatag representing the capabilities of this attachment */ 138 /* XXX Should be a child of the PCI bus dma tag */ 139 if (bus_dma_tag_create( /* parent */ NULL, 140 /* alignemnt */ 1, 141 /* boundary */ 0, 142 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 143 /* highaddr */ BUS_SPACE_MAXADDR, 144 /* filter */ NULL, 145 /* filterarg */ NULL, 146 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 147 /* nsegments */ ~0, 148 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 149 /* flags */ 0, 150 /* lockfunc */ busdma_lock_mutex, 151 /* lockarg */ &Giant, 152 &dpt->parent_dmat) != 0) { 153 dpt_free(dpt); 154 error = ENXIO; 155 goto bad; 156 } 157 158 s = splcam(); 159 160 if (dpt_init(dpt) != 0) { 161 dpt_free(dpt); 162 error = ENXIO; 163 goto bad; 164 } 165 166 /* Register with the XPT */ 167 dpt_attach(dpt); 168 169 splx(s); 170 171 if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY, 172 dpt_intr, dpt, &dpt->ih)) { 173 device_printf(dev, "Unable to register interrupt handler\n"); 174 error = ENXIO; 175 goto bad; 176 } 177 178 return (error); 179 180bad: 181 dpt_release_resources(dev); 182 183 if (dpt) 184 dpt_free(dpt); 185 186 return (error); 187} 188 189static device_method_t dpt_pci_methods[] = { 190 /* Device interface */ 191 DEVMETHOD(device_probe, dpt_pci_probe), 192 DEVMETHOD(device_attach, dpt_pci_attach), 193 DEVMETHOD(device_detach, dpt_detach), 194 195 { 0, 0 } 196}; 197 198static driver_t dpt_pci_driver = { 199 "dpt", 200 dpt_pci_methods, 201 sizeof(dpt_softc_t), 202}; 203 204DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0); 205