dpt_pci.c revision 112780 
1/*-
2 * Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Copyright (c) 1997 Simon Shapiro
6 * All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 *	$FreeBSD: head/sys/dev/dpt/dpt_pci.c 112780 2003-03-29 08:30:45Z mdodd $
30 */
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/module.h>
36#include <sys/bus.h>
37
38#include <machine/bus_memio.h>
39#include <machine/bus_pio.h>
40#include <machine/bus.h>
41#include <machine/resource.h>
42#include <sys/rman.h>
43
44#include <pci/pcireg.h>
45#include <pci/pcivar.h>
46
47#include <cam/scsi/scsi_all.h>
48
49#include <dev/dpt/dpt.h>
50
51#define	DPT_VENDOR_ID		0x1044
52#define	DPT_DEVICE_ID		0xa400
53
54#define	DPT_PCI_IOADDR		PCIR_MAPS		/* I/O Address */
55#define	DPT_PCI_MEMADDR		(PCIR_MAPS + 4)		/* Mem I/O Address */
56
57#define	ISA_PRIMARY_WD_ADDRESS	0x1f8
58
59static int	dpt_pci_probe	(device_t);
60static int	dpt_pci_attach	(device_t);
61
62static int
63dpt_pci_probe (device_t dev)
64{
65	if ((pci_get_vendor(dev) == DPT_VENDOR_ID) &&
66	    (pci_get_device(dev) == DPT_DEVICE_ID)) {
67		device_set_desc(dev, "DPT Caching SCSI RAID Controller");
68		return (0);
69	}
70	return (ENXIO);
71}
72
73static int
74dpt_pci_attach (device_t dev)
75{
76	dpt_softc_t *	dpt;
77	int		s;
78	int		error = 0;
79
80	u_int32_t	command;
81
82	dpt = device_get_softc(dev);
83
84	command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
85
86#ifdef DPT_ALLOW_MMIO
87	if ((command & PCIM_CMD_MEMEN) != 0) {
88		dpt->io_rid = DPT_PCI_MEMADDR;
89		dpt->io_type = SYS_RES_MEMORY;
90		dpt->io_res = bus_alloc_resource(dev, dpt->io_type,
91						 &dpt->io_rid,
92						 0, ~0, 1, RF_ACTIVE);
93	}
94#endif
95	if (dpt->io_res == NULL && (command &  PCIM_CMD_PORTEN) != 0) {
96		dpt->io_rid = DPT_PCI_IOADDR;
97		dpt->io_type = SYS_RES_IOPORT;
98		dpt->io_res = bus_alloc_resource(dev, dpt->io_type,
99						 &dpt->io_rid,
100						 0, ~0, 1, RF_ACTIVE);
101	}
102
103	if (dpt->io_res == NULL) {
104		device_printf(dev, "can't allocate register resources\n");
105		error = ENOMEM;
106		goto bad;
107	}
108	dpt->io_offset = 0x10;
109
110	dpt->irq_rid = 0;
111	dpt->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &dpt->irq_rid,
112					  0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
113	if (dpt->irq_res == NULL) {
114		device_printf(dev, "No irq?!\n");
115		error = ENOMEM;
116		goto bad;
117	}
118
119	/* Ensure busmastering is enabled */
120	command |= PCIM_CMD_BUSMASTEREN;
121	pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
122
123	if (rman_get_start(dpt->io_res) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) {
124#ifdef DPT_DEBUG_WARN
125		device_printf(dev, "Mapped as an IDE controller.  "
126				   "Disabling SCSI setup\n");
127#endif
128		error = ENXIO;
129		goto bad;
130	}
131
132	dpt_alloc(dev);
133
134	/* Allocate a dmatag representing the capabilities of this attachment */
135	/* XXX Should be a child of the PCI bus dma tag */
136	if (bus_dma_tag_create(	/* parent    */	NULL,
137				/* alignemnt */	1,
138				/* boundary  */	0,
139				/* lowaddr   */	BUS_SPACE_MAXADDR_32BIT,
140				/* highaddr  */	BUS_SPACE_MAXADDR,
141				/* filter    */	NULL,
142				/* filterarg */	NULL,
143				/* maxsize   */	BUS_SPACE_MAXSIZE_32BIT,
144				/* nsegments */	~0,
145				/* maxsegsz  */	BUS_SPACE_MAXSIZE_32BIT,
146				/* flags     */	0,
147				&dpt->parent_dmat) != 0) {
148		dpt_free(dpt);
149		error = ENXIO;
150		goto bad;
151	}
152
153	s = splcam();
154
155	if (dpt_init(dpt) != 0) {
156		dpt_free(dpt);
157		error = ENXIO;
158		goto bad;
159	}
160
161	/* Register with the XPT */
162	dpt_attach(dpt);
163
164	splx(s);
165
166	if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY,
167			   dpt_intr, dpt, &dpt->ih)) {
168		device_printf(dev, "Unable to register interrupt handler\n");
169		error = ENXIO;
170		goto bad;
171	}
172
173	return (error);
174
175bad:
176	dpt_release_resources(dev);
177
178	if (dpt)
179		dpt_free(dpt);
180
181	return (error);
182}
183
184static device_method_t dpt_pci_methods[] = {
185	/* Device interface */
186	DEVMETHOD(device_probe,         dpt_pci_probe),
187	DEVMETHOD(device_attach,        dpt_pci_attach),
188	DEVMETHOD(device_detach,        dpt_detach),
189
190	{ 0, 0 }
191};
192
193static driver_t dpt_pci_driver = {
194	"dpt",
195	dpt_pci_methods,
196	sizeof(dpt_softc_t),
197};
198
199DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0);
200