1305549Sjhb/*-
2305549Sjhb * Copyright (c) 2016 Chelsio Communications, Inc.
3305549Sjhb * All rights reserved.
4305549Sjhb * Written by: John Baldwin <jhb@FreeBSD.org>
5305549Sjhb *
6305549Sjhb * Redistribution and use in source and binary forms, with or without
7305549Sjhb * modification, are permitted provided that the following conditions
8305549Sjhb * are met:
9305549Sjhb * 1. Redistributions of source code must retain the above copyright
10305549Sjhb *    notice, this list of conditions and the following disclaimer.
11305549Sjhb * 2. Redistributions in binary form must reproduce the above copyright
12305549Sjhb *    notice, this list of conditions and the following disclaimer in the
13305549Sjhb *    documentation and/or other materials provided with the distribution.
14305549Sjhb *
15305549Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16305549Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17305549Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18305549Sjhb * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19305549Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20305549Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21305549Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22305549Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23305549Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24305549Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25305549Sjhb * SUCH DAMAGE.
26305549Sjhb */
27305549Sjhb
28305549Sjhb#include <sys/cdefs.h>
29305549Sjhb__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_vf.c 355253 2019-11-30 21:11:17Z np $");
30305549Sjhb
31305549Sjhb#include "opt_inet.h"
32305549Sjhb#include "opt_inet6.h"
33305549Sjhb
34305549Sjhb#include <sys/param.h>
35305549Sjhb#include <sys/bus.h>
36305549Sjhb#include <sys/conf.h>
37305549Sjhb#include <sys/kernel.h>
38305549Sjhb#include <sys/module.h>
39305549Sjhb#include <sys/priv.h>
40305549Sjhb#include <dev/pci/pcivar.h>
41305549Sjhb#if defined(__i386__) || defined(__amd64__)
42305549Sjhb#include <vm/vm.h>
43305549Sjhb#include <vm/pmap.h>
44305549Sjhb#endif
45305549Sjhb
46305549Sjhb#include "common/common.h"
47305549Sjhb#include "common/t4_regs.h"
48305549Sjhb#include "t4_ioctl.h"
49305549Sjhb#include "t4_mp_ring.h"
50305549Sjhb
51305549Sjhb/*
52305549Sjhb * Some notes:
53305549Sjhb *
54305549Sjhb * The Virtual Interfaces are connected to an internal switch on the chip
55305549Sjhb * which allows VIs attached to the same port to talk to each other even when
56305549Sjhb * the port link is down.  As a result, we might want to always report a
57305549Sjhb * VF's link as being "up".
58305549Sjhb *
59305549Sjhb * XXX: Add a TUNABLE and possible per-device sysctl for this?
60305549Sjhb */
61305549Sjhb
62305549Sjhbstruct intrs_and_queues {
63305549Sjhb	uint16_t intr_type;	/* MSI, or MSI-X */
64305549Sjhb	uint16_t nirq;		/* Total # of vectors */
65330307Snp	uint16_t ntxq;		/* # of NIC txq's for each port */
66330307Snp	uint16_t nrxq;		/* # of NIC rxq's for each port */
67305549Sjhb};
68305549Sjhb
69305549Sjhbstruct {
70305549Sjhb	uint16_t device;
71305549Sjhb	char *desc;
72305549Sjhb} t4vf_pciids[] = {
73305549Sjhb	{0x4800, "Chelsio T440-dbg VF"},
74305549Sjhb	{0x4801, "Chelsio T420-CR VF"},
75305549Sjhb	{0x4802, "Chelsio T422-CR VF"},
76305549Sjhb	{0x4803, "Chelsio T440-CR VF"},
77305549Sjhb	{0x4804, "Chelsio T420-BCH VF"},
78305549Sjhb	{0x4805, "Chelsio T440-BCH VF"},
79305549Sjhb	{0x4806, "Chelsio T440-CH VF"},
80305549Sjhb	{0x4807, "Chelsio T420-SO VF"},
81305549Sjhb	{0x4808, "Chelsio T420-CX VF"},
82305549Sjhb	{0x4809, "Chelsio T420-BT VF"},
83305549Sjhb	{0x480a, "Chelsio T404-BT VF"},
84305549Sjhb	{0x480e, "Chelsio T440-LP-CR VF"},
85305549Sjhb}, t5vf_pciids[] = {
86305549Sjhb	{0x5800, "Chelsio T580-dbg VF"},
87305549Sjhb	{0x5801,  "Chelsio T520-CR VF"},	/* 2 x 10G */
88305549Sjhb	{0x5802,  "Chelsio T522-CR VF"},	/* 2 x 10G, 2 X 1G */
89305549Sjhb	{0x5803,  "Chelsio T540-CR VF"},	/* 4 x 10G */
90305549Sjhb	{0x5807,  "Chelsio T520-SO VF"},	/* 2 x 10G, nomem */
91305549Sjhb	{0x5809,  "Chelsio T520-BT VF"},	/* 2 x 10GBaseT */
92305549Sjhb	{0x580a,  "Chelsio T504-BT VF"},	/* 4 x 1G */
93305549Sjhb	{0x580d,  "Chelsio T580-CR VF"},	/* 2 x 40G */
94305549Sjhb	{0x580e,  "Chelsio T540-LP-CR VF"},	/* 4 x 10G */
95305549Sjhb	{0x5810,  "Chelsio T580-LP-CR VF"},	/* 2 x 40G */
96305549Sjhb	{0x5811,  "Chelsio T520-LL-CR VF"},	/* 2 x 10G */
97305549Sjhb	{0x5812,  "Chelsio T560-CR VF"},	/* 1 x 40G, 2 x 10G */
98305549Sjhb	{0x5814,  "Chelsio T580-LP-SO-CR VF"},	/* 2 x 40G, nomem */
99305549Sjhb	{0x5815,  "Chelsio T502-BT VF"},	/* 2 x 1G */
100355253Snp	{0x5818,  "Chelsio T540-BT VF"},	/* 4 x 10GBaseT */
101355253Snp	{0x5819,  "Chelsio T540-LP-BT VF"},	/* 4 x 10GBaseT */
102355253Snp	{0x581a,  "Chelsio T540-SO-BT VF"},	/* 4 x 10GBaseT, nomem */
103355253Snp	{0x581b,  "Chelsio T540-SO-CR VF"},	/* 4 x 10G, nomem */
104309560Sjhb}, t6vf_pciids[] = {
105318843Snp	{0x6800, "Chelsio T6-DBG-25 VF"},	/* 2 x 10/25G, debug */
106309560Sjhb	{0x6801, "Chelsio T6225-CR VF"},	/* 2 x 10/25G */
107309560Sjhb	{0x6802, "Chelsio T6225-SO-CR VF"},	/* 2 x 10/25G, nomem */
108318843Snp	{0x6803, "Chelsio T6425-CR VF"},	/* 4 x 10/25G */
109318843Snp	{0x6804, "Chelsio T6425-SO-CR VF"},	/* 4 x 10/25G, nomem */
110318843Snp	{0x6805, "Chelsio T6225-OCP-SO VF"},	/* 2 x 10/25G, nomem */
111318843Snp	{0x6806, "Chelsio T62100-OCP-SO VF"},	/* 2 x 40/50/100G, nomem */
112309560Sjhb	{0x6807, "Chelsio T62100-LP-CR VF"},	/* 2 x 40/50/100G */
113309560Sjhb	{0x6808, "Chelsio T62100-SO-CR VF"},	/* 2 x 40/50/100G, nomem */
114318843Snp	{0x6809, "Chelsio T6210-BT VF"},	/* 2 x 10GBASE-T */
115309560Sjhb	{0x680d, "Chelsio T62100-CR VF"},	/* 2 x 40/50/100G */
116318843Snp	{0x6810, "Chelsio T6-DBG-100 VF"},	/* 2 x 40/50/100G, debug */
117318843Snp	{0x6811, "Chelsio T6225-LL-CR VF"},	/* 2 x 10/25G */
118318843Snp	{0x6814, "Chelsio T61100-OCP-SO VF"},	/* 1 x 40/50/100G, nomem */
119318843Snp	{0x6815, "Chelsio T6201-BT VF"},	/* 2 x 1000BASE-T */
120318843Snp
121318843Snp	/* Custom */
122318843Snp	{0x6880, "Chelsio T6225 80 VF"},
123318843Snp	{0x6881, "Chelsio T62100 81 VF"},
124355253Snp	{0x6882, "Chelsio T6225-CR 82 VF"},
125355253Snp	{0x6883, "Chelsio T62100-CR 83 VF"},
126355253Snp	{0x6884, "Chelsio T64100-CR 84 VF"},
127355253Snp	{0x6885, "Chelsio T6240-SO 85 VF"},
128355253Snp	{0x6886, "Chelsio T6225-SO-CR 86 VF"},
129355253Snp	{0x6887, "Chelsio T6225-CR 87 VF"},
130305549Sjhb};
131305549Sjhb
132305549Sjhbstatic d_ioctl_t t4vf_ioctl;
133305549Sjhb
134305549Sjhbstatic struct cdevsw t4vf_cdevsw = {
135305549Sjhb       .d_version = D_VERSION,
136305549Sjhb       .d_ioctl = t4vf_ioctl,
137305549Sjhb       .d_name = "t4vf",
138305549Sjhb};
139305549Sjhb
140305549Sjhbstatic int
141305549Sjhbt4vf_probe(device_t dev)
142305549Sjhb{
143306694Sjhb	uint16_t d;
144305549Sjhb	size_t i;
145305549Sjhb
146305549Sjhb	d = pci_get_device(dev);
147305549Sjhb	for (i = 0; i < nitems(t4vf_pciids); i++) {
148305549Sjhb		if (d == t4vf_pciids[i].device) {
149305549Sjhb			device_set_desc(dev, t4vf_pciids[i].desc);
150305549Sjhb			return (BUS_PROBE_DEFAULT);
151305549Sjhb		}
152305549Sjhb	}
153305549Sjhb	return (ENXIO);
154305549Sjhb}
155305549Sjhb
156305549Sjhbstatic int
157305549Sjhbt5vf_probe(device_t dev)
158305549Sjhb{
159306694Sjhb	uint16_t d;
160305549Sjhb	size_t i;
161305549Sjhb
162305549Sjhb	d = pci_get_device(dev);
163305549Sjhb	for (i = 0; i < nitems(t5vf_pciids); i++) {
164305549Sjhb		if (d == t5vf_pciids[i].device) {
165305549Sjhb			device_set_desc(dev, t5vf_pciids[i].desc);
166305549Sjhb			return (BUS_PROBE_DEFAULT);
167305549Sjhb		}
168305549Sjhb	}
169305549Sjhb	return (ENXIO);
170305549Sjhb}
171305549Sjhb
172309560Sjhbstatic int
173309560Sjhbt6vf_probe(device_t dev)
174309560Sjhb{
175309560Sjhb	uint16_t d;
176309560Sjhb	size_t i;
177309560Sjhb
178309560Sjhb	d = pci_get_device(dev);
179309560Sjhb	for (i = 0; i < nitems(t6vf_pciids); i++) {
180309560Sjhb		if (d == t6vf_pciids[i].device) {
181309560Sjhb			device_set_desc(dev, t6vf_pciids[i].desc);
182309560Sjhb			return (BUS_PROBE_DEFAULT);
183309560Sjhb		}
184309560Sjhb	}
185309560Sjhb	return (ENXIO);
186309560Sjhb}
187309560Sjhb
188305549Sjhb#define FW_PARAM_DEV(param) \
189305549Sjhb	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
190305549Sjhb	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
191305549Sjhb#define FW_PARAM_PFVF(param) \
192305549Sjhb	(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
193305549Sjhb	 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
194305549Sjhb
195305549Sjhbstatic int
196305549Sjhbget_params__pre_init(struct adapter *sc)
197305549Sjhb{
198305549Sjhb	int rc;
199305549Sjhb	uint32_t param[3], val[3];
200305549Sjhb
201305549Sjhb	param[0] = FW_PARAM_DEV(FWREV);
202305549Sjhb	param[1] = FW_PARAM_DEV(TPREV);
203305549Sjhb	param[2] = FW_PARAM_DEV(CCLK);
204305549Sjhb	rc = -t4vf_query_params(sc, nitems(param), param, val);
205305549Sjhb	if (rc != 0) {
206305549Sjhb		device_printf(sc->dev,
207305549Sjhb		    "failed to query parameters (pre_init): %d.\n", rc);
208305549Sjhb		return (rc);
209305549Sjhb	}
210305549Sjhb
211305549Sjhb	sc->params.fw_vers = val[0];
212305549Sjhb	sc->params.tp_vers = val[1];
213305549Sjhb	sc->params.vpd.cclk = val[2];
214305549Sjhb
215305549Sjhb	snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
216305549Sjhb	    G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
217305549Sjhb	    G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
218305549Sjhb	    G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
219305549Sjhb	    G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
220305549Sjhb
221305549Sjhb	snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
222305549Sjhb	    G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
223305549Sjhb	    G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
224305549Sjhb	    G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
225305549Sjhb	    G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
226305549Sjhb
227305549Sjhb	return (0);
228305549Sjhb}
229305549Sjhb
230305549Sjhbstatic int
231305549Sjhbget_params__post_init(struct adapter *sc)
232305549Sjhb{
233305549Sjhb	int rc;
234305549Sjhb
235305549Sjhb	rc = -t4vf_get_sge_params(sc);
236305549Sjhb	if (rc != 0) {
237305549Sjhb		device_printf(sc->dev,
238305549Sjhb		    "unable to retrieve adapter SGE parameters: %d\n", rc);
239305549Sjhb		return (rc);
240305549Sjhb	}
241305549Sjhb
242305549Sjhb	rc = -t4vf_get_rss_glb_config(sc);
243305549Sjhb	if (rc != 0) {
244305549Sjhb		device_printf(sc->dev,
245305549Sjhb		    "unable to retrieve adapter RSS parameters: %d\n", rc);
246305549Sjhb		return (rc);
247305549Sjhb	}
248305549Sjhb	if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
249305549Sjhb		device_printf(sc->dev,
250305549Sjhb		    "unable to operate with global RSS mode %d\n",
251305549Sjhb		    sc->params.rss.mode);
252305549Sjhb		return (EINVAL);
253305549Sjhb	}
254305549Sjhb
255305549Sjhb	rc = t4_read_chip_settings(sc);
256305549Sjhb	if (rc != 0)
257305549Sjhb		return (rc);
258305549Sjhb
259305549Sjhb	/*
260305549Sjhb	 * Grab our Virtual Interface resource allocation, extract the
261305549Sjhb	 * features that we're interested in and do a bit of sanity testing on
262305549Sjhb	 * what we discover.
263305549Sjhb	 */
264305549Sjhb	rc = -t4vf_get_vfres(sc);
265305549Sjhb	if (rc != 0) {
266305549Sjhb		device_printf(sc->dev,
267305549Sjhb		    "unable to get virtual interface resources: %d\n", rc);
268305549Sjhb		return (rc);
269305549Sjhb	}
270305549Sjhb
271305549Sjhb	/*
272305549Sjhb	 * Check for various parameter sanity issues.
273305549Sjhb	 */
274305549Sjhb	if (sc->params.vfres.pmask == 0) {
275305549Sjhb		device_printf(sc->dev, "no port access configured/usable!\n");
276305549Sjhb		return (EINVAL);
277305549Sjhb	}
278305549Sjhb	if (sc->params.vfres.nvi == 0) {
279305549Sjhb		device_printf(sc->dev,
280305549Sjhb		    "no virtual interfaces configured/usable!\n");
281305549Sjhb		return (EINVAL);
282305549Sjhb	}
283305549Sjhb	sc->params.portvec = sc->params.vfres.pmask;
284305549Sjhb
285305549Sjhb	return (0);
286305549Sjhb}
287305549Sjhb
288305549Sjhbstatic int
289305549Sjhbset_params__post_init(struct adapter *sc)
290305549Sjhb{
291305549Sjhb	uint32_t param, val;
292305549Sjhb
293305549Sjhb	/* ask for encapsulated CPLs */
294305549Sjhb	param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
295305549Sjhb	val = 1;
296305549Sjhb	(void)t4vf_set_params(sc, 1, &param, &val);
297305549Sjhb
298346964Snp	/* Enable 32b port caps if the firmware supports it. */
299346964Snp	param = FW_PARAM_PFVF(PORT_CAPS32);
300346964Snp	val = 1;
301346964Snp	if (t4vf_set_params(sc, 1, &param, &val) == 0)
302346964Snp		sc->params.port_caps32 = 1;
303346964Snp
304305549Sjhb	return (0);
305305549Sjhb}
306305549Sjhb
307305549Sjhb#undef FW_PARAM_PFVF
308305549Sjhb#undef FW_PARAM_DEV
309305549Sjhb
310305549Sjhbstatic int
311330307Snpcfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq)
312305549Sjhb{
313305549Sjhb	struct vf_resources *vfres;
314330307Snp	int nrxq, ntxq, nports;
315305549Sjhb	int itype, iq_avail, navail, rc;
316305549Sjhb
317305549Sjhb	/*
318305549Sjhb	 * Figure out the layout of queues across our VIs and ensure
319305549Sjhb	 * we can allocate enough interrupts for our layout.
320305549Sjhb	 */
321305549Sjhb	vfres = &sc->params.vfres;
322330307Snp	nports = sc->params.nports;
323305549Sjhb	bzero(iaq, sizeof(*iaq));
324305549Sjhb
325305549Sjhb	for (itype = INTR_MSIX; itype != 0; itype >>= 1) {
326305549Sjhb		if (itype == INTR_INTX)
327305549Sjhb			continue;
328305549Sjhb
329305549Sjhb		if (itype == INTR_MSIX)
330305549Sjhb			navail = pci_msix_count(sc->dev);
331305549Sjhb		else
332305549Sjhb			navail = pci_msi_count(sc->dev);
333305549Sjhb
334305549Sjhb		if (navail == 0)
335305549Sjhb			continue;
336305549Sjhb
337305549Sjhb		iaq->intr_type = itype;
338305549Sjhb
339305549Sjhb		/*
340305549Sjhb		 * XXX: The Linux driver reserves an Ingress Queue for
341305549Sjhb		 * forwarded interrupts when using MSI (but not MSI-X).
342305549Sjhb		 * It seems it just always asks for 2 interrupts and
343305549Sjhb		 * forwards all rxqs to the forwarded interrupt.
344305549Sjhb		 *
345305549Sjhb		 * We must reserve one IRQ for the for the firmware
346305549Sjhb		 * event queue.
347305549Sjhb		 *
348305549Sjhb		 * Every rxq requires an ingress queue with a free
349305549Sjhb		 * list and interrupts and an egress queue.  Every txq
350305549Sjhb		 * requires an ETH egress queue.
351305549Sjhb		 */
352305549Sjhb		iaq->nirq = T4VF_EXTRA_INTR;
353305549Sjhb
354305549Sjhb		/*
355305549Sjhb		 * First, determine how many queues we can allocate.
356305549Sjhb		 * Start by finding the upper bound on rxqs from the
357305549Sjhb		 * limit on ingress queues.
358305549Sjhb		 */
359305549Sjhb		iq_avail = vfres->niqflint - iaq->nirq;
360330307Snp		if (iq_avail < nports) {
361305549Sjhb			device_printf(sc->dev,
362305549Sjhb			    "Not enough ingress queues (%d) for %d ports\n",
363330307Snp			    vfres->niqflint, nports);
364305549Sjhb			return (ENXIO);
365305549Sjhb		}
366305549Sjhb
367305549Sjhb		/*
368305549Sjhb		 * Try to honor the cap on interrupts.  If there aren't
369305549Sjhb		 * enough interrupts for at least one interrupt per
370305549Sjhb		 * port, then don't bother, we will just forward all
371305549Sjhb		 * interrupts to one interrupt in that case.
372305549Sjhb		 */
373330307Snp		if (iaq->nirq + nports <= navail) {
374305549Sjhb			if (iq_avail > navail - iaq->nirq)
375305549Sjhb				iq_avail = navail - iaq->nirq;
376305549Sjhb		}
377305549Sjhb
378330307Snp		nrxq = nports * t4_nrxq;
379305549Sjhb		if (nrxq > iq_avail) {
380305549Sjhb			/*
381330307Snp			 * Too many ingress queues.  Use what we can.
382305549Sjhb			 */
383330307Snp			nrxq = (iq_avail / nports) * nports;
384305549Sjhb		}
385305549Sjhb		KASSERT(nrxq <= iq_avail, ("too many ingress queues"));
386305549Sjhb
387305549Sjhb		/*
388305549Sjhb		 * Next, determine the upper bound on txqs from the limit
389305549Sjhb		 * on ETH queues.
390305549Sjhb		 */
391330307Snp		if (vfres->nethctrl < nports) {
392305549Sjhb			device_printf(sc->dev,
393305549Sjhb			    "Not enough ETH queues (%d) for %d ports\n",
394330307Snp			    vfres->nethctrl, nports);
395305549Sjhb			return (ENXIO);
396305549Sjhb		}
397305549Sjhb
398330307Snp		ntxq = nports * t4_ntxq;
399305549Sjhb		if (ntxq > vfres->nethctrl) {
400305549Sjhb			/*
401330307Snp			 * Too many ETH queues.  Use what we can.
402305549Sjhb			 */
403330307Snp			ntxq = (vfres->nethctrl / nports) * nports;
404305549Sjhb		}
405305549Sjhb		KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
406305549Sjhb
407305549Sjhb		/*
408305549Sjhb		 * Finally, ensure we have enough egress queues.
409305549Sjhb		 */
410330307Snp		if (vfres->neq < nports * 2) {
411305549Sjhb			device_printf(sc->dev,
412305549Sjhb			    "Not enough egress queues (%d) for %d ports\n",
413330307Snp			    vfres->neq, nports);
414305549Sjhb			return (ENXIO);
415305549Sjhb		}
416305549Sjhb		if (nrxq + ntxq > vfres->neq) {
417305549Sjhb			/* Just punt and use 1 for everything. */
418330307Snp			nrxq = ntxq = nports;
419305549Sjhb		}
420305549Sjhb		KASSERT(nrxq <= iq_avail, ("too many ingress queues"));
421305549Sjhb		KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
422305549Sjhb		KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues"));
423305549Sjhb
424305549Sjhb		/*
425305549Sjhb		 * Do we have enough interrupts?  For MSI the interrupts
426305549Sjhb		 * have to be a power of 2 as well.
427305549Sjhb		 */
428305549Sjhb		iaq->nirq += nrxq;
429330307Snp		iaq->ntxq = ntxq;
430330307Snp		iaq->nrxq = nrxq;
431305549Sjhb		if (iaq->nirq <= navail &&
432305549Sjhb		    (itype != INTR_MSI || powerof2(iaq->nirq))) {
433305549Sjhb			navail = iaq->nirq;
434305549Sjhb			if (itype == INTR_MSIX)
435305549Sjhb				rc = pci_alloc_msix(sc->dev, &navail);
436305549Sjhb			else
437305549Sjhb				rc = pci_alloc_msi(sc->dev, &navail);
438305549Sjhb			if (rc != 0) {
439305549Sjhb				device_printf(sc->dev,
440305549Sjhb		    "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
441305549Sjhb				    itype, rc, iaq->nirq, navail);
442305549Sjhb				return (rc);
443305549Sjhb			}
444305549Sjhb			if (navail == iaq->nirq) {
445305549Sjhb				return (0);
446305549Sjhb			}
447305549Sjhb			pci_release_msi(sc->dev);
448305549Sjhb		}
449305549Sjhb
450305549Sjhb		/* Fall back to a single interrupt. */
451305549Sjhb		iaq->nirq = 1;
452305549Sjhb		navail = iaq->nirq;
453305549Sjhb		if (itype == INTR_MSIX)
454305549Sjhb			rc = pci_alloc_msix(sc->dev, &navail);
455305549Sjhb		else
456305549Sjhb			rc = pci_alloc_msi(sc->dev, &navail);
457305549Sjhb		if (rc != 0)
458305549Sjhb			device_printf(sc->dev,
459305549Sjhb		    "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
460305549Sjhb			    itype, rc, iaq->nirq, navail);
461305549Sjhb		return (rc);
462305549Sjhb	}
463305549Sjhb
464305549Sjhb	device_printf(sc->dev,
465305549Sjhb	    "failed to find a usable interrupt type.  "
466305549Sjhb	    "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
467305549Sjhb	    pci_msix_count(sc->dev), pci_msi_count(sc->dev));
468305549Sjhb
469305549Sjhb	return (ENXIO);
470305549Sjhb}
471305549Sjhb
472305549Sjhbstatic int
473305549Sjhbt4vf_attach(device_t dev)
474305549Sjhb{
475305549Sjhb	struct adapter *sc;
476330307Snp	int rc = 0, i, j, rqidx, tqidx;
477305549Sjhb	struct make_dev_args mda;
478305549Sjhb	struct intrs_and_queues iaq;
479305549Sjhb	struct sge *s;
480305549Sjhb
481305549Sjhb	sc = device_get_softc(dev);
482305549Sjhb	sc->dev = dev;
483305549Sjhb	pci_enable_busmaster(dev);
484305549Sjhb	pci_set_max_read_req(dev, 4096);
485305549Sjhb	sc->params.pci.mps = pci_get_max_payload(dev);
486305549Sjhb
487305549Sjhb	sc->flags |= IS_VF;
488346964Snp	TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
489305549Sjhb
490305549Sjhb	sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS);
491305549Sjhb	sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL);
492305549Sjhb	snprintf(sc->lockname, sizeof(sc->lockname), "%s",
493305549Sjhb	    device_get_nameunit(dev));
494305549Sjhb	mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
495305549Sjhb	t4_add_adapter(sc);
496305549Sjhb
497305549Sjhb	mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
498305549Sjhb	TAILQ_INIT(&sc->sfl);
499305549Sjhb	callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
500305549Sjhb
501305549Sjhb	mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
502305549Sjhb
503305549Sjhb	rc = t4_map_bars_0_and_4(sc);
504305549Sjhb	if (rc != 0)
505305549Sjhb		goto done; /* error message displayed already */
506305549Sjhb
507305549Sjhb	rc = -t4vf_prep_adapter(sc);
508305549Sjhb	if (rc != 0)
509305549Sjhb		goto done;
510305549Sjhb
511309560Sjhb	t4_init_devnames(sc);
512309560Sjhb	if (sc->names == NULL) {
513309560Sjhb		rc = ENOTSUP;
514309560Sjhb		goto done; /* error message displayed already */
515309560Sjhb	}
516309560Sjhb
517305549Sjhb	/*
518305549Sjhb	 * Leave the 'pf' and 'mbox' values as zero.  This ensures
519305549Sjhb	 * that various firmware messages do not set the fields which
520305549Sjhb	 * is the correct thing to do for a VF.
521305549Sjhb	 */
522305549Sjhb
523305549Sjhb	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
524305549Sjhb
525305549Sjhb	make_dev_args_init(&mda);
526305549Sjhb	mda.mda_devsw = &t4vf_cdevsw;
527305549Sjhb	mda.mda_uid = UID_ROOT;
528305549Sjhb	mda.mda_gid = GID_WHEEL;
529305549Sjhb	mda.mda_mode = 0600;
530305549Sjhb	mda.mda_si_drv1 = sc;
531305549Sjhb	rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
532305549Sjhb	if (rc != 0)
533305549Sjhb		device_printf(dev, "failed to create nexus char device: %d.\n",
534305549Sjhb		    rc);
535305549Sjhb
536305549Sjhb#if defined(__i386__)
537305549Sjhb	if ((cpu_feature & CPUID_CX8) == 0) {
538305549Sjhb		device_printf(dev, "64 bit atomics not available.\n");
539305549Sjhb		rc = ENOTSUP;
540305549Sjhb		goto done;
541305549Sjhb	}
542305549Sjhb#endif
543305549Sjhb
544305549Sjhb	/*
545305549Sjhb	 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux
546305549Sjhb	 * 2.6.31 and later we can't call pci_reset_function() in order to
547305549Sjhb	 * issue an FLR because of a self- deadlock on the device semaphore.
548305549Sjhb	 * Meanwhile, the OS infrastructure doesn't issue FLRs in all the
549305549Sjhb	 * cases where they're needed -- for instance, some versions of KVM
550305549Sjhb	 * fail to reset "Assigned Devices" when the VM reboots.  Therefore we
551305549Sjhb	 * use the firmware based reset in order to reset any per function
552305549Sjhb	 * state.
553305549Sjhb	 */
554305549Sjhb	rc = -t4vf_fw_reset(sc);
555305549Sjhb	if (rc != 0) {
556305549Sjhb		device_printf(dev, "FW reset failed: %d\n", rc);
557305549Sjhb		goto done;
558305549Sjhb	}
559305549Sjhb	sc->flags |= FW_OK;
560305549Sjhb
561305549Sjhb	/*
562305549Sjhb	 * Grab basic operational parameters.  These will predominantly have
563305549Sjhb	 * been set up by the Physical Function Driver or will be hard coded
564305549Sjhb	 * into the adapter.  We just have to live with them ...  Note that
565305549Sjhb	 * we _must_ get our VPD parameters before our SGE parameters because
566305549Sjhb	 * we need to know the adapter's core clock from the VPD in order to
567305549Sjhb	 * properly decode the SGE Timer Values.
568305549Sjhb	 */
569305549Sjhb	rc = get_params__pre_init(sc);
570305549Sjhb	if (rc != 0)
571305549Sjhb		goto done; /* error message displayed already */
572305549Sjhb	rc = get_params__post_init(sc);
573305549Sjhb	if (rc != 0)
574305549Sjhb		goto done; /* error message displayed already */
575305549Sjhb
576305549Sjhb	rc = set_params__post_init(sc);
577305549Sjhb	if (rc != 0)
578305549Sjhb		goto done; /* error message displayed already */
579305549Sjhb
580305549Sjhb	rc = t4_map_bar_2(sc);
581305549Sjhb	if (rc != 0)
582305549Sjhb		goto done; /* error message displayed already */
583305549Sjhb
584305549Sjhb	rc = t4_create_dma_tag(sc);
585305549Sjhb	if (rc != 0)
586305549Sjhb		goto done; /* error message displayed already */
587305549Sjhb
588305549Sjhb	/*
589305549Sjhb	 * The number of "ports" which we support is equal to the number of
590305549Sjhb	 * Virtual Interfaces with which we've been provisioned.
591305549Sjhb	 */
592305549Sjhb	sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS);
593305549Sjhb
594305549Sjhb	/*
595305549Sjhb	 * We may have been provisioned with more VIs than the number of
596305549Sjhb	 * ports we're allowed to access (our Port Access Rights Mask).
597305549Sjhb	 * Just use a single VI for each port.
598305549Sjhb	 */
599305549Sjhb	sc->params.nports = imin(sc->params.nports,
600305549Sjhb	    bitcount32(sc->params.vfres.pmask));
601305549Sjhb
602305549Sjhb#ifdef notyet
603305549Sjhb	/*
604305549Sjhb	 * XXX: The Linux VF driver will lower nports if it thinks there
605305549Sjhb	 * are too few resources in vfres (niqflint, nethctrl, neq).
606305549Sjhb	 */
607305549Sjhb#endif
608305549Sjhb
609305549Sjhb	/*
610305549Sjhb	 * First pass over all the ports - allocate VIs and initialize some
611330307Snp	 * basic parameters like mac address, port type, etc.
612305549Sjhb	 */
613305549Sjhb	for_each_port(sc, i) {
614305549Sjhb		struct port_info *pi;
615305549Sjhb
616305549Sjhb		pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
617305549Sjhb		sc->port[i] = pi;
618305549Sjhb
619305549Sjhb		/* These must be set before t4_port_init */
620305549Sjhb		pi->adapter = sc;
621305549Sjhb		pi->port_id = i;
622305549Sjhb		pi->nvi = 1;
623305549Sjhb		pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE,
624305549Sjhb		    M_ZERO | M_WAITOK);
625305549Sjhb
626305549Sjhb		/*
627305549Sjhb		 * Allocate the "main" VI and initialize parameters
628305549Sjhb		 * like mac addr.
629305549Sjhb		 */
630305549Sjhb		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
631305549Sjhb		if (rc != 0) {
632305549Sjhb			device_printf(dev, "unable to initialize port %d: %d\n",
633305549Sjhb			    i, rc);
634305549Sjhb			free(pi->vi, M_CXGBE);
635305549Sjhb			free(pi, M_CXGBE);
636305549Sjhb			sc->port[i] = NULL;
637305549Sjhb			goto done;
638305549Sjhb		}
639305549Sjhb
640305549Sjhb		/* No t4_link_start. */
641305549Sjhb
642305549Sjhb		snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
643305549Sjhb		    device_get_nameunit(dev), i);
644305549Sjhb		mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
645305549Sjhb		sc->chan_map[pi->tx_chan] = i;
646305549Sjhb
647346883Snp		/* All VIs on this port share this media. */
648346883Snp		ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
649346883Snp		    cxgbe_media_status);
650346883Snp
651309560Sjhb		pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, -1);
652305549Sjhb		if (pi->dev == NULL) {
653305549Sjhb			device_printf(dev,
654305549Sjhb			    "failed to add device for port %d.\n", i);
655305549Sjhb			rc = ENXIO;
656305549Sjhb			goto done;
657305549Sjhb		}
658305549Sjhb		pi->vi[0].dev = pi->dev;
659305549Sjhb		device_set_softc(pi->dev, pi);
660305549Sjhb	}
661306694Sjhb
662305549Sjhb	/*
663305549Sjhb	 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
664305549Sjhb	 */
665330307Snp	rc = cfg_itype_and_nqueues(sc, &iaq);
666305549Sjhb	if (rc != 0)
667305549Sjhb		goto done; /* error message displayed already */
668305549Sjhb
669305549Sjhb	sc->intr_type = iaq.intr_type;
670305549Sjhb	sc->intr_count = iaq.nirq;
671305549Sjhb
672305549Sjhb	s = &sc->sge;
673330307Snp	s->nrxq = sc->params.nports * iaq.nrxq;
674330307Snp	s->ntxq = sc->params.nports * iaq.ntxq;
675305549Sjhb	s->neq = s->ntxq + s->nrxq;	/* the free list in an rxq is an eq */
676346876Snp	s->neq += sc->params.nports;	/* ctrl queues: 1 per port */
677305549Sjhb	s->niq = s->nrxq + 1;		/* 1 extra for firmware event queue */
678305549Sjhb
679305549Sjhb	s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
680305549Sjhb	    M_ZERO | M_WAITOK);
681305549Sjhb	s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
682305549Sjhb	    M_ZERO | M_WAITOK);
683305549Sjhb	s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
684305549Sjhb	    M_ZERO | M_WAITOK);
685305549Sjhb	s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
686305549Sjhb	    M_ZERO | M_WAITOK);
687305549Sjhb
688305549Sjhb	sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
689305549Sjhb	    M_ZERO | M_WAITOK);
690305549Sjhb
691305549Sjhb	/*
692305549Sjhb	 * Second pass over the ports.  This time we know the number of rx and
693305549Sjhb	 * tx queues that each port should get.
694305549Sjhb	 */
695305549Sjhb	rqidx = tqidx = 0;
696305549Sjhb	for_each_port(sc, i) {
697305549Sjhb		struct port_info *pi = sc->port[i];
698305549Sjhb		struct vi_info *vi;
699305549Sjhb
700305549Sjhb		if (pi == NULL)
701305549Sjhb			continue;
702305549Sjhb
703305549Sjhb		for_each_vi(pi, j, vi) {
704305549Sjhb			vi->pi = pi;
705305549Sjhb			vi->qsize_rxq = t4_qsize_rxq;
706305549Sjhb			vi->qsize_txq = t4_qsize_txq;
707305549Sjhb
708305549Sjhb			vi->first_rxq = rqidx;
709305549Sjhb			vi->first_txq = tqidx;
710330307Snp			vi->tmr_idx = t4_tmr_idx;
711330307Snp			vi->pktc_idx = t4_pktc_idx;
712330307Snp			vi->nrxq = j == 0 ? iaq.nrxq: 1;
713330307Snp			vi->ntxq = j == 0 ? iaq.ntxq: 1;
714330307Snp
715305549Sjhb			rqidx += vi->nrxq;
716305549Sjhb			tqidx += vi->ntxq;
717305549Sjhb
718305549Sjhb			vi->rsrv_noflowq = 0;
719305549Sjhb		}
720305549Sjhb	}
721305549Sjhb
722305549Sjhb	rc = t4_setup_intr_handlers(sc);
723305549Sjhb	if (rc != 0) {
724305549Sjhb		device_printf(dev,
725305549Sjhb		    "failed to setup interrupt handlers: %d\n", rc);
726305549Sjhb		goto done;
727305549Sjhb	}
728305549Sjhb
729305549Sjhb	rc = bus_generic_attach(dev);
730305549Sjhb	if (rc != 0) {
731305549Sjhb		device_printf(dev,
732305549Sjhb		    "failed to attach all child ports: %d\n", rc);
733305549Sjhb		goto done;
734305549Sjhb	}
735305549Sjhb
736305549Sjhb	device_printf(dev,
737305549Sjhb	    "%d ports, %d %s interrupt%s, %d eq, %d iq\n",
738305549Sjhb	    sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ?
739305549Sjhb	    "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq,
740305549Sjhb	    sc->sge.niq);
741305549Sjhb
742305549Sjhbdone:
743305549Sjhb	if (rc != 0)
744305549Sjhb		t4_detach_common(dev);
745305549Sjhb	else
746305549Sjhb		t4_sysctls(sc);
747305549Sjhb
748305549Sjhb	return (rc);
749305549Sjhb}
750305549Sjhb
751305549Sjhbstatic void
752305549Sjhbget_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
753305549Sjhb{
754305549Sjhb
755305549Sjhb	/* 0x3f is used as the revision for VFs. */
756305549Sjhb	regs->version = chip_id(sc) | (0x3f << 10);
757305549Sjhb	t4_get_regs(sc, buf, regs->len);
758305549Sjhb}
759305549Sjhb
760305549Sjhbstatic void
761305549Sjhbt4_clr_vi_stats(struct adapter *sc)
762305549Sjhb{
763305549Sjhb	int reg;
764305549Sjhb
765305549Sjhb	for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
766305549Sjhb	     reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
767305549Sjhb		t4_write_reg(sc, VF_MPS_REG(reg), 0);
768305549Sjhb}
769305549Sjhb
770305549Sjhbstatic int
771305549Sjhbt4vf_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
772305549Sjhb    struct thread *td)
773305549Sjhb{
774305549Sjhb	int rc;
775305549Sjhb	struct adapter *sc = dev->si_drv1;
776305549Sjhb
777305549Sjhb	rc = priv_check(td, PRIV_DRIVER);
778305549Sjhb	if (rc != 0)
779305549Sjhb		return (rc);
780305549Sjhb
781305549Sjhb	switch (cmd) {
782305549Sjhb	case CHELSIO_T4_GETREG: {
783305549Sjhb		struct t4_reg *edata = (struct t4_reg *)data;
784305549Sjhb
785305549Sjhb		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
786305549Sjhb			return (EFAULT);
787305549Sjhb
788305549Sjhb		if (edata->size == 4)
789305549Sjhb			edata->val = t4_read_reg(sc, edata->addr);
790305549Sjhb		else if (edata->size == 8)
791305549Sjhb			edata->val = t4_read_reg64(sc, edata->addr);
792305549Sjhb		else
793305549Sjhb			return (EINVAL);
794305549Sjhb
795305549Sjhb		break;
796305549Sjhb	}
797305549Sjhb	case CHELSIO_T4_SETREG: {
798305549Sjhb		struct t4_reg *edata = (struct t4_reg *)data;
799305549Sjhb
800305549Sjhb		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
801305549Sjhb			return (EFAULT);
802305549Sjhb
803305549Sjhb		if (edata->size == 4) {
804305549Sjhb			if (edata->val & 0xffffffff00000000)
805305549Sjhb				return (EINVAL);
806305549Sjhb			t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
807305549Sjhb		} else if (edata->size == 8)
808305549Sjhb			t4_write_reg64(sc, edata->addr, edata->val);
809305549Sjhb		else
810305549Sjhb			return (EINVAL);
811305549Sjhb		break;
812305549Sjhb	}
813305549Sjhb	case CHELSIO_T4_REGDUMP: {
814305549Sjhb		struct t4_regdump *regs = (struct t4_regdump *)data;
815305549Sjhb		int reglen = t4_get_regs_len(sc);
816305549Sjhb		uint8_t *buf;
817305549Sjhb
818305549Sjhb		if (regs->len < reglen) {
819305549Sjhb			regs->len = reglen; /* hint to the caller */
820305549Sjhb			return (ENOBUFS);
821305549Sjhb		}
822305549Sjhb
823305549Sjhb		regs->len = reglen;
824305549Sjhb		buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
825305549Sjhb		get_regs(sc, regs, buf);
826305549Sjhb		rc = copyout(buf, regs->data, reglen);
827305549Sjhb		free(buf, M_CXGBE);
828305549Sjhb		break;
829305549Sjhb	}
830305549Sjhb	case CHELSIO_T4_CLEAR_STATS: {
831305549Sjhb		int i, v;
832305549Sjhb		u_int port_id = *(uint32_t *)data;
833305549Sjhb		struct port_info *pi;
834305549Sjhb		struct vi_info *vi;
835305549Sjhb
836305549Sjhb		if (port_id >= sc->params.nports)
837305549Sjhb			return (EINVAL);
838305549Sjhb		pi = sc->port[port_id];
839305549Sjhb
840305549Sjhb		/* MAC stats */
841305549Sjhb		pi->tx_parse_error = 0;
842305549Sjhb		t4_clr_vi_stats(sc);
843305549Sjhb
844305549Sjhb		/*
845305549Sjhb		 * Since this command accepts a port, clear stats for
846305549Sjhb		 * all VIs on this port.
847305549Sjhb		 */
848305549Sjhb		for_each_vi(pi, v, vi) {
849305549Sjhb			if (vi->flags & VI_INIT_DONE) {
850305549Sjhb				struct sge_rxq *rxq;
851305549Sjhb				struct sge_txq *txq;
852305549Sjhb
853305549Sjhb				for_each_rxq(vi, i, rxq) {
854305549Sjhb#if defined(INET) || defined(INET6)
855305549Sjhb					rxq->lro.lro_queued = 0;
856305549Sjhb					rxq->lro.lro_flushed = 0;
857305549Sjhb#endif
858305549Sjhb					rxq->rxcsum = 0;
859305549Sjhb					rxq->vlan_extraction = 0;
860305549Sjhb				}
861305549Sjhb
862305549Sjhb				for_each_txq(vi, i, txq) {
863305549Sjhb					txq->txcsum = 0;
864305549Sjhb					txq->tso_wrs = 0;
865305549Sjhb					txq->vlan_insertion = 0;
866305549Sjhb					txq->imm_wrs = 0;
867305549Sjhb					txq->sgl_wrs = 0;
868305549Sjhb					txq->txpkt_wrs = 0;
869305549Sjhb					txq->txpkts0_wrs = 0;
870305549Sjhb					txq->txpkts1_wrs = 0;
871305549Sjhb					txq->txpkts0_pkts = 0;
872305549Sjhb					txq->txpkts1_pkts = 0;
873305549Sjhb					mp_ring_reset_stats(txq->r);
874305549Sjhb				}
875305549Sjhb			}
876305549Sjhb		}
877305549Sjhb		break;
878305549Sjhb	}
879305549Sjhb	case CHELSIO_T4_SCHED_CLASS:
880305549Sjhb		rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
881305549Sjhb		break;
882305549Sjhb	case CHELSIO_T4_SCHED_QUEUE:
883305549Sjhb		rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
884305549Sjhb		break;
885305549Sjhb	default:
886305549Sjhb		rc = ENOTTY;
887305549Sjhb	}
888305549Sjhb
889305549Sjhb	return (rc);
890305549Sjhb}
891305549Sjhb
892305549Sjhbstatic device_method_t t4vf_methods[] = {
893305549Sjhb	DEVMETHOD(device_probe,		t4vf_probe),
894305549Sjhb	DEVMETHOD(device_attach,	t4vf_attach),
895305549Sjhb	DEVMETHOD(device_detach,	t4_detach_common),
896305549Sjhb
897305549Sjhb	DEVMETHOD_END
898305549Sjhb};
899305549Sjhb
900305549Sjhbstatic driver_t t4vf_driver = {
901305549Sjhb	"t4vf",
902305549Sjhb	t4vf_methods,
903305549Sjhb	sizeof(struct adapter)
904305549Sjhb};
905305549Sjhb
906305549Sjhbstatic device_method_t t5vf_methods[] = {
907305549Sjhb	DEVMETHOD(device_probe,		t5vf_probe),
908305549Sjhb	DEVMETHOD(device_attach,	t4vf_attach),
909305549Sjhb	DEVMETHOD(device_detach,	t4_detach_common),
910305549Sjhb
911305549Sjhb	DEVMETHOD_END
912305549Sjhb};
913305549Sjhb
914305549Sjhbstatic driver_t t5vf_driver = {
915305549Sjhb	"t5vf",
916305549Sjhb	t5vf_methods,
917305549Sjhb	sizeof(struct adapter)
918305549Sjhb};
919305549Sjhb
920309560Sjhbstatic device_method_t t6vf_methods[] = {
921309560Sjhb	DEVMETHOD(device_probe,		t6vf_probe),
922309560Sjhb	DEVMETHOD(device_attach,	t4vf_attach),
923309560Sjhb	DEVMETHOD(device_detach,	t4_detach_common),
924309560Sjhb
925309560Sjhb	DEVMETHOD_END
926309560Sjhb};
927309560Sjhb
928309560Sjhbstatic driver_t t6vf_driver = {
929309560Sjhb	"t6vf",
930309560Sjhb	t6vf_methods,
931309560Sjhb	sizeof(struct adapter)
932309560Sjhb};
933309560Sjhb
934305549Sjhbstatic driver_t cxgbev_driver = {
935305549Sjhb	"cxgbev",
936305549Sjhb	cxgbe_methods,
937305549Sjhb	sizeof(struct port_info)
938305549Sjhb};
939305549Sjhb
940305549Sjhbstatic driver_t cxlv_driver = {
941305549Sjhb	"cxlv",
942305549Sjhb	cxgbe_methods,
943305549Sjhb	sizeof(struct port_info)
944305549Sjhb};
945305549Sjhb
946309560Sjhbstatic driver_t ccv_driver = {
947309560Sjhb	"ccv",
948309560Sjhb	cxgbe_methods,
949309560Sjhb	sizeof(struct port_info)
950309560Sjhb};
951305549Sjhb
952309560Sjhbstatic devclass_t t4vf_devclass, t5vf_devclass, t6vf_devclass;
953309560Sjhbstatic devclass_t cxgbev_devclass, cxlv_devclass, ccv_devclass;
954309560Sjhb
955305549SjhbDRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0);
956305549SjhbMODULE_VERSION(t4vf, 1);
957305549SjhbMODULE_DEPEND(t4vf, t4nex, 1, 1, 1);
958305549Sjhb
959305549SjhbDRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0);
960305549SjhbMODULE_VERSION(t5vf, 1);
961305549SjhbMODULE_DEPEND(t5vf, t5nex, 1, 1, 1);
962305549Sjhb
963309560SjhbDRIVER_MODULE(t6vf, pci, t6vf_driver, t6vf_devclass, 0, 0);
964309560SjhbMODULE_VERSION(t6vf, 1);
965309560SjhbMODULE_DEPEND(t6vf, t6nex, 1, 1, 1);
966309560Sjhb
967305549SjhbDRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0);
968305549SjhbMODULE_VERSION(cxgbev, 1);
969305549Sjhb
970305549SjhbDRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0);
971305549SjhbMODULE_VERSION(cxlv, 1);
972309560Sjhb
973309560SjhbDRIVER_MODULE(ccv, t6vf, ccv_driver, ccv_devclass, 0, 0);
974309560SjhbMODULE_VERSION(ccv, 1);
975