t4_sge.c revision 269413
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/cxgbe/t4_sge.c 269413 2014-08-02 01:48:25Z np $"); 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#include <sys/types.h> 35#include <sys/eventhandler.h> 36#include <sys/mbuf.h> 37#include <sys/socket.h> 38#include <sys/kernel.h> 39#include <sys/kdb.h> 40#include <sys/malloc.h> 41#include <sys/queue.h> 42#include <sys/sbuf.h> 43#include <sys/taskqueue.h> 44#include <sys/time.h> 45#include <sys/sysctl.h> 46#include <sys/smp.h> 47#include <sys/counter.h> 48#include <net/bpf.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_vlan_var.h> 52#include <netinet/in.h> 53#include <netinet/ip.h> 54#include <netinet/ip6.h> 55#include <netinet/tcp.h> 56#include <machine/md_var.h> 57#include <vm/vm.h> 58#include <vm/pmap.h> 59#ifdef DEV_NETMAP 60#include <machine/bus.h> 61#include <sys/selinfo.h> 62#include <net/if_var.h> 63#include <net/netmap.h> 64#include <dev/netmap/netmap_kern.h> 65#endif 66 67#include "common/common.h" 68#include "common/t4_regs.h" 69#include "common/t4_regs_values.h" 70#include "common/t4_msg.h" 71 72#ifdef T4_PKT_TIMESTAMP 73#define RX_COPY_THRESHOLD (MINCLSIZE - 8) 74#else 75#define RX_COPY_THRESHOLD MINCLSIZE 76#endif 77 78/* 79 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 80 * 0-7 are valid values. 81 */ 82int fl_pktshift = 2; 83TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 84 85/* 86 * Pad ethernet payload up to this boundary. 87 * -1: driver should figure out a good value. 88 * 0: disable padding. 89 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 90 */ 91int fl_pad = -1; 92TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 93 94/* 95 * Status page length. 96 * -1: driver should figure out a good value. 97 * 64 or 128 are the only other valid values. 98 */ 99int spg_len = -1; 100TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 101 102/* 103 * Congestion drops. 104 * -1: no congestion feedback (not recommended). 105 * 0: backpressure the channel instead of dropping packets right away. 106 * 1: no backpressure, drop packets for the congested queue immediately. 107 */ 108static int cong_drop = 0; 109TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 110 111/* 112 * Deliver multiple frames in the same free list buffer if they fit. 113 * -1: let the driver decide whether to enable buffer packing or not. 114 * 0: disable buffer packing. 115 * 1: enable buffer packing. 116 */ 117static int buffer_packing = -1; 118TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 119 120/* 121 * Start next frame in a packed buffer at this boundary. 122 * -1: driver should figure out a good value. 123 * T4: 124 * --- 125 * if fl_pad != 0 126 * value specified here will be overridden by fl_pad. 127 * else 128 * power of 2 from 32 to 4096 (both inclusive) is a valid value here. 129 * T5: 130 * --- 131 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 132 */ 133static int fl_pack = -1; 134static int t4_fl_pack; 135static int t5_fl_pack; 136TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 137 138/* 139 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 140 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 141 * 1: ok to create mbuf(s) within a cluster if there is room. 142 */ 143static int allow_mbufs_in_cluster = 1; 144TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 145 146/* 147 * Largest rx cluster size that the driver is allowed to allocate. 148 */ 149static int largest_rx_cluster = MJUM16BYTES; 150TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 151 152/* 153 * Size of cluster allocation that's most likely to succeed. The driver will 154 * fall back to this size if it fails to allocate clusters larger than this. 155 */ 156static int safest_rx_cluster = PAGE_SIZE; 157TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 158 159/* Used to track coalesced tx work request */ 160struct txpkts { 161 uint64_t *flitp; /* ptr to flit where next pkt should start */ 162 uint8_t npkt; /* # of packets in this work request */ 163 uint8_t nflits; /* # of flits used by this work request */ 164 uint16_t plen; /* total payload (sum of all packets) */ 165}; 166 167/* A packet's SGL. This + m_pkthdr has all info needed for tx */ 168struct sgl { 169 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 170 int nflits; /* # of flits needed for the SGL */ 171 bus_dma_segment_t seg[TX_SGL_SEGS]; 172}; 173 174static int service_iq(struct sge_iq *, int); 175static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 176 int *); 177static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 178static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int); 179static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int, 180 char *); 181static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 182 char *); 183static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 184 bus_addr_t *, void **); 185static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 186 void *); 187static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 188 int, int); 189static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 190static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 191 struct sge_fl *); 192static int alloc_fwq(struct adapter *); 193static int free_fwq(struct adapter *); 194static int alloc_mgmtq(struct adapter *); 195static int free_mgmtq(struct adapter *); 196static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 197 struct sysctl_oid *); 198static int free_rxq(struct port_info *, struct sge_rxq *); 199#ifdef TCP_OFFLOAD 200static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 201 struct sysctl_oid *); 202static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 203#endif 204#ifdef DEV_NETMAP 205static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int, 206 struct sysctl_oid *); 207static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *); 208static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int, 209 struct sysctl_oid *); 210static int free_nm_txq(struct port_info *, struct sge_nm_txq *); 211#endif 212static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 213static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 214#ifdef TCP_OFFLOAD 215static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 216#endif 217static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 218static int free_eq(struct adapter *, struct sge_eq *); 219static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 220 struct sysctl_oid *); 221static int free_wrq(struct adapter *, struct sge_wrq *); 222static int alloc_txq(struct port_info *, struct sge_txq *, int, 223 struct sysctl_oid *); 224static int free_txq(struct port_info *, struct sge_txq *); 225static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 226static inline void ring_fl_db(struct adapter *, struct sge_fl *); 227static int refill_fl(struct adapter *, struct sge_fl *, int); 228static void refill_sfl(void *); 229static int alloc_fl_sdesc(struct sge_fl *); 230static void free_fl_sdesc(struct adapter *, struct sge_fl *); 231static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 232static void find_safe_refill_source(struct adapter *, struct sge_fl *); 233static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 234 235static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 236static int free_pkt_sgl(struct sge_txq *, struct sgl *); 237static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 238 struct sgl *); 239static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 240 struct mbuf *, struct sgl *); 241static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 242static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 243 struct txpkts *, struct mbuf *, struct sgl *); 244static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 245static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 246static inline void ring_eq_db(struct adapter *, struct sge_eq *); 247static inline int reclaimable(struct sge_eq *); 248static int reclaim_tx_descs(struct sge_txq *, int, int); 249static void write_eqflush_wr(struct sge_eq *); 250static __be64 get_flit(bus_dma_segment_t *, int, int); 251static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 252 struct mbuf *); 253static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 254 struct mbuf *); 255 256static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 257static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 258 259static counter_u64_t extfree_refs; 260static counter_u64_t extfree_rels; 261 262/* 263 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 264 */ 265void 266t4_sge_modload(void) 267{ 268 int pad; 269 270 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */ 271#if defined(__i386__) || defined(__amd64__) 272 pad = max(cpu_clflush_line_size, 16); 273#else 274 pad = max(CACHE_LINE_SIZE, 16); 275#endif 276 pad = min(pad, 4096); 277 278 if (fl_pktshift < 0 || fl_pktshift > 7) { 279 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 280 " using 2 instead.\n", fl_pktshift); 281 fl_pktshift = 2; 282 } 283 284 if (fl_pad != 0 && 285 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) { 286 287 if (fl_pad != -1) { 288 printf("Invalid hw.cxgbe.fl_pad value (%d)," 289 " using %d instead.\n", fl_pad, max(pad, 32)); 290 } 291 fl_pad = max(pad, 32); 292 } 293 294 /* 295 * T4 has the same pad and pack boundary. If a pad boundary is set, 296 * pack boundary must be set to the same value. Otherwise take the 297 * specified value or auto-calculate something reasonable. 298 */ 299 if (fl_pad) 300 t4_fl_pack = fl_pad; 301 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack)) 302 t4_fl_pack = max(pad, 32); 303 else 304 t4_fl_pack = fl_pack; 305 306 /* T5's pack boundary is independent of the pad boundary. */ 307 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 308 !powerof2(fl_pack)) 309 t5_fl_pack = max(pad, CACHE_LINE_SIZE); 310 else 311 t5_fl_pack = fl_pack; 312 313 if (spg_len != 64 && spg_len != 128) { 314 int len; 315 316#if defined(__i386__) || defined(__amd64__) 317 len = cpu_clflush_line_size > 64 ? 128 : 64; 318#else 319 len = 64; 320#endif 321 if (spg_len != -1) { 322 printf("Invalid hw.cxgbe.spg_len value (%d)," 323 " using %d instead.\n", spg_len, len); 324 } 325 spg_len = len; 326 } 327 328 if (cong_drop < -1 || cong_drop > 1) { 329 printf("Invalid hw.cxgbe.cong_drop value (%d)," 330 " using 0 instead.\n", cong_drop); 331 cong_drop = 0; 332 } 333 334 extfree_refs = counter_u64_alloc(M_WAITOK); 335 extfree_rels = counter_u64_alloc(M_WAITOK); 336 counter_u64_zero(extfree_refs); 337 counter_u64_zero(extfree_rels); 338} 339 340void 341t4_sge_modunload(void) 342{ 343 344 counter_u64_free(extfree_refs); 345 counter_u64_free(extfree_rels); 346} 347 348uint64_t 349t4_sge_extfree_refs(void) 350{ 351 uint64_t refs, rels; 352 353 rels = counter_u64_fetch(extfree_rels); 354 refs = counter_u64_fetch(extfree_refs); 355 356 return (refs - rels); 357} 358 359void 360t4_init_sge_cpl_handlers(struct adapter *sc) 361{ 362 363 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 364 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 365 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 366 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 367 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 368} 369 370/* 371 * adap->params.vpd.cclk must be set up before this is called. 372 */ 373void 374t4_tweak_chip_settings(struct adapter *sc) 375{ 376 int i; 377 uint32_t v, m; 378 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 379 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 380 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 381 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 382 static int sge_flbuf_sizes[] = { 383 MCLBYTES, 384#if MJUMPAGESIZE != MCLBYTES 385 MJUMPAGESIZE, 386 MJUMPAGESIZE - CL_METADATA_SIZE, 387 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 388#endif 389 MJUM9BYTES, 390 MJUM16BYTES, 391 MCLBYTES - MSIZE - CL_METADATA_SIZE, 392 MJUM9BYTES - CL_METADATA_SIZE, 393 MJUM16BYTES - CL_METADATA_SIZE, 394 }; 395 396 KASSERT(sc->flags & MASTER_PF, 397 ("%s: trying to change chip settings when not master.", __func__)); 398 399 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 400 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 401 V_EGRSTATUSPAGESIZE(spg_len == 128); 402 if (is_t4(sc) && (fl_pad || buffer_packing)) { 403 /* t4_fl_pack has the correct value even when fl_pad = 0 */ 404 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 405 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 406 } else if (is_t5(sc) && fl_pad) { 407 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 408 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 409 } 410 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 411 412 if (is_t5(sc) && buffer_packing) { 413 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 414 if (t5_fl_pack == 16) 415 v = V_INGPACKBOUNDARY(0); 416 else 417 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 418 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 419 } 420 421 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 422 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 423 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 424 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 425 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 426 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 427 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 428 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 429 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 430 431 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 432 ("%s: hw buffer size table too big", __func__)); 433 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 434 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 435 sge_flbuf_sizes[i]); 436 } 437 438 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 439 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 440 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 441 442 KASSERT(intr_timer[0] <= timer_max, 443 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 444 timer_max)); 445 for (i = 1; i < nitems(intr_timer); i++) { 446 KASSERT(intr_timer[i] >= intr_timer[i - 1], 447 ("%s: timers not listed in increasing order (%d)", 448 __func__, i)); 449 450 while (intr_timer[i] > timer_max) { 451 if (i == nitems(intr_timer) - 1) { 452 intr_timer[i] = timer_max; 453 break; 454 } 455 intr_timer[i] += intr_timer[i - 1]; 456 intr_timer[i] /= 2; 457 } 458 } 459 460 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 461 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 462 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 463 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 464 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 465 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 466 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 467 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 468 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 469 470 if (cong_drop == 0) { 471 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 472 F_TUNNELCNGDROP3; 473 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 474 } 475 476 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 477 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 478 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 479 480 m = v = F_TDDPTAGTCB; 481 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 482 483 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 484 F_RESETDDPOFFSET; 485 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 486 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 487} 488 489/* 490 * SGE wants the buffer to be at least 64B and then a multiple of the pad 491 * boundary or 16, whichever is greater. 492 */ 493static inline int 494hwsz_ok(int hwsz) 495{ 496 int mask = max(fl_pad, 16) - 1; 497 498 return (hwsz >= 64 && (hwsz & mask) == 0); 499} 500 501/* 502 * XXX: driver really should be able to deal with unexpected settings. 503 */ 504int 505t4_read_chip_settings(struct adapter *sc) 506{ 507 struct sge *s = &sc->sge; 508 int i, j, n, rc = 0; 509 uint32_t m, v, r; 510 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 511 static int sw_buf_sizes[] = { /* Sorted by size */ 512 MCLBYTES, 513#if MJUMPAGESIZE != MCLBYTES 514 MJUMPAGESIZE, 515#endif 516 MJUM9BYTES, 517 MJUM16BYTES 518 }; 519 struct sw_zone_info *swz, *safe_swz; 520 struct hw_buf_info *hwb; 521 522 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 523 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 524 V_EGRSTATUSPAGESIZE(spg_len == 128); 525 if (is_t4(sc) && (fl_pad || buffer_packing)) { 526 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 527 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 528 } else if (is_t5(sc) && fl_pad) { 529 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 530 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 531 } 532 r = t4_read_reg(sc, A_SGE_CONTROL); 533 if ((r & m) != v) { 534 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 535 rc = EINVAL; 536 } 537 538 if (is_t5(sc) && buffer_packing) { 539 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 540 if (t5_fl_pack == 16) 541 v = V_INGPACKBOUNDARY(0); 542 else 543 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 544 r = t4_read_reg(sc, A_SGE_CONTROL2); 545 if ((r & m) != v) { 546 device_printf(sc->dev, 547 "invalid SGE_CONTROL2(0x%x)\n", r); 548 rc = EINVAL; 549 } 550 } 551 s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack; 552 553 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 554 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 555 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 556 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 557 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 558 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 559 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 560 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 561 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 562 if (r != v) { 563 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 564 rc = EINVAL; 565 } 566 567 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 568 hwb = &s->hw_buf_info[0]; 569 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 570 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 571 hwb->size = r; 572 hwb->zidx = hwsz_ok(r) ? -1 : -2; 573 hwb->next = -1; 574 } 575 576 /* 577 * Create a sorted list in decreasing order of hw buffer sizes (and so 578 * increasing order of spare area) for each software zone. 579 */ 580 n = 0; /* no usable buffer size to begin with */ 581 swz = &s->sw_zone_info[0]; 582 safe_swz = NULL; 583 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 584 int8_t head = -1, tail = -1; 585 586 swz->size = sw_buf_sizes[i]; 587 swz->zone = m_getzone(swz->size); 588 swz->type = m_gettype(swz->size); 589 590 if (swz->size == safest_rx_cluster) 591 safe_swz = swz; 592 593 hwb = &s->hw_buf_info[0]; 594 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 595 if (hwb->zidx != -1 || hwb->size > swz->size) 596 continue; 597 hwb->zidx = i; 598 if (head == -1) 599 head = tail = j; 600 else if (hwb->size < s->hw_buf_info[tail].size) { 601 s->hw_buf_info[tail].next = j; 602 tail = j; 603 } else { 604 int8_t *cur; 605 struct hw_buf_info *t; 606 607 for (cur = &head; *cur != -1; cur = &t->next) { 608 t = &s->hw_buf_info[*cur]; 609 if (hwb->size == t->size) { 610 hwb->zidx = -2; 611 break; 612 } 613 if (hwb->size > t->size) { 614 hwb->next = *cur; 615 *cur = j; 616 break; 617 } 618 } 619 } 620 } 621 swz->head_hwidx = head; 622 swz->tail_hwidx = tail; 623 624 if (tail != -1) { 625 n++; 626 if (swz->size - s->hw_buf_info[tail].size >= 627 CL_METADATA_SIZE) 628 sc->flags |= BUF_PACKING_OK; 629 } 630 } 631 if (n == 0) { 632 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 633 rc = EINVAL; 634 } 635 636 s->safe_hwidx1 = -1; 637 s->safe_hwidx2 = -1; 638 if (safe_swz != NULL) { 639 s->safe_hwidx1 = safe_swz->head_hwidx; 640 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 641 int spare; 642 643 hwb = &s->hw_buf_info[i]; 644 spare = safe_swz->size - hwb->size; 645 if (spare < CL_METADATA_SIZE) 646 continue; 647 if (s->safe_hwidx2 == -1 || 648 spare == CL_METADATA_SIZE + MSIZE) 649 s->safe_hwidx2 = i; 650 if (spare >= CL_METADATA_SIZE + MSIZE) 651 break; 652 } 653 } 654 655 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 656 s->counter_val[0] = G_THRESHOLD_0(r); 657 s->counter_val[1] = G_THRESHOLD_1(r); 658 s->counter_val[2] = G_THRESHOLD_2(r); 659 s->counter_val[3] = G_THRESHOLD_3(r); 660 661 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 662 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 663 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 664 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 665 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 666 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 667 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 668 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 669 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 670 671 if (cong_drop == 0) { 672 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 673 F_TUNNELCNGDROP3; 674 r = t4_read_reg(sc, A_TP_PARA_REG3); 675 if (r & m) { 676 device_printf(sc->dev, 677 "invalid TP_PARA_REG3(0x%x)\n", r); 678 rc = EINVAL; 679 } 680 } 681 682 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 683 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 684 if (r != v) { 685 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 686 rc = EINVAL; 687 } 688 689 m = v = F_TDDPTAGTCB; 690 r = t4_read_reg(sc, A_ULP_RX_CTL); 691 if ((r & m) != v) { 692 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 693 rc = EINVAL; 694 } 695 696 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 697 F_RESETDDPOFFSET; 698 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 699 r = t4_read_reg(sc, A_TP_PARA_REG5); 700 if ((r & m) != v) { 701 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 702 rc = EINVAL; 703 } 704 705 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 706 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 707 if (is_t4(sc)) 708 s->fl_starve_threshold2 = s->fl_starve_threshold; 709 else 710 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 711 712 /* egress queues: log2 of # of doorbells per BAR2 page */ 713 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 714 r >>= S_QUEUESPERPAGEPF0 + 715 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 716 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 717 718 /* ingress queues: log2 of # of doorbells per BAR2 page */ 719 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 720 r >>= S_QUEUESPERPAGEPF0 + 721 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 722 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 723 724 t4_init_tp_params(sc); 725 726 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 727 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 728 729 return (rc); 730} 731 732int 733t4_create_dma_tag(struct adapter *sc) 734{ 735 int rc; 736 737 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 738 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 739 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 740 NULL, &sc->dmat); 741 if (rc != 0) { 742 device_printf(sc->dev, 743 "failed to create main DMA tag: %d\n", rc); 744 } 745 746 return (rc); 747} 748 749static inline int 750enable_buffer_packing(struct adapter *sc) 751{ 752 753 if (sc->flags & BUF_PACKING_OK && 754 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */ 755 (is_t4(sc) && buffer_packing == 1))) 756 return (1); 757 return (0); 758} 759 760void 761t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 762 struct sysctl_oid_list *children) 763{ 764 765 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 766 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 767 "freelist buffer sizes"); 768 769 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 770 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 771 772 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 773 NULL, fl_pad, "payload pad boundary (bytes)"); 774 775 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 776 NULL, spg_len, "status page size (bytes)"); 777 778 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 779 NULL, cong_drop, "congestion drop setting"); 780 781 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD, 782 NULL, enable_buffer_packing(sc), 783 "pack multiple frames in one fl buffer"); 784 785 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 786 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)"); 787} 788 789int 790t4_destroy_dma_tag(struct adapter *sc) 791{ 792 if (sc->dmat) 793 bus_dma_tag_destroy(sc->dmat); 794 795 return (0); 796} 797 798/* 799 * Allocate and initialize the firmware event queue and the management queue. 800 * 801 * Returns errno on failure. Resources allocated up to that point may still be 802 * allocated. Caller is responsible for cleanup in case this function fails. 803 */ 804int 805t4_setup_adapter_queues(struct adapter *sc) 806{ 807 int rc; 808 809 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 810 811 sysctl_ctx_init(&sc->ctx); 812 sc->flags |= ADAP_SYSCTL_CTX; 813 814 /* 815 * Firmware event queue 816 */ 817 rc = alloc_fwq(sc); 818 if (rc != 0) 819 return (rc); 820 821 /* 822 * Management queue. This is just a control queue that uses the fwq as 823 * its associated iq. 824 */ 825 rc = alloc_mgmtq(sc); 826 827 return (rc); 828} 829 830/* 831 * Idempotent 832 */ 833int 834t4_teardown_adapter_queues(struct adapter *sc) 835{ 836 837 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 838 839 /* Do this before freeing the queue */ 840 if (sc->flags & ADAP_SYSCTL_CTX) { 841 sysctl_ctx_free(&sc->ctx); 842 sc->flags &= ~ADAP_SYSCTL_CTX; 843 } 844 845 free_mgmtq(sc); 846 free_fwq(sc); 847 848 return (0); 849} 850 851static inline int 852port_intr_count(struct port_info *pi) 853{ 854 int rc = 0; 855 856 if (pi->flags & INTR_RXQ) 857 rc += pi->nrxq; 858#ifdef TCP_OFFLOAD 859 if (pi->flags & INTR_OFLD_RXQ) 860 rc += pi->nofldrxq; 861#endif 862#ifdef DEV_NETMAP 863 if (pi->flags & INTR_NM_RXQ) 864 rc += pi->nnmrxq; 865#endif 866 return (rc); 867} 868 869static inline int 870first_vector(struct port_info *pi) 871{ 872 struct adapter *sc = pi->adapter; 873 int rc = T4_EXTRA_INTR, i; 874 875 if (sc->intr_count == 1) 876 return (0); 877 878 for_each_port(sc, i) { 879 if (i == pi->port_id) 880 break; 881 882 rc += port_intr_count(sc->port[i]); 883 } 884 885 return (rc); 886} 887 888/* 889 * Given an arbitrary "index," come up with an iq that can be used by other 890 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 891 * The iq returned is guaranteed to be something that takes direct interrupts. 892 */ 893static struct sge_iq * 894port_intr_iq(struct port_info *pi, int idx) 895{ 896 struct adapter *sc = pi->adapter; 897 struct sge *s = &sc->sge; 898 struct sge_iq *iq = NULL; 899 int nintr, i; 900 901 if (sc->intr_count == 1) 902 return (&sc->sge.fwq); 903 904 nintr = port_intr_count(pi); 905 KASSERT(nintr != 0, 906 ("%s: pi %p has no exclusive interrupts, total interrupts = %d", 907 __func__, pi, sc->intr_count)); 908#ifdef DEV_NETMAP 909 /* Exclude netmap queues as they can't take anyone else's interrupts */ 910 if (pi->flags & INTR_NM_RXQ) 911 nintr -= pi->nnmrxq; 912 KASSERT(nintr > 0, 913 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__, 914 pi, nintr, pi->nnmrxq)); 915#endif 916 i = idx % nintr; 917 918 if (pi->flags & INTR_RXQ) { 919 if (i < pi->nrxq) { 920 iq = &s->rxq[pi->first_rxq + i].iq; 921 goto done; 922 } 923 i -= pi->nrxq; 924 } 925#ifdef TCP_OFFLOAD 926 if (pi->flags & INTR_OFLD_RXQ) { 927 if (i < pi->nofldrxq) { 928 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq; 929 goto done; 930 } 931 i -= pi->nofldrxq; 932 } 933#endif 934 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 935 pi, pi->flags & INTR_ALL, idx, nintr); 936done: 937 MPASS(iq != NULL); 938 KASSERT(iq->flags & IQ_INTR, 939 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi, 940 pi->flags & INTR_ALL, idx)); 941 return (iq); 942} 943 944/* Maximum payload that can be delivered with a single iq descriptor */ 945static inline int 946mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 947{ 948 int payload; 949 950#ifdef TCP_OFFLOAD 951 if (toe) { 952 payload = sc->tt.rx_coalesce ? 953 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 954 } else { 955#endif 956 /* large enough even when hw VLAN extraction is disabled */ 957 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 958 mtu; 959#ifdef TCP_OFFLOAD 960 } 961#endif 962 payload = roundup2(payload, fl_pad); 963 964 return (payload); 965} 966 967int 968t4_setup_port_queues(struct port_info *pi) 969{ 970 int rc = 0, i, j, intr_idx, iqid; 971 struct sge_rxq *rxq; 972 struct sge_txq *txq; 973 struct sge_wrq *ctrlq; 974#ifdef TCP_OFFLOAD 975 struct sge_ofld_rxq *ofld_rxq; 976 struct sge_wrq *ofld_txq; 977#endif 978#ifdef DEV_NETMAP 979 struct sge_nm_rxq *nm_rxq; 980 struct sge_nm_txq *nm_txq; 981#endif 982 char name[16]; 983 struct adapter *sc = pi->adapter; 984 struct ifnet *ifp = pi->ifp; 985 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 986 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 987 int maxp, pack, mtu = ifp->if_mtu; 988 989 /* Interrupt vector to start from (when using multiple vectors) */ 990 intr_idx = first_vector(pi); 991 992 /* 993 * First pass over all NIC and TOE rx queues: 994 * a) initialize iq and fl 995 * b) allocate queue iff it will take direct interrupts. 996 */ 997 maxp = mtu_to_max_payload(sc, mtu, 0); 998 pack = enable_buffer_packing(sc); 999 if (pi->flags & INTR_RXQ) { 1000 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 1001 CTLFLAG_RD, NULL, "rx queues"); 1002 } 1003 for_each_rxq(pi, i, rxq) { 1004 1005 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq); 1006 1007 snprintf(name, sizeof(name), "%s rxq%d-fl", 1008 device_get_nameunit(pi->dev), i); 1009 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 1010 1011 if (pi->flags & INTR_RXQ) { 1012 rxq->iq.flags |= IQ_INTR; 1013 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 1014 if (rc != 0) 1015 goto done; 1016 intr_idx++; 1017 } 1018 } 1019#ifdef TCP_OFFLOAD 1020 maxp = mtu_to_max_payload(sc, mtu, 1); 1021 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) { 1022 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 1023 CTLFLAG_RD, NULL, 1024 "rx queues for offloaded TCP connections"); 1025 } 1026 for_each_ofld_rxq(pi, i, ofld_rxq) { 1027 1028 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 1029 pi->qsize_rxq); 1030 1031 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1032 device_get_nameunit(pi->dev), i); 1033 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 1034 1035 if (pi->flags & INTR_OFLD_RXQ) { 1036 ofld_rxq->iq.flags |= IQ_INTR; 1037 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1038 if (rc != 0) 1039 goto done; 1040 intr_idx++; 1041 } 1042 } 1043#endif 1044#ifdef DEV_NETMAP 1045 /* 1046 * We don't have buffers to back the netmap rx queues right now so we 1047 * create the queues in a way that doesn't set off any congestion signal 1048 * in the chip. 1049 */ 1050 if (pi->flags & INTR_NM_RXQ) { 1051 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq", 1052 CTLFLAG_RD, NULL, "rx queues for netmap"); 1053 for_each_nm_rxq(pi, i, nm_rxq) { 1054 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid); 1055 if (rc != 0) 1056 goto done; 1057 intr_idx++; 1058 } 1059 } 1060#endif 1061 1062 /* 1063 * Second pass over all NIC and TOE rx queues. The queues forwarding 1064 * their interrupts are allocated now. 1065 */ 1066 j = 0; 1067 if (!(pi->flags & INTR_RXQ)) { 1068 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 1069 CTLFLAG_RD, NULL, "rx queues"); 1070 for_each_rxq(pi, i, rxq) { 1071 MPASS(!(rxq->iq.flags & IQ_INTR)); 1072 1073 intr_idx = port_intr_iq(pi, j)->abs_id; 1074 1075 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 1076 if (rc != 0) 1077 goto done; 1078 j++; 1079 } 1080 } 1081#ifdef TCP_OFFLOAD 1082 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) { 1083 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 1084 CTLFLAG_RD, NULL, 1085 "rx queues for offloaded TCP connections"); 1086 for_each_ofld_rxq(pi, i, ofld_rxq) { 1087 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1088 1089 intr_idx = port_intr_iq(pi, j)->abs_id; 1090 1091 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1092 if (rc != 0) 1093 goto done; 1094 j++; 1095 } 1096 } 1097#endif 1098#ifdef DEV_NETMAP 1099 if (!(pi->flags & INTR_NM_RXQ)) 1100 CXGBE_UNIMPLEMENTED(__func__); 1101#endif 1102 1103 /* 1104 * Now the tx queues. Only one pass needed. 1105 */ 1106 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1107 NULL, "tx queues"); 1108 j = 0; 1109 for_each_txq(pi, i, txq) { 1110 iqid = port_intr_iq(pi, j)->cntxt_id; 1111 snprintf(name, sizeof(name), "%s txq%d", 1112 device_get_nameunit(pi->dev), i); 1113 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 1114 name); 1115 1116 rc = alloc_txq(pi, txq, i, oid); 1117 if (rc != 0) 1118 goto done; 1119 j++; 1120 } 1121#ifdef TCP_OFFLOAD 1122 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 1123 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1124 for_each_ofld_txq(pi, i, ofld_txq) { 1125 struct sysctl_oid *oid2; 1126 1127 iqid = port_intr_iq(pi, j)->cntxt_id; 1128 snprintf(name, sizeof(name), "%s ofld_txq%d", 1129 device_get_nameunit(pi->dev), i); 1130 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 1131 iqid, name); 1132 1133 snprintf(name, sizeof(name), "%d", i); 1134 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1135 name, CTLFLAG_RD, NULL, "offload tx queue"); 1136 1137 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 1138 if (rc != 0) 1139 goto done; 1140 j++; 1141 } 1142#endif 1143#ifdef DEV_NETMAP 1144 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq", 1145 CTLFLAG_RD, NULL, "tx queues for netmap use"); 1146 for_each_nm_txq(pi, i, nm_txq) { 1147 iqid = pi->first_nm_rxq + (j % pi->nnmrxq); 1148 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid); 1149 if (rc != 0) 1150 goto done; 1151 j++; 1152 } 1153#endif 1154 1155 /* 1156 * Finally, the control queue. 1157 */ 1158 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1159 NULL, "ctrl queue"); 1160 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1161 iqid = port_intr_iq(pi, 0)->cntxt_id; 1162 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 1163 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 1164 rc = alloc_wrq(sc, pi, ctrlq, oid); 1165 1166done: 1167 if (rc) 1168 t4_teardown_port_queues(pi); 1169 1170 return (rc); 1171} 1172 1173/* 1174 * Idempotent 1175 */ 1176int 1177t4_teardown_port_queues(struct port_info *pi) 1178{ 1179 int i; 1180 struct adapter *sc = pi->adapter; 1181 struct sge_rxq *rxq; 1182 struct sge_txq *txq; 1183#ifdef TCP_OFFLOAD 1184 struct sge_ofld_rxq *ofld_rxq; 1185 struct sge_wrq *ofld_txq; 1186#endif 1187#ifdef DEV_NETMAP 1188 struct sge_nm_rxq *nm_rxq; 1189 struct sge_nm_txq *nm_txq; 1190#endif 1191 1192 /* Do this before freeing the queues */ 1193 if (pi->flags & PORT_SYSCTL_CTX) { 1194 sysctl_ctx_free(&pi->ctx); 1195 pi->flags &= ~PORT_SYSCTL_CTX; 1196 } 1197 1198 /* 1199 * Take down all the tx queues first, as they reference the rx queues 1200 * (for egress updates, etc.). 1201 */ 1202 1203 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1204 1205 for_each_txq(pi, i, txq) { 1206 free_txq(pi, txq); 1207 } 1208#ifdef TCP_OFFLOAD 1209 for_each_ofld_txq(pi, i, ofld_txq) { 1210 free_wrq(sc, ofld_txq); 1211 } 1212#endif 1213#ifdef DEV_NETMAP 1214 for_each_nm_txq(pi, i, nm_txq) 1215 free_nm_txq(pi, nm_txq); 1216#endif 1217 1218 /* 1219 * Then take down the rx queues that forward their interrupts, as they 1220 * reference other rx queues. 1221 */ 1222 1223 for_each_rxq(pi, i, rxq) { 1224 if ((rxq->iq.flags & IQ_INTR) == 0) 1225 free_rxq(pi, rxq); 1226 } 1227#ifdef TCP_OFFLOAD 1228 for_each_ofld_rxq(pi, i, ofld_rxq) { 1229 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1230 free_ofld_rxq(pi, ofld_rxq); 1231 } 1232#endif 1233#ifdef DEV_NETMAP 1234 for_each_nm_rxq(pi, i, nm_rxq) 1235 free_nm_rxq(pi, nm_rxq); 1236#endif 1237 1238 /* 1239 * Then take down the rx queues that take direct interrupts. 1240 */ 1241 1242 for_each_rxq(pi, i, rxq) { 1243 if (rxq->iq.flags & IQ_INTR) 1244 free_rxq(pi, rxq); 1245 } 1246#ifdef TCP_OFFLOAD 1247 for_each_ofld_rxq(pi, i, ofld_rxq) { 1248 if (ofld_rxq->iq.flags & IQ_INTR) 1249 free_ofld_rxq(pi, ofld_rxq); 1250 } 1251#endif 1252#ifdef DEV_NETMAP 1253 CXGBE_UNIMPLEMENTED(__func__); 1254#endif 1255 1256 return (0); 1257} 1258 1259/* 1260 * Deals with errors and the firmware event queue. All data rx queues forward 1261 * their interrupt to the firmware event queue. 1262 */ 1263void 1264t4_intr_all(void *arg) 1265{ 1266 struct adapter *sc = arg; 1267 struct sge_iq *fwq = &sc->sge.fwq; 1268 1269 t4_intr_err(arg); 1270 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1271 service_iq(fwq, 0); 1272 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1273 } 1274} 1275 1276/* Deals with error interrupts */ 1277void 1278t4_intr_err(void *arg) 1279{ 1280 struct adapter *sc = arg; 1281 1282 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1283 t4_slow_intr_handler(sc); 1284} 1285 1286void 1287t4_intr_evt(void *arg) 1288{ 1289 struct sge_iq *iq = arg; 1290 1291 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1292 service_iq(iq, 0); 1293 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1294 } 1295} 1296 1297void 1298t4_intr(void *arg) 1299{ 1300 struct sge_iq *iq = arg; 1301 1302 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1303 service_iq(iq, 0); 1304 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1305 } 1306} 1307 1308/* 1309 * Deals with anything and everything on the given ingress queue. 1310 */ 1311static int 1312service_iq(struct sge_iq *iq, int budget) 1313{ 1314 struct sge_iq *q; 1315 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1316 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 1317 struct adapter *sc = iq->adapter; 1318 struct iq_desc *d = &iq->desc[iq->cidx]; 1319 int ndescs = 0, limit, fl_bufs_used = 0; 1320 int rsp_type; 1321 uint32_t lq; 1322 struct mbuf *m0; 1323 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1324#if defined(INET) || defined(INET6) 1325 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1326#endif 1327 1328 limit = budget ? budget : iq->qsize / 8; 1329 1330 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1331 1332 /* 1333 * We always come back and check the descriptor ring for new indirect 1334 * interrupts and other responses after running a single handler. 1335 */ 1336 for (;;) { 1337 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) { 1338 1339 rmb(); 1340 1341 m0 = NULL; 1342 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen); 1343 lq = be32toh(d->rsp.pldbuflen_qid); 1344 1345 switch (rsp_type) { 1346 case X_RSPD_TYPE_FLBUF: 1347 1348 KASSERT(iq->flags & IQ_HAS_FL, 1349 ("%s: data for an iq (%p) with no freelist", 1350 __func__, iq)); 1351 1352 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 1353 if (__predict_false(m0 == NULL)) 1354 goto process_iql; 1355#ifdef T4_PKT_TIMESTAMP 1356 /* 1357 * 60 bit timestamp for the payload is 1358 * *(uint64_t *)m0->m_pktdat. Note that it is 1359 * in the leading free-space in the mbuf. The 1360 * kernel can clobber it during a pullup, 1361 * m_copymdata, etc. You need to make sure that 1362 * the mbuf reaches you unmolested if you care 1363 * about the timestamp. 1364 */ 1365 *(uint64_t *)m0->m_pktdat = 1366 be64toh(ctrl->u.last_flit) & 1367 0xfffffffffffffff; 1368#endif 1369 1370 /* fall through */ 1371 1372 case X_RSPD_TYPE_CPL: 1373 KASSERT(d->rss.opcode < NUM_CPL_CMDS, 1374 ("%s: bad opcode %02x.", __func__, 1375 d->rss.opcode)); 1376 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0); 1377 break; 1378 1379 case X_RSPD_TYPE_INTR: 1380 1381 /* 1382 * Interrupts should be forwarded only to queues 1383 * that are not forwarding their interrupts. 1384 * This means service_iq can recurse but only 1 1385 * level deep. 1386 */ 1387 KASSERT(budget == 0, 1388 ("%s: budget %u, rsp_type %u", __func__, 1389 budget, rsp_type)); 1390 1391 /* 1392 * There are 1K interrupt-capable queues (qids 0 1393 * through 1023). A response type indicating a 1394 * forwarded interrupt with a qid >= 1K is an 1395 * iWARP async notification. 1396 */ 1397 if (lq >= 1024) { 1398 sc->an_handler(iq, &d->rsp); 1399 break; 1400 } 1401 1402 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1403 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1404 IQS_BUSY)) { 1405 if (service_iq(q, q->qsize / 8) == 0) { 1406 atomic_cmpset_int(&q->state, 1407 IQS_BUSY, IQS_IDLE); 1408 } else { 1409 STAILQ_INSERT_TAIL(&iql, q, 1410 link); 1411 } 1412 } 1413 break; 1414 1415 default: 1416 KASSERT(0, 1417 ("%s: illegal response type %d on iq %p", 1418 __func__, rsp_type, iq)); 1419 log(LOG_ERR, 1420 "%s: illegal response type %d on iq %p", 1421 device_get_nameunit(sc->dev), rsp_type, iq); 1422 break; 1423 } 1424 1425 if (fl_bufs_used >= 16) { 1426 FL_LOCK(fl); 1427 fl->needed += fl_bufs_used; 1428 refill_fl(sc, fl, 32); 1429 FL_UNLOCK(fl); 1430 fl_bufs_used = 0; 1431 } 1432 1433 d++; 1434 if (__predict_false(++iq->cidx == iq->sidx)) { 1435 iq->cidx = 0; 1436 iq->gen ^= F_RSPD_GEN; 1437 d = &iq->desc[0]; 1438 } 1439 if (__predict_false(++ndescs == limit)) { 1440 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1441 V_CIDXINC(ndescs) | 1442 V_INGRESSQID(iq->cntxt_id) | 1443 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1444 ndescs = 0; 1445 1446#if defined(INET) || defined(INET6) 1447 if (iq->flags & IQ_LRO_ENABLED && 1448 sc->lro_timeout != 0) { 1449 tcp_lro_flush_inactive(&rxq->lro, 1450 &lro_timeout); 1451 } 1452#endif 1453 1454 if (budget) { 1455 if (fl_bufs_used) { 1456 FL_LOCK(fl); 1457 fl->needed += fl_bufs_used; 1458 refill_fl(sc, fl, 32); 1459 FL_UNLOCK(fl); 1460 } 1461 return (EINPROGRESS); 1462 } 1463 } 1464 } 1465 1466process_iql: 1467 if (STAILQ_EMPTY(&iql)) 1468 break; 1469 1470 /* 1471 * Process the head only, and send it to the back of the list if 1472 * it's still not done. 1473 */ 1474 q = STAILQ_FIRST(&iql); 1475 STAILQ_REMOVE_HEAD(&iql, link); 1476 if (service_iq(q, q->qsize / 8) == 0) 1477 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1478 else 1479 STAILQ_INSERT_TAIL(&iql, q, link); 1480 } 1481 1482#if defined(INET) || defined(INET6) 1483 if (iq->flags & IQ_LRO_ENABLED) { 1484 struct lro_ctrl *lro = &rxq->lro; 1485 struct lro_entry *l; 1486 1487 while (!SLIST_EMPTY(&lro->lro_active)) { 1488 l = SLIST_FIRST(&lro->lro_active); 1489 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1490 tcp_lro_flush(lro, l); 1491 } 1492 } 1493#endif 1494 1495 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1496 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1497 1498 if (iq->flags & IQ_HAS_FL) { 1499 int starved; 1500 1501 FL_LOCK(fl); 1502 fl->needed += fl_bufs_used; 1503 starved = refill_fl(sc, fl, 64); 1504 FL_UNLOCK(fl); 1505 if (__predict_false(starved != 0)) 1506 add_fl_to_sfl(sc, fl); 1507 } 1508 1509 return (0); 1510} 1511 1512static inline int 1513cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1514{ 1515 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1516 1517 if (rc) 1518 MPASS(cll->region3 >= CL_METADATA_SIZE); 1519 1520 return (rc); 1521} 1522 1523static inline struct cluster_metadata * 1524cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1525 caddr_t cl) 1526{ 1527 1528 if (cl_has_metadata(fl, cll)) { 1529 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1530 1531 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1532 } 1533 return (NULL); 1534} 1535 1536static void 1537rxb_free(struct mbuf *m, void *arg1, void *arg2) 1538{ 1539 uma_zone_t zone = arg1; 1540 caddr_t cl = arg2; 1541 1542 uma_zfree(zone, cl); 1543 counter_u64_add(extfree_rels, 1); 1544} 1545 1546/* 1547 * The mbuf returned by this function could be allocated from zone_mbuf or 1548 * constructed in spare room in the cluster. 1549 * 1550 * The mbuf carries the payload in one of these ways 1551 * a) frame inside the mbuf (mbuf from zone_mbuf) 1552 * b) m_cljset (for clusters without metadata) zone_mbuf 1553 * c) m_extaddref (cluster with metadata) inline mbuf 1554 * d) m_extaddref (cluster with metadata) zone_mbuf 1555 */ 1556static struct mbuf * 1557get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags) 1558{ 1559 struct mbuf *m; 1560 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1561 struct cluster_layout *cll = &sd->cll; 1562 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1563 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1564 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1565 int len, padded_len; 1566 caddr_t payload; 1567 1568 len = min(total, hwb->size - fl->rx_offset); 1569 padded_len = roundup2(len, fl_pad); 1570 payload = sd->cl + cll->region1 + fl->rx_offset; 1571 1572 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1573 1574 /* 1575 * Copy payload into a freshly allocated mbuf. 1576 */ 1577 1578 m = flags & M_PKTHDR ? 1579 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1580 if (m == NULL) 1581 return (NULL); 1582 fl->mbuf_allocated++; 1583#ifdef T4_PKT_TIMESTAMP 1584 /* Leave room for a timestamp */ 1585 m->m_data += 8; 1586#endif 1587 /* copy data to mbuf */ 1588 bcopy(payload, mtod(m, caddr_t), len); 1589 1590 } else if (sd->nmbuf * MSIZE < cll->region1) { 1591 1592 /* 1593 * There's spare room in the cluster for an mbuf. Create one 1594 * and associate it with the payload that's in the cluster. 1595 */ 1596 1597 MPASS(clm != NULL); 1598 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE); 1599 /* No bzero required */ 1600 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA, flags | M_NOFREE)) 1601 return (NULL); 1602 fl->mbuf_inlined++; 1603 m_extaddref(m, payload, padded_len, &clm->refcount, rxb_free, 1604 swz->zone, sd->cl); 1605 if (sd->nmbuf++ == 0) 1606 counter_u64_add(extfree_refs, 1); 1607 1608 } else { 1609 1610 /* 1611 * Grab an mbuf from zone_mbuf and associate it with the 1612 * payload in the cluster. 1613 */ 1614 1615 m = flags & M_PKTHDR ? 1616 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1617 if (m == NULL) 1618 return (NULL); 1619 fl->mbuf_allocated++; 1620 if (clm != NULL) { 1621 m_extaddref(m, payload, padded_len, &clm->refcount, 1622 rxb_free, swz->zone, sd->cl); 1623 if (sd->nmbuf++ == 0) 1624 counter_u64_add(extfree_refs, 1); 1625 } else { 1626 m_cljset(m, sd->cl, swz->type); 1627 sd->cl = NULL; /* consumed, not a recycle candidate */ 1628 } 1629 } 1630 if (flags & M_PKTHDR) 1631 m->m_pkthdr.len = total; 1632 m->m_len = len; 1633 1634 if (fl->flags & FL_BUF_PACKING) { 1635 fl->rx_offset += roundup2(padded_len, sc->sge.pack_boundary); 1636 MPASS(fl->rx_offset <= hwb->size); 1637 if (fl->rx_offset < hwb->size) 1638 return (m); /* without advancing the cidx */ 1639 } 1640 1641 if (__predict_false(++fl->cidx == fl->cap)) 1642 fl->cidx = 0; 1643 fl->rx_offset = 0; 1644 1645 return (m); 1646} 1647 1648static struct mbuf * 1649get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1650 int *fl_bufs_used) 1651{ 1652 struct mbuf *m0, *m, **pnext; 1653 u_int nbuf, len; 1654 1655 /* 1656 * No assertion for the fl lock because we don't need it. This routine 1657 * is called only from the rx interrupt handler and it only updates 1658 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1659 * updated in the rx interrupt handler or the starvation helper routine. 1660 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1661 * lock but this routine does not). 1662 */ 1663 1664 nbuf = 0; 1665 len = G_RSPD_LEN(len_newbuf); 1666 if (__predict_false(fl->m0 != NULL)) { 1667 M_ASSERTPKTHDR(fl->m0); 1668 MPASS(len == fl->m0->m_pkthdr.len); 1669 MPASS(fl->remaining < len); 1670 1671 m0 = fl->m0; 1672 pnext = fl->pnext; 1673 len = fl->remaining; 1674 fl->m0 = NULL; 1675 goto get_segment; 1676 } 1677 1678 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1679 nbuf++; 1680 fl->rx_offset = 0; 1681 if (__predict_false(++fl->cidx == fl->cap)) 1682 fl->cidx = 0; 1683 } 1684 1685 /* 1686 * Payload starts at rx_offset in the current hw buffer. Its length is 1687 * 'len' and it may span multiple hw buffers. 1688 */ 1689 1690 m0 = get_scatter_segment(sc, fl, len, M_PKTHDR); 1691 if (m0 == NULL) 1692 goto done; 1693 len -= m0->m_len; 1694 pnext = &m0->m_next; 1695 while (len > 0) { 1696 nbuf++; 1697get_segment: 1698 MPASS(fl->rx_offset == 0); 1699 m = get_scatter_segment(sc, fl, len, 0); 1700 if (m == NULL) { 1701 fl->m0 = m0; 1702 fl->pnext = pnext; 1703 fl->remaining = len; 1704 m0 = NULL; 1705 goto done; 1706 } 1707 *pnext = m; 1708 pnext = &m->m_next; 1709 len -= m->m_len; 1710 } 1711 *pnext = NULL; 1712 if (fl->rx_offset == 0) 1713 nbuf++; 1714done: 1715 (*fl_bufs_used) += nbuf; 1716 return (m0); 1717} 1718 1719static int 1720t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1721{ 1722 struct sge_rxq *rxq = iq_to_rxq(iq); 1723 struct ifnet *ifp = rxq->ifp; 1724 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1725#if defined(INET) || defined(INET6) 1726 struct lro_ctrl *lro = &rxq->lro; 1727#endif 1728 1729 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1730 rss->opcode)); 1731 1732 m0->m_pkthdr.len -= fl_pktshift; 1733 m0->m_len -= fl_pktshift; 1734 m0->m_data += fl_pktshift; 1735 1736 m0->m_pkthdr.rcvif = ifp; 1737 m0->m_flags |= M_FLOWID; 1738 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1739 1740 if (cpl->csum_calc && !cpl->err_vec) { 1741 if (ifp->if_capenable & IFCAP_RXCSUM && 1742 cpl->l2info & htobe32(F_RXF_IP)) { 1743 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1744 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1745 rxq->rxcsum++; 1746 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1747 cpl->l2info & htobe32(F_RXF_IP6)) { 1748 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1749 CSUM_PSEUDO_HDR); 1750 rxq->rxcsum++; 1751 } 1752 1753 if (__predict_false(cpl->ip_frag)) 1754 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1755 else 1756 m0->m_pkthdr.csum_data = 0xffff; 1757 } 1758 1759 if (cpl->vlan_ex) { 1760 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1761 m0->m_flags |= M_VLANTAG; 1762 rxq->vlan_extraction++; 1763 } 1764 1765#if defined(INET) || defined(INET6) 1766 if (cpl->l2info & htobe32(F_RXF_LRO) && 1767 iq->flags & IQ_LRO_ENABLED && 1768 tcp_lro_rx(lro, m0, 0) == 0) { 1769 /* queued for LRO */ 1770 } else 1771#endif 1772 ifp->if_input(ifp, m0); 1773 1774 return (0); 1775} 1776 1777/* 1778 * Doesn't fail. Holds on to work requests it can't send right away. 1779 */ 1780void 1781t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1782{ 1783 struct sge_eq *eq = &wrq->eq; 1784 int can_reclaim; 1785 caddr_t dst; 1786 1787 TXQ_LOCK_ASSERT_OWNED(wrq); 1788#ifdef TCP_OFFLOAD 1789 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1790 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1791 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1792#else 1793 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1794 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1795#endif 1796 1797 if (__predict_true(wr != NULL)) 1798 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1799 1800 can_reclaim = reclaimable(eq); 1801 if (__predict_false(eq->flags & EQ_STALLED)) { 1802 if (eq->avail + can_reclaim < tx_resume_threshold(eq)) 1803 return; 1804 eq->flags &= ~EQ_STALLED; 1805 eq->unstalled++; 1806 } 1807 eq->cidx += can_reclaim; 1808 eq->avail += can_reclaim; 1809 if (__predict_false(eq->cidx >= eq->cap)) 1810 eq->cidx -= eq->cap; 1811 1812 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1813 int ndesc; 1814 1815 if (__predict_false(wr->wr_len < 0 || 1816 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1817 1818#ifdef INVARIANTS 1819 panic("%s: work request with length %d", __func__, 1820 wr->wr_len); 1821#endif 1822#ifdef KDB 1823 kdb_backtrace(); 1824#endif 1825 log(LOG_ERR, "%s: %s work request with length %d", 1826 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1827 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1828 free_wrqe(wr); 1829 continue; 1830 } 1831 1832 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1833 if (eq->avail < ndesc) { 1834 wrq->no_desc++; 1835 break; 1836 } 1837 1838 dst = (void *)&eq->desc[eq->pidx]; 1839 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1840 1841 eq->pidx += ndesc; 1842 eq->avail -= ndesc; 1843 if (__predict_false(eq->pidx >= eq->cap)) 1844 eq->pidx -= eq->cap; 1845 1846 eq->pending += ndesc; 1847 if (eq->pending >= 8) 1848 ring_eq_db(sc, eq); 1849 1850 wrq->tx_wrs++; 1851 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1852 free_wrqe(wr); 1853 1854 if (eq->avail < 8) { 1855 can_reclaim = reclaimable(eq); 1856 eq->cidx += can_reclaim; 1857 eq->avail += can_reclaim; 1858 if (__predict_false(eq->cidx >= eq->cap)) 1859 eq->cidx -= eq->cap; 1860 } 1861 } 1862 1863 if (eq->pending) 1864 ring_eq_db(sc, eq); 1865 1866 if (wr != NULL) { 1867 eq->flags |= EQ_STALLED; 1868 if (callout_pending(&eq->tx_callout) == 0) 1869 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1870 } 1871} 1872 1873/* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1874#define TXPKTS_PKT_HDR ((\ 1875 sizeof(struct ulp_txpkt) + \ 1876 sizeof(struct ulptx_idata) + \ 1877 sizeof(struct cpl_tx_pkt_core) \ 1878 ) / 8) 1879 1880/* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1881#define TXPKTS_WR_HDR (\ 1882 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1883 TXPKTS_PKT_HDR) 1884 1885/* Header of a tx WR, before SGL of first packet (in flits) */ 1886#define TXPKT_WR_HDR ((\ 1887 sizeof(struct fw_eth_tx_pkt_wr) + \ 1888 sizeof(struct cpl_tx_pkt_core) \ 1889 ) / 8 ) 1890 1891/* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1892#define TXPKT_LSO_WR_HDR ((\ 1893 sizeof(struct fw_eth_tx_pkt_wr) + \ 1894 sizeof(struct cpl_tx_pkt_lso_core) + \ 1895 sizeof(struct cpl_tx_pkt_core) \ 1896 ) / 8 ) 1897 1898int 1899t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1900{ 1901 struct port_info *pi = (void *)ifp->if_softc; 1902 struct adapter *sc = pi->adapter; 1903 struct sge_eq *eq = &txq->eq; 1904 struct buf_ring *br = txq->br; 1905 struct mbuf *next; 1906 int rc, coalescing, can_reclaim; 1907 struct txpkts txpkts; 1908 struct sgl sgl; 1909 1910 TXQ_LOCK_ASSERT_OWNED(txq); 1911 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1912 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1913 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1914 1915 prefetch(&eq->desc[eq->pidx]); 1916 prefetch(&txq->sdesc[eq->pidx]); 1917 1918 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1919 coalescing = 0; 1920 1921 can_reclaim = reclaimable(eq); 1922 if (__predict_false(eq->flags & EQ_STALLED)) { 1923 if (eq->avail + can_reclaim < tx_resume_threshold(eq)) { 1924 txq->m = m; 1925 return (0); 1926 } 1927 eq->flags &= ~EQ_STALLED; 1928 eq->unstalled++; 1929 } 1930 1931 if (__predict_false(eq->flags & EQ_DOOMED)) { 1932 m_freem(m); 1933 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1934 m_freem(m); 1935 return (ENETDOWN); 1936 } 1937 1938 if (eq->avail < 8 && can_reclaim) 1939 reclaim_tx_descs(txq, can_reclaim, 32); 1940 1941 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1942 1943 if (eq->avail < 8) 1944 break; 1945 1946 next = m->m_nextpkt; 1947 m->m_nextpkt = NULL; 1948 1949 if (next || buf_ring_peek(br)) 1950 coalescing = 1; 1951 1952 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1953 if (rc != 0) { 1954 if (rc == ENOMEM) { 1955 1956 /* Short of resources, suspend tx */ 1957 1958 m->m_nextpkt = next; 1959 break; 1960 } 1961 1962 /* 1963 * Unrecoverable error for this packet, throw it away 1964 * and move on to the next. get_pkt_sgl may already 1965 * have freed m (it will be NULL in that case and the 1966 * m_freem here is still safe). 1967 */ 1968 1969 m_freem(m); 1970 continue; 1971 } 1972 1973 if (coalescing && 1974 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1975 1976 /* Successfully absorbed into txpkts */ 1977 1978 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1979 goto doorbell; 1980 } 1981 1982 /* 1983 * We weren't coalescing to begin with, or current frame could 1984 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1985 * given to it can't be coalesced). Either way there should be 1986 * nothing in txpkts. 1987 */ 1988 KASSERT(txpkts.npkt == 0, 1989 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1990 1991 /* We're sending out individual packets now */ 1992 coalescing = 0; 1993 1994 if (eq->avail < 8) 1995 reclaim_tx_descs(txq, 0, 8); 1996 rc = write_txpkt_wr(pi, txq, m, &sgl); 1997 if (rc != 0) { 1998 1999 /* Short of hardware descriptors, suspend tx */ 2000 2001 /* 2002 * This is an unlikely but expensive failure. We've 2003 * done all the hard work (DMA mappings etc.) and now we 2004 * can't send out the packet. What's worse, we have to 2005 * spend even more time freeing up everything in sgl. 2006 */ 2007 txq->no_desc++; 2008 free_pkt_sgl(txq, &sgl); 2009 2010 m->m_nextpkt = next; 2011 break; 2012 } 2013 2014 ETHER_BPF_MTAP(ifp, m); 2015 if (sgl.nsegs == 0) 2016 m_freem(m); 2017doorbell: 2018 if (eq->pending >= 8) 2019 ring_eq_db(sc, eq); 2020 2021 can_reclaim = reclaimable(eq); 2022 if (can_reclaim >= 32) 2023 reclaim_tx_descs(txq, can_reclaim, 64); 2024 } 2025 2026 if (txpkts.npkt > 0) 2027 write_txpkts_wr(txq, &txpkts); 2028 2029 /* 2030 * m not NULL means there was an error but we haven't thrown it away. 2031 * This can happen when we're short of tx descriptors (no_desc) or maybe 2032 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 2033 * will get things going again. 2034 */ 2035 if (m && !(eq->flags & EQ_CRFLUSHED)) { 2036 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 2037 2038 /* 2039 * If EQ_CRFLUSHED is not set then we know we have at least one 2040 * available descriptor because any WR that reduces eq->avail to 2041 * 0 also sets EQ_CRFLUSHED. 2042 */ 2043 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 2044 2045 txsd->desc_used = 1; 2046 txsd->credits = 0; 2047 write_eqflush_wr(eq); 2048 } 2049 txq->m = m; 2050 2051 if (eq->pending) 2052 ring_eq_db(sc, eq); 2053 2054 reclaim_tx_descs(txq, 0, 128); 2055 2056 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 2057 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 2058 2059 return (0); 2060} 2061 2062void 2063t4_update_fl_bufsize(struct ifnet *ifp) 2064{ 2065 struct port_info *pi = ifp->if_softc; 2066 struct adapter *sc = pi->adapter; 2067 struct sge_rxq *rxq; 2068#ifdef TCP_OFFLOAD 2069 struct sge_ofld_rxq *ofld_rxq; 2070#endif 2071 struct sge_fl *fl; 2072 int i, maxp, mtu = ifp->if_mtu; 2073 2074 maxp = mtu_to_max_payload(sc, mtu, 0); 2075 for_each_rxq(pi, i, rxq) { 2076 fl = &rxq->fl; 2077 2078 FL_LOCK(fl); 2079 find_best_refill_source(sc, fl, maxp); 2080 FL_UNLOCK(fl); 2081 } 2082#ifdef TCP_OFFLOAD 2083 maxp = mtu_to_max_payload(sc, mtu, 1); 2084 for_each_ofld_rxq(pi, i, ofld_rxq) { 2085 fl = &ofld_rxq->fl; 2086 2087 FL_LOCK(fl); 2088 find_best_refill_source(sc, fl, maxp); 2089 FL_UNLOCK(fl); 2090 } 2091#endif 2092} 2093 2094int 2095can_resume_tx(struct sge_eq *eq) 2096{ 2097 2098 return (eq->avail + reclaimable(eq) >= tx_resume_threshold(eq)); 2099} 2100 2101static inline void 2102init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2103 int qsize) 2104{ 2105 2106 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2107 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2108 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2109 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2110 2111 iq->flags = 0; 2112 iq->adapter = sc; 2113 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2114 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2115 if (pktc_idx >= 0) { 2116 iq->intr_params |= F_QINTR_CNT_EN; 2117 iq->intr_pktc_idx = pktc_idx; 2118 } 2119 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2120 iq->sidx = iq->qsize - spg_len / IQ_ESIZE; 2121} 2122 2123static inline void 2124init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack, 2125 char *name) 2126{ 2127 2128 fl->qsize = qsize; 2129 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2130 if (pack) 2131 fl->flags |= FL_BUF_PACKING; 2132 find_best_refill_source(sc, fl, maxp); 2133 find_safe_refill_source(sc, fl); 2134} 2135 2136static inline void 2137init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2138 uint16_t iqid, char *name) 2139{ 2140 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 2141 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2142 2143 eq->flags = eqtype & EQ_TYPEMASK; 2144 eq->tx_chan = tx_chan; 2145 eq->iqid = iqid; 2146 eq->qsize = qsize; 2147 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2148 2149 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 2150 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 2151} 2152 2153static int 2154alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2155 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2156{ 2157 int rc; 2158 2159 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2160 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2161 if (rc != 0) { 2162 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2163 goto done; 2164 } 2165 2166 rc = bus_dmamem_alloc(*tag, va, 2167 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2168 if (rc != 0) { 2169 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2170 goto done; 2171 } 2172 2173 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2174 if (rc != 0) { 2175 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2176 goto done; 2177 } 2178done: 2179 if (rc) 2180 free_ring(sc, *tag, *map, *pa, *va); 2181 2182 return (rc); 2183} 2184 2185static int 2186free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2187 bus_addr_t pa, void *va) 2188{ 2189 if (pa) 2190 bus_dmamap_unload(tag, map); 2191 if (va) 2192 bus_dmamem_free(tag, va, map); 2193 if (tag) 2194 bus_dma_tag_destroy(tag); 2195 2196 return (0); 2197} 2198 2199/* 2200 * Allocates the ring for an ingress queue and an optional freelist. If the 2201 * freelist is specified it will be allocated and then associated with the 2202 * ingress queue. 2203 * 2204 * Returns errno on failure. Resources allocated up to that point may still be 2205 * allocated. Caller is responsible for cleanup in case this function fails. 2206 * 2207 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2208 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2209 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2210 */ 2211static int 2212alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 2213 int intr_idx, int cong) 2214{ 2215 int rc, i, cntxt_id; 2216 size_t len; 2217 struct fw_iq_cmd c; 2218 struct adapter *sc = iq->adapter; 2219 __be32 v = 0; 2220 2221 len = iq->qsize * IQ_ESIZE; 2222 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2223 (void **)&iq->desc); 2224 if (rc != 0) 2225 return (rc); 2226 2227 bzero(&c, sizeof(c)); 2228 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2229 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2230 V_FW_IQ_CMD_VFN(0)); 2231 2232 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2233 FW_LEN16(c)); 2234 2235 /* Special handling for firmware event queue */ 2236 if (iq == &sc->sge.fwq) 2237 v |= F_FW_IQ_CMD_IQASYNCH; 2238 2239 if (iq->flags & IQ_INTR) { 2240 KASSERT(intr_idx < sc->intr_count, 2241 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2242 } else 2243 v |= F_FW_IQ_CMD_IQANDST; 2244 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2245 2246 c.type_to_iqandstindex = htobe32(v | 2247 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2248 V_FW_IQ_CMD_VIID(pi->viid) | 2249 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2250 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2251 F_FW_IQ_CMD_IQGTSMODE | 2252 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2253 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 2254 c.iqsize = htobe16(iq->qsize); 2255 c.iqaddr = htobe64(iq->ba); 2256 if (cong >= 0) 2257 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2258 2259 if (fl) { 2260 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2261 2262 len = fl->qsize * EQ_ESIZE; 2263 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2264 &fl->ba, (void **)&fl->desc); 2265 if (rc) 2266 return (rc); 2267 2268 /* Allocate space for one software descriptor per buffer. */ 2269 fl->cap = (fl->qsize - spg_len / EQ_ESIZE) * 8; 2270 rc = alloc_fl_sdesc(fl); 2271 if (rc != 0) { 2272 device_printf(sc->dev, 2273 "failed to setup fl software descriptors: %d\n", 2274 rc); 2275 return (rc); 2276 } 2277 fl->needed = fl->cap; 2278 fl->lowat = fl->flags & FL_BUF_PACKING ? 2279 roundup2(sc->sge.fl_starve_threshold2, 8) : 2280 roundup2(sc->sge.fl_starve_threshold, 8); 2281 2282 c.iqns_to_fl0congen |= 2283 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2284 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2285 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2286 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2287 0)); 2288 if (cong >= 0) { 2289 c.iqns_to_fl0congen |= 2290 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2291 F_FW_IQ_CMD_FL0CONGCIF | 2292 F_FW_IQ_CMD_FL0CONGEN); 2293 } 2294 c.fl0dcaen_to_fl0cidxfthresh = 2295 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 2296 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2297 c.fl0size = htobe16(fl->qsize); 2298 c.fl0addr = htobe64(fl->ba); 2299 } 2300 2301 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2302 if (rc != 0) { 2303 device_printf(sc->dev, 2304 "failed to create ingress queue: %d\n", rc); 2305 return (rc); 2306 } 2307 2308 iq->cidx = 0; 2309 iq->gen = F_RSPD_GEN; 2310 iq->intr_next = iq->intr_params; 2311 iq->cntxt_id = be16toh(c.iqid); 2312 iq->abs_id = be16toh(c.physiqid); 2313 iq->flags |= IQ_ALLOCATED; 2314 2315 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2316 if (cntxt_id >= sc->sge.niq) { 2317 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2318 cntxt_id, sc->sge.niq - 1); 2319 } 2320 sc->sge.iqmap[cntxt_id] = iq; 2321 2322 if (fl) { 2323 fl->cntxt_id = be16toh(c.fl0id); 2324 fl->pidx = fl->cidx = 0; 2325 2326 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2327 if (cntxt_id >= sc->sge.neq) { 2328 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2329 __func__, cntxt_id, sc->sge.neq - 1); 2330 } 2331 sc->sge.eqmap[cntxt_id] = (void *)fl; 2332 2333 FL_LOCK(fl); 2334 /* Enough to make sure the SGE doesn't think it's starved */ 2335 refill_fl(sc, fl, fl->lowat); 2336 FL_UNLOCK(fl); 2337 2338 iq->flags |= IQ_HAS_FL; 2339 } 2340 2341 if (is_t5(sc) && cong >= 0) { 2342 uint32_t param, val; 2343 2344 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2345 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2346 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2347 if (cong == 0) 2348 val = 1 << 19; 2349 else { 2350 val = 2 << 19; 2351 for (i = 0; i < 4; i++) { 2352 if (cong & (1 << i)) 2353 val |= 1 << (i << 2); 2354 } 2355 } 2356 2357 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2358 if (rc != 0) { 2359 /* report error but carry on */ 2360 device_printf(sc->dev, 2361 "failed to set congestion manager context for " 2362 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2363 } 2364 } 2365 2366 /* Enable IQ interrupts */ 2367 atomic_store_rel_int(&iq->state, IQS_IDLE); 2368 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2369 V_INGRESSQID(iq->cntxt_id)); 2370 2371 return (0); 2372} 2373 2374static int 2375free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 2376{ 2377 int rc; 2378 struct adapter *sc = iq->adapter; 2379 device_t dev; 2380 2381 if (sc == NULL) 2382 return (0); /* nothing to do */ 2383 2384 dev = pi ? pi->dev : sc->dev; 2385 2386 if (iq->flags & IQ_ALLOCATED) { 2387 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2388 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2389 fl ? fl->cntxt_id : 0xffff, 0xffff); 2390 if (rc != 0) { 2391 device_printf(dev, 2392 "failed to free queue %p: %d\n", iq, rc); 2393 return (rc); 2394 } 2395 iq->flags &= ~IQ_ALLOCATED; 2396 } 2397 2398 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2399 2400 bzero(iq, sizeof(*iq)); 2401 2402 if (fl) { 2403 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2404 fl->desc); 2405 2406 if (fl->sdesc) 2407 free_fl_sdesc(sc, fl); 2408 2409 if (mtx_initialized(&fl->fl_lock)) 2410 mtx_destroy(&fl->fl_lock); 2411 2412 bzero(fl, sizeof(*fl)); 2413 } 2414 2415 return (0); 2416} 2417 2418static void 2419add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2420 struct sge_fl *fl) 2421{ 2422 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2423 2424 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2425 "freelist"); 2426 children = SYSCTL_CHILDREN(oid); 2427 2428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2429 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2430 "SGE context id of the freelist"); 2431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2432 0, "consumer index"); 2433 if (fl->flags & FL_BUF_PACKING) { 2434 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2435 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2436 } 2437 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2438 0, "producer index"); 2439 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2440 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2441 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2442 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2443 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2444 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2445 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2446 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2447 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2448 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2449} 2450 2451static int 2452alloc_fwq(struct adapter *sc) 2453{ 2454 int rc, intr_idx; 2455 struct sge_iq *fwq = &sc->sge.fwq; 2456 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2457 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2458 2459 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE); 2460 fwq->flags |= IQ_INTR; /* always */ 2461 intr_idx = sc->intr_count > 1 ? 1 : 0; 2462 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 2463 if (rc != 0) { 2464 device_printf(sc->dev, 2465 "failed to create firmware event queue: %d\n", rc); 2466 return (rc); 2467 } 2468 2469 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2470 NULL, "firmware event queue"); 2471 children = SYSCTL_CHILDREN(oid); 2472 2473 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2474 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2475 "absolute id of the queue"); 2476 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2477 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2478 "SGE context id of the queue"); 2479 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2480 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2481 "consumer index"); 2482 2483 return (0); 2484} 2485 2486static int 2487free_fwq(struct adapter *sc) 2488{ 2489 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2490} 2491 2492static int 2493alloc_mgmtq(struct adapter *sc) 2494{ 2495 int rc; 2496 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2497 char name[16]; 2498 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2499 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2500 2501 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2502 NULL, "management queue"); 2503 2504 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2505 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2506 sc->sge.fwq.cntxt_id, name); 2507 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2508 if (rc != 0) { 2509 device_printf(sc->dev, 2510 "failed to create management queue: %d\n", rc); 2511 return (rc); 2512 } 2513 2514 return (0); 2515} 2516 2517static int 2518free_mgmtq(struct adapter *sc) 2519{ 2520 2521 return free_wrq(sc, &sc->sge.mgmtq); 2522} 2523 2524static inline int 2525tnl_cong(struct port_info *pi) 2526{ 2527 2528 if (cong_drop == -1) 2529 return (-1); 2530 else if (cong_drop == 1) 2531 return (0); 2532 else 2533 return (pi->rx_chan_map); 2534} 2535 2536static int 2537alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2538 struct sysctl_oid *oid) 2539{ 2540 int rc; 2541 struct sysctl_oid_list *children; 2542 char name[16]; 2543 2544 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2545 if (rc != 0) 2546 return (rc); 2547 2548 FL_LOCK(&rxq->fl); 2549 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2550 FL_UNLOCK(&rxq->fl); 2551 2552#if defined(INET) || defined(INET6) 2553 rc = tcp_lro_init(&rxq->lro); 2554 if (rc != 0) 2555 return (rc); 2556 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2557 2558 if (pi->ifp->if_capenable & IFCAP_LRO) 2559 rxq->iq.flags |= IQ_LRO_ENABLED; 2560#endif 2561 rxq->ifp = pi->ifp; 2562 2563 children = SYSCTL_CHILDREN(oid); 2564 2565 snprintf(name, sizeof(name), "%d", idx); 2566 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2567 NULL, "rx queue"); 2568 children = SYSCTL_CHILDREN(oid); 2569 2570 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2571 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2572 "absolute id of the queue"); 2573 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2574 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2575 "SGE context id of the queue"); 2576 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2577 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2578 "consumer index"); 2579#if defined(INET) || defined(INET6) 2580 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2581 &rxq->lro.lro_queued, 0, NULL); 2582 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2583 &rxq->lro.lro_flushed, 0, NULL); 2584#endif 2585 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2586 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2587 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2588 CTLFLAG_RD, &rxq->vlan_extraction, 2589 "# of times hardware extracted 802.1Q tag"); 2590 2591 add_fl_sysctls(&pi->ctx, oid, &rxq->fl); 2592 2593 return (rc); 2594} 2595 2596static int 2597free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2598{ 2599 int rc; 2600 2601#if defined(INET) || defined(INET6) 2602 if (rxq->lro.ifp) { 2603 tcp_lro_free(&rxq->lro); 2604 rxq->lro.ifp = NULL; 2605 } 2606#endif 2607 2608 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2609 if (rc == 0) 2610 bzero(rxq, sizeof(*rxq)); 2611 2612 return (rc); 2613} 2614 2615#ifdef TCP_OFFLOAD 2616static int 2617alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2618 int intr_idx, int idx, struct sysctl_oid *oid) 2619{ 2620 int rc; 2621 struct sysctl_oid_list *children; 2622 char name[16]; 2623 2624 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2625 pi->rx_chan_map); 2626 if (rc != 0) 2627 return (rc); 2628 2629 children = SYSCTL_CHILDREN(oid); 2630 2631 snprintf(name, sizeof(name), "%d", idx); 2632 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2633 NULL, "rx queue"); 2634 children = SYSCTL_CHILDREN(oid); 2635 2636 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2637 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2638 "I", "absolute id of the queue"); 2639 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2640 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2641 "I", "SGE context id of the queue"); 2642 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2643 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2644 "consumer index"); 2645 2646 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl); 2647 2648 return (rc); 2649} 2650 2651static int 2652free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2653{ 2654 int rc; 2655 2656 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2657 if (rc == 0) 2658 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2659 2660 return (rc); 2661} 2662#endif 2663 2664#ifdef DEV_NETMAP 2665static int 2666alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx, 2667 int idx, struct sysctl_oid *oid) 2668{ 2669 int rc; 2670 struct sysctl_oid_list *children; 2671 struct sysctl_ctx_list *ctx; 2672 char name[16]; 2673 size_t len; 2674 struct adapter *sc = pi->adapter; 2675 struct netmap_adapter *na = NA(pi->nm_ifp); 2676 2677 MPASS(na != NULL); 2678 2679 len = pi->qsize_rxq * IQ_ESIZE; 2680 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 2681 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 2682 if (rc != 0) 2683 return (rc); 2684 2685 len = na->num_rx_desc * EQ_ESIZE + spg_len; 2686 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 2687 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 2688 if (rc != 0) 2689 return (rc); 2690 2691 nm_rxq->pi = pi; 2692 nm_rxq->nid = idx; 2693 nm_rxq->iq_cidx = 0; 2694 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / IQ_ESIZE; 2695 nm_rxq->iq_gen = F_RSPD_GEN; 2696 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 2697 nm_rxq->fl_sidx = na->num_rx_desc; 2698 nm_rxq->intr_idx = intr_idx; 2699 2700 ctx = &pi->ctx; 2701 children = SYSCTL_CHILDREN(oid); 2702 2703 snprintf(name, sizeof(name), "%d", idx); 2704 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 2705 "rx queue"); 2706 children = SYSCTL_CHILDREN(oid); 2707 2708 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 2709 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 2710 "I", "absolute id of the queue"); 2711 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2712 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 2713 "I", "SGE context id of the queue"); 2714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2715 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 2716 "consumer index"); 2717 2718 children = SYSCTL_CHILDREN(oid); 2719 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2720 "freelist"); 2721 children = SYSCTL_CHILDREN(oid); 2722 2723 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2724 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 2725 "I", "SGE context id of the freelist"); 2726 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2727 &nm_rxq->fl_cidx, 0, "consumer index"); 2728 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2729 &nm_rxq->fl_pidx, 0, "producer index"); 2730 2731 return (rc); 2732} 2733 2734 2735static int 2736free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq) 2737{ 2738 struct adapter *sc = pi->adapter; 2739 2740 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 2741 nm_rxq->iq_desc); 2742 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 2743 nm_rxq->fl_desc); 2744 2745 return (0); 2746} 2747 2748static int 2749alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 2750 struct sysctl_oid *oid) 2751{ 2752 int rc; 2753 size_t len; 2754 struct adapter *sc = pi->adapter; 2755 struct netmap_adapter *na = NA(pi->nm_ifp); 2756 char name[16]; 2757 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2758 2759 len = na->num_tx_desc * EQ_ESIZE + spg_len; 2760 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 2761 &nm_txq->ba, (void **)&nm_txq->desc); 2762 if (rc) 2763 return (rc); 2764 2765 nm_txq->pidx = nm_txq->cidx = 0; 2766 nm_txq->sidx = na->num_tx_desc; 2767 nm_txq->nid = idx; 2768 nm_txq->iqidx = iqidx; 2769 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 2770 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf)); 2771 2772 snprintf(name, sizeof(name), "%d", idx); 2773 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2774 NULL, "netmap tx queue"); 2775 children = SYSCTL_CHILDREN(oid); 2776 2777 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2778 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 2779 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2780 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 2781 "consumer index"); 2782 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2783 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 2784 "producer index"); 2785 2786 return (rc); 2787} 2788 2789static int 2790free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq) 2791{ 2792 struct adapter *sc = pi->adapter; 2793 2794 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 2795 nm_txq->desc); 2796 2797 return (0); 2798} 2799#endif 2800 2801static int 2802ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2803{ 2804 int rc, cntxt_id; 2805 struct fw_eq_ctrl_cmd c; 2806 2807 bzero(&c, sizeof(c)); 2808 2809 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2810 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2811 V_FW_EQ_CTRL_CMD_VFN(0)); 2812 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2813 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2814 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2815 c.physeqid_pkd = htobe32(0); 2816 c.fetchszm_to_iqid = 2817 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2818 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2819 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2820 c.dcaen_to_eqsize = 2821 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2822 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2823 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2824 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2825 c.eqaddr = htobe64(eq->ba); 2826 2827 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2828 if (rc != 0) { 2829 device_printf(sc->dev, 2830 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2831 return (rc); 2832 } 2833 eq->flags |= EQ_ALLOCATED; 2834 2835 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2836 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2837 if (cntxt_id >= sc->sge.neq) 2838 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2839 cntxt_id, sc->sge.neq - 1); 2840 sc->sge.eqmap[cntxt_id] = eq; 2841 2842 return (rc); 2843} 2844 2845static int 2846eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2847{ 2848 int rc, cntxt_id; 2849 struct fw_eq_eth_cmd c; 2850 2851 bzero(&c, sizeof(c)); 2852 2853 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2854 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2855 V_FW_EQ_ETH_CMD_VFN(0)); 2856 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2857 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2858 c.autoequiqe_to_viid = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2859 c.fetchszm_to_iqid = 2860 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2861 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2862 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2863 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2864 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2865 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2866 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2867 c.eqaddr = htobe64(eq->ba); 2868 2869 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2870 if (rc != 0) { 2871 device_printf(pi->dev, 2872 "failed to create Ethernet egress queue: %d\n", rc); 2873 return (rc); 2874 } 2875 eq->flags |= EQ_ALLOCATED; 2876 2877 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2878 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2879 if (cntxt_id >= sc->sge.neq) 2880 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2881 cntxt_id, sc->sge.neq - 1); 2882 sc->sge.eqmap[cntxt_id] = eq; 2883 2884 return (rc); 2885} 2886 2887#ifdef TCP_OFFLOAD 2888static int 2889ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2890{ 2891 int rc, cntxt_id; 2892 struct fw_eq_ofld_cmd c; 2893 2894 bzero(&c, sizeof(c)); 2895 2896 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2897 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2898 V_FW_EQ_OFLD_CMD_VFN(0)); 2899 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2900 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2901 c.fetchszm_to_iqid = 2902 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2903 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2904 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2905 c.dcaen_to_eqsize = 2906 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2907 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2908 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2909 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2910 c.eqaddr = htobe64(eq->ba); 2911 2912 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2913 if (rc != 0) { 2914 device_printf(pi->dev, 2915 "failed to create egress queue for TCP offload: %d\n", rc); 2916 return (rc); 2917 } 2918 eq->flags |= EQ_ALLOCATED; 2919 2920 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2921 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2922 if (cntxt_id >= sc->sge.neq) 2923 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2924 cntxt_id, sc->sge.neq - 1); 2925 sc->sge.eqmap[cntxt_id] = eq; 2926 2927 return (rc); 2928} 2929#endif 2930 2931static int 2932alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2933{ 2934 int rc; 2935 size_t len; 2936 2937 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2938 2939 len = eq->qsize * EQ_ESIZE; 2940 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2941 &eq->ba, (void **)&eq->desc); 2942 if (rc) 2943 return (rc); 2944 2945 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2946 eq->spg = (void *)&eq->desc[eq->cap]; 2947 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2948 eq->pidx = eq->cidx = 0; 2949 eq->doorbells = sc->doorbells; 2950 2951 switch (eq->flags & EQ_TYPEMASK) { 2952 case EQ_CTRL: 2953 rc = ctrl_eq_alloc(sc, eq); 2954 break; 2955 2956 case EQ_ETH: 2957 rc = eth_eq_alloc(sc, pi, eq); 2958 break; 2959 2960#ifdef TCP_OFFLOAD 2961 case EQ_OFLD: 2962 rc = ofld_eq_alloc(sc, pi, eq); 2963 break; 2964#endif 2965 2966 default: 2967 panic("%s: invalid eq type %d.", __func__, 2968 eq->flags & EQ_TYPEMASK); 2969 } 2970 if (rc != 0) { 2971 device_printf(sc->dev, 2972 "failed to allocate egress queue(%d): %d\n", 2973 eq->flags & EQ_TYPEMASK, rc); 2974 } 2975 2976 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2977 2978 if (isset(&eq->doorbells, DOORBELL_UDB) || 2979 isset(&eq->doorbells, DOORBELL_UDBWC) || 2980 isset(&eq->doorbells, DOORBELL_WCWR)) { 2981 uint32_t s_qpp = sc->sge.eq_s_qpp; 2982 uint32_t mask = (1 << s_qpp) - 1; 2983 volatile uint8_t *udb; 2984 2985 udb = sc->udbs_base + UDBS_DB_OFFSET; 2986 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2987 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2988 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 2989 clrbit(&eq->doorbells, DOORBELL_WCWR); 2990 else { 2991 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2992 eq->udb_qid = 0; 2993 } 2994 eq->udb = (volatile void *)udb; 2995 } 2996 2997 return (rc); 2998} 2999 3000static int 3001free_eq(struct adapter *sc, struct sge_eq *eq) 3002{ 3003 int rc; 3004 3005 if (eq->flags & EQ_ALLOCATED) { 3006 switch (eq->flags & EQ_TYPEMASK) { 3007 case EQ_CTRL: 3008 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 3009 eq->cntxt_id); 3010 break; 3011 3012 case EQ_ETH: 3013 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 3014 eq->cntxt_id); 3015 break; 3016 3017#ifdef TCP_OFFLOAD 3018 case EQ_OFLD: 3019 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 3020 eq->cntxt_id); 3021 break; 3022#endif 3023 3024 default: 3025 panic("%s: invalid eq type %d.", __func__, 3026 eq->flags & EQ_TYPEMASK); 3027 } 3028 if (rc != 0) { 3029 device_printf(sc->dev, 3030 "failed to free egress queue (%d): %d\n", 3031 eq->flags & EQ_TYPEMASK, rc); 3032 return (rc); 3033 } 3034 eq->flags &= ~EQ_ALLOCATED; 3035 } 3036 3037 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3038 3039 if (mtx_initialized(&eq->eq_lock)) 3040 mtx_destroy(&eq->eq_lock); 3041 3042 bzero(eq, sizeof(*eq)); 3043 return (0); 3044} 3045 3046static int 3047alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 3048 struct sysctl_oid *oid) 3049{ 3050 int rc; 3051 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 3052 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3053 3054 rc = alloc_eq(sc, pi, &wrq->eq); 3055 if (rc) 3056 return (rc); 3057 3058 wrq->adapter = sc; 3059 STAILQ_INIT(&wrq->wr_list); 3060 3061 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3062 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3063 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3064 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3065 "consumer index"); 3066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3067 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3068 "producer index"); 3069 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 3070 &wrq->tx_wrs, "# of work requests"); 3071 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3072 &wrq->no_desc, 0, 3073 "# of times queue ran out of hardware descriptors"); 3074 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3075 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 3076 3077 return (rc); 3078} 3079 3080static int 3081free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3082{ 3083 int rc; 3084 3085 rc = free_eq(sc, &wrq->eq); 3086 if (rc) 3087 return (rc); 3088 3089 bzero(wrq, sizeof(*wrq)); 3090 return (0); 3091} 3092 3093static int 3094alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 3095 struct sysctl_oid *oid) 3096{ 3097 int rc; 3098 struct adapter *sc = pi->adapter; 3099 struct sge_eq *eq = &txq->eq; 3100 char name[16]; 3101 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3102 3103 rc = alloc_eq(sc, pi, eq); 3104 if (rc) 3105 return (rc); 3106 3107 txq->ifp = pi->ifp; 3108 3109 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 3110 M_ZERO | M_WAITOK); 3111 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 3112 3113 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 3114 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 3115 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 3116 if (rc != 0) { 3117 device_printf(sc->dev, 3118 "failed to create tx DMA tag: %d\n", rc); 3119 return (rc); 3120 } 3121 3122 /* 3123 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 3124 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 3125 * sized for the worst case. 3126 */ 3127 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 3128 M_WAITOK); 3129 if (rc != 0) { 3130 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 3131 return (rc); 3132 } 3133 3134 snprintf(name, sizeof(name), "%d", idx); 3135 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3136 NULL, "tx queue"); 3137 children = SYSCTL_CHILDREN(oid); 3138 3139 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3140 &eq->cntxt_id, 0, "SGE context id of the queue"); 3141 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 3142 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3143 "consumer index"); 3144 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 3145 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3146 "producer index"); 3147 3148 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3149 &txq->txcsum, "# of times hardware assisted with checksum"); 3150 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 3151 CTLFLAG_RD, &txq->vlan_insertion, 3152 "# of times hardware inserted 802.1Q tag"); 3153 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3154 &txq->tso_wrs, "# of TSO work requests"); 3155 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3156 &txq->imm_wrs, "# of work requests with immediate data"); 3157 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3158 &txq->sgl_wrs, "# of work requests with direct SGL"); 3159 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3160 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3161 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 3162 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 3163 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 3164 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 3165 3166 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 3167 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 3168 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 3169 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 3170 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3171 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 3172 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 3173 &eq->egr_update, 0, "egress update notifications from the SGE"); 3174 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3175 &eq->unstalled, 0, "# of times txq recovered after stall"); 3176 3177 return (rc); 3178} 3179 3180static int 3181free_txq(struct port_info *pi, struct sge_txq *txq) 3182{ 3183 int rc; 3184 struct adapter *sc = pi->adapter; 3185 struct sge_eq *eq = &txq->eq; 3186 3187 rc = free_eq(sc, eq); 3188 if (rc) 3189 return (rc); 3190 3191 free(txq->sdesc, M_CXGBE); 3192 3193 if (txq->txmaps.maps) 3194 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 3195 3196 buf_ring_free(txq->br, M_CXGBE); 3197 3198 if (txq->tx_tag) 3199 bus_dma_tag_destroy(txq->tx_tag); 3200 3201 bzero(txq, sizeof(*txq)); 3202 return (0); 3203} 3204 3205static void 3206oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3207{ 3208 bus_addr_t *ba = arg; 3209 3210 KASSERT(nseg == 1, 3211 ("%s meant for single segment mappings only.", __func__)); 3212 3213 *ba = error ? 0 : segs->ds_addr; 3214} 3215 3216#define FL_HW_IDX(x) ((x) >> 3) 3217static inline void 3218ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3219{ 3220 int ndesc = fl->pending / 8; 3221 uint32_t v; 3222 3223 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 3224 ndesc--; /* hold back one credit */ 3225 3226 if (ndesc <= 0) 3227 return; /* nothing to do */ 3228 3229 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 3230 if (is_t5(sc)) 3231 v |= F_DBTYPE; 3232 3233 wmb(); 3234 3235 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3236 fl->pending -= ndesc * 8; 3237} 3238 3239/* 3240 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 3241 * 3242 * Returns non-zero to indicate that it should be added to the list of starving 3243 * freelists. 3244 */ 3245static int 3246refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 3247{ 3248 __be64 *d = &fl->desc[fl->pidx]; 3249 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 3250 uintptr_t pa; 3251 caddr_t cl; 3252 struct cluster_layout *cll = &fl->cll_def; /* default layout */ 3253 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 3254 struct cluster_metadata *clm; 3255 3256 FL_LOCK_ASSERT_OWNED(fl); 3257 3258 if (nbufs > fl->needed) 3259 nbufs = fl->needed; 3260 nbufs -= (fl->pidx + nbufs) % 8; 3261 3262 while (nbufs--) { 3263 3264 if (sd->cl != NULL) { 3265 3266 if (sd->nmbuf == 0) { 3267 /* 3268 * Fast recycle without involving any atomics on 3269 * the cluster's metadata (if the cluster has 3270 * metadata). This happens when all frames 3271 * received in the cluster were small enough to 3272 * fit within a single mbuf each. 3273 */ 3274 fl->cl_fast_recycled++; 3275#ifdef INVARIANTS 3276 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3277 if (clm != NULL) 3278 MPASS(clm->refcount == 1); 3279#endif 3280 goto recycled_fast; 3281 } 3282 3283 /* 3284 * Cluster is guaranteed to have metadata. Clusters 3285 * without metadata always take the fast recycle path 3286 * when they're recycled. 3287 */ 3288 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3289 MPASS(clm != NULL); 3290 3291 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3292 fl->cl_recycled++; 3293 counter_u64_add(extfree_rels, 1); 3294 goto recycled; 3295 } 3296 sd->cl = NULL; /* gave up my reference */ 3297 } 3298 MPASS(sd->cl == NULL); 3299alloc: 3300 cl = uma_zalloc(swz->zone, M_NOWAIT); 3301 if (__predict_false(cl == NULL)) { 3302 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3303 fl->cll_def.zidx == fl->cll_alt.zidx) 3304 break; 3305 3306 /* fall back to the safe zone */ 3307 cll = &fl->cll_alt; 3308 swz = &sc->sge.sw_zone_info[cll->zidx]; 3309 goto alloc; 3310 } 3311 fl->cl_allocated++; 3312 3313 pa = pmap_kextract((vm_offset_t)cl); 3314 pa += cll->region1; 3315 sd->cl = cl; 3316 sd->cll = *cll; 3317 *d = htobe64(pa | cll->hwidx); 3318 clm = cl_metadata(sc, fl, cll, cl); 3319 if (clm != NULL) { 3320recycled: 3321#ifdef INVARIANTS 3322 clm->sd = sd; 3323#endif 3324 clm->refcount = 1; 3325 } 3326 sd->nmbuf = 0; 3327recycled_fast: 3328 fl->pending++; 3329 fl->needed--; 3330 d++; 3331 sd++; 3332 if (__predict_false(++fl->pidx == fl->cap)) { 3333 fl->pidx = 0; 3334 sd = fl->sdesc; 3335 d = fl->desc; 3336 } 3337 } 3338 3339 if (fl->pending >= 8) 3340 ring_fl_db(sc, fl); 3341 3342 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3343} 3344 3345/* 3346 * Attempt to refill all starving freelists. 3347 */ 3348static void 3349refill_sfl(void *arg) 3350{ 3351 struct adapter *sc = arg; 3352 struct sge_fl *fl, *fl_temp; 3353 3354 mtx_lock(&sc->sfl_lock); 3355 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3356 FL_LOCK(fl); 3357 refill_fl(sc, fl, 64); 3358 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3359 TAILQ_REMOVE(&sc->sfl, fl, link); 3360 fl->flags &= ~FL_STARVING; 3361 } 3362 FL_UNLOCK(fl); 3363 } 3364 3365 if (!TAILQ_EMPTY(&sc->sfl)) 3366 callout_schedule(&sc->sfl_callout, hz / 5); 3367 mtx_unlock(&sc->sfl_lock); 3368} 3369 3370static int 3371alloc_fl_sdesc(struct sge_fl *fl) 3372{ 3373 3374 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 3375 M_ZERO | M_WAITOK); 3376 3377 return (0); 3378} 3379 3380static void 3381free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3382{ 3383 struct fl_sdesc *sd; 3384 struct cluster_metadata *clm; 3385 struct cluster_layout *cll; 3386 int i; 3387 3388 sd = fl->sdesc; 3389 for (i = 0; i < fl->cap; i++, sd++) { 3390 if (sd->cl == NULL) 3391 continue; 3392 3393 cll = &sd->cll; 3394 clm = cl_metadata(sc, fl, cll, sd->cl); 3395 if (sd->nmbuf == 0) 3396 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3397 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3398 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3399 counter_u64_add(extfree_rels, 1); 3400 } 3401 sd->cl = NULL; 3402 } 3403 3404 free(fl->sdesc, M_CXGBE); 3405 fl->sdesc = NULL; 3406} 3407 3408int 3409t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 3410 int flags) 3411{ 3412 struct tx_map *txm; 3413 int i, rc; 3414 3415 txmaps->map_total = txmaps->map_avail = count; 3416 txmaps->map_cidx = txmaps->map_pidx = 0; 3417 3418 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 3419 M_ZERO | flags); 3420 3421 txm = txmaps->maps; 3422 for (i = 0; i < count; i++, txm++) { 3423 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 3424 if (rc != 0) 3425 goto failed; 3426 } 3427 3428 return (0); 3429failed: 3430 while (--i >= 0) { 3431 txm--; 3432 bus_dmamap_destroy(tx_tag, txm->map); 3433 } 3434 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 3435 3436 free(txmaps->maps, M_CXGBE); 3437 txmaps->maps = NULL; 3438 3439 return (rc); 3440} 3441 3442void 3443t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 3444{ 3445 struct tx_map *txm; 3446 int i; 3447 3448 txm = txmaps->maps; 3449 for (i = 0; i < txmaps->map_total; i++, txm++) { 3450 3451 if (txm->m) { 3452 bus_dmamap_unload(tx_tag, txm->map); 3453 m_freem(txm->m); 3454 txm->m = NULL; 3455 } 3456 3457 bus_dmamap_destroy(tx_tag, txm->map); 3458 } 3459 3460 free(txmaps->maps, M_CXGBE); 3461 txmaps->maps = NULL; 3462} 3463 3464/* 3465 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 3466 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 3467 * of immediate data. 3468 */ 3469#define IMM_LEN ( \ 3470 2 * EQ_ESIZE \ 3471 - sizeof(struct fw_eth_tx_pkt_wr) \ 3472 - sizeof(struct cpl_tx_pkt_core)) 3473 3474/* 3475 * Returns non-zero on failure, no need to cleanup anything in that case. 3476 * 3477 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 3478 * if the resulting chain still won't fit in a tx descriptor. 3479 * 3480 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 3481 * does not have the TCP header in it. 3482 */ 3483static int 3484get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 3485 int sgl_only) 3486{ 3487 struct mbuf *m = *fp; 3488 struct tx_maps *txmaps; 3489 struct tx_map *txm; 3490 int rc, defragged = 0, n; 3491 3492 TXQ_LOCK_ASSERT_OWNED(txq); 3493 3494 if (m->m_pkthdr.tso_segsz) 3495 sgl_only = 1; /* Do not allow immediate data with LSO */ 3496 3497start: sgl->nsegs = 0; 3498 3499 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 3500 return (0); /* nsegs = 0 tells caller to use imm. tx */ 3501 3502 txmaps = &txq->txmaps; 3503 if (txmaps->map_avail == 0) { 3504 txq->no_dmamap++; 3505 return (ENOMEM); 3506 } 3507 txm = &txmaps->maps[txmaps->map_pidx]; 3508 3509 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 3510 *fp = m_pullup(m, 50); 3511 m = *fp; 3512 if (m == NULL) 3513 return (ENOBUFS); 3514 } 3515 3516 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 3517 &sgl->nsegs, BUS_DMA_NOWAIT); 3518 if (rc == EFBIG && defragged == 0) { 3519 m = m_defrag(m, M_NOWAIT); 3520 if (m == NULL) 3521 return (EFBIG); 3522 3523 defragged = 1; 3524 *fp = m; 3525 goto start; 3526 } 3527 if (rc != 0) 3528 return (rc); 3529 3530 txm->m = m; 3531 txmaps->map_avail--; 3532 if (++txmaps->map_pidx == txmaps->map_total) 3533 txmaps->map_pidx = 0; 3534 3535 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 3536 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 3537 3538 /* 3539 * Store the # of flits required to hold this frame's SGL in nflits. An 3540 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 3541 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 3542 * then len1 must be set to 0. 3543 */ 3544 n = sgl->nsegs - 1; 3545 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 3546 3547 return (0); 3548} 3549 3550 3551/* 3552 * Releases all the txq resources used up in the specified sgl. 3553 */ 3554static int 3555free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 3556{ 3557 struct tx_maps *txmaps; 3558 struct tx_map *txm; 3559 3560 TXQ_LOCK_ASSERT_OWNED(txq); 3561 3562 if (sgl->nsegs == 0) 3563 return (0); /* didn't use any map */ 3564 3565 txmaps = &txq->txmaps; 3566 3567 /* 1 pkt uses exactly 1 map, back it out */ 3568 3569 txmaps->map_avail++; 3570 if (txmaps->map_pidx > 0) 3571 txmaps->map_pidx--; 3572 else 3573 txmaps->map_pidx = txmaps->map_total - 1; 3574 3575 txm = &txmaps->maps[txmaps->map_pidx]; 3576 bus_dmamap_unload(txq->tx_tag, txm->map); 3577 txm->m = NULL; 3578 3579 return (0); 3580} 3581 3582static int 3583write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 3584 struct sgl *sgl) 3585{ 3586 struct sge_eq *eq = &txq->eq; 3587 struct fw_eth_tx_pkt_wr *wr; 3588 struct cpl_tx_pkt_core *cpl; 3589 uint32_t ctrl; /* used in many unrelated places */ 3590 uint64_t ctrl1; 3591 int nflits, ndesc, pktlen; 3592 struct tx_sdesc *txsd; 3593 caddr_t dst; 3594 3595 TXQ_LOCK_ASSERT_OWNED(txq); 3596 3597 pktlen = m->m_pkthdr.len; 3598 3599 /* 3600 * Do we have enough flits to send this frame out? 3601 */ 3602 ctrl = sizeof(struct cpl_tx_pkt_core); 3603 if (m->m_pkthdr.tso_segsz) { 3604 nflits = TXPKT_LSO_WR_HDR; 3605 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3606 } else 3607 nflits = TXPKT_WR_HDR; 3608 if (sgl->nsegs > 0) 3609 nflits += sgl->nflits; 3610 else { 3611 nflits += howmany(pktlen, 8); 3612 ctrl += pktlen; 3613 } 3614 ndesc = howmany(nflits, 8); 3615 if (ndesc > eq->avail) 3616 return (ENOMEM); 3617 3618 /* Firmware work request header */ 3619 wr = (void *)&eq->desc[eq->pidx]; 3620 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3621 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3622 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3623 if (eq->avail == ndesc) { 3624 if (!(eq->flags & EQ_CRFLUSHED)) { 3625 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3626 eq->flags |= EQ_CRFLUSHED; 3627 } 3628 eq->flags |= EQ_STALLED; 3629 } 3630 3631 wr->equiq_to_len16 = htobe32(ctrl); 3632 wr->r3 = 0; 3633 3634 if (m->m_pkthdr.tso_segsz) { 3635 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3636 struct ether_header *eh; 3637 void *l3hdr; 3638#if defined(INET) || defined(INET6) 3639 struct tcphdr *tcp; 3640#endif 3641 uint16_t eh_type; 3642 3643 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3644 F_LSO_LAST_SLICE; 3645 3646 eh = mtod(m, struct ether_header *); 3647 eh_type = ntohs(eh->ether_type); 3648 if (eh_type == ETHERTYPE_VLAN) { 3649 struct ether_vlan_header *evh = (void *)eh; 3650 3651 ctrl |= V_LSO_ETHHDR_LEN(1); 3652 l3hdr = evh + 1; 3653 eh_type = ntohs(evh->evl_proto); 3654 } else 3655 l3hdr = eh + 1; 3656 3657 switch (eh_type) { 3658#ifdef INET6 3659 case ETHERTYPE_IPV6: 3660 { 3661 struct ip6_hdr *ip6 = l3hdr; 3662 3663 /* 3664 * XXX-BZ For now we do not pretend to support 3665 * IPv6 extension headers. 3666 */ 3667 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3668 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3669 tcp = (struct tcphdr *)(ip6 + 1); 3670 ctrl |= F_LSO_IPV6; 3671 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3672 V_LSO_TCPHDR_LEN(tcp->th_off); 3673 break; 3674 } 3675#endif 3676#ifdef INET 3677 case ETHERTYPE_IP: 3678 { 3679 struct ip *ip = l3hdr; 3680 3681 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3682 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3683 V_LSO_TCPHDR_LEN(tcp->th_off); 3684 break; 3685 } 3686#endif 3687 default: 3688 panic("%s: CSUM_TSO but no supported IP version " 3689 "(0x%04x)", __func__, eh_type); 3690 } 3691 3692 lso->lso_ctrl = htobe32(ctrl); 3693 lso->ipid_ofst = htobe16(0); 3694 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3695 lso->seqno_offset = htobe32(0); 3696 lso->len = htobe32(pktlen); 3697 3698 cpl = (void *)(lso + 1); 3699 3700 txq->tso_wrs++; 3701 } else 3702 cpl = (void *)(wr + 1); 3703 3704 /* Checksum offload */ 3705 ctrl1 = 0; 3706 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3707 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3708 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3709 CSUM_TCP_IPV6 | CSUM_TSO))) 3710 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3711 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3712 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3713 txq->txcsum++; /* some hardware assistance provided */ 3714 3715 /* VLAN tag insertion */ 3716 if (m->m_flags & M_VLANTAG) { 3717 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3718 txq->vlan_insertion++; 3719 } 3720 3721 /* CPL header */ 3722 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3723 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3724 cpl->pack = 0; 3725 cpl->len = htobe16(pktlen); 3726 cpl->ctrl1 = htobe64(ctrl1); 3727 3728 /* Software descriptor */ 3729 txsd = &txq->sdesc[eq->pidx]; 3730 txsd->desc_used = ndesc; 3731 3732 eq->pending += ndesc; 3733 eq->avail -= ndesc; 3734 eq->pidx += ndesc; 3735 if (eq->pidx >= eq->cap) 3736 eq->pidx -= eq->cap; 3737 3738 /* SGL */ 3739 dst = (void *)(cpl + 1); 3740 if (sgl->nsegs > 0) { 3741 txsd->credits = 1; 3742 txq->sgl_wrs++; 3743 write_sgl_to_txd(eq, sgl, &dst); 3744 } else { 3745 txsd->credits = 0; 3746 txq->imm_wrs++; 3747 for (; m; m = m->m_next) { 3748 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3749#ifdef INVARIANTS 3750 pktlen -= m->m_len; 3751#endif 3752 } 3753#ifdef INVARIANTS 3754 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3755#endif 3756 3757 } 3758 3759 txq->txpkt_wrs++; 3760 return (0); 3761} 3762 3763/* 3764 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3765 * request. It has either been folded into txpkts or txpkts was flushed and m 3766 * has started a new coalesced work request (as the first frame in a fresh 3767 * txpkts). 3768 * 3769 * Returns non-zero to indicate a failure - caller is responsible for 3770 * transmitting m, if there was anything in txpkts it has been flushed. 3771 */ 3772static int 3773add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3774 struct mbuf *m, struct sgl *sgl) 3775{ 3776 struct sge_eq *eq = &txq->eq; 3777 int can_coalesce; 3778 struct tx_sdesc *txsd; 3779 int flits; 3780 3781 TXQ_LOCK_ASSERT_OWNED(txq); 3782 3783 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3784 3785 if (txpkts->npkt > 0) { 3786 flits = TXPKTS_PKT_HDR + sgl->nflits; 3787 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3788 txpkts->nflits + flits <= TX_WR_FLITS && 3789 txpkts->nflits + flits <= eq->avail * 8 && 3790 txpkts->plen + m->m_pkthdr.len < 65536; 3791 3792 if (can_coalesce) { 3793 txpkts->npkt++; 3794 txpkts->nflits += flits; 3795 txpkts->plen += m->m_pkthdr.len; 3796 3797 txsd = &txq->sdesc[eq->pidx]; 3798 txsd->credits++; 3799 3800 return (0); 3801 } 3802 3803 /* 3804 * Couldn't coalesce m into txpkts. The first order of business 3805 * is to send txpkts on its way. Then we'll revisit m. 3806 */ 3807 write_txpkts_wr(txq, txpkts); 3808 } 3809 3810 /* 3811 * Check if we can start a new coalesced tx work request with m as 3812 * the first packet in it. 3813 */ 3814 3815 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3816 3817 flits = TXPKTS_WR_HDR + sgl->nflits; 3818 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3819 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3820 3821 if (can_coalesce == 0) 3822 return (EINVAL); 3823 3824 /* 3825 * Start a fresh coalesced tx WR with m as the first frame in it. 3826 */ 3827 txpkts->npkt = 1; 3828 txpkts->nflits = flits; 3829 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3830 txpkts->plen = m->m_pkthdr.len; 3831 3832 txsd = &txq->sdesc[eq->pidx]; 3833 txsd->credits = 1; 3834 3835 return (0); 3836} 3837 3838/* 3839 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3840 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3841 * coalescing only if sufficient hardware descriptors are available. 3842 */ 3843static void 3844write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3845{ 3846 struct sge_eq *eq = &txq->eq; 3847 struct fw_eth_tx_pkts_wr *wr; 3848 struct tx_sdesc *txsd; 3849 uint32_t ctrl; 3850 int ndesc; 3851 3852 TXQ_LOCK_ASSERT_OWNED(txq); 3853 3854 ndesc = howmany(txpkts->nflits, 8); 3855 3856 wr = (void *)&eq->desc[eq->pidx]; 3857 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3858 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3859 if (eq->avail == ndesc) { 3860 if (!(eq->flags & EQ_CRFLUSHED)) { 3861 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3862 eq->flags |= EQ_CRFLUSHED; 3863 } 3864 eq->flags |= EQ_STALLED; 3865 } 3866 wr->equiq_to_len16 = htobe32(ctrl); 3867 wr->plen = htobe16(txpkts->plen); 3868 wr->npkt = txpkts->npkt; 3869 wr->r3 = wr->type = 0; 3870 3871 /* Everything else already written */ 3872 3873 txsd = &txq->sdesc[eq->pidx]; 3874 txsd->desc_used = ndesc; 3875 3876 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3877 3878 eq->pending += ndesc; 3879 eq->avail -= ndesc; 3880 eq->pidx += ndesc; 3881 if (eq->pidx >= eq->cap) 3882 eq->pidx -= eq->cap; 3883 3884 txq->txpkts_pkts += txpkts->npkt; 3885 txq->txpkts_wrs++; 3886 txpkts->npkt = 0; /* emptied */ 3887} 3888 3889static inline void 3890write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3891 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3892{ 3893 struct ulp_txpkt *ulpmc; 3894 struct ulptx_idata *ulpsc; 3895 struct cpl_tx_pkt_core *cpl; 3896 struct sge_eq *eq = &txq->eq; 3897 uintptr_t flitp, start, end; 3898 uint64_t ctrl; 3899 caddr_t dst; 3900 3901 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3902 3903 start = (uintptr_t)eq->desc; 3904 end = (uintptr_t)eq->spg; 3905 3906 /* Checksum offload */ 3907 ctrl = 0; 3908 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3909 ctrl |= F_TXPKT_IPCSUM_DIS; 3910 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3911 CSUM_TCP_IPV6 | CSUM_TSO))) 3912 ctrl |= F_TXPKT_L4CSUM_DIS; 3913 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3914 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3915 txq->txcsum++; /* some hardware assistance provided */ 3916 3917 /* VLAN tag insertion */ 3918 if (m->m_flags & M_VLANTAG) { 3919 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3920 txq->vlan_insertion++; 3921 } 3922 3923 /* 3924 * The previous packet's SGL must have ended at a 16 byte boundary (this 3925 * is required by the firmware/hardware). It follows that flitp cannot 3926 * wrap around between the ULPTX master command and ULPTX subcommand (8 3927 * bytes each), and that it can not wrap around in the middle of the 3928 * cpl_tx_pkt_core either. 3929 */ 3930 flitp = (uintptr_t)txpkts->flitp; 3931 KASSERT((flitp & 0xf) == 0, 3932 ("%s: last SGL did not end at 16 byte boundary: %p", 3933 __func__, txpkts->flitp)); 3934 3935 /* ULP master command */ 3936 ulpmc = (void *)flitp; 3937 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3938 V_ULP_TXPKT_FID(eq->iqid)); 3939 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3940 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3941 3942 /* ULP subcommand */ 3943 ulpsc = (void *)(ulpmc + 1); 3944 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3945 F_ULP_TX_SC_MORE); 3946 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3947 3948 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3949 if (flitp == end) 3950 flitp = start; 3951 3952 /* CPL_TX_PKT */ 3953 cpl = (void *)flitp; 3954 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3955 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3956 cpl->pack = 0; 3957 cpl->len = htobe16(m->m_pkthdr.len); 3958 cpl->ctrl1 = htobe64(ctrl); 3959 3960 flitp += sizeof(*cpl); 3961 if (flitp == end) 3962 flitp = start; 3963 3964 /* SGL for this frame */ 3965 dst = (caddr_t)flitp; 3966 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3967 txpkts->flitp = (void *)dst; 3968 3969 KASSERT(((uintptr_t)dst & 0xf) == 0, 3970 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3971} 3972 3973/* 3974 * If the SGL ends on an address that is not 16 byte aligned, this function will 3975 * add a 0 filled flit at the end. It returns 1 in that case. 3976 */ 3977static int 3978write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3979{ 3980 __be64 *flitp, *end; 3981 struct ulptx_sgl *usgl; 3982 bus_dma_segment_t *seg; 3983 int i, padded; 3984 3985 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3986 ("%s: bad SGL - nsegs=%d, nflits=%d", 3987 __func__, sgl->nsegs, sgl->nflits)); 3988 3989 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3990 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3991 3992 flitp = (__be64 *)(*to); 3993 end = flitp + sgl->nflits; 3994 seg = &sgl->seg[0]; 3995 usgl = (void *)flitp; 3996 3997 /* 3998 * We start at a 16 byte boundary somewhere inside the tx descriptor 3999 * ring, so we're at least 16 bytes away from the status page. There is 4000 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 4001 */ 4002 4003 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 4004 V_ULPTX_NSGE(sgl->nsegs)); 4005 usgl->len0 = htobe32(seg->ds_len); 4006 usgl->addr0 = htobe64(seg->ds_addr); 4007 seg++; 4008 4009 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 4010 4011 /* Won't wrap around at all */ 4012 4013 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 4014 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 4015 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 4016 } 4017 if (i & 1) 4018 usgl->sge[i / 2].len[1] = htobe32(0); 4019 } else { 4020 4021 /* Will wrap somewhere in the rest of the SGL */ 4022 4023 /* 2 flits already written, write the rest flit by flit */ 4024 flitp = (void *)(usgl + 1); 4025 for (i = 0; i < sgl->nflits - 2; i++) { 4026 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 4027 flitp = (void *)eq->desc; 4028 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 4029 } 4030 end = flitp; 4031 } 4032 4033 if ((uintptr_t)end & 0xf) { 4034 *(uint64_t *)end = 0; 4035 end++; 4036 padded = 1; 4037 } else 4038 padded = 0; 4039 4040 if ((uintptr_t)end == (uintptr_t)eq->spg) 4041 *to = (void *)eq->desc; 4042 else 4043 *to = (void *)end; 4044 4045 return (padded); 4046} 4047 4048static inline void 4049copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4050{ 4051 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 4052 bcopy(from, *to, len); 4053 (*to) += len; 4054 } else { 4055 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 4056 4057 bcopy(from, *to, portion); 4058 from += portion; 4059 portion = len - portion; /* remaining */ 4060 bcopy(from, (void *)eq->desc, portion); 4061 (*to) = (caddr_t)eq->desc + portion; 4062 } 4063} 4064 4065static inline void 4066ring_eq_db(struct adapter *sc, struct sge_eq *eq) 4067{ 4068 u_int db, pending; 4069 4070 db = eq->doorbells; 4071 pending = eq->pending; 4072 if (pending > 1) 4073 clrbit(&db, DOORBELL_WCWR); 4074 eq->pending = 0; 4075 wmb(); 4076 4077 switch (ffs(db) - 1) { 4078 case DOORBELL_UDB: 4079 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4080 return; 4081 4082 case DOORBELL_WCWR: { 4083 volatile uint64_t *dst, *src; 4084 int i; 4085 4086 /* 4087 * Queues whose 128B doorbell segment fits in the page do not 4088 * use relative qid (udb_qid is always 0). Only queues with 4089 * doorbell segments can do WCWR. 4090 */ 4091 KASSERT(eq->udb_qid == 0 && pending == 1, 4092 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4093 __func__, eq->doorbells, pending, eq->pidx, eq)); 4094 4095 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4096 UDBS_DB_OFFSET); 4097 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 4098 src = (void *)&eq->desc[i]; 4099 while (src != (void *)&eq->desc[i + 1]) 4100 *dst++ = *src++; 4101 wmb(); 4102 return; 4103 } 4104 4105 case DOORBELL_UDBWC: 4106 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4107 wmb(); 4108 return; 4109 4110 case DOORBELL_KDB: 4111 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 4112 V_QID(eq->cntxt_id) | V_PIDX(pending)); 4113 return; 4114 } 4115} 4116 4117static inline int 4118reclaimable(struct sge_eq *eq) 4119{ 4120 unsigned int cidx; 4121 4122 cidx = eq->spg->cidx; /* stable snapshot */ 4123 cidx = be16toh(cidx); 4124 4125 if (cidx >= eq->cidx) 4126 return (cidx - eq->cidx); 4127 else 4128 return (cidx + eq->cap - eq->cidx); 4129} 4130 4131/* 4132 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 4133 * many as possible but stop when there are around "n" mbufs to free. 4134 * 4135 * The actual number reclaimed is provided as the return value. 4136 */ 4137static int 4138reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 4139{ 4140 struct tx_sdesc *txsd; 4141 struct tx_maps *txmaps; 4142 struct tx_map *txm; 4143 unsigned int reclaimed, maps; 4144 struct sge_eq *eq = &txq->eq; 4145 4146 TXQ_LOCK_ASSERT_OWNED(txq); 4147 4148 if (can_reclaim == 0) 4149 can_reclaim = reclaimable(eq); 4150 4151 maps = reclaimed = 0; 4152 while (can_reclaim && maps < n) { 4153 int ndesc; 4154 4155 txsd = &txq->sdesc[eq->cidx]; 4156 ndesc = txsd->desc_used; 4157 4158 /* Firmware doesn't return "partial" credits. */ 4159 KASSERT(can_reclaim >= ndesc, 4160 ("%s: unexpected number of credits: %d, %d", 4161 __func__, can_reclaim, ndesc)); 4162 4163 maps += txsd->credits; 4164 4165 reclaimed += ndesc; 4166 can_reclaim -= ndesc; 4167 4168 eq->cidx += ndesc; 4169 if (__predict_false(eq->cidx >= eq->cap)) 4170 eq->cidx -= eq->cap; 4171 } 4172 4173 txmaps = &txq->txmaps; 4174 txm = &txmaps->maps[txmaps->map_cidx]; 4175 if (maps) 4176 prefetch(txm->m); 4177 4178 eq->avail += reclaimed; 4179 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 4180 ("%s: too many descriptors available", __func__)); 4181 4182 txmaps->map_avail += maps; 4183 KASSERT(txmaps->map_avail <= txmaps->map_total, 4184 ("%s: too many maps available", __func__)); 4185 4186 while (maps--) { 4187 struct tx_map *next; 4188 4189 next = txm + 1; 4190 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 4191 next = txmaps->maps; 4192 prefetch(next->m); 4193 4194 bus_dmamap_unload(txq->tx_tag, txm->map); 4195 m_freem(txm->m); 4196 txm->m = NULL; 4197 4198 txm = next; 4199 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 4200 txmaps->map_cidx = 0; 4201 } 4202 4203 return (reclaimed); 4204} 4205 4206static void 4207write_eqflush_wr(struct sge_eq *eq) 4208{ 4209 struct fw_eq_flush_wr *wr; 4210 4211 EQ_LOCK_ASSERT_OWNED(eq); 4212 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 4213 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 4214 4215 wr = (void *)&eq->desc[eq->pidx]; 4216 bzero(wr, sizeof(*wr)); 4217 wr->opcode = FW_EQ_FLUSH_WR; 4218 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 4219 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 4220 4221 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 4222 eq->pending++; 4223 eq->avail--; 4224 if (++eq->pidx == eq->cap) 4225 eq->pidx = 0; 4226} 4227 4228static __be64 4229get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 4230{ 4231 int i = (idx / 3) * 2; 4232 4233 switch (idx % 3) { 4234 case 0: { 4235 __be64 rc; 4236 4237 rc = htobe32(sgl[i].ds_len); 4238 if (i + 1 < nsegs) 4239 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 4240 4241 return (rc); 4242 } 4243 case 1: 4244 return htobe64(sgl[i].ds_addr); 4245 case 2: 4246 return htobe64(sgl[i + 1].ds_addr); 4247 } 4248 4249 return (0); 4250} 4251 4252static void 4253find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4254{ 4255 int8_t zidx, hwidx, idx; 4256 uint16_t region1, region3; 4257 int spare, spare_needed, n; 4258 struct sw_zone_info *swz; 4259 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4260 4261 /* 4262 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4263 * large enough for the max payload and cluster metadata. Otherwise 4264 * settle for the largest bufsize that leaves enough room in the cluster 4265 * for metadata. 4266 * 4267 * Without buffer packing: Look for the smallest zone which has a 4268 * bufsize large enough for the max payload. Settle for the largest 4269 * bufsize available if there's nothing big enough for max payload. 4270 */ 4271 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4272 swz = &sc->sge.sw_zone_info[0]; 4273 hwidx = -1; 4274 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4275 if (swz->size > largest_rx_cluster) { 4276 if (__predict_true(hwidx != -1)) 4277 break; 4278 4279 /* 4280 * This is a misconfiguration. largest_rx_cluster is 4281 * preventing us from finding a refill source. See 4282 * dev.t5nex.<n>.buffer_sizes to figure out why. 4283 */ 4284 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4285 " refill source for fl %p (dma %u). Ignored.\n", 4286 largest_rx_cluster, fl, maxp); 4287 } 4288 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4289 hwb = &hwb_list[idx]; 4290 spare = swz->size - hwb->size; 4291 if (spare < spare_needed) 4292 continue; 4293 4294 hwidx = idx; /* best option so far */ 4295 if (hwb->size >= maxp) { 4296 4297 if ((fl->flags & FL_BUF_PACKING) == 0) 4298 goto done; /* stop looking (not packing) */ 4299 4300 if (swz->size >= safest_rx_cluster) 4301 goto done; /* stop looking (packing) */ 4302 } 4303 break; /* keep looking, next zone */ 4304 } 4305 } 4306done: 4307 /* A usable hwidx has been located. */ 4308 MPASS(hwidx != -1); 4309 hwb = &hwb_list[hwidx]; 4310 zidx = hwb->zidx; 4311 swz = &sc->sge.sw_zone_info[zidx]; 4312 region1 = 0; 4313 region3 = swz->size - hwb->size; 4314 4315 /* 4316 * Stay within this zone and see if there is a better match when mbuf 4317 * inlining is allowed. Remember that the hwidx's are sorted in 4318 * decreasing order of size (so in increasing order of spare area). 4319 */ 4320 for (idx = hwidx; idx != -1; idx = hwb->next) { 4321 hwb = &hwb_list[idx]; 4322 spare = swz->size - hwb->size; 4323 4324 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4325 break; 4326 if (spare < CL_METADATA_SIZE + MSIZE) 4327 continue; 4328 n = (spare - CL_METADATA_SIZE) / MSIZE; 4329 if (n > howmany(hwb->size, maxp)) 4330 break; 4331 4332 hwidx = idx; 4333 if (fl->flags & FL_BUF_PACKING) { 4334 region1 = n * MSIZE; 4335 region3 = spare - region1; 4336 } else { 4337 region1 = MSIZE; 4338 region3 = spare - region1; 4339 break; 4340 } 4341 } 4342 4343 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4344 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4345 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4346 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4347 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4348 sc->sge.sw_zone_info[zidx].size, 4349 ("%s: bad buffer layout for fl %p, maxp %d. " 4350 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4351 sc->sge.sw_zone_info[zidx].size, region1, 4352 sc->sge.hw_buf_info[hwidx].size, region3)); 4353 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4354 KASSERT(region3 >= CL_METADATA_SIZE, 4355 ("%s: no room for metadata. fl %p, maxp %d; " 4356 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4357 sc->sge.sw_zone_info[zidx].size, region1, 4358 sc->sge.hw_buf_info[hwidx].size, region3)); 4359 KASSERT(region1 % MSIZE == 0, 4360 ("%s: bad mbuf region for fl %p, maxp %d. " 4361 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4362 sc->sge.sw_zone_info[zidx].size, region1, 4363 sc->sge.hw_buf_info[hwidx].size, region3)); 4364 } 4365 4366 fl->cll_def.zidx = zidx; 4367 fl->cll_def.hwidx = hwidx; 4368 fl->cll_def.region1 = region1; 4369 fl->cll_def.region3 = region3; 4370} 4371 4372static void 4373find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4374{ 4375 struct sge *s = &sc->sge; 4376 struct hw_buf_info *hwb; 4377 struct sw_zone_info *swz; 4378 int spare; 4379 int8_t hwidx; 4380 4381 if (fl->flags & FL_BUF_PACKING) 4382 hwidx = s->safe_hwidx2; /* with room for metadata */ 4383 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4384 hwidx = s->safe_hwidx2; 4385 hwb = &s->hw_buf_info[hwidx]; 4386 swz = &s->sw_zone_info[hwb->zidx]; 4387 spare = swz->size - hwb->size; 4388 4389 /* no good if there isn't room for an mbuf as well */ 4390 if (spare < CL_METADATA_SIZE + MSIZE) 4391 hwidx = s->safe_hwidx1; 4392 } else 4393 hwidx = s->safe_hwidx1; 4394 4395 if (hwidx == -1) { 4396 /* No fallback source */ 4397 fl->cll_alt.hwidx = -1; 4398 fl->cll_alt.zidx = -1; 4399 4400 return; 4401 } 4402 4403 hwb = &s->hw_buf_info[hwidx]; 4404 swz = &s->sw_zone_info[hwb->zidx]; 4405 spare = swz->size - hwb->size; 4406 fl->cll_alt.hwidx = hwidx; 4407 fl->cll_alt.zidx = hwb->zidx; 4408 if (allow_mbufs_in_cluster) 4409 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4410 else 4411 fl->cll_alt.region1 = 0; 4412 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4413} 4414 4415static void 4416add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4417{ 4418 mtx_lock(&sc->sfl_lock); 4419 FL_LOCK(fl); 4420 if ((fl->flags & FL_DOOMED) == 0) { 4421 fl->flags |= FL_STARVING; 4422 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4423 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4424 } 4425 FL_UNLOCK(fl); 4426 mtx_unlock(&sc->sfl_lock); 4427} 4428 4429static int 4430handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4431 struct mbuf *m) 4432{ 4433 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4434 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4435 struct adapter *sc = iq->adapter; 4436 struct sge *s = &sc->sge; 4437 struct sge_eq *eq; 4438 4439 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4440 rss->opcode)); 4441 4442 eq = s->eqmap[qid - s->eq_start]; 4443 EQ_LOCK(eq); 4444 KASSERT(eq->flags & EQ_CRFLUSHED, 4445 ("%s: unsolicited egress update", __func__)); 4446 eq->flags &= ~EQ_CRFLUSHED; 4447 eq->egr_update++; 4448 4449 if (__predict_false(eq->flags & EQ_DOOMED)) 4450 wakeup_one(eq); 4451 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 4452 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 4453 EQ_UNLOCK(eq); 4454 4455 return (0); 4456} 4457 4458/* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4459CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4460 offsetof(struct cpl_fw6_msg, data)); 4461 4462static int 4463handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4464{ 4465 struct adapter *sc = iq->adapter; 4466 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4467 4468 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4469 rss->opcode)); 4470 4471 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4472 const struct rss_header *rss2; 4473 4474 rss2 = (const struct rss_header *)&cpl->data[0]; 4475 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4476 } 4477 4478 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4479} 4480 4481static int 4482sysctl_uint16(SYSCTL_HANDLER_ARGS) 4483{ 4484 uint16_t *id = arg1; 4485 int i = *id; 4486 4487 return sysctl_handle_int(oidp, &i, 0, req); 4488} 4489 4490static int 4491sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4492{ 4493 struct sge *s = arg1; 4494 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4495 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4496 int i, rc; 4497 struct sbuf sb; 4498 char c; 4499 4500 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4501 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4502 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4503 c = '*'; 4504 else 4505 c = '\0'; 4506 4507 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4508 } 4509 sbuf_trim(&sb); 4510 sbuf_finish(&sb); 4511 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4512 sbuf_delete(&sb); 4513 return (rc); 4514} 4515