t4_sge.c revision 267600
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/cxgbe/t4_sge.c 267600 2014-06-18 00:16:35Z np $"); 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#include <sys/types.h> 35#include <sys/eventhandler.h> 36#include <sys/mbuf.h> 37#include <sys/socket.h> 38#include <sys/kernel.h> 39#include <sys/kdb.h> 40#include <sys/malloc.h> 41#include <sys/queue.h> 42#include <sys/sbuf.h> 43#include <sys/taskqueue.h> 44#include <sys/time.h> 45#include <sys/sysctl.h> 46#include <sys/smp.h> 47#include <net/bpf.h> 48#include <net/ethernet.h> 49#include <net/if.h> 50#include <net/if_vlan_var.h> 51#include <netinet/in.h> 52#include <netinet/ip.h> 53#include <netinet/ip6.h> 54#include <netinet/tcp.h> 55#include <machine/md_var.h> 56#include <vm/vm.h> 57#include <vm/pmap.h> 58#ifdef DEV_NETMAP 59#include <machine/bus.h> 60#include <sys/selinfo.h> 61#include <net/if_var.h> 62#include <net/netmap.h> 63#include <dev/netmap/netmap_kern.h> 64#endif 65 66#include "common/common.h" 67#include "common/t4_regs.h" 68#include "common/t4_regs_values.h" 69#include "common/t4_msg.h" 70 71#ifdef T4_PKT_TIMESTAMP 72#define RX_COPY_THRESHOLD (MINCLSIZE - 8) 73#else 74#define RX_COPY_THRESHOLD MINCLSIZE 75#endif 76 77/* 78 * Ethernet frames are DMA'd at this byte offset into the freelist buffer. 79 * 0-7 are valid values. 80 */ 81int fl_pktshift = 2; 82TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift); 83 84/* 85 * Pad ethernet payload up to this boundary. 86 * -1: driver should figure out a good value. 87 * 0: disable padding. 88 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value. 89 */ 90int fl_pad = -1; 91TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad); 92 93/* 94 * Status page length. 95 * -1: driver should figure out a good value. 96 * 64 or 128 are the only other valid values. 97 */ 98int spg_len = -1; 99TUNABLE_INT("hw.cxgbe.spg_len", &spg_len); 100 101/* 102 * Congestion drops. 103 * -1: no congestion feedback (not recommended). 104 * 0: backpressure the channel instead of dropping packets right away. 105 * 1: no backpressure, drop packets for the congested queue immediately. 106 */ 107static int cong_drop = 0; 108TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop); 109 110/* 111 * Deliver multiple frames in the same free list buffer if they fit. 112 * -1: let the driver decide whether to enable buffer packing or not. 113 * 0: disable buffer packing. 114 * 1: enable buffer packing. 115 */ 116static int buffer_packing = -1; 117TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing); 118 119/* 120 * Start next frame in a packed buffer at this boundary. 121 * -1: driver should figure out a good value. 122 * T4: 123 * --- 124 * if fl_pad != 0 125 * value specified here will be overridden by fl_pad. 126 * else 127 * power of 2 from 32 to 4096 (both inclusive) is a valid value here. 128 * T5: 129 * --- 130 * 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value. 131 */ 132static int fl_pack = -1; 133static int t4_fl_pack; 134static int t5_fl_pack; 135TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack); 136 137/* 138 * Allow the driver to create mbuf(s) in a cluster allocated for rx. 139 * 0: never; always allocate mbufs from the zone_mbuf UMA zone. 140 * 1: ok to create mbuf(s) within a cluster if there is room. 141 */ 142static int allow_mbufs_in_cluster = 1; 143TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster); 144 145/* 146 * Largest rx cluster size that the driver is allowed to allocate. 147 */ 148static int largest_rx_cluster = MJUM16BYTES; 149TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster); 150 151/* 152 * Size of cluster allocation that's most likely to succeed. The driver will 153 * fall back to this size if it fails to allocate clusters larger than this. 154 */ 155static int safest_rx_cluster = PAGE_SIZE; 156TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster); 157 158/* Used to track coalesced tx work request */ 159struct txpkts { 160 uint64_t *flitp; /* ptr to flit where next pkt should start */ 161 uint8_t npkt; /* # of packets in this work request */ 162 uint8_t nflits; /* # of flits used by this work request */ 163 uint16_t plen; /* total payload (sum of all packets) */ 164}; 165 166/* A packet's SGL. This + m_pkthdr has all info needed for tx */ 167struct sgl { 168 int nsegs; /* # of segments in the SGL, 0 means imm. tx */ 169 int nflits; /* # of flits needed for the SGL */ 170 bus_dma_segment_t seg[TX_SGL_SEGS]; 171}; 172 173static int service_iq(struct sge_iq *, int); 174static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t, 175 int *); 176static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *); 177static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, 178 int); 179static inline void init_fl(struct adapter *, struct sge_fl *, int, int, int, 180 char *); 181static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t, 182 char *); 183static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 184 bus_addr_t *, void **); 185static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 186 void *); 187static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, 188 int, int); 189static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); 190static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *, 191 struct sge_fl *); 192static int alloc_fwq(struct adapter *); 193static int free_fwq(struct adapter *); 194static int alloc_mgmtq(struct adapter *); 195static int free_mgmtq(struct adapter *); 196static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int, 197 struct sysctl_oid *); 198static int free_rxq(struct port_info *, struct sge_rxq *); 199#ifdef TCP_OFFLOAD 200static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int, 201 struct sysctl_oid *); 202static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *); 203#endif 204#ifdef DEV_NETMAP 205static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int, 206 struct sysctl_oid *); 207static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *); 208static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int, 209 struct sysctl_oid *); 210static int free_nm_txq(struct port_info *, struct sge_nm_txq *); 211#endif 212static int ctrl_eq_alloc(struct adapter *, struct sge_eq *); 213static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 214#ifdef TCP_OFFLOAD 215static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *); 216#endif 217static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *); 218static int free_eq(struct adapter *, struct sge_eq *); 219static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *, 220 struct sysctl_oid *); 221static int free_wrq(struct adapter *, struct sge_wrq *); 222static int alloc_txq(struct port_info *, struct sge_txq *, int, 223 struct sysctl_oid *); 224static int free_txq(struct port_info *, struct sge_txq *); 225static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); 226static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); 227static inline void iq_next(struct sge_iq *); 228static inline void ring_fl_db(struct adapter *, struct sge_fl *); 229static int refill_fl(struct adapter *, struct sge_fl *, int); 230static void refill_sfl(void *); 231static int alloc_fl_sdesc(struct sge_fl *); 232static void free_fl_sdesc(struct adapter *, struct sge_fl *); 233static void find_best_refill_source(struct adapter *, struct sge_fl *, int); 234static void find_safe_refill_source(struct adapter *, struct sge_fl *); 235static void add_fl_to_sfl(struct adapter *, struct sge_fl *); 236 237static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); 238static int free_pkt_sgl(struct sge_txq *, struct sgl *); 239static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, 240 struct sgl *); 241static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, 242 struct mbuf *, struct sgl *); 243static void write_txpkts_wr(struct sge_txq *, struct txpkts *); 244static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, 245 struct txpkts *, struct mbuf *, struct sgl *); 246static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); 247static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); 248static inline void ring_eq_db(struct adapter *, struct sge_eq *); 249static inline int reclaimable(struct sge_eq *); 250static int reclaim_tx_descs(struct sge_txq *, int, int); 251static void write_eqflush_wr(struct sge_eq *); 252static __be64 get_flit(bus_dma_segment_t *, int, int); 253static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *, 254 struct mbuf *); 255static int handle_fw_msg(struct sge_iq *, const struct rss_header *, 256 struct mbuf *); 257 258static int sysctl_uint16(SYSCTL_HANDLER_ARGS); 259static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS); 260 261/* 262 * Called on MOD_LOAD. Validates and calculates the SGE tunables. 263 */ 264void 265t4_sge_modload(void) 266{ 267 int pad; 268 269 /* set pad to a reasonable powerof2 between 16 and 4096 (inclusive) */ 270#if defined(__i386__) || defined(__amd64__) 271 pad = max(cpu_clflush_line_size, 16); 272#else 273 pad = max(CACHE_LINE_SIZE, 16); 274#endif 275 pad = min(pad, 4096); 276 277 if (fl_pktshift < 0 || fl_pktshift > 7) { 278 printf("Invalid hw.cxgbe.fl_pktshift value (%d)," 279 " using 2 instead.\n", fl_pktshift); 280 fl_pktshift = 2; 281 } 282 283 if (fl_pad != 0 && 284 (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad))) { 285 286 if (fl_pad != -1) { 287 printf("Invalid hw.cxgbe.fl_pad value (%d)," 288 " using %d instead.\n", fl_pad, max(pad, 32)); 289 } 290 fl_pad = max(pad, 32); 291 } 292 293 /* 294 * T4 has the same pad and pack boundary. If a pad boundary is set, 295 * pack boundary must be set to the same value. Otherwise take the 296 * specified value or auto-calculate something reasonable. 297 */ 298 if (fl_pad) 299 t4_fl_pack = fl_pad; 300 else if (fl_pack < 32 || fl_pack > 4096 || !powerof2(fl_pack)) 301 t4_fl_pack = max(pad, 32); 302 else 303 t4_fl_pack = fl_pack; 304 305 /* T5's pack boundary is independent of the pad boundary. */ 306 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 || 307 !powerof2(fl_pack)) 308 t5_fl_pack = max(pad, CACHE_LINE_SIZE); 309 else 310 t5_fl_pack = fl_pack; 311 312 if (spg_len != 64 && spg_len != 128) { 313 int len; 314 315#if defined(__i386__) || defined(__amd64__) 316 len = cpu_clflush_line_size > 64 ? 128 : 64; 317#else 318 len = 64; 319#endif 320 if (spg_len != -1) { 321 printf("Invalid hw.cxgbe.spg_len value (%d)," 322 " using %d instead.\n", spg_len, len); 323 } 324 spg_len = len; 325 } 326 327 if (cong_drop < -1 || cong_drop > 1) { 328 printf("Invalid hw.cxgbe.cong_drop value (%d)," 329 " using 0 instead.\n", cong_drop); 330 cong_drop = 0; 331 } 332} 333 334void 335t4_init_sge_cpl_handlers(struct adapter *sc) 336{ 337 338 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg); 339 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg); 340 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update); 341 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); 342 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl); 343} 344 345/* 346 * adap->params.vpd.cclk must be set up before this is called. 347 */ 348void 349t4_tweak_chip_settings(struct adapter *sc) 350{ 351 int i; 352 uint32_t v, m; 353 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; 354 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk; 355 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ 356 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 357 static int sge_flbuf_sizes[] = { 358 MCLBYTES, 359#if MJUMPAGESIZE != MCLBYTES 360 MJUMPAGESIZE, 361 MJUMPAGESIZE - CL_METADATA_SIZE, 362 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE, 363#endif 364 MJUM9BYTES, 365 MJUM16BYTES, 366 MCLBYTES - MSIZE - CL_METADATA_SIZE, 367 MJUM9BYTES - CL_METADATA_SIZE, 368 MJUM16BYTES - CL_METADATA_SIZE, 369 }; 370 371 KASSERT(sc->flags & MASTER_PF, 372 ("%s: trying to change chip settings when not master.", __func__)); 373 374 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 375 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 376 V_EGRSTATUSPAGESIZE(spg_len == 128); 377 if (is_t4(sc) && (fl_pad || buffer_packing)) { 378 /* t4_fl_pack has the correct value even when fl_pad = 0 */ 379 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 380 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 381 } else if (is_t5(sc) && fl_pad) { 382 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 383 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 384 } 385 t4_set_reg_field(sc, A_SGE_CONTROL, m, v); 386 387 if (is_t5(sc) && buffer_packing) { 388 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 389 if (t5_fl_pack == 16) 390 v = V_INGPACKBOUNDARY(0); 391 else 392 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 393 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v); 394 } 395 396 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 397 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 398 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 399 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 400 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 401 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 402 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 403 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 404 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v); 405 406 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES, 407 ("%s: hw buffer size table too big", __func__)); 408 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) { 409 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), 410 sge_flbuf_sizes[i]); 411 } 412 413 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) | 414 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]); 415 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v); 416 417 KASSERT(intr_timer[0] <= timer_max, 418 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0], 419 timer_max)); 420 for (i = 1; i < nitems(intr_timer); i++) { 421 KASSERT(intr_timer[i] >= intr_timer[i - 1], 422 ("%s: timers not listed in increasing order (%d)", 423 __func__, i)); 424 425 while (intr_timer[i] > timer_max) { 426 if (i == nitems(intr_timer) - 1) { 427 intr_timer[i] = timer_max; 428 break; 429 } 430 intr_timer[i] += intr_timer[i - 1]; 431 intr_timer[i] /= 2; 432 } 433 } 434 435 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) | 436 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1])); 437 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v); 438 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) | 439 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3])); 440 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v); 441 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) | 442 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5])); 443 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v); 444 445 if (cong_drop == 0) { 446 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 447 F_TUNNELCNGDROP3; 448 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0); 449 } 450 451 /* 4K, 16K, 64K, 256K DDP "page sizes" */ 452 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 453 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v); 454 455 m = v = F_TDDPTAGTCB; 456 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v); 457 458 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 459 F_RESETDDPOFFSET; 460 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 461 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v); 462} 463 464/* 465 * SGE wants the buffer to be at least 64B and then a multiple of the pad 466 * boundary or 16, whichever is greater. 467 */ 468static inline int 469hwsz_ok(int hwsz) 470{ 471 int mask = max(fl_pad, 16) - 1; 472 473 return (hwsz >= 64 && (hwsz & mask) == 0); 474} 475 476/* 477 * XXX: driver really should be able to deal with unexpected settings. 478 */ 479int 480t4_read_chip_settings(struct adapter *sc) 481{ 482 struct sge *s = &sc->sge; 483 int i, j, n, rc = 0; 484 uint32_t m, v, r; 485 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE); 486 static int sw_buf_sizes[] = { /* Sorted by size */ 487 MCLBYTES, 488#if MJUMPAGESIZE != MCLBYTES 489 MJUMPAGESIZE, 490#endif 491 MJUM9BYTES, 492 MJUM16BYTES 493 }; 494 struct sw_zone_info *swz, *safe_swz; 495 struct hw_buf_info *hwb; 496 497 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE; 498 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE | 499 V_EGRSTATUSPAGESIZE(spg_len == 128); 500 if (is_t4(sc) && (fl_pad || buffer_packing)) { 501 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 502 v |= V_INGPADBOUNDARY(ilog2(t4_fl_pack) - 5); 503 } else if (is_t5(sc) && fl_pad) { 504 m |= V_INGPADBOUNDARY(M_INGPADBOUNDARY); 505 v |= V_INGPADBOUNDARY(ilog2(fl_pad) - 5); 506 } 507 r = t4_read_reg(sc, A_SGE_CONTROL); 508 if ((r & m) != v) { 509 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r); 510 rc = EINVAL; 511 } 512 513 if (is_t5(sc) && buffer_packing) { 514 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY); 515 if (t5_fl_pack == 16) 516 v = V_INGPACKBOUNDARY(0); 517 else 518 v = V_INGPACKBOUNDARY(ilog2(t5_fl_pack) - 5); 519 r = t4_read_reg(sc, A_SGE_CONTROL2); 520 if ((r & m) != v) { 521 device_printf(sc->dev, 522 "invalid SGE_CONTROL2(0x%x)\n", r); 523 rc = EINVAL; 524 } 525 } 526 s->pack_boundary = is_t4(sc) ? t4_fl_pack : t5_fl_pack; 527 528 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) | 529 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) | 530 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) | 531 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) | 532 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) | 533 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) | 534 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) | 535 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10); 536 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE); 537 if (r != v) { 538 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r); 539 rc = EINVAL; 540 } 541 542 /* Filter out unusable hw buffer sizes entirely (mark with -2). */ 543 hwb = &s->hw_buf_info[0]; 544 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) { 545 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 546 hwb->size = r; 547 hwb->zidx = hwsz_ok(r) ? -1 : -2; 548 hwb->next = -1; 549 } 550 551 /* 552 * Create a sorted list in decreasing order of hw buffer sizes (and so 553 * increasing order of spare area) for each software zone. 554 */ 555 n = 0; /* no usable buffer size to begin with */ 556 swz = &s->sw_zone_info[0]; 557 safe_swz = NULL; 558 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) { 559 int8_t head = -1, tail = -1; 560 561 swz->size = sw_buf_sizes[i]; 562 swz->zone = m_getzone(swz->size); 563 swz->type = m_gettype(swz->size); 564 565 if (swz->size == safest_rx_cluster) 566 safe_swz = swz; 567 568 hwb = &s->hw_buf_info[0]; 569 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) { 570 if (hwb->zidx != -1 || hwb->size > swz->size) 571 continue; 572 hwb->zidx = i; 573 if (head == -1) 574 head = tail = j; 575 else if (hwb->size < s->hw_buf_info[tail].size) { 576 s->hw_buf_info[tail].next = j; 577 tail = j; 578 } else { 579 int8_t *cur; 580 struct hw_buf_info *t; 581 582 for (cur = &head; *cur != -1; cur = &t->next) { 583 t = &s->hw_buf_info[*cur]; 584 if (hwb->size == t->size) { 585 hwb->zidx = -2; 586 break; 587 } 588 if (hwb->size > t->size) { 589 hwb->next = *cur; 590 *cur = j; 591 break; 592 } 593 } 594 } 595 } 596 swz->head_hwidx = head; 597 swz->tail_hwidx = tail; 598 599 if (tail != -1) { 600 n++; 601 if (swz->size - s->hw_buf_info[tail].size >= 602 CL_METADATA_SIZE) 603 sc->flags |= BUF_PACKING_OK; 604 } 605 } 606 if (n == 0) { 607 device_printf(sc->dev, "no usable SGE FL buffer size.\n"); 608 rc = EINVAL; 609 } 610 611 s->safe_hwidx1 = -1; 612 s->safe_hwidx2 = -1; 613 if (safe_swz != NULL) { 614 s->safe_hwidx1 = safe_swz->head_hwidx; 615 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) { 616 int spare; 617 618 hwb = &s->hw_buf_info[i]; 619 spare = safe_swz->size - hwb->size; 620 if (spare < CL_METADATA_SIZE) 621 continue; 622 if (s->safe_hwidx2 == -1 || 623 spare == CL_METADATA_SIZE + MSIZE) 624 s->safe_hwidx2 = i; 625 if (spare >= CL_METADATA_SIZE + MSIZE) 626 break; 627 } 628 } 629 630 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD); 631 s->counter_val[0] = G_THRESHOLD_0(r); 632 s->counter_val[1] = G_THRESHOLD_1(r); 633 s->counter_val[2] = G_THRESHOLD_2(r); 634 s->counter_val[3] = G_THRESHOLD_3(r); 635 636 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1); 637 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc); 638 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc); 639 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3); 640 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc); 641 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc); 642 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5); 643 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc); 644 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc); 645 646 if (cong_drop == 0) { 647 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | 648 F_TUNNELCNGDROP3; 649 r = t4_read_reg(sc, A_TP_PARA_REG3); 650 if (r & m) { 651 device_printf(sc->dev, 652 "invalid TP_PARA_REG3(0x%x)\n", r); 653 rc = EINVAL; 654 } 655 } 656 657 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6); 658 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ); 659 if (r != v) { 660 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r); 661 rc = EINVAL; 662 } 663 664 m = v = F_TDDPTAGTCB; 665 r = t4_read_reg(sc, A_ULP_RX_CTL); 666 if ((r & m) != v) { 667 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r); 668 rc = EINVAL; 669 } 670 671 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET | 672 F_RESETDDPOFFSET; 673 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET; 674 r = t4_read_reg(sc, A_TP_PARA_REG5); 675 if ((r & m) != v) { 676 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r); 677 rc = EINVAL; 678 } 679 680 r = t4_read_reg(sc, A_SGE_CONM_CTRL); 681 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 682 if (is_t4(sc)) 683 s->fl_starve_threshold2 = s->fl_starve_threshold; 684 else 685 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 686 687 /* egress queues: log2 of # of doorbells per BAR2 page */ 688 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 689 r >>= S_QUEUESPERPAGEPF0 + 690 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 691 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 692 693 /* ingress queues: log2 of # of doorbells per BAR2 page */ 694 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 695 r >>= S_QUEUESPERPAGEPF0 + 696 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; 697 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 698 699 t4_init_tp_params(sc); 700 701 t4_read_mtu_tbl(sc, sc->params.mtus, NULL); 702 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd); 703 704 return (rc); 705} 706 707int 708t4_create_dma_tag(struct adapter *sc) 709{ 710 int rc; 711 712 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 713 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, 714 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, 715 NULL, &sc->dmat); 716 if (rc != 0) { 717 device_printf(sc->dev, 718 "failed to create main DMA tag: %d\n", rc); 719 } 720 721 return (rc); 722} 723 724static inline int 725enable_buffer_packing(struct adapter *sc) 726{ 727 728 if (sc->flags & BUF_PACKING_OK && 729 ((is_t5(sc) && buffer_packing) || /* 1 or -1 both ok for T5 */ 730 (is_t4(sc) && buffer_packing == 1))) 731 return (1); 732 return (0); 733} 734 735void 736t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx, 737 struct sysctl_oid_list *children) 738{ 739 740 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes", 741 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A", 742 "freelist buffer sizes"); 743 744 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD, 745 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)"); 746 747 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD, 748 NULL, fl_pad, "payload pad boundary (bytes)"); 749 750 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD, 751 NULL, spg_len, "status page size (bytes)"); 752 753 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD, 754 NULL, cong_drop, "congestion drop setting"); 755 756 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "buffer_packing", CTLFLAG_RD, 757 NULL, enable_buffer_packing(sc), 758 "pack multiple frames in one fl buffer"); 759 760 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD, 761 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)"); 762} 763 764int 765t4_destroy_dma_tag(struct adapter *sc) 766{ 767 if (sc->dmat) 768 bus_dma_tag_destroy(sc->dmat); 769 770 return (0); 771} 772 773/* 774 * Allocate and initialize the firmware event queue and the management queue. 775 * 776 * Returns errno on failure. Resources allocated up to that point may still be 777 * allocated. Caller is responsible for cleanup in case this function fails. 778 */ 779int 780t4_setup_adapter_queues(struct adapter *sc) 781{ 782 int rc; 783 784 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 785 786 sysctl_ctx_init(&sc->ctx); 787 sc->flags |= ADAP_SYSCTL_CTX; 788 789 /* 790 * Firmware event queue 791 */ 792 rc = alloc_fwq(sc); 793 if (rc != 0) 794 return (rc); 795 796 /* 797 * Management queue. This is just a control queue that uses the fwq as 798 * its associated iq. 799 */ 800 rc = alloc_mgmtq(sc); 801 802 return (rc); 803} 804 805/* 806 * Idempotent 807 */ 808int 809t4_teardown_adapter_queues(struct adapter *sc) 810{ 811 812 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 813 814 /* Do this before freeing the queue */ 815 if (sc->flags & ADAP_SYSCTL_CTX) { 816 sysctl_ctx_free(&sc->ctx); 817 sc->flags &= ~ADAP_SYSCTL_CTX; 818 } 819 820 free_mgmtq(sc); 821 free_fwq(sc); 822 823 return (0); 824} 825 826static inline int 827port_intr_count(struct port_info *pi) 828{ 829 int rc = 0; 830 831 if (pi->flags & INTR_RXQ) 832 rc += pi->nrxq; 833#ifdef TCP_OFFLOAD 834 if (pi->flags & INTR_OFLD_RXQ) 835 rc += pi->nofldrxq; 836#endif 837#ifdef DEV_NETMAP 838 if (pi->flags & INTR_NM_RXQ) 839 rc += pi->nnmrxq; 840#endif 841 return (rc); 842} 843 844static inline int 845first_vector(struct port_info *pi) 846{ 847 struct adapter *sc = pi->adapter; 848 int rc = T4_EXTRA_INTR, i; 849 850 if (sc->intr_count == 1) 851 return (0); 852 853 for_each_port(sc, i) { 854 if (i == pi->port_id) 855 break; 856 857 rc += port_intr_count(sc->port[i]); 858 } 859 860 return (rc); 861} 862 863/* 864 * Given an arbitrary "index," come up with an iq that can be used by other 865 * queues (of this port) for interrupt forwarding, SGE egress updates, etc. 866 * The iq returned is guaranteed to be something that takes direct interrupts. 867 */ 868static struct sge_iq * 869port_intr_iq(struct port_info *pi, int idx) 870{ 871 struct adapter *sc = pi->adapter; 872 struct sge *s = &sc->sge; 873 struct sge_iq *iq = NULL; 874 int nintr, i; 875 876 if (sc->intr_count == 1) 877 return (&sc->sge.fwq); 878 879 nintr = port_intr_count(pi); 880 KASSERT(nintr != 0, 881 ("%s: pi %p has no exclusive interrupts, total interrupts = %d", 882 __func__, pi, sc->intr_count)); 883#ifdef DEV_NETMAP 884 /* Exclude netmap queues as they can't take anyone else's interrupts */ 885 if (pi->flags & INTR_NM_RXQ) 886 nintr -= pi->nnmrxq; 887 KASSERT(nintr > 0, 888 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__, 889 pi, nintr, pi->nnmrxq)); 890#endif 891 i = idx % nintr; 892 893 if (pi->flags & INTR_RXQ) { 894 if (i < pi->nrxq) { 895 iq = &s->rxq[pi->first_rxq + i].iq; 896 goto done; 897 } 898 i -= pi->nrxq; 899 } 900#ifdef TCP_OFFLOAD 901 if (pi->flags & INTR_OFLD_RXQ) { 902 if (i < pi->nofldrxq) { 903 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq; 904 goto done; 905 } 906 i -= pi->nofldrxq; 907 } 908#endif 909 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__, 910 pi, pi->flags & INTR_ALL, idx, nintr); 911done: 912 MPASS(iq != NULL); 913 KASSERT(iq->flags & IQ_INTR, 914 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi, 915 pi->flags & INTR_ALL, idx)); 916 return (iq); 917} 918 919/* Maximum payload that can be delivered with a single iq descriptor */ 920static inline int 921mtu_to_max_payload(struct adapter *sc, int mtu, const int toe) 922{ 923 int payload; 924 925#ifdef TCP_OFFLOAD 926 if (toe) { 927 payload = sc->tt.rx_coalesce ? 928 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu; 929 } else { 930#endif 931 /* large enough even when hw VLAN extraction is disabled */ 932 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 933 mtu; 934#ifdef TCP_OFFLOAD 935 } 936#endif 937 payload = roundup2(payload, fl_pad); 938 939 return (payload); 940} 941 942int 943t4_setup_port_queues(struct port_info *pi) 944{ 945 int rc = 0, i, j, intr_idx, iqid; 946 struct sge_rxq *rxq; 947 struct sge_txq *txq; 948 struct sge_wrq *ctrlq; 949#ifdef TCP_OFFLOAD 950 struct sge_ofld_rxq *ofld_rxq; 951 struct sge_wrq *ofld_txq; 952#endif 953#ifdef DEV_NETMAP 954 struct sge_nm_rxq *nm_rxq; 955 struct sge_nm_txq *nm_txq; 956#endif 957 char name[16]; 958 struct adapter *sc = pi->adapter; 959 struct ifnet *ifp = pi->ifp; 960 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); 961 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 962 int maxp, pack, mtu = ifp->if_mtu; 963 964 /* Interrupt vector to start from (when using multiple vectors) */ 965 intr_idx = first_vector(pi); 966 967 /* 968 * First pass over all NIC and TOE rx queues: 969 * a) initialize iq and fl 970 * b) allocate queue iff it will take direct interrupts. 971 */ 972 maxp = mtu_to_max_payload(sc, mtu, 0); 973 pack = enable_buffer_packing(sc); 974 if (pi->flags & INTR_RXQ) { 975 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 976 CTLFLAG_RD, NULL, "rx queues"); 977 } 978 for_each_rxq(pi, i, rxq) { 979 980 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq, 981 RX_IQ_ESIZE); 982 983 snprintf(name, sizeof(name), "%s rxq%d-fl", 984 device_get_nameunit(pi->dev), i); 985 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 986 987 if (pi->flags & INTR_RXQ) { 988 rxq->iq.flags |= IQ_INTR; 989 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 990 if (rc != 0) 991 goto done; 992 intr_idx++; 993 } 994 } 995#ifdef TCP_OFFLOAD 996 maxp = mtu_to_max_payload(sc, mtu, 1); 997 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) { 998 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 999 CTLFLAG_RD, NULL, 1000 "rx queues for offloaded TCP connections"); 1001 } 1002 for_each_ofld_rxq(pi, i, ofld_rxq) { 1003 1004 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, 1005 pi->qsize_rxq, RX_IQ_ESIZE); 1006 1007 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl", 1008 device_get_nameunit(pi->dev), i); 1009 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, pack, name); 1010 1011 if (pi->flags & INTR_OFLD_RXQ) { 1012 ofld_rxq->iq.flags |= IQ_INTR; 1013 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1014 if (rc != 0) 1015 goto done; 1016 intr_idx++; 1017 } 1018 } 1019#endif 1020#ifdef DEV_NETMAP 1021 /* 1022 * We don't have buffers to back the netmap rx queues right now so we 1023 * create the queues in a way that doesn't set off any congestion signal 1024 * in the chip. 1025 */ 1026 if (pi->flags & INTR_NM_RXQ) { 1027 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq", 1028 CTLFLAG_RD, NULL, "rx queues for netmap"); 1029 for_each_nm_rxq(pi, i, nm_rxq) { 1030 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid); 1031 if (rc != 0) 1032 goto done; 1033 intr_idx++; 1034 } 1035 } 1036#endif 1037 1038 /* 1039 * Second pass over all NIC and TOE rx queues. The queues forwarding 1040 * their interrupts are allocated now. 1041 */ 1042 j = 0; 1043 if (!(pi->flags & INTR_RXQ)) { 1044 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", 1045 CTLFLAG_RD, NULL, "rx queues"); 1046 for_each_rxq(pi, i, rxq) { 1047 MPASS(!(rxq->iq.flags & IQ_INTR)); 1048 1049 intr_idx = port_intr_iq(pi, j)->abs_id; 1050 1051 rc = alloc_rxq(pi, rxq, intr_idx, i, oid); 1052 if (rc != 0) 1053 goto done; 1054 j++; 1055 } 1056 } 1057#ifdef TCP_OFFLOAD 1058 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) { 1059 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq", 1060 CTLFLAG_RD, NULL, 1061 "rx queues for offloaded TCP connections"); 1062 for_each_ofld_rxq(pi, i, ofld_rxq) { 1063 MPASS(!(ofld_rxq->iq.flags & IQ_INTR)); 1064 1065 intr_idx = port_intr_iq(pi, j)->abs_id; 1066 1067 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid); 1068 if (rc != 0) 1069 goto done; 1070 j++; 1071 } 1072 } 1073#endif 1074#ifdef DEV_NETMAP 1075 if (!(pi->flags & INTR_NM_RXQ)) 1076 CXGBE_UNIMPLEMENTED(__func__); 1077#endif 1078 1079 /* 1080 * Now the tx queues. Only one pass needed. 1081 */ 1082 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, 1083 NULL, "tx queues"); 1084 j = 0; 1085 for_each_txq(pi, i, txq) { 1086 iqid = port_intr_iq(pi, j)->cntxt_id; 1087 snprintf(name, sizeof(name), "%s txq%d", 1088 device_get_nameunit(pi->dev), i); 1089 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid, 1090 name); 1091 1092 rc = alloc_txq(pi, txq, i, oid); 1093 if (rc != 0) 1094 goto done; 1095 j++; 1096 } 1097#ifdef TCP_OFFLOAD 1098 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq", 1099 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections"); 1100 for_each_ofld_txq(pi, i, ofld_txq) { 1101 struct sysctl_oid *oid2; 1102 1103 iqid = port_intr_iq(pi, j)->cntxt_id; 1104 snprintf(name, sizeof(name), "%s ofld_txq%d", 1105 device_get_nameunit(pi->dev), i); 1106 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan, 1107 iqid, name); 1108 1109 snprintf(name, sizeof(name), "%d", i); 1110 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 1111 name, CTLFLAG_RD, NULL, "offload tx queue"); 1112 1113 rc = alloc_wrq(sc, pi, ofld_txq, oid2); 1114 if (rc != 0) 1115 goto done; 1116 j++; 1117 } 1118#endif 1119#ifdef DEV_NETMAP 1120 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq", 1121 CTLFLAG_RD, NULL, "tx queues for netmap use"); 1122 for_each_nm_txq(pi, i, nm_txq) { 1123 iqid = pi->first_nm_rxq + (j % pi->nnmrxq); 1124 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid); 1125 if (rc != 0) 1126 goto done; 1127 j++; 1128 } 1129#endif 1130 1131 /* 1132 * Finally, the control queue. 1133 */ 1134 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, 1135 NULL, "ctrl queue"); 1136 ctrlq = &sc->sge.ctrlq[pi->port_id]; 1137 iqid = port_intr_iq(pi, 0)->cntxt_id; 1138 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev)); 1139 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name); 1140 rc = alloc_wrq(sc, pi, ctrlq, oid); 1141 1142done: 1143 if (rc) 1144 t4_teardown_port_queues(pi); 1145 1146 return (rc); 1147} 1148 1149/* 1150 * Idempotent 1151 */ 1152int 1153t4_teardown_port_queues(struct port_info *pi) 1154{ 1155 int i; 1156 struct adapter *sc = pi->adapter; 1157 struct sge_rxq *rxq; 1158 struct sge_txq *txq; 1159#ifdef TCP_OFFLOAD 1160 struct sge_ofld_rxq *ofld_rxq; 1161 struct sge_wrq *ofld_txq; 1162#endif 1163#ifdef DEV_NETMAP 1164 struct sge_nm_rxq *nm_rxq; 1165 struct sge_nm_txq *nm_txq; 1166#endif 1167 1168 /* Do this before freeing the queues */ 1169 if (pi->flags & PORT_SYSCTL_CTX) { 1170 sysctl_ctx_free(&pi->ctx); 1171 pi->flags &= ~PORT_SYSCTL_CTX; 1172 } 1173 1174 /* 1175 * Take down all the tx queues first, as they reference the rx queues 1176 * (for egress updates, etc.). 1177 */ 1178 1179 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 1180 1181 for_each_txq(pi, i, txq) { 1182 free_txq(pi, txq); 1183 } 1184#ifdef TCP_OFFLOAD 1185 for_each_ofld_txq(pi, i, ofld_txq) { 1186 free_wrq(sc, ofld_txq); 1187 } 1188#endif 1189#ifdef DEV_NETMAP 1190 for_each_nm_txq(pi, i, nm_txq) 1191 free_nm_txq(pi, nm_txq); 1192#endif 1193 1194 /* 1195 * Then take down the rx queues that forward their interrupts, as they 1196 * reference other rx queues. 1197 */ 1198 1199 for_each_rxq(pi, i, rxq) { 1200 if ((rxq->iq.flags & IQ_INTR) == 0) 1201 free_rxq(pi, rxq); 1202 } 1203#ifdef TCP_OFFLOAD 1204 for_each_ofld_rxq(pi, i, ofld_rxq) { 1205 if ((ofld_rxq->iq.flags & IQ_INTR) == 0) 1206 free_ofld_rxq(pi, ofld_rxq); 1207 } 1208#endif 1209#ifdef DEV_NETMAP 1210 for_each_nm_rxq(pi, i, nm_rxq) 1211 free_nm_rxq(pi, nm_rxq); 1212#endif 1213 1214 /* 1215 * Then take down the rx queues that take direct interrupts. 1216 */ 1217 1218 for_each_rxq(pi, i, rxq) { 1219 if (rxq->iq.flags & IQ_INTR) 1220 free_rxq(pi, rxq); 1221 } 1222#ifdef TCP_OFFLOAD 1223 for_each_ofld_rxq(pi, i, ofld_rxq) { 1224 if (ofld_rxq->iq.flags & IQ_INTR) 1225 free_ofld_rxq(pi, ofld_rxq); 1226 } 1227#endif 1228#ifdef DEV_NETMAP 1229 CXGBE_UNIMPLEMENTED(__func__); 1230#endif 1231 1232 return (0); 1233} 1234 1235/* 1236 * Deals with errors and the firmware event queue. All data rx queues forward 1237 * their interrupt to the firmware event queue. 1238 */ 1239void 1240t4_intr_all(void *arg) 1241{ 1242 struct adapter *sc = arg; 1243 struct sge_iq *fwq = &sc->sge.fwq; 1244 1245 t4_intr_err(arg); 1246 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) { 1247 service_iq(fwq, 0); 1248 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE); 1249 } 1250} 1251 1252/* Deals with error interrupts */ 1253void 1254t4_intr_err(void *arg) 1255{ 1256 struct adapter *sc = arg; 1257 1258 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); 1259 t4_slow_intr_handler(sc); 1260} 1261 1262void 1263t4_intr_evt(void *arg) 1264{ 1265 struct sge_iq *iq = arg; 1266 1267 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1268 service_iq(iq, 0); 1269 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1270 } 1271} 1272 1273void 1274t4_intr(void *arg) 1275{ 1276 struct sge_iq *iq = arg; 1277 1278 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) { 1279 service_iq(iq, 0); 1280 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE); 1281 } 1282} 1283 1284/* 1285 * Deals with anything and everything on the given ingress queue. 1286 */ 1287static int 1288service_iq(struct sge_iq *iq, int budget) 1289{ 1290 struct sge_iq *q; 1291 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */ 1292 struct sge_fl *fl = &rxq->fl; /* Use iff IQ_HAS_FL */ 1293 struct adapter *sc = iq->adapter; 1294 struct rsp_ctrl *ctrl; 1295 const struct rss_header *rss; 1296 int ndescs = 0, limit, fl_bufs_used = 0; 1297 int rsp_type; 1298 uint32_t lq; 1299 struct mbuf *m0; 1300 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql); 1301#if defined(INET) || defined(INET6) 1302 const struct timeval lro_timeout = {0, sc->lro_timeout}; 1303#endif 1304 1305 limit = budget ? budget : iq->qsize / 8; 1306 1307 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq)); 1308 1309 /* 1310 * We always come back and check the descriptor ring for new indirect 1311 * interrupts and other responses after running a single handler. 1312 */ 1313 for (;;) { 1314 while (is_new_response(iq, &ctrl)) { 1315 1316 rmb(); 1317 1318 m0 = NULL; 1319 rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); 1320 lq = be32toh(ctrl->pldbuflen_qid); 1321 rss = (const void *)iq->cdesc; 1322 1323 switch (rsp_type) { 1324 case X_RSPD_TYPE_FLBUF: 1325 1326 KASSERT(iq->flags & IQ_HAS_FL, 1327 ("%s: data for an iq (%p) with no freelist", 1328 __func__, iq)); 1329 1330 m0 = get_fl_payload(sc, fl, lq, &fl_bufs_used); 1331 if (__predict_false(m0 == NULL)) 1332 goto process_iql; 1333#ifdef T4_PKT_TIMESTAMP 1334 /* 1335 * 60 bit timestamp for the payload is 1336 * *(uint64_t *)m0->m_pktdat. Note that it is 1337 * in the leading free-space in the mbuf. The 1338 * kernel can clobber it during a pullup, 1339 * m_copymdata, etc. You need to make sure that 1340 * the mbuf reaches you unmolested if you care 1341 * about the timestamp. 1342 */ 1343 *(uint64_t *)m0->m_pktdat = 1344 be64toh(ctrl->u.last_flit) & 1345 0xfffffffffffffff; 1346#endif 1347 1348 /* fall through */ 1349 1350 case X_RSPD_TYPE_CPL: 1351 KASSERT(rss->opcode < NUM_CPL_CMDS, 1352 ("%s: bad opcode %02x.", __func__, 1353 rss->opcode)); 1354 sc->cpl_handler[rss->opcode](iq, rss, m0); 1355 break; 1356 1357 case X_RSPD_TYPE_INTR: 1358 1359 /* 1360 * Interrupts should be forwarded only to queues 1361 * that are not forwarding their interrupts. 1362 * This means service_iq can recurse but only 1 1363 * level deep. 1364 */ 1365 KASSERT(budget == 0, 1366 ("%s: budget %u, rsp_type %u", __func__, 1367 budget, rsp_type)); 1368 1369 /* 1370 * There are 1K interrupt-capable queues (qids 0 1371 * through 1023). A response type indicating a 1372 * forwarded interrupt with a qid >= 1K is an 1373 * iWARP async notification. 1374 */ 1375 if (lq >= 1024) { 1376 sc->an_handler(iq, ctrl); 1377 break; 1378 } 1379 1380 q = sc->sge.iqmap[lq - sc->sge.iq_start]; 1381 if (atomic_cmpset_int(&q->state, IQS_IDLE, 1382 IQS_BUSY)) { 1383 if (service_iq(q, q->qsize / 8) == 0) { 1384 atomic_cmpset_int(&q->state, 1385 IQS_BUSY, IQS_IDLE); 1386 } else { 1387 STAILQ_INSERT_TAIL(&iql, q, 1388 link); 1389 } 1390 } 1391 break; 1392 1393 default: 1394 KASSERT(0, 1395 ("%s: illegal response type %d on iq %p", 1396 __func__, rsp_type, iq)); 1397 log(LOG_ERR, 1398 "%s: illegal response type %d on iq %p", 1399 device_get_nameunit(sc->dev), rsp_type, iq); 1400 break; 1401 } 1402 1403 if (fl_bufs_used >= 16) { 1404 FL_LOCK(fl); 1405 fl->needed += fl_bufs_used; 1406 refill_fl(sc, fl, 32); 1407 FL_UNLOCK(fl); 1408 fl_bufs_used = 0; 1409 } 1410 1411 iq_next(iq); 1412 if (++ndescs == limit) { 1413 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 1414 V_CIDXINC(ndescs) | 1415 V_INGRESSQID(iq->cntxt_id) | 1416 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1417 ndescs = 0; 1418 1419#if defined(INET) || defined(INET6) 1420 if (iq->flags & IQ_LRO_ENABLED && 1421 sc->lro_timeout != 0) { 1422 tcp_lro_flush_inactive(&rxq->lro, 1423 &lro_timeout); 1424 } 1425#endif 1426 1427 if (budget) { 1428 if (fl_bufs_used) { 1429 FL_LOCK(fl); 1430 fl->needed += fl_bufs_used; 1431 refill_fl(sc, fl, 32); 1432 FL_UNLOCK(fl); 1433 } 1434 return (EINPROGRESS); 1435 } 1436 } 1437 } 1438 1439process_iql: 1440 if (STAILQ_EMPTY(&iql)) 1441 break; 1442 1443 /* 1444 * Process the head only, and send it to the back of the list if 1445 * it's still not done. 1446 */ 1447 q = STAILQ_FIRST(&iql); 1448 STAILQ_REMOVE_HEAD(&iql, link); 1449 if (service_iq(q, q->qsize / 8) == 0) 1450 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE); 1451 else 1452 STAILQ_INSERT_TAIL(&iql, q, link); 1453 } 1454 1455#if defined(INET) || defined(INET6) 1456 if (iq->flags & IQ_LRO_ENABLED) { 1457 struct lro_ctrl *lro = &rxq->lro; 1458 struct lro_entry *l; 1459 1460 while (!SLIST_EMPTY(&lro->lro_active)) { 1461 l = SLIST_FIRST(&lro->lro_active); 1462 SLIST_REMOVE_HEAD(&lro->lro_active, next); 1463 tcp_lro_flush(lro, l); 1464 } 1465 } 1466#endif 1467 1468 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | 1469 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); 1470 1471 if (iq->flags & IQ_HAS_FL) { 1472 int starved; 1473 1474 FL_LOCK(fl); 1475 fl->needed += fl_bufs_used; 1476 starved = refill_fl(sc, fl, 64); 1477 FL_UNLOCK(fl); 1478 if (__predict_false(starved != 0)) 1479 add_fl_to_sfl(sc, fl); 1480 } 1481 1482 return (0); 1483} 1484 1485static inline int 1486cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll) 1487{ 1488 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0; 1489 1490 if (rc) 1491 MPASS(cll->region3 >= CL_METADATA_SIZE); 1492 1493 return (rc); 1494} 1495 1496static inline struct cluster_metadata * 1497cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll, 1498 caddr_t cl) 1499{ 1500 1501 if (cl_has_metadata(fl, cll)) { 1502 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1503 1504 return ((struct cluster_metadata *)(cl + swz->size) - 1); 1505 } 1506 return (NULL); 1507} 1508 1509static int 1510rxb_free(struct mbuf *m, void *arg1, void *arg2) 1511{ 1512 uma_zone_t zone = arg1; 1513 caddr_t cl = arg2; 1514 1515 uma_zfree(zone, cl); 1516 1517 return (EXT_FREE_OK); 1518} 1519 1520/* 1521 * The mbuf returned by this function could be allocated from zone_mbuf or 1522 * constructed in spare room in the cluster. 1523 * 1524 * The mbuf carries the payload in one of these ways 1525 * a) frame inside the mbuf (mbuf from zone_mbuf) 1526 * b) m_cljset (for clusters without metadata) zone_mbuf 1527 * c) m_extaddref (cluster with metadata) inline mbuf 1528 * d) m_extaddref (cluster with metadata) zone_mbuf 1529 */ 1530static struct mbuf * 1531get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int total, int flags) 1532{ 1533 struct mbuf *m; 1534 struct fl_sdesc *sd = &fl->sdesc[fl->cidx]; 1535 struct cluster_layout *cll = &sd->cll; 1536 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 1537 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx]; 1538 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl); 1539 int len, padded_len; 1540 caddr_t payload; 1541 1542 len = min(total, hwb->size - fl->rx_offset); 1543 padded_len = roundup2(len, fl_pad); 1544 payload = sd->cl + cll->region1 + fl->rx_offset; 1545 1546 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) { 1547 1548 /* 1549 * Copy payload into a freshly allocated mbuf. 1550 */ 1551 1552 m = flags & M_PKTHDR ? 1553 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1554 if (m == NULL) 1555 return (NULL); 1556 fl->mbuf_allocated++; 1557#ifdef T4_PKT_TIMESTAMP 1558 /* Leave room for a timestamp */ 1559 m->m_data += 8; 1560#endif 1561 /* copy data to mbuf */ 1562 bcopy(payload, mtod(m, caddr_t), len); 1563 1564 } else if (sd->nimbuf * MSIZE < cll->region1) { 1565 1566 /* 1567 * There's spare room in the cluster for an mbuf. Create one 1568 * and associate it with the payload that's in the cluster. 1569 */ 1570 1571 MPASS(clm != NULL); 1572 m = (struct mbuf *)(sd->cl + sd->nimbuf * MSIZE); 1573 /* No bzero required */ 1574 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA, flags | M_NOFREE)) 1575 return (NULL); 1576 fl->mbuf_inlined++; 1577 m_extaddref(m, payload, padded_len, &clm->refcount, rxb_free, 1578 swz->zone, sd->cl); 1579 sd->nimbuf++; 1580 1581 } else { 1582 1583 /* 1584 * Grab an mbuf from zone_mbuf and associate it with the 1585 * payload in the cluster. 1586 */ 1587 1588 m = flags & M_PKTHDR ? 1589 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA); 1590 if (m == NULL) 1591 return (NULL); 1592 fl->mbuf_allocated++; 1593 if (clm != NULL) { 1594 m_extaddref(m, payload, padded_len, &clm->refcount, 1595 rxb_free, swz->zone, sd->cl); 1596 sd->nembuf++; 1597 } else { 1598 m_cljset(m, sd->cl, swz->type); 1599 sd->cl = NULL; /* consumed, not a recycle candidate */ 1600 } 1601 } 1602 if (flags & M_PKTHDR) 1603 m->m_pkthdr.len = total; 1604 m->m_len = len; 1605 1606 if (fl->flags & FL_BUF_PACKING) { 1607 fl->rx_offset += roundup2(padded_len, sc->sge.pack_boundary); 1608 MPASS(fl->rx_offset <= hwb->size); 1609 if (fl->rx_offset < hwb->size) 1610 return (m); /* without advancing the cidx */ 1611 } 1612 1613 if (__predict_false(++fl->cidx == fl->cap)) 1614 fl->cidx = 0; 1615 fl->rx_offset = 0; 1616 1617 return (m); 1618} 1619 1620static struct mbuf * 1621get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf, 1622 int *fl_bufs_used) 1623{ 1624 struct mbuf *m0, *m, **pnext; 1625 u_int nbuf, len; 1626 1627 /* 1628 * No assertion for the fl lock because we don't need it. This routine 1629 * is called only from the rx interrupt handler and it only updates 1630 * fl->cidx. (Contrast that with fl->pidx/fl->needed which could be 1631 * updated in the rx interrupt handler or the starvation helper routine. 1632 * That's why code that manipulates fl->pidx/fl->needed needs the fl 1633 * lock but this routine does not). 1634 */ 1635 1636 nbuf = 0; 1637 len = G_RSPD_LEN(len_newbuf); 1638 if (__predict_false(fl->m0 != NULL)) { 1639 M_ASSERTPKTHDR(fl->m0); 1640 MPASS(len == fl->m0->m_pkthdr.len); 1641 MPASS(fl->remaining < len); 1642 1643 m0 = fl->m0; 1644 pnext = fl->pnext; 1645 len = fl->remaining; 1646 fl->m0 = NULL; 1647 goto get_segment; 1648 } 1649 1650 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) { 1651 nbuf++; 1652 fl->rx_offset = 0; 1653 if (__predict_false(++fl->cidx == fl->cap)) 1654 fl->cidx = 0; 1655 } 1656 1657 /* 1658 * Payload starts at rx_offset in the current hw buffer. Its length is 1659 * 'len' and it may span multiple hw buffers. 1660 */ 1661 1662 m0 = get_scatter_segment(sc, fl, len, M_PKTHDR); 1663 if (m0 == NULL) 1664 goto done; 1665 len -= m0->m_len; 1666 pnext = &m0->m_next; 1667 while (len > 0) { 1668 nbuf++; 1669get_segment: 1670 MPASS(fl->rx_offset == 0); 1671 m = get_scatter_segment(sc, fl, len, 0); 1672 if (m == NULL) { 1673 fl->m0 = m0; 1674 fl->pnext = pnext; 1675 fl->remaining = len; 1676 m0 = NULL; 1677 goto done; 1678 } 1679 *pnext = m; 1680 pnext = &m->m_next; 1681 len -= m->m_len; 1682 } 1683 *pnext = NULL; 1684 if (fl->rx_offset == 0) 1685 nbuf++; 1686done: 1687 (*fl_bufs_used) += nbuf; 1688 return (m0); 1689} 1690 1691static int 1692t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0) 1693{ 1694 struct sge_rxq *rxq = iq_to_rxq(iq); 1695 struct ifnet *ifp = rxq->ifp; 1696 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1); 1697#if defined(INET) || defined(INET6) 1698 struct lro_ctrl *lro = &rxq->lro; 1699#endif 1700 1701 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__, 1702 rss->opcode)); 1703 1704 m0->m_pkthdr.len -= fl_pktshift; 1705 m0->m_len -= fl_pktshift; 1706 m0->m_data += fl_pktshift; 1707 1708 m0->m_pkthdr.rcvif = ifp; 1709 m0->m_flags |= M_FLOWID; 1710 m0->m_pkthdr.flowid = be32toh(rss->hash_val); 1711 1712 if (cpl->csum_calc && !cpl->err_vec) { 1713 if (ifp->if_capenable & IFCAP_RXCSUM && 1714 cpl->l2info & htobe32(F_RXF_IP)) { 1715 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | 1716 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1717 rxq->rxcsum++; 1718 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 && 1719 cpl->l2info & htobe32(F_RXF_IP6)) { 1720 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 | 1721 CSUM_PSEUDO_HDR); 1722 rxq->rxcsum++; 1723 } 1724 1725 if (__predict_false(cpl->ip_frag)) 1726 m0->m_pkthdr.csum_data = be16toh(cpl->csum); 1727 else 1728 m0->m_pkthdr.csum_data = 0xffff; 1729 } 1730 1731 if (cpl->vlan_ex) { 1732 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); 1733 m0->m_flags |= M_VLANTAG; 1734 rxq->vlan_extraction++; 1735 } 1736 1737#if defined(INET) || defined(INET6) 1738 if (cpl->l2info & htobe32(F_RXF_LRO) && 1739 iq->flags & IQ_LRO_ENABLED && 1740 tcp_lro_rx(lro, m0, 0) == 0) { 1741 /* queued for LRO */ 1742 } else 1743#endif 1744 ifp->if_input(ifp, m0); 1745 1746 return (0); 1747} 1748 1749/* 1750 * Doesn't fail. Holds on to work requests it can't send right away. 1751 */ 1752void 1753t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr) 1754{ 1755 struct sge_eq *eq = &wrq->eq; 1756 int can_reclaim; 1757 caddr_t dst; 1758 1759 TXQ_LOCK_ASSERT_OWNED(wrq); 1760#ifdef TCP_OFFLOAD 1761 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD || 1762 (eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1763 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1764#else 1765 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL, 1766 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1767#endif 1768 1769 if (__predict_true(wr != NULL)) 1770 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link); 1771 1772 can_reclaim = reclaimable(eq); 1773 if (__predict_false(eq->flags & EQ_STALLED)) { 1774 if (can_reclaim < tx_resume_threshold(eq)) 1775 return; 1776 eq->flags &= ~EQ_STALLED; 1777 eq->unstalled++; 1778 } 1779 eq->cidx += can_reclaim; 1780 eq->avail += can_reclaim; 1781 if (__predict_false(eq->cidx >= eq->cap)) 1782 eq->cidx -= eq->cap; 1783 1784 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) { 1785 int ndesc; 1786 1787 if (__predict_false(wr->wr_len < 0 || 1788 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) { 1789 1790#ifdef INVARIANTS 1791 panic("%s: work request with length %d", __func__, 1792 wr->wr_len); 1793#endif 1794#ifdef KDB 1795 kdb_backtrace(); 1796#endif 1797 log(LOG_ERR, "%s: %s work request with length %d", 1798 device_get_nameunit(sc->dev), __func__, wr->wr_len); 1799 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1800 free_wrqe(wr); 1801 continue; 1802 } 1803 1804 ndesc = howmany(wr->wr_len, EQ_ESIZE); 1805 if (eq->avail < ndesc) { 1806 wrq->no_desc++; 1807 break; 1808 } 1809 1810 dst = (void *)&eq->desc[eq->pidx]; 1811 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len); 1812 1813 eq->pidx += ndesc; 1814 eq->avail -= ndesc; 1815 if (__predict_false(eq->pidx >= eq->cap)) 1816 eq->pidx -= eq->cap; 1817 1818 eq->pending += ndesc; 1819 if (eq->pending >= 8) 1820 ring_eq_db(sc, eq); 1821 1822 wrq->tx_wrs++; 1823 STAILQ_REMOVE_HEAD(&wrq->wr_list, link); 1824 free_wrqe(wr); 1825 1826 if (eq->avail < 8) { 1827 can_reclaim = reclaimable(eq); 1828 eq->cidx += can_reclaim; 1829 eq->avail += can_reclaim; 1830 if (__predict_false(eq->cidx >= eq->cap)) 1831 eq->cidx -= eq->cap; 1832 } 1833 } 1834 1835 if (eq->pending) 1836 ring_eq_db(sc, eq); 1837 1838 if (wr != NULL) { 1839 eq->flags |= EQ_STALLED; 1840 if (callout_pending(&eq->tx_callout) == 0) 1841 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 1842 } 1843} 1844 1845/* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ 1846#define TXPKTS_PKT_HDR ((\ 1847 sizeof(struct ulp_txpkt) + \ 1848 sizeof(struct ulptx_idata) + \ 1849 sizeof(struct cpl_tx_pkt_core) \ 1850 ) / 8) 1851 1852/* Header of a coalesced tx WR, before SGL of first packet (in flits) */ 1853#define TXPKTS_WR_HDR (\ 1854 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ 1855 TXPKTS_PKT_HDR) 1856 1857/* Header of a tx WR, before SGL of first packet (in flits) */ 1858#define TXPKT_WR_HDR ((\ 1859 sizeof(struct fw_eth_tx_pkt_wr) + \ 1860 sizeof(struct cpl_tx_pkt_core) \ 1861 ) / 8 ) 1862 1863/* Header of a tx LSO WR, before SGL of first packet (in flits) */ 1864#define TXPKT_LSO_WR_HDR ((\ 1865 sizeof(struct fw_eth_tx_pkt_wr) + \ 1866 sizeof(struct cpl_tx_pkt_lso_core) + \ 1867 sizeof(struct cpl_tx_pkt_core) \ 1868 ) / 8 ) 1869 1870int 1871t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) 1872{ 1873 struct port_info *pi = (void *)ifp->if_softc; 1874 struct adapter *sc = pi->adapter; 1875 struct sge_eq *eq = &txq->eq; 1876 struct buf_ring *br = txq->br; 1877 struct mbuf *next; 1878 int rc, coalescing, can_reclaim; 1879 struct txpkts txpkts; 1880 struct sgl sgl; 1881 1882 TXQ_LOCK_ASSERT_OWNED(txq); 1883 KASSERT(m, ("%s: called with nothing to do.", __func__)); 1884 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH, 1885 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK)); 1886 1887 prefetch(&eq->desc[eq->pidx]); 1888 prefetch(&txq->sdesc[eq->pidx]); 1889 1890 txpkts.npkt = 0;/* indicates there's nothing in txpkts */ 1891 coalescing = 0; 1892 1893 can_reclaim = reclaimable(eq); 1894 if (__predict_false(eq->flags & EQ_STALLED)) { 1895 if (can_reclaim < tx_resume_threshold(eq)) { 1896 txq->m = m; 1897 return (0); 1898 } 1899 eq->flags &= ~EQ_STALLED; 1900 eq->unstalled++; 1901 } 1902 1903 if (__predict_false(eq->flags & EQ_DOOMED)) { 1904 m_freem(m); 1905 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) 1906 m_freem(m); 1907 return (ENETDOWN); 1908 } 1909 1910 if (eq->avail < 8 && can_reclaim) 1911 reclaim_tx_descs(txq, can_reclaim, 32); 1912 1913 for (; m; m = next ? next : drbr_dequeue(ifp, br)) { 1914 1915 if (eq->avail < 8) 1916 break; 1917 1918 next = m->m_nextpkt; 1919 m->m_nextpkt = NULL; 1920 1921 if (next || buf_ring_peek(br)) 1922 coalescing = 1; 1923 1924 rc = get_pkt_sgl(txq, &m, &sgl, coalescing); 1925 if (rc != 0) { 1926 if (rc == ENOMEM) { 1927 1928 /* Short of resources, suspend tx */ 1929 1930 m->m_nextpkt = next; 1931 break; 1932 } 1933 1934 /* 1935 * Unrecoverable error for this packet, throw it away 1936 * and move on to the next. get_pkt_sgl may already 1937 * have freed m (it will be NULL in that case and the 1938 * m_freem here is still safe). 1939 */ 1940 1941 m_freem(m); 1942 continue; 1943 } 1944 1945 if (coalescing && 1946 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { 1947 1948 /* Successfully absorbed into txpkts */ 1949 1950 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); 1951 goto doorbell; 1952 } 1953 1954 /* 1955 * We weren't coalescing to begin with, or current frame could 1956 * not be coalesced (add_to_txpkts flushes txpkts if a frame 1957 * given to it can't be coalesced). Either way there should be 1958 * nothing in txpkts. 1959 */ 1960 KASSERT(txpkts.npkt == 0, 1961 ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); 1962 1963 /* We're sending out individual packets now */ 1964 coalescing = 0; 1965 1966 if (eq->avail < 8) 1967 reclaim_tx_descs(txq, 0, 8); 1968 rc = write_txpkt_wr(pi, txq, m, &sgl); 1969 if (rc != 0) { 1970 1971 /* Short of hardware descriptors, suspend tx */ 1972 1973 /* 1974 * This is an unlikely but expensive failure. We've 1975 * done all the hard work (DMA mappings etc.) and now we 1976 * can't send out the packet. What's worse, we have to 1977 * spend even more time freeing up everything in sgl. 1978 */ 1979 txq->no_desc++; 1980 free_pkt_sgl(txq, &sgl); 1981 1982 m->m_nextpkt = next; 1983 break; 1984 } 1985 1986 ETHER_BPF_MTAP(ifp, m); 1987 if (sgl.nsegs == 0) 1988 m_freem(m); 1989doorbell: 1990 if (eq->pending >= 8) 1991 ring_eq_db(sc, eq); 1992 1993 can_reclaim = reclaimable(eq); 1994 if (can_reclaim >= 32) 1995 reclaim_tx_descs(txq, can_reclaim, 64); 1996 } 1997 1998 if (txpkts.npkt > 0) 1999 write_txpkts_wr(txq, &txpkts); 2000 2001 /* 2002 * m not NULL means there was an error but we haven't thrown it away. 2003 * This can happen when we're short of tx descriptors (no_desc) or maybe 2004 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim 2005 * will get things going again. 2006 */ 2007 if (m && !(eq->flags & EQ_CRFLUSHED)) { 2008 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; 2009 2010 /* 2011 * If EQ_CRFLUSHED is not set then we know we have at least one 2012 * available descriptor because any WR that reduces eq->avail to 2013 * 0 also sets EQ_CRFLUSHED. 2014 */ 2015 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__)); 2016 2017 txsd->desc_used = 1; 2018 txsd->credits = 0; 2019 write_eqflush_wr(eq); 2020 } 2021 txq->m = m; 2022 2023 if (eq->pending) 2024 ring_eq_db(sc, eq); 2025 2026 reclaim_tx_descs(txq, 0, 128); 2027 2028 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0) 2029 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq); 2030 2031 return (0); 2032} 2033 2034void 2035t4_update_fl_bufsize(struct ifnet *ifp) 2036{ 2037 struct port_info *pi = ifp->if_softc; 2038 struct adapter *sc = pi->adapter; 2039 struct sge_rxq *rxq; 2040#ifdef TCP_OFFLOAD 2041 struct sge_ofld_rxq *ofld_rxq; 2042#endif 2043 struct sge_fl *fl; 2044 int i, maxp, mtu = ifp->if_mtu; 2045 2046 maxp = mtu_to_max_payload(sc, mtu, 0); 2047 for_each_rxq(pi, i, rxq) { 2048 fl = &rxq->fl; 2049 2050 FL_LOCK(fl); 2051 find_best_refill_source(sc, fl, maxp); 2052 FL_UNLOCK(fl); 2053 } 2054#ifdef TCP_OFFLOAD 2055 maxp = mtu_to_max_payload(sc, mtu, 1); 2056 for_each_ofld_rxq(pi, i, ofld_rxq) { 2057 fl = &ofld_rxq->fl; 2058 2059 FL_LOCK(fl); 2060 find_best_refill_source(sc, fl, maxp); 2061 FL_UNLOCK(fl); 2062 } 2063#endif 2064} 2065 2066int 2067can_resume_tx(struct sge_eq *eq) 2068{ 2069 return (reclaimable(eq) >= tx_resume_threshold(eq)); 2070} 2071 2072static inline void 2073init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, 2074 int qsize, int esize) 2075{ 2076 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, 2077 ("%s: bad tmr_idx %d", __func__, tmr_idx)); 2078 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ 2079 ("%s: bad pktc_idx %d", __func__, pktc_idx)); 2080 2081 iq->flags = 0; 2082 iq->adapter = sc; 2083 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx); 2084 iq->intr_pktc_idx = SGE_NCOUNTERS - 1; 2085 if (pktc_idx >= 0) { 2086 iq->intr_params |= F_QINTR_CNT_EN; 2087 iq->intr_pktc_idx = pktc_idx; 2088 } 2089 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */ 2090 iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ 2091} 2092 2093static inline void 2094init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, int pack, 2095 char *name) 2096{ 2097 2098 fl->qsize = qsize; 2099 strlcpy(fl->lockname, name, sizeof(fl->lockname)); 2100 if (pack) 2101 fl->flags |= FL_BUF_PACKING; 2102 find_best_refill_source(sc, fl, maxp); 2103 find_safe_refill_source(sc, fl); 2104} 2105 2106static inline void 2107init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan, 2108 uint16_t iqid, char *name) 2109{ 2110 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan)); 2111 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype)); 2112 2113 eq->flags = eqtype & EQ_TYPEMASK; 2114 eq->tx_chan = tx_chan; 2115 eq->iqid = iqid; 2116 eq->qsize = qsize; 2117 strlcpy(eq->lockname, name, sizeof(eq->lockname)); 2118 2119 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq); 2120 callout_init(&eq->tx_callout, CALLOUT_MPSAFE); 2121} 2122 2123static int 2124alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, 2125 bus_dmamap_t *map, bus_addr_t *pa, void **va) 2126{ 2127 int rc; 2128 2129 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, 2130 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); 2131 if (rc != 0) { 2132 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); 2133 goto done; 2134 } 2135 2136 rc = bus_dmamem_alloc(*tag, va, 2137 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); 2138 if (rc != 0) { 2139 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); 2140 goto done; 2141 } 2142 2143 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); 2144 if (rc != 0) { 2145 device_printf(sc->dev, "cannot load DMA map: %d\n", rc); 2146 goto done; 2147 } 2148done: 2149 if (rc) 2150 free_ring(sc, *tag, *map, *pa, *va); 2151 2152 return (rc); 2153} 2154 2155static int 2156free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, 2157 bus_addr_t pa, void *va) 2158{ 2159 if (pa) 2160 bus_dmamap_unload(tag, map); 2161 if (va) 2162 bus_dmamem_free(tag, va, map); 2163 if (tag) 2164 bus_dma_tag_destroy(tag); 2165 2166 return (0); 2167} 2168 2169/* 2170 * Allocates the ring for an ingress queue and an optional freelist. If the 2171 * freelist is specified it will be allocated and then associated with the 2172 * ingress queue. 2173 * 2174 * Returns errno on failure. Resources allocated up to that point may still be 2175 * allocated. Caller is responsible for cleanup in case this function fails. 2176 * 2177 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then 2178 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies 2179 * the abs_id of the ingress queue to which its interrupts should be forwarded. 2180 */ 2181static int 2182alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, 2183 int intr_idx, int cong) 2184{ 2185 int rc, i, cntxt_id; 2186 size_t len; 2187 struct fw_iq_cmd c; 2188 struct adapter *sc = iq->adapter; 2189 __be32 v = 0; 2190 2191 len = iq->qsize * iq->esize; 2192 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, 2193 (void **)&iq->desc); 2194 if (rc != 0) 2195 return (rc); 2196 2197 bzero(&c, sizeof(c)); 2198 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 2199 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 2200 V_FW_IQ_CMD_VFN(0)); 2201 2202 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 2203 FW_LEN16(c)); 2204 2205 /* Special handling for firmware event queue */ 2206 if (iq == &sc->sge.fwq) 2207 v |= F_FW_IQ_CMD_IQASYNCH; 2208 2209 if (iq->flags & IQ_INTR) { 2210 KASSERT(intr_idx < sc->intr_count, 2211 ("%s: invalid direct intr_idx %d", __func__, intr_idx)); 2212 } else 2213 v |= F_FW_IQ_CMD_IQANDST; 2214 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); 2215 2216 c.type_to_iqandstindex = htobe32(v | 2217 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 2218 V_FW_IQ_CMD_VIID(pi->viid) | 2219 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 2220 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | 2221 F_FW_IQ_CMD_IQGTSMODE | 2222 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | 2223 V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); 2224 c.iqsize = htobe16(iq->qsize); 2225 c.iqaddr = htobe64(iq->ba); 2226 if (cong >= 0) 2227 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); 2228 2229 if (fl) { 2230 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); 2231 2232 len = fl->qsize * RX_FL_ESIZE; 2233 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, 2234 &fl->ba, (void **)&fl->desc); 2235 if (rc) 2236 return (rc); 2237 2238 /* Allocate space for one software descriptor per buffer. */ 2239 fl->cap = (fl->qsize - spg_len / RX_FL_ESIZE) * 8; 2240 rc = alloc_fl_sdesc(fl); 2241 if (rc != 0) { 2242 device_printf(sc->dev, 2243 "failed to setup fl software descriptors: %d\n", 2244 rc); 2245 return (rc); 2246 } 2247 fl->needed = fl->cap; 2248 fl->lowat = fl->flags & FL_BUF_PACKING ? 2249 roundup2(sc->sge.fl_starve_threshold2, 8) : 2250 roundup2(sc->sge.fl_starve_threshold, 8); 2251 2252 c.iqns_to_fl0congen |= 2253 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 2254 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 2255 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 2256 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN : 2257 0)); 2258 if (cong >= 0) { 2259 c.iqns_to_fl0congen |= 2260 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | 2261 F_FW_IQ_CMD_FL0CONGCIF | 2262 F_FW_IQ_CMD_FL0CONGEN); 2263 } 2264 c.fl0dcaen_to_fl0cidxfthresh = 2265 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | 2266 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 2267 c.fl0size = htobe16(fl->qsize); 2268 c.fl0addr = htobe64(fl->ba); 2269 } 2270 2271 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2272 if (rc != 0) { 2273 device_printf(sc->dev, 2274 "failed to create ingress queue: %d\n", rc); 2275 return (rc); 2276 } 2277 2278 iq->cdesc = iq->desc; 2279 iq->cidx = 0; 2280 iq->gen = 1; 2281 iq->intr_next = iq->intr_params; 2282 iq->cntxt_id = be16toh(c.iqid); 2283 iq->abs_id = be16toh(c.physiqid); 2284 iq->flags |= IQ_ALLOCATED; 2285 2286 cntxt_id = iq->cntxt_id - sc->sge.iq_start; 2287 if (cntxt_id >= sc->sge.niq) { 2288 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, 2289 cntxt_id, sc->sge.niq - 1); 2290 } 2291 sc->sge.iqmap[cntxt_id] = iq; 2292 2293 if (fl) { 2294 fl->cntxt_id = be16toh(c.fl0id); 2295 fl->pidx = fl->cidx = 0; 2296 2297 cntxt_id = fl->cntxt_id - sc->sge.eq_start; 2298 if (cntxt_id >= sc->sge.neq) { 2299 panic("%s: fl->cntxt_id (%d) more than the max (%d)", 2300 __func__, cntxt_id, sc->sge.neq - 1); 2301 } 2302 sc->sge.eqmap[cntxt_id] = (void *)fl; 2303 2304 FL_LOCK(fl); 2305 /* Enough to make sure the SGE doesn't think it's starved */ 2306 refill_fl(sc, fl, fl->lowat); 2307 FL_UNLOCK(fl); 2308 2309 iq->flags |= IQ_HAS_FL; 2310 } 2311 2312 if (is_t5(sc) && cong >= 0) { 2313 uint32_t param, val; 2314 2315 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 2316 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 2317 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); 2318 if (cong == 0) 2319 val = 1 << 19; 2320 else { 2321 val = 2 << 19; 2322 for (i = 0; i < 4; i++) { 2323 if (cong & (1 << i)) 2324 val |= 1 << (i << 2); 2325 } 2326 } 2327 2328 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2329 if (rc != 0) { 2330 /* report error but carry on */ 2331 device_printf(sc->dev, 2332 "failed to set congestion manager context for " 2333 "ingress queue %d: %d\n", iq->cntxt_id, rc); 2334 } 2335 } 2336 2337 /* Enable IQ interrupts */ 2338 atomic_store_rel_int(&iq->state, IQS_IDLE); 2339 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | 2340 V_INGRESSQID(iq->cntxt_id)); 2341 2342 return (0); 2343} 2344 2345static int 2346free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) 2347{ 2348 int rc; 2349 struct adapter *sc = iq->adapter; 2350 device_t dev; 2351 2352 if (sc == NULL) 2353 return (0); /* nothing to do */ 2354 2355 dev = pi ? pi->dev : sc->dev; 2356 2357 if (iq->flags & IQ_ALLOCATED) { 2358 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, 2359 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, 2360 fl ? fl->cntxt_id : 0xffff, 0xffff); 2361 if (rc != 0) { 2362 device_printf(dev, 2363 "failed to free queue %p: %d\n", iq, rc); 2364 return (rc); 2365 } 2366 iq->flags &= ~IQ_ALLOCATED; 2367 } 2368 2369 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); 2370 2371 bzero(iq, sizeof(*iq)); 2372 2373 if (fl) { 2374 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, 2375 fl->desc); 2376 2377 if (fl->sdesc) 2378 free_fl_sdesc(sc, fl); 2379 2380 if (mtx_initialized(&fl->fl_lock)) 2381 mtx_destroy(&fl->fl_lock); 2382 2383 bzero(fl, sizeof(*fl)); 2384 } 2385 2386 return (0); 2387} 2388 2389static void 2390add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid, 2391 struct sge_fl *fl) 2392{ 2393 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2394 2395 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2396 "freelist"); 2397 children = SYSCTL_CHILDREN(oid); 2398 2399 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2400 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I", 2401 "SGE context id of the freelist"); 2402 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx, 2403 0, "consumer index"); 2404 if (fl->flags & FL_BUF_PACKING) { 2405 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset", 2406 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset"); 2407 } 2408 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx, 2409 0, "producer index"); 2410 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated", 2411 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated"); 2412 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined", 2413 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters"); 2414 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated", 2415 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated"); 2416 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled", 2417 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled"); 2418 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled", 2419 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)"); 2420} 2421 2422static int 2423alloc_fwq(struct adapter *sc) 2424{ 2425 int rc, intr_idx; 2426 struct sge_iq *fwq = &sc->sge.fwq; 2427 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2428 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2429 2430 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE); 2431 fwq->flags |= IQ_INTR; /* always */ 2432 intr_idx = sc->intr_count > 1 ? 1 : 0; 2433 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); 2434 if (rc != 0) { 2435 device_printf(sc->dev, 2436 "failed to create firmware event queue: %d\n", rc); 2437 return (rc); 2438 } 2439 2440 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD, 2441 NULL, "firmware event queue"); 2442 children = SYSCTL_CHILDREN(oid); 2443 2444 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id", 2445 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I", 2446 "absolute id of the queue"); 2447 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id", 2448 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I", 2449 "SGE context id of the queue"); 2450 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", 2451 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", 2452 "consumer index"); 2453 2454 return (0); 2455} 2456 2457static int 2458free_fwq(struct adapter *sc) 2459{ 2460 return free_iq_fl(NULL, &sc->sge.fwq, NULL); 2461} 2462 2463static int 2464alloc_mgmtq(struct adapter *sc) 2465{ 2466 int rc; 2467 struct sge_wrq *mgmtq = &sc->sge.mgmtq; 2468 char name[16]; 2469 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); 2470 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2471 2472 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD, 2473 NULL, "management queue"); 2474 2475 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev)); 2476 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, 2477 sc->sge.fwq.cntxt_id, name); 2478 rc = alloc_wrq(sc, NULL, mgmtq, oid); 2479 if (rc != 0) { 2480 device_printf(sc->dev, 2481 "failed to create management queue: %d\n", rc); 2482 return (rc); 2483 } 2484 2485 return (0); 2486} 2487 2488static int 2489free_mgmtq(struct adapter *sc) 2490{ 2491 2492 return free_wrq(sc, &sc->sge.mgmtq); 2493} 2494 2495static inline int 2496tnl_cong(struct port_info *pi) 2497{ 2498 2499 if (cong_drop == -1) 2500 return (-1); 2501 else if (cong_drop == 1) 2502 return (0); 2503 else 2504 return (pi->rx_chan_map); 2505} 2506 2507static int 2508alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx, 2509 struct sysctl_oid *oid) 2510{ 2511 int rc; 2512 struct sysctl_oid_list *children; 2513 char name[16]; 2514 2515 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi)); 2516 if (rc != 0) 2517 return (rc); 2518 2519 FL_LOCK(&rxq->fl); 2520 refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8); 2521 FL_UNLOCK(&rxq->fl); 2522 2523#if defined(INET) || defined(INET6) 2524 rc = tcp_lro_init(&rxq->lro); 2525 if (rc != 0) 2526 return (rc); 2527 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ 2528 2529 if (pi->ifp->if_capenable & IFCAP_LRO) 2530 rxq->iq.flags |= IQ_LRO_ENABLED; 2531#endif 2532 rxq->ifp = pi->ifp; 2533 2534 children = SYSCTL_CHILDREN(oid); 2535 2536 snprintf(name, sizeof(name), "%d", idx); 2537 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2538 NULL, "rx queue"); 2539 children = SYSCTL_CHILDREN(oid); 2540 2541 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2542 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", 2543 "absolute id of the queue"); 2544 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2545 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I", 2546 "SGE context id of the queue"); 2547 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2548 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I", 2549 "consumer index"); 2550#if defined(INET) || defined(INET6) 2551 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, 2552 &rxq->lro.lro_queued, 0, NULL); 2553 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, 2554 &rxq->lro.lro_flushed, 0, NULL); 2555#endif 2556 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, 2557 &rxq->rxcsum, "# of times hardware assisted with checksum"); 2558 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", 2559 CTLFLAG_RD, &rxq->vlan_extraction, 2560 "# of times hardware extracted 802.1Q tag"); 2561 2562 add_fl_sysctls(&pi->ctx, oid, &rxq->fl); 2563 2564 return (rc); 2565} 2566 2567static int 2568free_rxq(struct port_info *pi, struct sge_rxq *rxq) 2569{ 2570 int rc; 2571 2572#if defined(INET) || defined(INET6) 2573 if (rxq->lro.ifp) { 2574 tcp_lro_free(&rxq->lro); 2575 rxq->lro.ifp = NULL; 2576 } 2577#endif 2578 2579 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); 2580 if (rc == 0) 2581 bzero(rxq, sizeof(*rxq)); 2582 2583 return (rc); 2584} 2585 2586#ifdef TCP_OFFLOAD 2587static int 2588alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq, 2589 int intr_idx, int idx, struct sysctl_oid *oid) 2590{ 2591 int rc; 2592 struct sysctl_oid_list *children; 2593 char name[16]; 2594 2595 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 2596 pi->rx_chan_map); 2597 if (rc != 0) 2598 return (rc); 2599 2600 children = SYSCTL_CHILDREN(oid); 2601 2602 snprintf(name, sizeof(name), "%d", idx); 2603 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2604 NULL, "rx queue"); 2605 children = SYSCTL_CHILDREN(oid); 2606 2607 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", 2608 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16, 2609 "I", "absolute id of the queue"); 2610 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id", 2611 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16, 2612 "I", "SGE context id of the queue"); 2613 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2614 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I", 2615 "consumer index"); 2616 2617 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl); 2618 2619 return (rc); 2620} 2621 2622static int 2623free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq) 2624{ 2625 int rc; 2626 2627 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl); 2628 if (rc == 0) 2629 bzero(ofld_rxq, sizeof(*ofld_rxq)); 2630 2631 return (rc); 2632} 2633#endif 2634 2635#ifdef DEV_NETMAP 2636static int 2637alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx, 2638 int idx, struct sysctl_oid *oid) 2639{ 2640 int rc; 2641 struct sysctl_oid_list *children; 2642 struct sysctl_ctx_list *ctx; 2643 char name[16]; 2644 size_t len; 2645 struct adapter *sc = pi->adapter; 2646 struct netmap_adapter *na = NA(pi->nm_ifp); 2647 2648 MPASS(na != NULL); 2649 2650 len = pi->qsize_rxq * RX_IQ_ESIZE; 2651 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map, 2652 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc); 2653 if (rc != 0) 2654 return (rc); 2655 2656 len = na->num_rx_desc * RX_FL_ESIZE + spg_len; 2657 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map, 2658 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc); 2659 if (rc != 0) 2660 return (rc); 2661 2662 nm_rxq->pi = pi; 2663 nm_rxq->nid = idx; 2664 nm_rxq->iq_cidx = 0; 2665 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / RX_IQ_ESIZE; 2666 nm_rxq->iq_gen = F_RSPD_GEN; 2667 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 2668 nm_rxq->fl_sidx = na->num_rx_desc; 2669 nm_rxq->intr_idx = intr_idx; 2670 2671 ctx = &pi->ctx; 2672 children = SYSCTL_CHILDREN(oid); 2673 2674 snprintf(name, sizeof(name), "%d", idx); 2675 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, 2676 "rx queue"); 2677 children = SYSCTL_CHILDREN(oid); 2678 2679 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id", 2680 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16, 2681 "I", "absolute id of the queue"); 2682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2683 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16, 2684 "I", "SGE context id of the queue"); 2685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 2686 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I", 2687 "consumer index"); 2688 2689 children = SYSCTL_CHILDREN(oid); 2690 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL, 2691 "freelist"); 2692 children = SYSCTL_CHILDREN(oid); 2693 2694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id", 2695 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16, 2696 "I", "SGE context id of the freelist"); 2697 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, 2698 &nm_rxq->fl_cidx, 0, "consumer index"); 2699 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, 2700 &nm_rxq->fl_pidx, 0, "producer index"); 2701 2702 return (rc); 2703} 2704 2705 2706static int 2707free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq) 2708{ 2709 struct adapter *sc = pi->adapter; 2710 2711 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba, 2712 nm_rxq->iq_desc); 2713 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba, 2714 nm_rxq->fl_desc); 2715 2716 return (0); 2717} 2718 2719static int 2720alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx, 2721 struct sysctl_oid *oid) 2722{ 2723 int rc; 2724 size_t len; 2725 struct adapter *sc = pi->adapter; 2726 struct netmap_adapter *na = NA(pi->nm_ifp); 2727 char name[16]; 2728 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 2729 2730 len = na->num_tx_desc * EQ_ESIZE + spg_len; 2731 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map, 2732 &nm_txq->ba, (void **)&nm_txq->desc); 2733 if (rc) 2734 return (rc); 2735 2736 nm_txq->pidx = nm_txq->cidx = 0; 2737 nm_txq->sidx = na->num_tx_desc; 2738 nm_txq->nid = idx; 2739 nm_txq->iqidx = iqidx; 2740 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 2741 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf)); 2742 2743 snprintf(name, sizeof(name), "%d", idx); 2744 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 2745 NULL, "netmap tx queue"); 2746 children = SYSCTL_CHILDREN(oid); 2747 2748 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 2749 &nm_txq->cntxt_id, 0, "SGE context id of the queue"); 2750 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 2751 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I", 2752 "consumer index"); 2753 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 2754 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I", 2755 "producer index"); 2756 2757 return (rc); 2758} 2759 2760static int 2761free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq) 2762{ 2763 struct adapter *sc = pi->adapter; 2764 2765 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba, 2766 nm_txq->desc); 2767 2768 return (0); 2769} 2770#endif 2771 2772static int 2773ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq) 2774{ 2775 int rc, cntxt_id; 2776 struct fw_eq_ctrl_cmd c; 2777 2778 bzero(&c, sizeof(c)); 2779 2780 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 2781 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | 2782 V_FW_EQ_CTRL_CMD_VFN(0)); 2783 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | 2784 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); 2785 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ 2786 c.physeqid_pkd = htobe32(0); 2787 c.fetchszm_to_iqid = 2788 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2789 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) | 2790 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); 2791 c.dcaen_to_eqsize = 2792 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2793 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2794 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2795 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); 2796 c.eqaddr = htobe64(eq->ba); 2797 2798 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2799 if (rc != 0) { 2800 device_printf(sc->dev, 2801 "failed to create control queue %d: %d\n", eq->tx_chan, rc); 2802 return (rc); 2803 } 2804 eq->flags |= EQ_ALLOCATED; 2805 2806 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); 2807 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2808 if (cntxt_id >= sc->sge.neq) 2809 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2810 cntxt_id, sc->sge.neq - 1); 2811 sc->sge.eqmap[cntxt_id] = eq; 2812 2813 return (rc); 2814} 2815 2816static int 2817eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2818{ 2819 int rc, cntxt_id; 2820 struct fw_eq_eth_cmd c; 2821 2822 bzero(&c, sizeof(c)); 2823 2824 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 2825 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 2826 V_FW_EQ_ETH_CMD_VFN(0)); 2827 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 2828 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 2829 c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); 2830 c.fetchszm_to_iqid = 2831 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2832 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 2833 V_FW_EQ_ETH_CMD_IQID(eq->iqid)); 2834 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2835 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2836 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2837 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); 2838 c.eqaddr = htobe64(eq->ba); 2839 2840 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2841 if (rc != 0) { 2842 device_printf(pi->dev, 2843 "failed to create Ethernet egress queue: %d\n", rc); 2844 return (rc); 2845 } 2846 eq->flags |= EQ_ALLOCATED; 2847 2848 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 2849 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2850 if (cntxt_id >= sc->sge.neq) 2851 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2852 cntxt_id, sc->sge.neq - 1); 2853 sc->sge.eqmap[cntxt_id] = eq; 2854 2855 return (rc); 2856} 2857 2858#ifdef TCP_OFFLOAD 2859static int 2860ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2861{ 2862 int rc, cntxt_id; 2863 struct fw_eq_ofld_cmd c; 2864 2865 bzero(&c, sizeof(c)); 2866 2867 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 2868 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) | 2869 V_FW_EQ_OFLD_CMD_VFN(0)); 2870 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC | 2871 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c)); 2872 c.fetchszm_to_iqid = 2873 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | 2874 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) | 2875 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid)); 2876 c.dcaen_to_eqsize = 2877 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 2878 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 2879 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | 2880 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize)); 2881 c.eqaddr = htobe64(eq->ba); 2882 2883 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 2884 if (rc != 0) { 2885 device_printf(pi->dev, 2886 "failed to create egress queue for TCP offload: %d\n", rc); 2887 return (rc); 2888 } 2889 eq->flags |= EQ_ALLOCATED; 2890 2891 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd)); 2892 cntxt_id = eq->cntxt_id - sc->sge.eq_start; 2893 if (cntxt_id >= sc->sge.neq) 2894 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, 2895 cntxt_id, sc->sge.neq - 1); 2896 sc->sge.eqmap[cntxt_id] = eq; 2897 2898 return (rc); 2899} 2900#endif 2901 2902static int 2903alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) 2904{ 2905 int rc; 2906 size_t len; 2907 2908 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); 2909 2910 len = eq->qsize * EQ_ESIZE; 2911 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, 2912 &eq->ba, (void **)&eq->desc); 2913 if (rc) 2914 return (rc); 2915 2916 eq->cap = eq->qsize - spg_len / EQ_ESIZE; 2917 eq->spg = (void *)&eq->desc[eq->cap]; 2918 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ 2919 eq->pidx = eq->cidx = 0; 2920 eq->doorbells = sc->doorbells; 2921 2922 switch (eq->flags & EQ_TYPEMASK) { 2923 case EQ_CTRL: 2924 rc = ctrl_eq_alloc(sc, eq); 2925 break; 2926 2927 case EQ_ETH: 2928 rc = eth_eq_alloc(sc, pi, eq); 2929 break; 2930 2931#ifdef TCP_OFFLOAD 2932 case EQ_OFLD: 2933 rc = ofld_eq_alloc(sc, pi, eq); 2934 break; 2935#endif 2936 2937 default: 2938 panic("%s: invalid eq type %d.", __func__, 2939 eq->flags & EQ_TYPEMASK); 2940 } 2941 if (rc != 0) { 2942 device_printf(sc->dev, 2943 "failed to allocate egress queue(%d): %d", 2944 eq->flags & EQ_TYPEMASK, rc); 2945 } 2946 2947 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus; 2948 2949 if (isset(&eq->doorbells, DOORBELL_UDB) || 2950 isset(&eq->doorbells, DOORBELL_UDBWC) || 2951 isset(&eq->doorbells, DOORBELL_WCWR)) { 2952 uint32_t s_qpp = sc->sge.eq_s_qpp; 2953 uint32_t mask = (1 << s_qpp) - 1; 2954 volatile uint8_t *udb; 2955 2956 udb = sc->udbs_base + UDBS_DB_OFFSET; 2957 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ 2958 eq->udb_qid = eq->cntxt_id & mask; /* id in page */ 2959 if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) 2960 clrbit(&eq->doorbells, DOORBELL_WCWR); 2961 else { 2962 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ 2963 eq->udb_qid = 0; 2964 } 2965 eq->udb = (volatile void *)udb; 2966 } 2967 2968 return (rc); 2969} 2970 2971static int 2972free_eq(struct adapter *sc, struct sge_eq *eq) 2973{ 2974 int rc; 2975 2976 if (eq->flags & EQ_ALLOCATED) { 2977 switch (eq->flags & EQ_TYPEMASK) { 2978 case EQ_CTRL: 2979 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, 2980 eq->cntxt_id); 2981 break; 2982 2983 case EQ_ETH: 2984 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, 2985 eq->cntxt_id); 2986 break; 2987 2988#ifdef TCP_OFFLOAD 2989 case EQ_OFLD: 2990 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, 2991 eq->cntxt_id); 2992 break; 2993#endif 2994 2995 default: 2996 panic("%s: invalid eq type %d.", __func__, 2997 eq->flags & EQ_TYPEMASK); 2998 } 2999 if (rc != 0) { 3000 device_printf(sc->dev, 3001 "failed to free egress queue (%d): %d\n", 3002 eq->flags & EQ_TYPEMASK, rc); 3003 return (rc); 3004 } 3005 eq->flags &= ~EQ_ALLOCATED; 3006 } 3007 3008 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); 3009 3010 if (mtx_initialized(&eq->eq_lock)) 3011 mtx_destroy(&eq->eq_lock); 3012 3013 bzero(eq, sizeof(*eq)); 3014 return (0); 3015} 3016 3017static int 3018alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq, 3019 struct sysctl_oid *oid) 3020{ 3021 int rc; 3022 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx; 3023 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3024 3025 rc = alloc_eq(sc, pi, &wrq->eq); 3026 if (rc) 3027 return (rc); 3028 3029 wrq->adapter = sc; 3030 STAILQ_INIT(&wrq->wr_list); 3031 3032 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3033 &wrq->eq.cntxt_id, 0, "SGE context id of the queue"); 3034 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx", 3035 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I", 3036 "consumer index"); 3037 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx", 3038 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I", 3039 "producer index"); 3040 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD, 3041 &wrq->tx_wrs, "# of work requests"); 3042 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3043 &wrq->no_desc, 0, 3044 "# of times queue ran out of hardware descriptors"); 3045 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3046 &wrq->eq.unstalled, 0, "# of times queue recovered after stall"); 3047 3048 return (rc); 3049} 3050 3051static int 3052free_wrq(struct adapter *sc, struct sge_wrq *wrq) 3053{ 3054 int rc; 3055 3056 rc = free_eq(sc, &wrq->eq); 3057 if (rc) 3058 return (rc); 3059 3060 bzero(wrq, sizeof(*wrq)); 3061 return (0); 3062} 3063 3064static int 3065alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx, 3066 struct sysctl_oid *oid) 3067{ 3068 int rc; 3069 struct adapter *sc = pi->adapter; 3070 struct sge_eq *eq = &txq->eq; 3071 char name[16]; 3072 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); 3073 3074 rc = alloc_eq(sc, pi, eq); 3075 if (rc) 3076 return (rc); 3077 3078 txq->ifp = pi->ifp; 3079 3080 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, 3081 M_ZERO | M_WAITOK); 3082 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); 3083 3084 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, 3085 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, 3086 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); 3087 if (rc != 0) { 3088 device_printf(sc->dev, 3089 "failed to create tx DMA tag: %d\n", rc); 3090 return (rc); 3091 } 3092 3093 /* 3094 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE 3095 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is 3096 * sized for the worst case. 3097 */ 3098 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8, 3099 M_WAITOK); 3100 if (rc != 0) { 3101 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); 3102 return (rc); 3103 } 3104 3105 snprintf(name, sizeof(name), "%d", idx); 3106 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, 3107 NULL, "tx queue"); 3108 children = SYSCTL_CHILDREN(oid); 3109 3110 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD, 3111 &eq->cntxt_id, 0, "SGE context id of the queue"); 3112 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx", 3113 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I", 3114 "consumer index"); 3115 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx", 3116 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I", 3117 "producer index"); 3118 3119 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, 3120 &txq->txcsum, "# of times hardware assisted with checksum"); 3121 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", 3122 CTLFLAG_RD, &txq->vlan_insertion, 3123 "# of times hardware inserted 802.1Q tag"); 3124 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, 3125 &txq->tso_wrs, "# of TSO work requests"); 3126 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, 3127 &txq->imm_wrs, "# of work requests with immediate data"); 3128 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, 3129 &txq->sgl_wrs, "# of work requests with direct SGL"); 3130 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, 3131 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); 3132 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, 3133 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); 3134 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, 3135 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); 3136 3137 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD, 3138 &txq->br->br_drops, "# of drops in the buf_ring for this queue"); 3139 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, 3140 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); 3141 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, 3142 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); 3143 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, 3144 &eq->egr_update, 0, "egress update notifications from the SGE"); 3145 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD, 3146 &eq->unstalled, 0, "# of times txq recovered after stall"); 3147 3148 return (rc); 3149} 3150 3151static int 3152free_txq(struct port_info *pi, struct sge_txq *txq) 3153{ 3154 int rc; 3155 struct adapter *sc = pi->adapter; 3156 struct sge_eq *eq = &txq->eq; 3157 3158 rc = free_eq(sc, eq); 3159 if (rc) 3160 return (rc); 3161 3162 free(txq->sdesc, M_CXGBE); 3163 3164 if (txq->txmaps.maps) 3165 t4_free_tx_maps(&txq->txmaps, txq->tx_tag); 3166 3167 buf_ring_free(txq->br, M_CXGBE); 3168 3169 if (txq->tx_tag) 3170 bus_dma_tag_destroy(txq->tx_tag); 3171 3172 bzero(txq, sizeof(*txq)); 3173 return (0); 3174} 3175 3176static void 3177oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3178{ 3179 bus_addr_t *ba = arg; 3180 3181 KASSERT(nseg == 1, 3182 ("%s meant for single segment mappings only.", __func__)); 3183 3184 *ba = error ? 0 : segs->ds_addr; 3185} 3186 3187static inline bool 3188is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) 3189{ 3190 *ctrl = (void *)((uintptr_t)iq->cdesc + 3191 (iq->esize - sizeof(struct rsp_ctrl))); 3192 3193 return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); 3194} 3195 3196static inline void 3197iq_next(struct sge_iq *iq) 3198{ 3199 iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); 3200 if (__predict_false(++iq->cidx == iq->qsize - spg_len / iq->esize)) { 3201 iq->cidx = 0; 3202 iq->gen ^= 1; 3203 iq->cdesc = iq->desc; 3204 } 3205} 3206 3207#define FL_HW_IDX(x) ((x) >> 3) 3208static inline void 3209ring_fl_db(struct adapter *sc, struct sge_fl *fl) 3210{ 3211 int ndesc = fl->pending / 8; 3212 uint32_t v; 3213 3214 if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) 3215 ndesc--; /* hold back one credit */ 3216 3217 if (ndesc <= 0) 3218 return; /* nothing to do */ 3219 3220 v = F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); 3221 if (is_t5(sc)) 3222 v |= F_DBTYPE; 3223 3224 wmb(); 3225 3226 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); 3227 fl->pending -= ndesc * 8; 3228} 3229 3230/* 3231 * Fill up the freelist by upto nbufs and maybe ring its doorbell. 3232 * 3233 * Returns non-zero to indicate that it should be added to the list of starving 3234 * freelists. 3235 */ 3236static int 3237refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs) 3238{ 3239 __be64 *d = &fl->desc[fl->pidx]; 3240 struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; 3241 uintptr_t pa; 3242 caddr_t cl; 3243 struct cluster_layout *cll = &fl->cll_def; /* default layout */ 3244 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx]; 3245 struct cluster_metadata *clm; 3246 3247 FL_LOCK_ASSERT_OWNED(fl); 3248 3249 if (nbufs > fl->needed) 3250 nbufs = fl->needed; 3251 nbufs -= (fl->pidx + nbufs) % 8; 3252 3253 while (nbufs--) { 3254 3255 if (sd->cl != NULL) { 3256 3257 if (sd->nimbuf + sd->nembuf == 0) { 3258 /* 3259 * Fast recycle without involving any atomics on 3260 * the cluster's metadata (if the cluster has 3261 * metadata). This happens when all frames 3262 * received in the cluster were small enough to 3263 * fit within a single mbuf each. 3264 */ 3265 fl->cl_fast_recycled++; 3266#ifdef INVARIANTS 3267 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3268 if (clm != NULL) 3269 MPASS(clm->refcount == 1); 3270#endif 3271 goto recycled_fast; 3272 } 3273 3274 /* 3275 * Cluster is guaranteed to have metadata. Clusters 3276 * without metadata always take the fast recycle path 3277 * when they're recycled. 3278 */ 3279 clm = cl_metadata(sc, fl, &sd->cll, sd->cl); 3280 MPASS(clm != NULL); 3281 3282 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) { 3283 fl->cl_recycled++; 3284 goto recycled; 3285 } 3286 sd->cl = NULL; /* gave up my reference */ 3287 } 3288 MPASS(sd->cl == NULL); 3289alloc: 3290 cl = uma_zalloc(swz->zone, M_NOWAIT); 3291 if (__predict_false(cl == NULL)) { 3292 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 || 3293 fl->cll_def.zidx == fl->cll_alt.zidx) 3294 break; 3295 3296 /* fall back to the safe zone */ 3297 cll = &fl->cll_alt; 3298 swz = &sc->sge.sw_zone_info[cll->zidx]; 3299 goto alloc; 3300 } 3301 fl->cl_allocated++; 3302 3303 pa = pmap_kextract((vm_offset_t)cl); 3304 pa += cll->region1; 3305 sd->cl = cl; 3306 sd->cll = *cll; 3307 *d = htobe64(pa | cll->hwidx); 3308 clm = cl_metadata(sc, fl, cll, cl); 3309 if (clm != NULL) { 3310recycled: 3311#ifdef INVARIANTS 3312 clm->sd = sd; 3313#endif 3314 clm->refcount = 1; 3315 } 3316 sd->nimbuf = 0; 3317 sd->nembuf = 0; 3318recycled_fast: 3319 fl->pending++; 3320 fl->needed--; 3321 d++; 3322 sd++; 3323 if (__predict_false(++fl->pidx == fl->cap)) { 3324 fl->pidx = 0; 3325 sd = fl->sdesc; 3326 d = fl->desc; 3327 } 3328 } 3329 3330 if (fl->pending >= 8) 3331 ring_fl_db(sc, fl); 3332 3333 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING)); 3334} 3335 3336/* 3337 * Attempt to refill all starving freelists. 3338 */ 3339static void 3340refill_sfl(void *arg) 3341{ 3342 struct adapter *sc = arg; 3343 struct sge_fl *fl, *fl_temp; 3344 3345 mtx_lock(&sc->sfl_lock); 3346 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) { 3347 FL_LOCK(fl); 3348 refill_fl(sc, fl, 64); 3349 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) { 3350 TAILQ_REMOVE(&sc->sfl, fl, link); 3351 fl->flags &= ~FL_STARVING; 3352 } 3353 FL_UNLOCK(fl); 3354 } 3355 3356 if (!TAILQ_EMPTY(&sc->sfl)) 3357 callout_schedule(&sc->sfl_callout, hz / 5); 3358 mtx_unlock(&sc->sfl_lock); 3359} 3360 3361static int 3362alloc_fl_sdesc(struct sge_fl *fl) 3363{ 3364 3365 fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, 3366 M_ZERO | M_WAITOK); 3367 3368 return (0); 3369} 3370 3371static void 3372free_fl_sdesc(struct adapter *sc, struct sge_fl *fl) 3373{ 3374 struct fl_sdesc *sd; 3375 struct cluster_metadata *clm; 3376 struct cluster_layout *cll; 3377 int i; 3378 3379 sd = fl->sdesc; 3380 for (i = 0; i < fl->cap; i++, sd++) { 3381 if (sd->cl == NULL) 3382 continue; 3383 3384 cll = &sd->cll; 3385 clm = cl_metadata(sc, fl, cll, sd->cl); 3386 if (sd->nimbuf + sd->nembuf == 0 || 3387 (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1)) { 3388 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl); 3389 } 3390 sd->cl = NULL; 3391 } 3392 3393 free(fl->sdesc, M_CXGBE); 3394 fl->sdesc = NULL; 3395} 3396 3397int 3398t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count, 3399 int flags) 3400{ 3401 struct tx_map *txm; 3402 int i, rc; 3403 3404 txmaps->map_total = txmaps->map_avail = count; 3405 txmaps->map_cidx = txmaps->map_pidx = 0; 3406 3407 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, 3408 M_ZERO | flags); 3409 3410 txm = txmaps->maps; 3411 for (i = 0; i < count; i++, txm++) { 3412 rc = bus_dmamap_create(tx_tag, 0, &txm->map); 3413 if (rc != 0) 3414 goto failed; 3415 } 3416 3417 return (0); 3418failed: 3419 while (--i >= 0) { 3420 txm--; 3421 bus_dmamap_destroy(tx_tag, txm->map); 3422 } 3423 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__)); 3424 3425 free(txmaps->maps, M_CXGBE); 3426 txmaps->maps = NULL; 3427 3428 return (rc); 3429} 3430 3431void 3432t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag) 3433{ 3434 struct tx_map *txm; 3435 int i; 3436 3437 txm = txmaps->maps; 3438 for (i = 0; i < txmaps->map_total; i++, txm++) { 3439 3440 if (txm->m) { 3441 bus_dmamap_unload(tx_tag, txm->map); 3442 m_freem(txm->m); 3443 txm->m = NULL; 3444 } 3445 3446 bus_dmamap_destroy(tx_tag, txm->map); 3447 } 3448 3449 free(txmaps->maps, M_CXGBE); 3450 txmaps->maps = NULL; 3451} 3452 3453/* 3454 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're 3455 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes 3456 * of immediate data. 3457 */ 3458#define IMM_LEN ( \ 3459 2 * EQ_ESIZE \ 3460 - sizeof(struct fw_eth_tx_pkt_wr) \ 3461 - sizeof(struct cpl_tx_pkt_core)) 3462 3463/* 3464 * Returns non-zero on failure, no need to cleanup anything in that case. 3465 * 3466 * Note 1: We always try to defrag the mbuf if required and return EFBIG only 3467 * if the resulting chain still won't fit in a tx descriptor. 3468 * 3469 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf 3470 * does not have the TCP header in it. 3471 */ 3472static int 3473get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, 3474 int sgl_only) 3475{ 3476 struct mbuf *m = *fp; 3477 struct tx_maps *txmaps; 3478 struct tx_map *txm; 3479 int rc, defragged = 0, n; 3480 3481 TXQ_LOCK_ASSERT_OWNED(txq); 3482 3483 if (m->m_pkthdr.tso_segsz) 3484 sgl_only = 1; /* Do not allow immediate data with LSO */ 3485 3486start: sgl->nsegs = 0; 3487 3488 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) 3489 return (0); /* nsegs = 0 tells caller to use imm. tx */ 3490 3491 txmaps = &txq->txmaps; 3492 if (txmaps->map_avail == 0) { 3493 txq->no_dmamap++; 3494 return (ENOMEM); 3495 } 3496 txm = &txmaps->maps[txmaps->map_pidx]; 3497 3498 if (m->m_pkthdr.tso_segsz && m->m_len < 50) { 3499 *fp = m_pullup(m, 50); 3500 m = *fp; 3501 if (m == NULL) 3502 return (ENOBUFS); 3503 } 3504 3505 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, 3506 &sgl->nsegs, BUS_DMA_NOWAIT); 3507 if (rc == EFBIG && defragged == 0) { 3508 m = m_defrag(m, M_NOWAIT); 3509 if (m == NULL) 3510 return (EFBIG); 3511 3512 defragged = 1; 3513 *fp = m; 3514 goto start; 3515 } 3516 if (rc != 0) 3517 return (rc); 3518 3519 txm->m = m; 3520 txmaps->map_avail--; 3521 if (++txmaps->map_pidx == txmaps->map_total) 3522 txmaps->map_pidx = 0; 3523 3524 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, 3525 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); 3526 3527 /* 3528 * Store the # of flits required to hold this frame's SGL in nflits. An 3529 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by 3530 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used 3531 * then len1 must be set to 0. 3532 */ 3533 n = sgl->nsegs - 1; 3534 sgl->nflits = (3 * n) / 2 + (n & 1) + 2; 3535 3536 return (0); 3537} 3538 3539 3540/* 3541 * Releases all the txq resources used up in the specified sgl. 3542 */ 3543static int 3544free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) 3545{ 3546 struct tx_maps *txmaps; 3547 struct tx_map *txm; 3548 3549 TXQ_LOCK_ASSERT_OWNED(txq); 3550 3551 if (sgl->nsegs == 0) 3552 return (0); /* didn't use any map */ 3553 3554 txmaps = &txq->txmaps; 3555 3556 /* 1 pkt uses exactly 1 map, back it out */ 3557 3558 txmaps->map_avail++; 3559 if (txmaps->map_pidx > 0) 3560 txmaps->map_pidx--; 3561 else 3562 txmaps->map_pidx = txmaps->map_total - 1; 3563 3564 txm = &txmaps->maps[txmaps->map_pidx]; 3565 bus_dmamap_unload(txq->tx_tag, txm->map); 3566 txm->m = NULL; 3567 3568 return (0); 3569} 3570 3571static int 3572write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, 3573 struct sgl *sgl) 3574{ 3575 struct sge_eq *eq = &txq->eq; 3576 struct fw_eth_tx_pkt_wr *wr; 3577 struct cpl_tx_pkt_core *cpl; 3578 uint32_t ctrl; /* used in many unrelated places */ 3579 uint64_t ctrl1; 3580 int nflits, ndesc, pktlen; 3581 struct tx_sdesc *txsd; 3582 caddr_t dst; 3583 3584 TXQ_LOCK_ASSERT_OWNED(txq); 3585 3586 pktlen = m->m_pkthdr.len; 3587 3588 /* 3589 * Do we have enough flits to send this frame out? 3590 */ 3591 ctrl = sizeof(struct cpl_tx_pkt_core); 3592 if (m->m_pkthdr.tso_segsz) { 3593 nflits = TXPKT_LSO_WR_HDR; 3594 ctrl += sizeof(struct cpl_tx_pkt_lso_core); 3595 } else 3596 nflits = TXPKT_WR_HDR; 3597 if (sgl->nsegs > 0) 3598 nflits += sgl->nflits; 3599 else { 3600 nflits += howmany(pktlen, 8); 3601 ctrl += pktlen; 3602 } 3603 ndesc = howmany(nflits, 8); 3604 if (ndesc > eq->avail) 3605 return (ENOMEM); 3606 3607 /* Firmware work request header */ 3608 wr = (void *)&eq->desc[eq->pidx]; 3609 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | 3610 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl)); 3611 ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); 3612 if (eq->avail == ndesc) { 3613 if (!(eq->flags & EQ_CRFLUSHED)) { 3614 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3615 eq->flags |= EQ_CRFLUSHED; 3616 } 3617 eq->flags |= EQ_STALLED; 3618 } 3619 3620 wr->equiq_to_len16 = htobe32(ctrl); 3621 wr->r3 = 0; 3622 3623 if (m->m_pkthdr.tso_segsz) { 3624 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); 3625 struct ether_header *eh; 3626 void *l3hdr; 3627#if defined(INET) || defined(INET6) 3628 struct tcphdr *tcp; 3629#endif 3630 uint16_t eh_type; 3631 3632 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | 3633 F_LSO_LAST_SLICE; 3634 3635 eh = mtod(m, struct ether_header *); 3636 eh_type = ntohs(eh->ether_type); 3637 if (eh_type == ETHERTYPE_VLAN) { 3638 struct ether_vlan_header *evh = (void *)eh; 3639 3640 ctrl |= V_LSO_ETHHDR_LEN(1); 3641 l3hdr = evh + 1; 3642 eh_type = ntohs(evh->evl_proto); 3643 } else 3644 l3hdr = eh + 1; 3645 3646 switch (eh_type) { 3647#ifdef INET6 3648 case ETHERTYPE_IPV6: 3649 { 3650 struct ip6_hdr *ip6 = l3hdr; 3651 3652 /* 3653 * XXX-BZ For now we do not pretend to support 3654 * IPv6 extension headers. 3655 */ 3656 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO " 3657 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt)); 3658 tcp = (struct tcphdr *)(ip6 + 1); 3659 ctrl |= F_LSO_IPV6; 3660 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) | 3661 V_LSO_TCPHDR_LEN(tcp->th_off); 3662 break; 3663 } 3664#endif 3665#ifdef INET 3666 case ETHERTYPE_IP: 3667 { 3668 struct ip *ip = l3hdr; 3669 3670 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); 3671 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | 3672 V_LSO_TCPHDR_LEN(tcp->th_off); 3673 break; 3674 } 3675#endif 3676 default: 3677 panic("%s: CSUM_TSO but no supported IP version " 3678 "(0x%04x)", __func__, eh_type); 3679 } 3680 3681 lso->lso_ctrl = htobe32(ctrl); 3682 lso->ipid_ofst = htobe16(0); 3683 lso->mss = htobe16(m->m_pkthdr.tso_segsz); 3684 lso->seqno_offset = htobe32(0); 3685 lso->len = htobe32(pktlen); 3686 3687 cpl = (void *)(lso + 1); 3688 3689 txq->tso_wrs++; 3690 } else 3691 cpl = (void *)(wr + 1); 3692 3693 /* Checksum offload */ 3694 ctrl1 = 0; 3695 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3696 ctrl1 |= F_TXPKT_IPCSUM_DIS; 3697 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3698 CSUM_TCP_IPV6 | CSUM_TSO))) 3699 ctrl1 |= F_TXPKT_L4CSUM_DIS; 3700 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3701 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3702 txq->txcsum++; /* some hardware assistance provided */ 3703 3704 /* VLAN tag insertion */ 3705 if (m->m_flags & M_VLANTAG) { 3706 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3707 txq->vlan_insertion++; 3708 } 3709 3710 /* CPL header */ 3711 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3712 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3713 cpl->pack = 0; 3714 cpl->len = htobe16(pktlen); 3715 cpl->ctrl1 = htobe64(ctrl1); 3716 3717 /* Software descriptor */ 3718 txsd = &txq->sdesc[eq->pidx]; 3719 txsd->desc_used = ndesc; 3720 3721 eq->pending += ndesc; 3722 eq->avail -= ndesc; 3723 eq->pidx += ndesc; 3724 if (eq->pidx >= eq->cap) 3725 eq->pidx -= eq->cap; 3726 3727 /* SGL */ 3728 dst = (void *)(cpl + 1); 3729 if (sgl->nsegs > 0) { 3730 txsd->credits = 1; 3731 txq->sgl_wrs++; 3732 write_sgl_to_txd(eq, sgl, &dst); 3733 } else { 3734 txsd->credits = 0; 3735 txq->imm_wrs++; 3736 for (; m; m = m->m_next) { 3737 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); 3738#ifdef INVARIANTS 3739 pktlen -= m->m_len; 3740#endif 3741 } 3742#ifdef INVARIANTS 3743 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); 3744#endif 3745 3746 } 3747 3748 txq->txpkt_wrs++; 3749 return (0); 3750} 3751 3752/* 3753 * Returns 0 to indicate that m has been accepted into a coalesced tx work 3754 * request. It has either been folded into txpkts or txpkts was flushed and m 3755 * has started a new coalesced work request (as the first frame in a fresh 3756 * txpkts). 3757 * 3758 * Returns non-zero to indicate a failure - caller is responsible for 3759 * transmitting m, if there was anything in txpkts it has been flushed. 3760 */ 3761static int 3762add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, 3763 struct mbuf *m, struct sgl *sgl) 3764{ 3765 struct sge_eq *eq = &txq->eq; 3766 int can_coalesce; 3767 struct tx_sdesc *txsd; 3768 int flits; 3769 3770 TXQ_LOCK_ASSERT_OWNED(txq); 3771 3772 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__)); 3773 3774 if (txpkts->npkt > 0) { 3775 flits = TXPKTS_PKT_HDR + sgl->nflits; 3776 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3777 txpkts->nflits + flits <= TX_WR_FLITS && 3778 txpkts->nflits + flits <= eq->avail * 8 && 3779 txpkts->plen + m->m_pkthdr.len < 65536; 3780 3781 if (can_coalesce) { 3782 txpkts->npkt++; 3783 txpkts->nflits += flits; 3784 txpkts->plen += m->m_pkthdr.len; 3785 3786 txsd = &txq->sdesc[eq->pidx]; 3787 txsd->credits++; 3788 3789 return (0); 3790 } 3791 3792 /* 3793 * Couldn't coalesce m into txpkts. The first order of business 3794 * is to send txpkts on its way. Then we'll revisit m. 3795 */ 3796 write_txpkts_wr(txq, txpkts); 3797 } 3798 3799 /* 3800 * Check if we can start a new coalesced tx work request with m as 3801 * the first packet in it. 3802 */ 3803 3804 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); 3805 3806 flits = TXPKTS_WR_HDR + sgl->nflits; 3807 can_coalesce = m->m_pkthdr.tso_segsz == 0 && 3808 flits <= eq->avail * 8 && flits <= TX_WR_FLITS; 3809 3810 if (can_coalesce == 0) 3811 return (EINVAL); 3812 3813 /* 3814 * Start a fresh coalesced tx WR with m as the first frame in it. 3815 */ 3816 txpkts->npkt = 1; 3817 txpkts->nflits = flits; 3818 txpkts->flitp = &eq->desc[eq->pidx].flit[2]; 3819 txpkts->plen = m->m_pkthdr.len; 3820 3821 txsd = &txq->sdesc[eq->pidx]; 3822 txsd->credits = 1; 3823 3824 return (0); 3825} 3826 3827/* 3828 * Note that write_txpkts_wr can never run out of hardware descriptors (but 3829 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for 3830 * coalescing only if sufficient hardware descriptors are available. 3831 */ 3832static void 3833write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) 3834{ 3835 struct sge_eq *eq = &txq->eq; 3836 struct fw_eth_tx_pkts_wr *wr; 3837 struct tx_sdesc *txsd; 3838 uint32_t ctrl; 3839 int ndesc; 3840 3841 TXQ_LOCK_ASSERT_OWNED(txq); 3842 3843 ndesc = howmany(txpkts->nflits, 8); 3844 3845 wr = (void *)&eq->desc[eq->pidx]; 3846 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 3847 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); 3848 if (eq->avail == ndesc) { 3849 if (!(eq->flags & EQ_CRFLUSHED)) { 3850 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; 3851 eq->flags |= EQ_CRFLUSHED; 3852 } 3853 eq->flags |= EQ_STALLED; 3854 } 3855 wr->equiq_to_len16 = htobe32(ctrl); 3856 wr->plen = htobe16(txpkts->plen); 3857 wr->npkt = txpkts->npkt; 3858 wr->r3 = wr->type = 0; 3859 3860 /* Everything else already written */ 3861 3862 txsd = &txq->sdesc[eq->pidx]; 3863 txsd->desc_used = ndesc; 3864 3865 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); 3866 3867 eq->pending += ndesc; 3868 eq->avail -= ndesc; 3869 eq->pidx += ndesc; 3870 if (eq->pidx >= eq->cap) 3871 eq->pidx -= eq->cap; 3872 3873 txq->txpkts_pkts += txpkts->npkt; 3874 txq->txpkts_wrs++; 3875 txpkts->npkt = 0; /* emptied */ 3876} 3877 3878static inline void 3879write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, 3880 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) 3881{ 3882 struct ulp_txpkt *ulpmc; 3883 struct ulptx_idata *ulpsc; 3884 struct cpl_tx_pkt_core *cpl; 3885 struct sge_eq *eq = &txq->eq; 3886 uintptr_t flitp, start, end; 3887 uint64_t ctrl; 3888 caddr_t dst; 3889 3890 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); 3891 3892 start = (uintptr_t)eq->desc; 3893 end = (uintptr_t)eq->spg; 3894 3895 /* Checksum offload */ 3896 ctrl = 0; 3897 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))) 3898 ctrl |= F_TXPKT_IPCSUM_DIS; 3899 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | 3900 CSUM_TCP_IPV6 | CSUM_TSO))) 3901 ctrl |= F_TXPKT_L4CSUM_DIS; 3902 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | 3903 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) 3904 txq->txcsum++; /* some hardware assistance provided */ 3905 3906 /* VLAN tag insertion */ 3907 if (m->m_flags & M_VLANTAG) { 3908 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); 3909 txq->vlan_insertion++; 3910 } 3911 3912 /* 3913 * The previous packet's SGL must have ended at a 16 byte boundary (this 3914 * is required by the firmware/hardware). It follows that flitp cannot 3915 * wrap around between the ULPTX master command and ULPTX subcommand (8 3916 * bytes each), and that it can not wrap around in the middle of the 3917 * cpl_tx_pkt_core either. 3918 */ 3919 flitp = (uintptr_t)txpkts->flitp; 3920 KASSERT((flitp & 0xf) == 0, 3921 ("%s: last SGL did not end at 16 byte boundary: %p", 3922 __func__, txpkts->flitp)); 3923 3924 /* ULP master command */ 3925 ulpmc = (void *)flitp; 3926 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | 3927 V_ULP_TXPKT_FID(eq->iqid)); 3928 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + 3929 sizeof(*cpl) + 8 * sgl->nflits, 16)); 3930 3931 /* ULP subcommand */ 3932 ulpsc = (void *)(ulpmc + 1); 3933 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | 3934 F_ULP_TX_SC_MORE); 3935 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); 3936 3937 flitp += sizeof(*ulpmc) + sizeof(*ulpsc); 3938 if (flitp == end) 3939 flitp = start; 3940 3941 /* CPL_TX_PKT */ 3942 cpl = (void *)flitp; 3943 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | 3944 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); 3945 cpl->pack = 0; 3946 cpl->len = htobe16(m->m_pkthdr.len); 3947 cpl->ctrl1 = htobe64(ctrl); 3948 3949 flitp += sizeof(*cpl); 3950 if (flitp == end) 3951 flitp = start; 3952 3953 /* SGL for this frame */ 3954 dst = (caddr_t)flitp; 3955 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); 3956 txpkts->flitp = (void *)dst; 3957 3958 KASSERT(((uintptr_t)dst & 0xf) == 0, 3959 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); 3960} 3961 3962/* 3963 * If the SGL ends on an address that is not 16 byte aligned, this function will 3964 * add a 0 filled flit at the end. It returns 1 in that case. 3965 */ 3966static int 3967write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) 3968{ 3969 __be64 *flitp, *end; 3970 struct ulptx_sgl *usgl; 3971 bus_dma_segment_t *seg; 3972 int i, padded; 3973 3974 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, 3975 ("%s: bad SGL - nsegs=%d, nflits=%d", 3976 __func__, sgl->nsegs, sgl->nflits)); 3977 3978 KASSERT(((uintptr_t)(*to) & 0xf) == 0, 3979 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); 3980 3981 flitp = (__be64 *)(*to); 3982 end = flitp + sgl->nflits; 3983 seg = &sgl->seg[0]; 3984 usgl = (void *)flitp; 3985 3986 /* 3987 * We start at a 16 byte boundary somewhere inside the tx descriptor 3988 * ring, so we're at least 16 bytes away from the status page. There is 3989 * no chance of a wrap around in the middle of usgl (which is 16 bytes). 3990 */ 3991 3992 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 3993 V_ULPTX_NSGE(sgl->nsegs)); 3994 usgl->len0 = htobe32(seg->ds_len); 3995 usgl->addr0 = htobe64(seg->ds_addr); 3996 seg++; 3997 3998 if ((uintptr_t)end <= (uintptr_t)eq->spg) { 3999 4000 /* Won't wrap around at all */ 4001 4002 for (i = 0; i < sgl->nsegs - 1; i++, seg++) { 4003 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); 4004 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); 4005 } 4006 if (i & 1) 4007 usgl->sge[i / 2].len[1] = htobe32(0); 4008 } else { 4009 4010 /* Will wrap somewhere in the rest of the SGL */ 4011 4012 /* 2 flits already written, write the rest flit by flit */ 4013 flitp = (void *)(usgl + 1); 4014 for (i = 0; i < sgl->nflits - 2; i++) { 4015 if ((uintptr_t)flitp == (uintptr_t)eq->spg) 4016 flitp = (void *)eq->desc; 4017 *flitp++ = get_flit(seg, sgl->nsegs - 1, i); 4018 } 4019 end = flitp; 4020 } 4021 4022 if ((uintptr_t)end & 0xf) { 4023 *(uint64_t *)end = 0; 4024 end++; 4025 padded = 1; 4026 } else 4027 padded = 0; 4028 4029 if ((uintptr_t)end == (uintptr_t)eq->spg) 4030 *to = (void *)eq->desc; 4031 else 4032 *to = (void *)end; 4033 4034 return (padded); 4035} 4036 4037static inline void 4038copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) 4039{ 4040 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) { 4041 bcopy(from, *to, len); 4042 (*to) += len; 4043 } else { 4044 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); 4045 4046 bcopy(from, *to, portion); 4047 from += portion; 4048 portion = len - portion; /* remaining */ 4049 bcopy(from, (void *)eq->desc, portion); 4050 (*to) = (caddr_t)eq->desc + portion; 4051 } 4052} 4053 4054static inline void 4055ring_eq_db(struct adapter *sc, struct sge_eq *eq) 4056{ 4057 u_int db, pending; 4058 4059 db = eq->doorbells; 4060 pending = eq->pending; 4061 if (pending > 1) 4062 clrbit(&db, DOORBELL_WCWR); 4063 eq->pending = 0; 4064 wmb(); 4065 4066 switch (ffs(db) - 1) { 4067 case DOORBELL_UDB: 4068 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4069 return; 4070 4071 case DOORBELL_WCWR: { 4072 volatile uint64_t *dst, *src; 4073 int i; 4074 4075 /* 4076 * Queues whose 128B doorbell segment fits in the page do not 4077 * use relative qid (udb_qid is always 0). Only queues with 4078 * doorbell segments can do WCWR. 4079 */ 4080 KASSERT(eq->udb_qid == 0 && pending == 1, 4081 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p", 4082 __func__, eq->doorbells, pending, eq->pidx, eq)); 4083 4084 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET - 4085 UDBS_DB_OFFSET); 4086 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; 4087 src = (void *)&eq->desc[i]; 4088 while (src != (void *)&eq->desc[i + 1]) 4089 *dst++ = *src++; 4090 wmb(); 4091 return; 4092 } 4093 4094 case DOORBELL_UDBWC: 4095 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending)); 4096 wmb(); 4097 return; 4098 4099 case DOORBELL_KDB: 4100 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 4101 V_QID(eq->cntxt_id) | V_PIDX(pending)); 4102 return; 4103 } 4104} 4105 4106static inline int 4107reclaimable(struct sge_eq *eq) 4108{ 4109 unsigned int cidx; 4110 4111 cidx = eq->spg->cidx; /* stable snapshot */ 4112 cidx = be16toh(cidx); 4113 4114 if (cidx >= eq->cidx) 4115 return (cidx - eq->cidx); 4116 else 4117 return (cidx + eq->cap - eq->cidx); 4118} 4119 4120/* 4121 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as 4122 * many as possible but stop when there are around "n" mbufs to free. 4123 * 4124 * The actual number reclaimed is provided as the return value. 4125 */ 4126static int 4127reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) 4128{ 4129 struct tx_sdesc *txsd; 4130 struct tx_maps *txmaps; 4131 struct tx_map *txm; 4132 unsigned int reclaimed, maps; 4133 struct sge_eq *eq = &txq->eq; 4134 4135 TXQ_LOCK_ASSERT_OWNED(txq); 4136 4137 if (can_reclaim == 0) 4138 can_reclaim = reclaimable(eq); 4139 4140 maps = reclaimed = 0; 4141 while (can_reclaim && maps < n) { 4142 int ndesc; 4143 4144 txsd = &txq->sdesc[eq->cidx]; 4145 ndesc = txsd->desc_used; 4146 4147 /* Firmware doesn't return "partial" credits. */ 4148 KASSERT(can_reclaim >= ndesc, 4149 ("%s: unexpected number of credits: %d, %d", 4150 __func__, can_reclaim, ndesc)); 4151 4152 maps += txsd->credits; 4153 4154 reclaimed += ndesc; 4155 can_reclaim -= ndesc; 4156 4157 eq->cidx += ndesc; 4158 if (__predict_false(eq->cidx >= eq->cap)) 4159 eq->cidx -= eq->cap; 4160 } 4161 4162 txmaps = &txq->txmaps; 4163 txm = &txmaps->maps[txmaps->map_cidx]; 4164 if (maps) 4165 prefetch(txm->m); 4166 4167 eq->avail += reclaimed; 4168 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ 4169 ("%s: too many descriptors available", __func__)); 4170 4171 txmaps->map_avail += maps; 4172 KASSERT(txmaps->map_avail <= txmaps->map_total, 4173 ("%s: too many maps available", __func__)); 4174 4175 while (maps--) { 4176 struct tx_map *next; 4177 4178 next = txm + 1; 4179 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total)) 4180 next = txmaps->maps; 4181 prefetch(next->m); 4182 4183 bus_dmamap_unload(txq->tx_tag, txm->map); 4184 m_freem(txm->m); 4185 txm->m = NULL; 4186 4187 txm = next; 4188 if (__predict_false(++txmaps->map_cidx == txmaps->map_total)) 4189 txmaps->map_cidx = 0; 4190 } 4191 4192 return (reclaimed); 4193} 4194 4195static void 4196write_eqflush_wr(struct sge_eq *eq) 4197{ 4198 struct fw_eq_flush_wr *wr; 4199 4200 EQ_LOCK_ASSERT_OWNED(eq); 4201 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); 4202 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__)); 4203 4204 wr = (void *)&eq->desc[eq->pidx]; 4205 bzero(wr, sizeof(*wr)); 4206 wr->opcode = FW_EQ_FLUSH_WR; 4207 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | 4208 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); 4209 4210 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED); 4211 eq->pending++; 4212 eq->avail--; 4213 if (++eq->pidx == eq->cap) 4214 eq->pidx = 0; 4215} 4216 4217static __be64 4218get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) 4219{ 4220 int i = (idx / 3) * 2; 4221 4222 switch (idx % 3) { 4223 case 0: { 4224 __be64 rc; 4225 4226 rc = htobe32(sgl[i].ds_len); 4227 if (i + 1 < nsegs) 4228 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; 4229 4230 return (rc); 4231 } 4232 case 1: 4233 return htobe64(sgl[i].ds_addr); 4234 case 2: 4235 return htobe64(sgl[i + 1].ds_addr); 4236 } 4237 4238 return (0); 4239} 4240 4241static void 4242find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp) 4243{ 4244 int8_t zidx, hwidx, idx; 4245 uint16_t region1, region3; 4246 int spare, spare_needed, n; 4247 struct sw_zone_info *swz; 4248 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0]; 4249 4250 /* 4251 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize 4252 * large enough for the max payload and cluster metadata. Otherwise 4253 * settle for the largest bufsize that leaves enough room in the cluster 4254 * for metadata. 4255 * 4256 * Without buffer packing: Look for the smallest zone which has a 4257 * bufsize large enough for the max payload. Settle for the largest 4258 * bufsize available if there's nothing big enough for max payload. 4259 */ 4260 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0; 4261 swz = &sc->sge.sw_zone_info[0]; 4262 hwidx = -1; 4263 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) { 4264 if (swz->size > largest_rx_cluster) { 4265 if (__predict_true(hwidx != -1)) 4266 break; 4267 4268 /* 4269 * This is a misconfiguration. largest_rx_cluster is 4270 * preventing us from finding a refill source. See 4271 * dev.t5nex.<n>.buffer_sizes to figure out why. 4272 */ 4273 device_printf(sc->dev, "largest_rx_cluster=%u leaves no" 4274 " refill source for fl %p (dma %u). Ignored.\n", 4275 largest_rx_cluster, fl, maxp); 4276 } 4277 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) { 4278 hwb = &hwb_list[idx]; 4279 spare = swz->size - hwb->size; 4280 if (spare < spare_needed) 4281 continue; 4282 4283 hwidx = idx; /* best option so far */ 4284 if (hwb->size >= maxp) { 4285 4286 if ((fl->flags & FL_BUF_PACKING) == 0) 4287 goto done; /* stop looking (not packing) */ 4288 4289 if (swz->size >= safest_rx_cluster) 4290 goto done; /* stop looking (packing) */ 4291 } 4292 break; /* keep looking, next zone */ 4293 } 4294 } 4295done: 4296 /* A usable hwidx has been located. */ 4297 MPASS(hwidx != -1); 4298 hwb = &hwb_list[hwidx]; 4299 zidx = hwb->zidx; 4300 swz = &sc->sge.sw_zone_info[zidx]; 4301 region1 = 0; 4302 region3 = swz->size - hwb->size; 4303 4304 /* 4305 * Stay within this zone and see if there is a better match when mbuf 4306 * inlining is allowed. Remember that the hwidx's are sorted in 4307 * decreasing order of size (so in increasing order of spare area). 4308 */ 4309 for (idx = hwidx; idx != -1; idx = hwb->next) { 4310 hwb = &hwb_list[idx]; 4311 spare = swz->size - hwb->size; 4312 4313 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp) 4314 break; 4315 if (spare < CL_METADATA_SIZE + MSIZE) 4316 continue; 4317 n = (spare - CL_METADATA_SIZE) / MSIZE; 4318 if (n > howmany(hwb->size, maxp)) 4319 break; 4320 4321 hwidx = idx; 4322 if (fl->flags & FL_BUF_PACKING) { 4323 region1 = n * MSIZE; 4324 region3 = spare - region1; 4325 } else { 4326 region1 = MSIZE; 4327 region3 = spare - region1; 4328 break; 4329 } 4330 } 4331 4332 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES, 4333 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp)); 4334 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES, 4335 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp)); 4336 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 == 4337 sc->sge.sw_zone_info[zidx].size, 4338 ("%s: bad buffer layout for fl %p, maxp %d. " 4339 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4340 sc->sge.sw_zone_info[zidx].size, region1, 4341 sc->sge.hw_buf_info[hwidx].size, region3)); 4342 if (fl->flags & FL_BUF_PACKING || region1 > 0) { 4343 KASSERT(region3 >= CL_METADATA_SIZE, 4344 ("%s: no room for metadata. fl %p, maxp %d; " 4345 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4346 sc->sge.sw_zone_info[zidx].size, region1, 4347 sc->sge.hw_buf_info[hwidx].size, region3)); 4348 KASSERT(region1 % MSIZE == 0, 4349 ("%s: bad mbuf region for fl %p, maxp %d. " 4350 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp, 4351 sc->sge.sw_zone_info[zidx].size, region1, 4352 sc->sge.hw_buf_info[hwidx].size, region3)); 4353 } 4354 4355 fl->cll_def.zidx = zidx; 4356 fl->cll_def.hwidx = hwidx; 4357 fl->cll_def.region1 = region1; 4358 fl->cll_def.region3 = region3; 4359} 4360 4361static void 4362find_safe_refill_source(struct adapter *sc, struct sge_fl *fl) 4363{ 4364 struct sge *s = &sc->sge; 4365 struct hw_buf_info *hwb; 4366 struct sw_zone_info *swz; 4367 int spare; 4368 int8_t hwidx; 4369 4370 if (fl->flags & FL_BUF_PACKING) 4371 hwidx = s->safe_hwidx2; /* with room for metadata */ 4372 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) { 4373 hwidx = s->safe_hwidx2; 4374 hwb = &s->hw_buf_info[hwidx]; 4375 swz = &s->sw_zone_info[hwb->zidx]; 4376 spare = swz->size - hwb->size; 4377 4378 /* no good if there isn't room for an mbuf as well */ 4379 if (spare < CL_METADATA_SIZE + MSIZE) 4380 hwidx = s->safe_hwidx1; 4381 } else 4382 hwidx = s->safe_hwidx1; 4383 4384 if (hwidx == -1) { 4385 /* No fallback source */ 4386 fl->cll_alt.hwidx = -1; 4387 fl->cll_alt.zidx = -1; 4388 4389 return; 4390 } 4391 4392 hwb = &s->hw_buf_info[hwidx]; 4393 swz = &s->sw_zone_info[hwb->zidx]; 4394 spare = swz->size - hwb->size; 4395 fl->cll_alt.hwidx = hwidx; 4396 fl->cll_alt.zidx = hwb->zidx; 4397 if (allow_mbufs_in_cluster) 4398 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE; 4399 else 4400 fl->cll_alt.region1 = 0; 4401 fl->cll_alt.region3 = spare - fl->cll_alt.region1; 4402} 4403 4404static void 4405add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl) 4406{ 4407 mtx_lock(&sc->sfl_lock); 4408 FL_LOCK(fl); 4409 if ((fl->flags & FL_DOOMED) == 0) { 4410 fl->flags |= FL_STARVING; 4411 TAILQ_INSERT_TAIL(&sc->sfl, fl, link); 4412 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc); 4413 } 4414 FL_UNLOCK(fl); 4415 mtx_unlock(&sc->sfl_lock); 4416} 4417 4418static int 4419handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss, 4420 struct mbuf *m) 4421{ 4422 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1); 4423 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); 4424 struct adapter *sc = iq->adapter; 4425 struct sge *s = &sc->sge; 4426 struct sge_eq *eq; 4427 4428 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4429 rss->opcode)); 4430 4431 eq = s->eqmap[qid - s->eq_start]; 4432 EQ_LOCK(eq); 4433 KASSERT(eq->flags & EQ_CRFLUSHED, 4434 ("%s: unsolicited egress update", __func__)); 4435 eq->flags &= ~EQ_CRFLUSHED; 4436 eq->egr_update++; 4437 4438 if (__predict_false(eq->flags & EQ_DOOMED)) 4439 wakeup_one(eq); 4440 else if (eq->flags & EQ_STALLED && can_resume_tx(eq)) 4441 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task); 4442 EQ_UNLOCK(eq); 4443 4444 return (0); 4445} 4446 4447/* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */ 4448CTASSERT(offsetof(struct cpl_fw4_msg, data) == \ 4449 offsetof(struct cpl_fw6_msg, data)); 4450 4451static int 4452handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 4453{ 4454 struct adapter *sc = iq->adapter; 4455 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); 4456 4457 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 4458 rss->opcode)); 4459 4460 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { 4461 const struct rss_header *rss2; 4462 4463 rss2 = (const struct rss_header *)&cpl->data[0]; 4464 return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); 4465 } 4466 4467 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); 4468} 4469 4470static int 4471sysctl_uint16(SYSCTL_HANDLER_ARGS) 4472{ 4473 uint16_t *id = arg1; 4474 int i = *id; 4475 4476 return sysctl_handle_int(oidp, &i, 0, req); 4477} 4478 4479static int 4480sysctl_bufsizes(SYSCTL_HANDLER_ARGS) 4481{ 4482 struct sge *s = arg1; 4483 struct hw_buf_info *hwb = &s->hw_buf_info[0]; 4484 struct sw_zone_info *swz = &s->sw_zone_info[0]; 4485 int i, rc; 4486 struct sbuf sb; 4487 char c; 4488 4489 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); 4490 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 4491 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster) 4492 c = '*'; 4493 else 4494 c = '\0'; 4495 4496 sbuf_printf(&sb, "%u%c ", hwb->size, c); 4497 } 4498 sbuf_trim(&sb); 4499 sbuf_finish(&sb); 4500 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 4501 sbuf_delete(&sb); 4502 return (rc); 4503} 4504