1/*
2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include "opt_inet.h"
36
37#ifdef TCP_OFFLOAD
38#include <linux/slab.h>
39
40#include "iw_cxgbe.h"
41
42static void post_qp_event(struct c4iw_dev *dev, struct c4iw_cq *chp,
43			  struct c4iw_qp *qhp,
44			  struct t4_cqe *err_cqe,
45			  enum ib_event_type ib_event)
46{
47	struct ib_event event;
48	struct c4iw_qp_attributes attrs;
49	unsigned long flag;
50
51	if ((qhp->attr.state == C4IW_QP_STATE_ERROR) ||
52	    (qhp->attr.state == C4IW_QP_STATE_TERMINATE)) {
53		CTR4(KTR_IW_CXGBE, "%s AE received after RTS - "
54		     "qp state %d qpid 0x%x status 0x%x", __func__,
55		     qhp->attr.state, qhp->wq.sq.qid, CQE_STATUS(err_cqe));
56		return;
57	}
58
59	printf("AE qpid 0x%x opcode %d status 0x%x "
60	       "type %d wrid.hi 0x%x wrid.lo 0x%x\n",
61	       CQE_QPID(err_cqe), CQE_OPCODE(err_cqe),
62	       CQE_STATUS(err_cqe), CQE_TYPE(err_cqe),
63	       CQE_WRID_HI(err_cqe), CQE_WRID_LOW(err_cqe));
64
65	if (qhp->attr.state == C4IW_QP_STATE_RTS) {
66		attrs.next_state = C4IW_QP_STATE_TERMINATE;
67		c4iw_modify_qp(qhp->rhp, qhp, C4IW_QP_ATTR_NEXT_STATE,
68			       &attrs, 0);
69	}
70
71	event.event = ib_event;
72	event.device = chp->ibcq.device;
73	if (ib_event == IB_EVENT_CQ_ERR)
74		event.element.cq = &chp->ibcq;
75	else
76		event.element.qp = &qhp->ibqp;
77	if (qhp->ibqp.event_handler)
78		(*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context);
79
80	spin_lock_irqsave(&chp->comp_handler_lock, flag);
81	(*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
82	spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
83}
84
85void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe)
86{
87	struct c4iw_cq *chp;
88	struct c4iw_qp *qhp;
89	u32 cqid;
90
91	spin_lock_irq(&dev->lock);
92	qhp = get_qhp(dev, CQE_QPID(err_cqe));
93	if (!qhp) {
94		printf("BAD AE qpid 0x%x opcode %d "
95		       "status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",
96		       CQE_QPID(err_cqe),
97		       CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),
98		       CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),
99		       CQE_WRID_LOW(err_cqe));
100		spin_unlock_irq(&dev->lock);
101		goto out;
102	}
103
104	if (SQ_TYPE(err_cqe))
105		cqid = qhp->attr.scq;
106	else
107		cqid = qhp->attr.rcq;
108	chp = get_chp(dev, cqid);
109	if (!chp) {
110		printf("BAD AE cqid 0x%x qpid 0x%x opcode %d "
111		       "status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",
112		       cqid, CQE_QPID(err_cqe),
113		       CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),
114		       CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),
115		       CQE_WRID_LOW(err_cqe));
116		spin_unlock_irq(&dev->lock);
117		goto out;
118	}
119
120	c4iw_qp_add_ref(&qhp->ibqp);
121	atomic_inc(&chp->refcnt);
122	spin_unlock_irq(&dev->lock);
123
124	/* Bad incoming write */
125	if (RQ_TYPE(err_cqe) &&
126	    (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE)) {
127		post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_REQ_ERR);
128		goto done;
129	}
130
131	switch (CQE_STATUS(err_cqe)) {
132
133	/* Completion Events */
134	case T4_ERR_SUCCESS:
135		printf(KERN_ERR MOD "AE with status 0!\n");
136		break;
137
138	case T4_ERR_STAG:
139	case T4_ERR_PDID:
140	case T4_ERR_QPID:
141	case T4_ERR_ACCESS:
142	case T4_ERR_WRAP:
143	case T4_ERR_BOUND:
144	case T4_ERR_INVALIDATE_SHARED_MR:
145	case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
146		post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_ACCESS_ERR);
147		break;
148
149	/* Device Fatal Errors */
150	case T4_ERR_ECC:
151	case T4_ERR_ECC_PSTAG:
152	case T4_ERR_INTERNAL_ERR:
153		post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_DEVICE_FATAL);
154		break;
155
156	/* QP Fatal Errors */
157	case T4_ERR_OUT_OF_RQE:
158	case T4_ERR_PBL_ADDR_BOUND:
159	case T4_ERR_CRC:
160	case T4_ERR_MARKER:
161	case T4_ERR_PDU_LEN_ERR:
162	case T4_ERR_DDP_VERSION:
163	case T4_ERR_RDMA_VERSION:
164	case T4_ERR_OPCODE:
165	case T4_ERR_DDP_QUEUE_NUM:
166	case T4_ERR_MSN:
167	case T4_ERR_TBIT:
168	case T4_ERR_MO:
169	case T4_ERR_MSN_GAP:
170	case T4_ERR_MSN_RANGE:
171	case T4_ERR_RQE_ADDR_BOUND:
172	case T4_ERR_IRD_OVERFLOW:
173		post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);
174		break;
175
176	default:
177		printf("Unknown T4 status 0x%x QPID 0x%x\n",
178		       CQE_STATUS(err_cqe), qhp->wq.sq.qid);
179		post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);
180		break;
181	}
182done:
183	if (atomic_dec_and_test(&chp->refcnt))
184		wake_up(&chp->wait);
185	c4iw_qp_rem_ref(&qhp->ibqp);
186out:
187	return;
188}
189
190int c4iw_ev_handler(struct sge_iq *iq, const struct rsp_ctrl *rc)
191{
192	struct c4iw_dev *dev = iq->adapter->iwarp_softc;
193	u32 qid = be32_to_cpu(rc->pldbuflen_qid);
194	struct c4iw_cq *chp;
195	unsigned long flag;
196
197	spin_lock_irqsave(&dev->lock, flag);
198	chp = get_chp(dev, qid);
199	if (chp) {
200		atomic_inc(&chp->refcnt);
201		spin_unlock_irqrestore(&dev->lock, flag);
202
203		spin_lock_irqsave(&chp->comp_handler_lock, flag);
204		(*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
205		spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
206		if (atomic_dec_and_test(&chp->refcnt))
207			wake_up(&chp->wait);
208	} else {
209		CTR2(KTR_IW_CXGBE, "%s unknown cqid 0x%x", __func__, qid);
210		spin_unlock_irqrestore(&dev->lock, flag);
211	}
212
213	return 0;
214}
215#endif
216