adapter.h revision 331769
1218792Snp/*- 2218792Snp * Copyright (c) 2011 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * Written by: Navdeep Parhar <np@FreeBSD.org> 5218792Snp * 6218792Snp * Redistribution and use in source and binary forms, with or without 7218792Snp * modification, are permitted provided that the following conditions 8218792Snp * are met: 9218792Snp * 1. Redistributions of source code must retain the above copyright 10218792Snp * notice, this list of conditions and the following disclaimer. 11218792Snp * 2. Redistributions in binary form must reproduce the above copyright 12218792Snp * notice, this list of conditions and the following disclaimer in the 13218792Snp * documentation and/or other materials provided with the distribution. 14218792Snp * 15218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25218792Snp * SUCH DAMAGE. 26218792Snp * 27218792Snp * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 331769 2018-03-30 18:06:29Z hselasky $ 28218792Snp * 29218792Snp */ 30218792Snp 31218792Snp#ifndef __T4_ADAPTER_H__ 32218792Snp#define __T4_ADAPTER_H__ 33218792Snp 34228561Snp#include <sys/kernel.h> 35218792Snp#include <sys/bus.h> 36218792Snp#include <sys/rman.h> 37218792Snp#include <sys/types.h> 38257176Sglebius#include <sys/lock.h> 39218792Snp#include <sys/malloc.h> 40257176Sglebius#include <sys/rwlock.h> 41257176Sglebius#include <sys/sx.h> 42257176Sglebius#include <vm/uma.h> 43257176Sglebius 44218792Snp#include <dev/pci/pcivar.h> 45218792Snp#include <dev/pci/pcireg.h> 46218792Snp#include <machine/bus.h> 47218792Snp#include <sys/socket.h> 48218792Snp#include <sys/sysctl.h> 49218792Snp#include <net/ethernet.h> 50218792Snp#include <net/if.h> 51257176Sglebius#include <net/if_var.h> 52218792Snp#include <net/if_media.h> 53235944Sbz#include <netinet/in.h> 54218792Snp#include <netinet/tcp_lro.h> 55218792Snp 56218792Snp#include "offload.h" 57301535Snp#include "t4_ioctl.h" 58266757Snp#include "common/t4_msg.h" 59228561Snp#include "firmware/t4fw_interface.h" 60218792Snp 61275733Snp#define KTR_CXGBE KTR_SPARE3 62218792SnpMALLOC_DECLARE(M_CXGBE); 63218792Snp#define CXGBE_UNIMPLEMENTED(s) \ 64218792Snp panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65218792Snp 66218792Snp#if defined(__i386__) || defined(__amd64__) 67218792Snpstatic __inline void 68218792Snpprefetch(void *x) 69218792Snp{ 70218792Snp __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71218792Snp} 72218792Snp#else 73218792Snp#define prefetch(x) 74218792Snp#endif 75218792Snp 76231115Snp#ifndef SYSCTL_ADD_UQUAD 77231115Snp#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78231115Snp#define sysctl_handle_64 sysctl_handle_quad 79231115Snp#define CTLTYPE_U64 CTLTYPE_QUAD 80231115Snp#endif 81231115Snp 82231115Snp#if (__FreeBSD_version >= 900030) || \ 83231115Snp ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84231115Snp#define SBUF_DRAIN 1 85231115Snp#endif 86231115Snp 87218792Snpstruct adapter; 88218792Snptypedef struct adapter adapter_t; 89218792Snp 90218792Snpenum { 91269411Snp /* 92269411Snp * All ingress queues use this entry size. Note that the firmware event 93269411Snp * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94269411Snp * be at least 64. 95269411Snp */ 96269411Snp IQ_ESIZE = 64, 97269411Snp 98269411Snp /* Default queue sizes for all kinds of ingress queues */ 99218792Snp FW_IQ_QSIZE = 256, 100218792Snp RX_IQ_QSIZE = 1024, 101218792Snp 102269411Snp /* All egress queues use this entry size */ 103269411Snp EQ_ESIZE = 64, 104218792Snp 105269411Snp /* Default queue sizes for all kinds of egress queues */ 106269411Snp CTRL_EQ_QSIZE = 128, 107269411Snp TX_EQ_QSIZE = 1024, 108269411Snp 109219392Snp#if MJUMPAGESIZE != MCLBYTES 110263317Snp SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111219392Snp#else 112263317Snp SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113219392Snp#endif 114275554Snp CL_METADATA_SIZE = CACHE_LINE_SIZE, 115218792Snp 116269411Snp SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117276485Snp TX_SGL_SEGS = 39, 118276485Snp TX_SGL_SEGS_TSO = 38, 119218792Snp TX_WR_FLITS = SGE_MAX_WR_LEN / 8 120218792Snp}; 121218792Snp 122218792Snpenum { 123219944Snp /* adapter intr_type */ 124219944Snp INTR_INTX = (1 << 0), 125219944Snp INTR_MSI = (1 << 1), 126219944Snp INTR_MSIX = (1 << 2) 127219944Snp}; 128219944Snp 129219944Snpenum { 130266757Snp XGMAC_MTU = (1 << 0), 131266757Snp XGMAC_PROMISC = (1 << 1), 132266757Snp XGMAC_ALLMULTI = (1 << 2), 133266757Snp XGMAC_VLANEX = (1 << 3), 134266757Snp XGMAC_UCADDR = (1 << 4), 135266757Snp XGMAC_MCADDRS = (1 << 5), 136266757Snp 137266757Snp XGMAC_ALL = 0xffff 138266757Snp}; 139266757Snp 140266757Snpenum { 141245274Snp /* flags understood by begin_synchronized_op */ 142245274Snp HOLD_LOCK = (1 << 0), 143245274Snp SLEEP_OK = (1 << 1), 144245274Snp INTR_OK = (1 << 2), 145245274Snp 146245274Snp /* flags understood by end_synchronized_op */ 147245274Snp LOCK_HELD = HOLD_LOCK, 148245274Snp}; 149245274Snp 150245274Snpenum { 151218792Snp /* adapter flags */ 152218792Snp FULL_INIT_DONE = (1 << 0), 153218792Snp FW_OK = (1 << 1), 154330307Snp CHK_MBOX_ACCESS = (1 << 2), 155228561Snp MASTER_PF = (1 << 3), 156228561Snp ADAP_SYSCTL_CTX = (1 << 4), 157278374Snp /* TOM_INIT_DONE= (1 << 5), No longer used */ 158255050Snp BUF_PACKING_OK = (1 << 6), 159306664Sjhb IS_VF = (1 << 7), 160218792Snp 161218792Snp CXGBE_BUSY = (1 << 9), 162218792Snp 163218792Snp /* port flags */ 164291665Sjhb HAS_TRACEQ = (1 << 3), 165291665Sjhb 166291665Sjhb /* VI flags */ 167218792Snp DOOMED = (1 << 0), 168291665Sjhb VI_INIT_DONE = (1 << 1), 169291665Sjhb VI_SYSCTL_CTX = (1 << 2), 170284445Snp 171284445Snp /* adapter debug_flags */ 172330307Snp DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 173330307Snp DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 174330307Snp DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 175218792Snp}; 176218792Snp 177291665Sjhb#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 178291665Sjhb#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 179245274Snp#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 180245274Snp#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 181245274Snp#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 182218792Snp 183291665Sjhbstruct vi_info { 184218792Snp device_t dev; 185291665Sjhb struct port_info *pi; 186218792Snp 187218792Snp struct ifnet *ifp; 188218792Snp 189218792Snp unsigned long flags; 190218792Snp int if_flags; 191218792Snp 192302110Snp uint16_t *rss, *nm_rss; 193309560Sjhb int smt_idx; /* for convenience */ 194218792Snp uint16_t viid; 195218792Snp int16_t xact_addr_filt;/* index of exact MAC address filter */ 196218792Snp uint16_t rss_size; /* size of VI's RSS table slice */ 197285648Snp uint16_t rss_base; /* start of VI's RSS table slice */ 198218792Snp 199291665Sjhb eventhandler_tag vlan_c; 200291665Sjhb 201291665Sjhb int nintr; 202291665Sjhb int first_intr; 203291665Sjhb 204218792Snp /* These need to be int as they are used in sysctl */ 205318854Snp int ntxq; /* # of tx queues */ 206318854Snp int first_txq; /* index of first tx queue */ 207318854Snp int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 208318854Snp int nrxq; /* # of rx queues */ 209318854Snp int first_rxq; /* index of first rx queue */ 210228561Snp int nofldtxq; /* # of offload tx queues */ 211228561Snp int first_ofld_txq; /* index of first offload tx queue */ 212228561Snp int nofldrxq; /* # of offload rx queues */ 213228561Snp int first_ofld_rxq; /* index of first offload rx queue */ 214302110Snp int nnmtxq; 215302110Snp int first_nm_txq; 216302110Snp int nnmrxq; 217302110Snp int first_nm_rxq; 218218792Snp int tmr_idx; 219330307Snp int ofld_tmr_idx; 220218792Snp int pktc_idx; 221330307Snp int ofld_pktc_idx; 222218792Snp int qsize_rxq; 223218792Snp int qsize_txq; 224218792Snp 225291665Sjhb struct timeval last_refreshed; 226291665Sjhb struct fw_vi_stats_vf stats; 227291665Sjhb 228291665Sjhb struct callout tick; 229291665Sjhb struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 230291665Sjhb 231291665Sjhb uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 232291665Sjhb}; 233291665Sjhb 234318850Snpstruct tx_ch_rl_params { 235318850Snp enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 236318850Snp uint32_t maxrate; 237318850Snp}; 238318850Snp 239301535Snpenum { 240318850Snp TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 241318850Snp TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 242301535Snp}; 243301535Snp 244318850Snpstruct tx_cl_rl_params { 245301535Snp int refcount; 246318850Snp u_int flags; 247318850Snp enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 248318850Snp enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 249318850Snp enum fw_sched_params_mode mode; /* aggr or per-flow */ 250318850Snp uint32_t maxrate; 251318850Snp uint16_t pktsize; 252301535Snp}; 253301535Snp 254318850Snp/* Tx scheduler parameters for a channel/port */ 255318850Snpstruct tx_sched_params { 256318850Snp /* Channel Rate Limiter */ 257318850Snp struct tx_ch_rl_params ch_rl; 258318850Snp 259318850Snp /* Class WRR */ 260318850Snp /* XXX */ 261318850Snp 262318850Snp /* Class Rate Limiter */ 263318850Snp struct tx_cl_rl_params cl_rl[]; 264318850Snp}; 265318850Snp 266291665Sjhbstruct port_info { 267291665Sjhb device_t dev; 268291665Sjhb struct adapter *adapter; 269291665Sjhb 270291665Sjhb struct vi_info *vi; 271291665Sjhb int nvi; 272291665Sjhb int up_vis; 273291665Sjhb int uld_vis; 274291665Sjhb 275318850Snp struct tx_sched_params *sched_params; 276301535Snp 277291665Sjhb struct mtx pi_lock; 278291665Sjhb char lockname[16]; 279291665Sjhb unsigned long flags; 280291665Sjhb 281291665Sjhb uint8_t lport; /* associated offload logical port */ 282291665Sjhb int8_t mdio_addr; 283291665Sjhb uint8_t port_type; 284291665Sjhb uint8_t mod_type; 285291665Sjhb uint8_t port_id; 286291665Sjhb uint8_t tx_chan; 287330307Snp uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 288330307Snp uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 289291665Sjhb 290218792Snp struct link_config link_cfg; 291330307Snp struct link_config old_link_cfg; 292330307Snp struct ifmedia media; 293218792Snp 294272200Snp struct timeval last_refreshed; 295272200Snp struct port_stats stats; 296272200Snp u_int tnl_cong_drops; 297276485Snp u_int tx_parse_error; 298272200Snp 299218792Snp struct callout tick; 300218792Snp}; 301218792Snp 302291665Sjhb#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 303291665Sjhb 304263317Snp/* Where the cluster came from, how it has been carved up. */ 305263317Snpstruct cluster_layout { 306263317Snp int8_t zidx; 307263317Snp int8_t hwidx; 308263317Snp uint16_t region1; /* mbufs laid out within this region */ 309263317Snp /* region2 is the DMA region */ 310263317Snp uint16_t region3; /* cluster_metadata within this region */ 311263317Snp}; 312263317Snp 313263317Snpstruct cluster_metadata { 314263317Snp u_int refcount; 315263317Snp struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 316218792Snp}; 317218792Snp 318263317Snpstruct fl_sdesc { 319263317Snp caddr_t cl; 320268971Snp uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 321263317Snp struct cluster_layout cll; 322263317Snp}; 323263317Snp 324218792Snpstruct tx_desc { 325218792Snp __be64 flit[8]; 326218792Snp}; 327218792Snp 328218792Snpstruct tx_sdesc { 329276485Snp struct mbuf *m; /* m_nextpkt linked chain of frames */ 330218792Snp uint8_t desc_used; /* # of hardware descriptors used by the WR */ 331218792Snp}; 332218792Snp 333269411Snp 334269411Snp#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 335269411Snpstruct iq_desc { 336269411Snp struct rss_header rss; 337269411Snp uint8_t cpl[IQ_PAD]; 338269411Snp struct rsp_ctrl rsp; 339269411Snp}; 340269411Snp#undef IQ_PAD 341269411SnpCTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 342269411Snp 343218792Snpenum { 344218792Snp /* iq flags */ 345228561Snp IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 346228561Snp IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 347330307Snp /* 1 << 2 Used to be IQ_INTR */ 348228561Snp IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 349318842Snp IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 350220649Snp 351220649Snp /* iq state */ 352220649Snp IQS_DISABLED = 0, 353220649Snp IQS_BUSY = 1, 354220649Snp IQS_IDLE = 2, 355302110Snp 356302110Snp /* netmap related flags */ 357302110Snp NM_OFF = 0, 358302110Snp NM_ON = 1, 359302110Snp NM_BUSY = 2, 360218792Snp}; 361218792Snp 362302339Snpstruct sge_iq; 363302339Snpstruct rss_header; 364302339Snptypedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 365302339Snp struct mbuf *); 366302339Snptypedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 367302339Snptypedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 368302339Snp 369218792Snp/* 370218792Snp * Ingress Queue: T4 is producer, driver is consumer. 371218792Snp */ 372218792Snpstruct sge_iq { 373219290Snp uint32_t flags; 374228561Snp volatile int state; 375218792Snp struct adapter *adapter; 376302339Snp cpl_handler_t set_tcb_rpl; 377302339Snp cpl_handler_t l2t_write_rpl; 378269411Snp struct iq_desc *desc; /* KVA of descriptor ring */ 379269411Snp int8_t intr_pktc_idx; /* packet count threshold index */ 380218792Snp uint8_t gen; /* generation bit */ 381218792Snp uint8_t intr_params; /* interrupt holdoff parameters */ 382228561Snp uint8_t intr_next; /* XXX: holdoff for next interrupt */ 383218792Snp uint16_t qsize; /* size (# of entries) of the queue */ 384269411Snp uint16_t sidx; /* index of the entry with the status page */ 385218792Snp uint16_t cidx; /* consumer index */ 386228561Snp uint16_t cntxt_id; /* SGE context id for the iq */ 387269411Snp uint16_t abs_id; /* absolute SGE id for the iq */ 388228561Snp 389228561Snp STAILQ_ENTRY(sge_iq) link; 390269411Snp 391269411Snp bus_dma_tag_t desc_tag; 392269411Snp bus_dmamap_t desc_map; 393269411Snp bus_addr_t ba; /* bus address of descriptor ring */ 394218792Snp}; 395218792Snp 396218792Snpenum { 397228561Snp EQ_CTRL = 1, 398228561Snp EQ_ETH = 2, 399228561Snp EQ_OFLD = 3, 400228561Snp 401218792Snp /* eq flags */ 402276485Snp EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 403276485Snp EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 404276485Snp EQ_ENABLED = (1 << 3), /* open for business */ 405318854Snp EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 406218792Snp}; 407218792Snp 408248925Snp/* Listed in order of preference. Update t4_sysctls too if you change these */ 409249392Snpenum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 410248925Snp 411218792Snp/* 412218792Snp * Egress Queue: driver is producer, T4 is consumer. 413218792Snp * 414218792Snp * Note: A free list is an egress queue (driver produces the buffers and T4 415218792Snp * consumes them) but it's special enough to have its own struct (see sge_fl). 416218792Snp */ 417218792Snpstruct sge_eq { 418228561Snp unsigned int flags; /* MUST be first */ 419228561Snp unsigned int cntxt_id; /* SGE context id for the eq */ 420306664Sjhb unsigned int abs_id; /* absolute SGE id for the eq */ 421218792Snp struct mtx eq_lock; 422218792Snp 423218792Snp struct tx_desc *desc; /* KVA of descriptor ring */ 424266757Snp uint16_t doorbells; 425248925Snp volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 426248925Snp u_int udb_qid; /* relative qid within the doorbell page */ 427276485Snp uint16_t sidx; /* index of the entry with the status page */ 428218792Snp uint16_t cidx; /* consumer idx (desc idx) */ 429218792Snp uint16_t pidx; /* producer idx (desc idx) */ 430276485Snp uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 431276485Snp uint16_t dbidx; /* pidx of the most recent doorbell */ 432219288Snp uint16_t iqid; /* iq that gets egr_update for the eq */ 433228561Snp uint8_t tx_chan; /* tx channel used by the eq */ 434276485Snp volatile u_int equiq; /* EQUIQ outstanding */ 435228561Snp 436276485Snp bus_dma_tag_t desc_tag; 437276485Snp bus_dmamap_t desc_map; 438276485Snp bus_addr_t ba; /* bus address of descriptor ring */ 439276485Snp char lockname[16]; 440220873Snp}; 441218792Snp 442263317Snpstruct sw_zone_info { 443263317Snp uma_zone_t zone; /* zone that this cluster comes from */ 444263317Snp int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 445263317Snp int type; /* EXT_xxx type of the cluster */ 446263317Snp int8_t head_hwidx; 447263317Snp int8_t tail_hwidx; 448255050Snp}; 449255050Snp 450263317Snpstruct hw_buf_info { 451263317Snp int8_t zidx; /* backpointer to zone; -ve means unused */ 452263317Snp int8_t next; /* next hwidx for this zone; -1 means no more */ 453263317Snp int size; 454263317Snp}; 455263317Snp 456228561Snpenum { 457296603Snp NUM_MEMWIN = 3, 458296603Snp 459296603Snp MEMWIN0_APERTURE = 2048, 460296603Snp MEMWIN0_BASE = 0x1b800, 461296603Snp 462296603Snp MEMWIN1_APERTURE = 32768, 463296603Snp MEMWIN1_BASE = 0x28000, 464296603Snp 465296603Snp MEMWIN2_APERTURE_T4 = 65536, 466296603Snp MEMWIN2_BASE_T4 = 0x30000, 467296603Snp 468296603Snp MEMWIN2_APERTURE_T5 = 128 * 1024, 469296603Snp MEMWIN2_BASE_T5 = 0x60000, 470296603Snp}; 471296603Snp 472296603Snpstruct memwin { 473296603Snp struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 474296603Snp uint32_t mw_base; /* constant after setup_memwin */ 475296603Snp uint32_t mw_aperture; /* ditto */ 476296603Snp uint32_t mw_curpos; /* protected by mw_lock */ 477296603Snp}; 478296603Snp 479296603Snpenum { 480228561Snp FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 481228561Snp FL_DOOMED = (1 << 1), /* about to be destroyed */ 482255050Snp FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 483269428Snp FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 484228561Snp}; 485228561Snp 486269428Snp#define FL_RUNNING_LOW(fl) \ 487269428Snp (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 488269428Snp#define FL_NOT_RUNNING_LOW(fl) \ 489269428Snp (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 490228561Snp 491218792Snpstruct sge_fl { 492218792Snp struct mtx fl_lock; 493218792Snp __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 494218792Snp struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 495269428Snp struct cluster_layout cll_def; /* default refill zone, layout */ 496269428Snp uint16_t lowat; /* # of buffers <= this means fl needs help */ 497269428Snp int flags; 498269428Snp uint16_t buf_boundary; 499263317Snp 500269428Snp /* The 16b idx all deal with hw descriptors */ 501269428Snp uint16_t dbidx; /* hw pidx after last doorbell */ 502269428Snp uint16_t sidx; /* index of status page */ 503269428Snp volatile uint16_t hw_cidx; 504263317Snp 505269428Snp /* The 32b idx are all buffer idx, not hardware descriptor idx */ 506269428Snp uint32_t cidx; /* consumer index */ 507269428Snp uint32_t pidx; /* producer index */ 508269428Snp 509269428Snp uint32_t dbval; 510269428Snp u_int rx_offset; /* offset in fl buf (when buffer packing) */ 511269428Snp volatile uint32_t *udb; 512269428Snp 513263317Snp uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 514263317Snp uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 515263317Snp uint64_t cl_allocated; /* # of clusters allocated */ 516263317Snp uint64_t cl_recycled; /* # of clusters recycled */ 517263317Snp uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 518269428Snp 519269428Snp /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 520269428Snp struct mbuf *m0; 521269428Snp struct mbuf **pnext; 522269428Snp u_int remaining; 523269428Snp 524269428Snp uint16_t qsize; /* # of hw descriptors (status page included) */ 525269428Snp uint16_t cntxt_id; /* SGE context id for the freelist */ 526269428Snp TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 527269428Snp bus_dma_tag_t desc_tag; 528269428Snp bus_dmamap_t desc_map; 529269428Snp char lockname[16]; 530269428Snp bus_addr_t ba; /* bus address of descriptor ring */ 531269428Snp struct cluster_layout cll_alt; /* alternate refill zone, layout */ 532218792Snp}; 533218792Snp 534276485Snpstruct mp_ring; 535276485Snp 536220873Snp/* txq: SGE egress queue + what's needed for Ethernet NIC */ 537218792Snpstruct sge_txq { 538218792Snp struct sge_eq eq; /* MUST be first */ 539220873Snp 540220873Snp struct ifnet *ifp; /* the interface this txq belongs to */ 541276485Snp struct mp_ring *r; /* tx software ring */ 542220873Snp struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 543276485Snp struct sglist *gl; 544276485Snp __be32 cpl_ctrl0; /* for convenience */ 545301628Snp int tc_idx; /* traffic class */ 546218792Snp 547276485Snp struct task tx_reclaim_task; 548218792Snp /* stats for common events first */ 549218792Snp 550218792Snp uint64_t txcsum; /* # of times hardware assisted with checksum */ 551237819Snp uint64_t tso_wrs; /* # of TSO work requests */ 552218792Snp uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 553218792Snp uint64_t imm_wrs; /* # of work requests with immediate data */ 554218792Snp uint64_t sgl_wrs; /* # of work requests with direct SGL */ 555218792Snp uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 556276485Snp uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 557276485Snp uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 558276485Snp uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 559276485Snp uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 560218792Snp 561218792Snp /* stats for not-that-common events */ 562220873Snp} __aligned(CACHE_LINE_SIZE); 563218792Snp 564218792Snp/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 565218792Snpstruct sge_rxq { 566218792Snp struct sge_iq iq; /* MUST be first */ 567228561Snp struct sge_fl fl; /* MUST follow iq */ 568218792Snp 569219290Snp struct ifnet *ifp; /* the interface this rxq belongs to */ 570237819Snp#if defined(INET) || defined(INET6) 571218792Snp struct lro_ctrl lro; /* LRO state */ 572219290Snp#endif 573218792Snp 574218792Snp /* stats for common events first */ 575218792Snp 576218792Snp uint64_t rxcsum; /* # of times hardware assisted with checksum */ 577218792Snp uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 578218792Snp 579218792Snp /* stats for not-that-common events */ 580218792Snp 581218792Snp} __aligned(CACHE_LINE_SIZE); 582218792Snp 583237263Snpstatic inline struct sge_rxq * 584237263Snpiq_to_rxq(struct sge_iq *iq) 585237263Snp{ 586237263Snp 587241733Sed return (__containerof(iq, struct sge_rxq, iq)); 588237263Snp} 589237263Snp 590237263Snp 591228561Snp/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 592228561Snpstruct sge_ofld_rxq { 593228561Snp struct sge_iq iq; /* MUST be first */ 594228561Snp struct sge_fl fl; /* MUST follow iq */ 595228561Snp} __aligned(CACHE_LINE_SIZE); 596237263Snp 597237263Snpstatic inline struct sge_ofld_rxq * 598237263Snpiq_to_ofld_rxq(struct sge_iq *iq) 599237263Snp{ 600237263Snp 601241733Sed return (__containerof(iq, struct sge_ofld_rxq, iq)); 602237263Snp} 603228561Snp 604237263Snpstruct wrqe { 605237263Snp STAILQ_ENTRY(wrqe) link; 606237263Snp struct sge_wrq *wrq; 607237263Snp int wr_len; 608276485Snp char wr[] __aligned(16); 609237263Snp}; 610237263Snp 611276485Snpstruct wrq_cookie { 612276485Snp TAILQ_ENTRY(wrq_cookie) link; 613276485Snp int ndesc; 614276485Snp int pidx; 615276485Snp}; 616276485Snp 617228561Snp/* 618228561Snp * wrq: SGE egress queue that is given prebuilt work requests. Both the control 619228561Snp * and offload tx queues are of this type. 620228561Snp */ 621228561Snpstruct sge_wrq { 622220873Snp struct sge_eq eq; /* MUST be first */ 623220873Snp 624228561Snp struct adapter *adapter; 625276485Snp struct task wrq_tx_task; 626228561Snp 627276485Snp /* Tx desc reserved but WR not "committed" yet. */ 628276485Snp TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 629276485Snp 630276485Snp /* List of WRs ready to go out as soon as descriptors are available. */ 631237263Snp STAILQ_HEAD(, wrqe) wr_list; 632276485Snp u_int nwr_pending; 633276485Snp u_int ndesc_needed; 634237263Snp 635220873Snp /* stats for common events first */ 636220873Snp 637276485Snp uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 638276485Snp uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 639276485Snp uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 640220873Snp 641220873Snp /* stats for not-that-common events */ 642220873Snp 643276485Snp /* 644276485Snp * Scratch space for work requests that wrap around after reaching the 645298955Spfg * status page, and some information about the last WR that used it. 646276485Snp */ 647276485Snp uint16_t ss_pidx; 648276485Snp uint16_t ss_len; 649276485Snp uint8_t ss[SGE_MAX_WR_LEN]; 650276485Snp 651220873Snp} __aligned(CACHE_LINE_SIZE); 652220873Snp 653266757Snp 654266757Snpstruct sge_nm_rxq { 655291665Sjhb struct vi_info *vi; 656266757Snp 657269411Snp struct iq_desc *iq_desc; 658266757Snp uint16_t iq_abs_id; 659266757Snp uint16_t iq_cntxt_id; 660266757Snp uint16_t iq_cidx; 661266757Snp uint16_t iq_sidx; 662266757Snp uint8_t iq_gen; 663266757Snp 664266757Snp __be64 *fl_desc; 665266757Snp uint16_t fl_cntxt_id; 666266757Snp uint32_t fl_cidx; 667266757Snp uint32_t fl_pidx; 668266757Snp uint32_t fl_sidx; 669266757Snp uint32_t fl_db_val; 670266757Snp u_int fl_hwidx:4; 671266757Snp 672266757Snp u_int nid; /* netmap ring # for this queue */ 673266757Snp 674266757Snp /* infrequently used items after this */ 675266757Snp 676266757Snp bus_dma_tag_t iq_desc_tag; 677266757Snp bus_dmamap_t iq_desc_map; 678266757Snp bus_addr_t iq_ba; 679266757Snp int intr_idx; 680266757Snp 681266757Snp bus_dma_tag_t fl_desc_tag; 682266757Snp bus_dmamap_t fl_desc_map; 683266757Snp bus_addr_t fl_ba; 684266757Snp} __aligned(CACHE_LINE_SIZE); 685266757Snp 686266757Snpstruct sge_nm_txq { 687266757Snp struct tx_desc *desc; 688266757Snp uint16_t cidx; 689266757Snp uint16_t pidx; 690266757Snp uint16_t sidx; 691266757Snp uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 692266757Snp uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 693266757Snp uint16_t dbidx; /* pidx of the most recent doorbell */ 694266757Snp uint16_t doorbells; 695266757Snp volatile uint32_t *udb; 696266757Snp u_int udb_qid; 697266757Snp u_int cntxt_id; 698266757Snp __be32 cpl_ctrl0; /* for convenience */ 699266757Snp u_int nid; /* netmap ring # for this queue */ 700266757Snp 701266757Snp /* infrequently used items after this */ 702266757Snp 703266757Snp bus_dma_tag_t desc_tag; 704266757Snp bus_dmamap_t desc_map; 705266757Snp bus_addr_t ba; 706266757Snp int iqidx; 707266757Snp} __aligned(CACHE_LINE_SIZE); 708266757Snp 709218792Snpstruct sge { 710228561Snp int nrxq; /* total # of Ethernet rx queues */ 711318854Snp int ntxq; /* total # of Ethernet tx queues */ 712228561Snp int nofldrxq; /* total # of TOE rx queues */ 713228561Snp int nofldtxq; /* total # of TOE tx queues */ 714266757Snp int nnmrxq; /* total # of netmap rx queues */ 715266757Snp int nnmtxq; /* total # of netmap tx queues */ 716228561Snp int niq; /* total # of ingress queues */ 717228561Snp int neq; /* total # of egress queues */ 718218792Snp 719218792Snp struct sge_iq fwq; /* Firmware event queue */ 720228561Snp struct sge_wrq mgmtq; /* Management queue (control queue) */ 721228561Snp struct sge_wrq *ctrlq; /* Control queues */ 722218792Snp struct sge_txq *txq; /* NIC tx queues */ 723218792Snp struct sge_rxq *rxq; /* NIC rx queues */ 724228561Snp struct sge_wrq *ofld_txq; /* TOE tx queues */ 725228561Snp struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 726266757Snp struct sge_nm_txq *nm_txq; /* netmap tx queues */ 727266757Snp struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 728218792Snp 729306664Sjhb uint16_t iq_start; /* first cntxt_id */ 730306664Sjhb uint16_t iq_base; /* first abs_id */ 731306664Sjhb int eq_start; /* first cntxt_id */ 732306664Sjhb int eq_base; /* first abs_id */ 733218792Snp struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 734218792Snp struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 735255050Snp 736263317Snp int8_t safe_hwidx1; /* may not have room for metadata */ 737263317Snp int8_t safe_hwidx2; /* with room for metadata and maybe more */ 738263317Snp struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 739263317Snp struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 740218792Snp}; 741218792Snp 742309560Sjhbstruct devnames { 743309560Sjhb const char *nexus_name; 744309560Sjhb const char *ifnet_name; 745309560Sjhb const char *vi_ifnet_name; 746309560Sjhb const char *pf03_drv_name; 747309560Sjhb const char *vf_nexus_name; 748309560Sjhb const char *vf_ifnet_name; 749309560Sjhb}; 750309560Sjhb 751218792Snpstruct adapter { 752228561Snp SLIST_ENTRY(adapter) link; 753218792Snp device_t dev; 754218792Snp struct cdev *cdev; 755309560Sjhb const struct devnames *names; 756218792Snp 757218792Snp /* PCIe register resources */ 758218792Snp int regs_rid; 759218792Snp struct resource *regs_res; 760218792Snp int msix_rid; 761218792Snp struct resource *msix_res; 762218792Snp bus_space_handle_t bh; 763218792Snp bus_space_tag_t bt; 764218792Snp bus_size_t mmio_len; 765248925Snp int udbs_rid; 766248925Snp struct resource *udbs_res; 767248925Snp volatile uint8_t *udbs_base; 768218792Snp 769218792Snp unsigned int pf; 770218792Snp unsigned int mbox; 771296489Snp unsigned int vpd_busy; 772296489Snp unsigned int vpd_flag; 773218792Snp 774218792Snp /* Interrupt information */ 775218792Snp int intr_type; 776218792Snp int intr_count; 777218792Snp struct irq { 778218792Snp struct resource *res; 779218792Snp int rid; 780302110Snp volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 781218792Snp void *tag; 782302110Snp struct sge_rxq *rxq; 783302110Snp struct sge_nm_rxq *nm_rxq; 784302110Snp } __aligned(CACHE_LINE_SIZE) *irq; 785306664Sjhb int sge_gts_reg; 786306664Sjhb int sge_kdoorbell_reg; 787218792Snp 788218792Snp bus_dma_tag_t dmat; /* Parent DMA tag */ 789218792Snp 790218792Snp struct sge sge; 791255015Snp int lro_timeout; 792302339Snp int sc_do_rxcopy; 793218792Snp 794296383Snp struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 795218792Snp struct port_info *port[MAX_NPORTS]; 796330307Snp uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 797218792Snp 798237263Snp void *tom_softc; /* (struct tom_data *) */ 799228561Snp struct tom_tunables tt; 800331769Shselasky struct iw_tunables iwt; 801255005Snp void *iwarp_softc; /* (struct c4iw_dev *) */ 802292736Snp void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 803222509Snp struct l2t_data *l2t; /* L2 table */ 804218792Snp struct tid_info tids; 805218792Snp 806266757Snp uint16_t doorbells; 807278374Snp int offload_map; /* ports with IFCAP_TOE enabled */ 808278374Snp int active_ulds; /* ULDs activated on this adapter */ 809218792Snp int flags; 810284445Snp int debug_flags; 811218792Snp 812253691Snp char ifp_lockname[16]; 813253691Snp struct mtx ifp_lock; 814253691Snp struct ifnet *ifp; /* tracer ifp */ 815253691Snp struct ifmedia media; 816253691Snp int traceq; /* iq used by all tracers, -1 if none */ 817253691Snp int tracer_valid; /* bitmap of valid tracers */ 818253691Snp int tracer_enabled; /* bitmap of enabled tracers */ 819253691Snp 820296641Snp char fw_version[16]; 821296641Snp char tp_version[16]; 822309458Sjhb char er_version[16]; 823309458Sjhb char bs_version[16]; 824245936Snp char cfg_file[32]; 825245936Snp u_int cfcsum; 826218792Snp struct adapter_params params; 827296383Snp const struct chip_params *chip_params; 828218792Snp struct t4_virt_res vres; 829218792Snp 830296710Snp uint16_t nbmcaps; 831228561Snp uint16_t linkcaps; 832296710Snp uint16_t switchcaps; 833228561Snp uint16_t niccaps; 834228561Snp uint16_t toecaps; 835228561Snp uint16_t rdmacaps; 836309560Sjhb uint16_t cryptocaps; 837228561Snp uint16_t iscsicaps; 838228561Snp uint16_t fcoecaps; 839220873Snp 840228561Snp struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 841228561Snp 842218792Snp struct mtx sc_lock; 843218792Snp char lockname[16]; 844228561Snp 845228561Snp /* Starving free lists */ 846228561Snp struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 847228561Snp TAILQ_HEAD(, sge_fl) sfl; 848228561Snp struct callout sfl_callout; 849228561Snp 850296552Snp struct mtx reg_lock; /* for indirect register access */ 851272200Snp 852296603Snp struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 853296603Snp 854318850Snp struct mtx tc_lock; 855318850Snp struct task tc_task; 856318850Snp 857245274Snp const char *last_op; 858245274Snp const void *last_op_thr; 859286926Snp int last_op_flags; 860218792Snp}; 861218792Snp 862218792Snp#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 863218792Snp#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 864218792Snp#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 865218792Snp#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 866218792Snp 867245274Snp#define ASSERT_SYNCHRONIZED_OP(sc) \ 868245274Snp KASSERT(IS_BUSY(sc) && \ 869245274Snp (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 870245274Snp ("%s: operation not synchronized.", __func__)) 871245274Snp 872218792Snp#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 873218792Snp#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 874218792Snp#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 875218792Snp#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 876218792Snp 877218792Snp#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 878218792Snp#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 879218792Snp#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 880218792Snp#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 881218792Snp#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 882218792Snp 883218792Snp#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 884218792Snp#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 885218792Snp#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 886218792Snp#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 887218792Snp 888218792Snp#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 889218792Snp#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 890218792Snp#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 891218792Snp#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 892218792Snp#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 893218792Snp 894218792Snp#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 895218792Snp#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 896218792Snp#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 897218792Snp#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 898218792Snp#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 899218792Snp 900284445Snp#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 901284445Snp do { \ 902284445Snp if (sc->debug_flags & DF_DUMP_MBOX) { \ 903284445Snp log(LOG_NOTICE, \ 904284445Snp "%s mbox %u: %016llx %016llx %016llx %016llx " \ 905284445Snp "%016llx %016llx %016llx %016llx\n", \ 906284445Snp device_get_nameunit(sc->dev), mbox, \ 907284445Snp (unsigned long long)t4_read_reg64(sc, data_reg), \ 908284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 909284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 910284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 911284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 912284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 913284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 914284445Snp (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 915284445Snp } \ 916284445Snp } while (0) 917284445Snp 918291665Sjhb#define for_each_txq(vi, iter, q) \ 919291665Sjhb for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 920291665Sjhb iter < vi->ntxq; ++iter, ++q) 921291665Sjhb#define for_each_rxq(vi, iter, q) \ 922291665Sjhb for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 923291665Sjhb iter < vi->nrxq; ++iter, ++q) 924291665Sjhb#define for_each_ofld_txq(vi, iter, q) \ 925291665Sjhb for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 926291665Sjhb iter < vi->nofldtxq; ++iter, ++q) 927291665Sjhb#define for_each_ofld_rxq(vi, iter, q) \ 928291665Sjhb for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 929291665Sjhb iter < vi->nofldrxq; ++iter, ++q) 930291665Sjhb#define for_each_nm_txq(vi, iter, q) \ 931302110Snp for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 932302110Snp iter < vi->nnmtxq; ++iter, ++q) 933291665Sjhb#define for_each_nm_rxq(vi, iter, q) \ 934302110Snp for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 935302110Snp iter < vi->nnmrxq; ++iter, ++q) 936291665Sjhb#define for_each_vi(_pi, _iter, _vi) \ 937291665Sjhb for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 938291665Sjhb ++(_iter), ++(_vi)) 939218792Snp 940269428Snp#define IDXINCR(idx, incr, wrap) do { \ 941269428Snp idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 942269411Snp} while (0) 943269411Snp#define IDXDIFF(head, tail, wrap) \ 944269428Snp ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 945269411Snp 946222510Snp/* One for errors, one for firmware events */ 947222510Snp#define T4_EXTRA_INTR 2 948218792Snp 949306664Sjhb/* One for firmware events */ 950306664Sjhb#define T4VF_EXTRA_INTR 1 951306664Sjhb 952330307Snpstatic inline int 953330307Snpforwarding_intr_to_fwq(struct adapter *sc) 954330307Snp{ 955330307Snp 956330307Snp return (sc->intr_count == 1); 957330307Snp} 958330307Snp 959218792Snpstatic inline uint32_t 960218792Snpt4_read_reg(struct adapter *sc, uint32_t reg) 961218792Snp{ 962237263Snp 963218792Snp return bus_space_read_4(sc->bt, sc->bh, reg); 964218792Snp} 965218792Snp 966218792Snpstatic inline void 967218792Snpt4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 968218792Snp{ 969237263Snp 970218792Snp bus_space_write_4(sc->bt, sc->bh, reg, val); 971218792Snp} 972218792Snp 973218792Snpstatic inline uint64_t 974218792Snpt4_read_reg64(struct adapter *sc, uint32_t reg) 975218792Snp{ 976237263Snp 977311260Snp#ifdef __LP64__ 978311260Snp return bus_space_read_8(sc->bt, sc->bh, reg); 979311260Snp#else 980311260Snp return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 981311260Snp ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 982311260Snp 983311260Snp#endif 984218792Snp} 985218792Snp 986218792Snpstatic inline void 987218792Snpt4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 988218792Snp{ 989237263Snp 990311260Snp#ifdef __LP64__ 991311260Snp bus_space_write_8(sc->bt, sc->bh, reg, val); 992311260Snp#else 993311260Snp bus_space_write_4(sc->bt, sc->bh, reg, val); 994311260Snp bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 995311260Snp#endif 996218792Snp} 997218792Snp 998218792Snpstatic inline void 999218792Snpt4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1000218792Snp{ 1001237263Snp 1002218792Snp *val = pci_read_config(sc->dev, reg, 1); 1003218792Snp} 1004218792Snp 1005218792Snpstatic inline void 1006218792Snpt4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1007218792Snp{ 1008237263Snp 1009218792Snp pci_write_config(sc->dev, reg, val, 1); 1010218792Snp} 1011218792Snp 1012218792Snpstatic inline void 1013218792Snpt4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1014218792Snp{ 1015237263Snp 1016218792Snp *val = pci_read_config(sc->dev, reg, 2); 1017218792Snp} 1018218792Snp 1019218792Snpstatic inline void 1020218792Snpt4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1021218792Snp{ 1022237263Snp 1023218792Snp pci_write_config(sc->dev, reg, val, 2); 1024218792Snp} 1025218792Snp 1026218792Snpstatic inline void 1027218792Snpt4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1028218792Snp{ 1029237263Snp 1030218792Snp *val = pci_read_config(sc->dev, reg, 4); 1031218792Snp} 1032218792Snp 1033218792Snpstatic inline void 1034218792Snpt4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1035218792Snp{ 1036237263Snp 1037218792Snp pci_write_config(sc->dev, reg, val, 4); 1038218792Snp} 1039218792Snp 1040218792Snpstatic inline struct port_info * 1041218792Snpadap2pinfo(struct adapter *sc, int idx) 1042218792Snp{ 1043237263Snp 1044218792Snp return (sc->port[idx]); 1045218792Snp} 1046218792Snp 1047218792Snpstatic inline void 1048330307Snpt4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1049218792Snp{ 1050237263Snp 1051330307Snp bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1052218792Snp} 1053218792Snp 1054248925Snpstatic inline bool 1055248925Snpis_10G_port(const struct port_info *pi) 1056218792Snp{ 1057237263Snp 1058218792Snp return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1059218792Snp} 1060218792Snp 1061250092Snpstatic inline bool 1062309560Sjhbis_25G_port(const struct port_info *pi) 1063309560Sjhb{ 1064309560Sjhb 1065309560Sjhb return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1066309560Sjhb} 1067309560Sjhb 1068309560Sjhbstatic inline bool 1069250092Snpis_40G_port(const struct port_info *pi) 1070250092Snp{ 1071250092Snp 1072250092Snp return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1073250092Snp} 1074250092Snp 1075309560Sjhbstatic inline bool 1076309560Sjhbis_100G_port(const struct port_info *pi) 1077309560Sjhb{ 1078309560Sjhb 1079309560Sjhb return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1080309560Sjhb} 1081309560Sjhb 1082248925Snpstatic inline int 1083296018Snpport_top_speed(const struct port_info *pi) 1084296018Snp{ 1085296018Snp 1086296018Snp if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1087296018Snp return (100); 1088296018Snp if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1089296018Snp return (40); 1090309560Sjhb if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1091309560Sjhb return (25); 1092296018Snp if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1093296018Snp return (10); 1094296018Snp if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1095296018Snp return (1); 1096296018Snp 1097296018Snp return (0); 1098296018Snp} 1099296018Snp 1100296018Snpstatic inline int 1101248925Snptx_resume_threshold(struct sge_eq *eq) 1102228561Snp{ 1103237263Snp 1104276485Snp /* not quite the same as qsize / 4, but this will do. */ 1105276485Snp return (eq->sidx / 4); 1106228561Snp} 1107228561Snp 1108296481Snpstatic inline int 1109296481Snpt4_use_ldst(struct adapter *sc) 1110296481Snp{ 1111296481Snp 1112296481Snp#ifdef notyet 1113296481Snp return (sc->flags & FW_OK || !sc->use_bd); 1114296481Snp#else 1115296481Snp return (0); 1116296481Snp#endif 1117296481Snp} 1118296481Snp 1119219286Snp/* t4_main.c */ 1120330307Snpextern int t4_ntxq; 1121330307Snpextern int t4_nrxq; 1122306664Sjhbextern int t4_intr_types; 1123330307Snpextern int t4_tmr_idx; 1124330307Snpextern int t4_pktc_idx; 1125306664Sjhbextern unsigned int t4_qsize_rxq; 1126306664Sjhbextern unsigned int t4_qsize_txq; 1127306664Sjhbextern device_method_t cxgbe_methods[]; 1128306664Sjhb 1129218792Snpint t4_os_find_pci_capability(struct adapter *, int); 1130218792Snpint t4_os_pci_save_state(struct adapter *); 1131218792Snpint t4_os_pci_restore_state(struct adapter *); 1132330307Snpvoid t4_os_portmod_changed(struct port_info *); 1133330307Snpvoid t4_os_link_changed(struct port_info *); 1134228561Snpvoid t4_iterate(void (*)(struct adapter *, void *), void *); 1135309560Sjhbvoid t4_init_devnames(struct adapter *); 1136306664Sjhbvoid t4_add_adapter(struct adapter *); 1137306664Sjhbint t4_detach_common(device_t); 1138239338Snpint t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1139306664Sjhbint t4_map_bars_0_and_4(struct adapter *); 1140306664Sjhbint t4_map_bar_2(struct adapter *); 1141306664Sjhbint t4_setup_intr_handlers(struct adapter *); 1142306664Sjhbvoid t4_sysctls(struct adapter *); 1143291665Sjhbint begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1144291665Sjhbvoid doom_vi(struct adapter *, struct vi_info *); 1145245274Snpvoid end_synchronized_op(struct adapter *, int); 1146266757Snpint update_mac_settings(struct ifnet *, int); 1147266757Snpint adapter_full_init(struct adapter *); 1148266757Snpint adapter_full_uninit(struct adapter *); 1149291665Sjhbuint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1150291665Sjhbint vi_full_init(struct vi_info *); 1151291665Sjhbint vi_full_uninit(struct vi_info *); 1152291665Sjhbvoid vi_sysctls(struct vi_info *); 1153291665Sjhbvoid vi_tick(void *); 1154218792Snp 1155266757Snp#ifdef DEV_NETMAP 1156266757Snp/* t4_netmap.c */ 1157302110Snpvoid cxgbe_nm_attach(struct vi_info *); 1158302110Snpvoid cxgbe_nm_detach(struct vi_info *); 1159266757Snpvoid t4_nm_intr(void *); 1160266757Snp#endif 1161266757Snp 1162219286Snp/* t4_sge.c */ 1163219392Snpvoid t4_sge_modload(void); 1164269032Snpvoid t4_sge_modunload(void); 1165269032Snpuint64_t t4_sge_extfree_refs(void); 1166248925Snpvoid t4_tweak_chip_settings(struct adapter *); 1167248925Snpint t4_read_chip_settings(struct adapter *); 1168218792Snpint t4_create_dma_tag(struct adapter *); 1169253829Snpvoid t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1170253829Snp struct sysctl_oid_list *); 1171218792Snpint t4_destroy_dma_tag(struct adapter *); 1172220873Snpint t4_setup_adapter_queues(struct adapter *); 1173220873Snpint t4_teardown_adapter_queues(struct adapter *); 1174291665Sjhbint t4_setup_vi_queues(struct vi_info *); 1175291665Sjhbint t4_teardown_vi_queues(struct vi_info *); 1176218792Snpvoid t4_intr_all(void *); 1177222510Snpvoid t4_intr(void *); 1178302110Snpvoid t4_vi_intr(void *); 1179218792Snpvoid t4_intr_err(void *); 1180218792Snpvoid t4_intr_evt(void *); 1181237263Snpvoid t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1182218792Snpvoid t4_update_fl_bufsize(struct ifnet *); 1183306664Sjhbint parse_pkt(struct adapter *, struct mbuf **); 1184276485Snpvoid *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1185276485Snpvoid commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1186285221Snpint tnl_cong(struct port_info *, int); 1187302339Snpint t4_register_an_handler(an_handler_t); 1188302339Snpint t4_register_fw_msg_handler(int, fw_msg_handler_t); 1189302339Snpint t4_register_cpl_handler(int, cpl_handler_t); 1190218792Snp 1191253691Snp/* t4_tracer.c */ 1192253691Snpstruct t4_tracer; 1193253691Snpvoid t4_tracer_modload(void); 1194253691Snpvoid t4_tracer_modunload(void); 1195253691Snpvoid t4_tracer_port_detach(struct adapter *); 1196253691Snpint t4_get_tracer(struct adapter *, struct t4_tracer *); 1197253691Snpint t4_set_tracer(struct adapter *, struct t4_tracer *); 1198253691Snpint t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1199253691Snpint t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1200253691Snp 1201318850Snp/* t4_sched.c */ 1202318850Snpint t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1203318850Snpint t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1204318850Snpint t4_init_tx_sched(struct adapter *); 1205318850Snpint t4_free_tx_sched(struct adapter *); 1206318850Snpvoid t4_update_tx_sched(struct adapter *); 1207318850Snpint t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1208318850Snpvoid t4_release_cl_rl_kbps(struct adapter *, int, int); 1209318850Snp 1210237263Snpstatic inline struct wrqe * 1211237263Snpalloc_wrqe(int wr_len, struct sge_wrq *wrq) 1212228561Snp{ 1213237263Snp int len = offsetof(struct wrqe, wr) + wr_len; 1214237263Snp struct wrqe *wr; 1215228561Snp 1216237263Snp wr = malloc(len, M_CXGBE, M_NOWAIT); 1217237263Snp if (__predict_false(wr == NULL)) 1218237263Snp return (NULL); 1219237263Snp wr->wr_len = wr_len; 1220237263Snp wr->wrq = wrq; 1221237263Snp return (wr); 1222237263Snp} 1223237263Snp 1224237263Snpstatic inline void * 1225237263Snpwrtod(struct wrqe *wr) 1226237263Snp{ 1227237263Snp return (&wr->wr[0]); 1228237263Snp} 1229237263Snp 1230237263Snpstatic inline void 1231237263Snpfree_wrqe(struct wrqe *wr) 1232237263Snp{ 1233237263Snp free(wr, M_CXGBE); 1234237263Snp} 1235237263Snp 1236237263Snpstatic inline void 1237237263Snpt4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1238237263Snp{ 1239237263Snp struct sge_wrq *wrq = wr->wrq; 1240237263Snp 1241228561Snp TXQ_LOCK(wrq); 1242237263Snp t4_wrq_tx_locked(sc, wrq, wr); 1243228561Snp TXQ_UNLOCK(wrq); 1244228561Snp} 1245228561Snp 1246218792Snp#endif 1247