adapter.h revision 331769
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 331769 2018-03-30 18:06:29Z hselasky $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/rwlock.h> 41#include <sys/sx.h> 42#include <vm/uma.h> 43 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include <machine/bus.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_var.h> 52#include <net/if_media.h> 53#include <netinet/in.h> 54#include <netinet/tcp_lro.h> 55 56#include "offload.h" 57#include "t4_ioctl.h" 58#include "common/t4_msg.h" 59#include "firmware/t4fw_interface.h" 60 61#define KTR_CXGBE KTR_SPARE3 62MALLOC_DECLARE(M_CXGBE); 63#define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66#if defined(__i386__) || defined(__amd64__) 67static __inline void 68prefetch(void *x) 69{ 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71} 72#else 73#define prefetch(x) 74#endif 75 76#ifndef SYSCTL_ADD_UQUAD 77#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78#define sysctl_handle_64 sysctl_handle_quad 79#define CTLTYPE_U64 CTLTYPE_QUAD 80#endif 81 82#if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84#define SBUF_DRAIN 1 85#endif 86 87struct adapter; 88typedef struct adapter adapter_t; 89 90enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 128, 107 TX_EQ_QSIZE = 1024, 108 109#if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111#else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113#endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 120}; 121 122enum { 123 /* adapter intr_type */ 124 INTR_INTX = (1 << 0), 125 INTR_MSI = (1 << 1), 126 INTR_MSIX = (1 << 2) 127}; 128 129enum { 130 XGMAC_MTU = (1 << 0), 131 XGMAC_PROMISC = (1 << 1), 132 XGMAC_ALLMULTI = (1 << 2), 133 XGMAC_VLANEX = (1 << 3), 134 XGMAC_UCADDR = (1 << 4), 135 XGMAC_MCADDRS = (1 << 5), 136 137 XGMAC_ALL = 0xffff 138}; 139 140enum { 141 /* flags understood by begin_synchronized_op */ 142 HOLD_LOCK = (1 << 0), 143 SLEEP_OK = (1 << 1), 144 INTR_OK = (1 << 2), 145 146 /* flags understood by end_synchronized_op */ 147 LOCK_HELD = HOLD_LOCK, 148}; 149 150enum { 151 /* adapter flags */ 152 FULL_INIT_DONE = (1 << 0), 153 FW_OK = (1 << 1), 154 CHK_MBOX_ACCESS = (1 << 2), 155 MASTER_PF = (1 << 3), 156 ADAP_SYSCTL_CTX = (1 << 4), 157 /* TOM_INIT_DONE= (1 << 5), No longer used */ 158 BUF_PACKING_OK = (1 << 6), 159 IS_VF = (1 << 7), 160 161 CXGBE_BUSY = (1 << 9), 162 163 /* port flags */ 164 HAS_TRACEQ = (1 << 3), 165 166 /* VI flags */ 167 DOOMED = (1 << 0), 168 VI_INIT_DONE = (1 << 1), 169 VI_SYSCTL_CTX = (1 << 2), 170 171 /* adapter debug_flags */ 172 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 173 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 174 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 175}; 176 177#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 178#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 179#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 180#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 181#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 182 183struct vi_info { 184 device_t dev; 185 struct port_info *pi; 186 187 struct ifnet *ifp; 188 189 unsigned long flags; 190 int if_flags; 191 192 uint16_t *rss, *nm_rss; 193 int smt_idx; /* for convenience */ 194 uint16_t viid; 195 int16_t xact_addr_filt;/* index of exact MAC address filter */ 196 uint16_t rss_size; /* size of VI's RSS table slice */ 197 uint16_t rss_base; /* start of VI's RSS table slice */ 198 199 eventhandler_tag vlan_c; 200 201 int nintr; 202 int first_intr; 203 204 /* These need to be int as they are used in sysctl */ 205 int ntxq; /* # of tx queues */ 206 int first_txq; /* index of first tx queue */ 207 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 208 int nrxq; /* # of rx queues */ 209 int first_rxq; /* index of first rx queue */ 210 int nofldtxq; /* # of offload tx queues */ 211 int first_ofld_txq; /* index of first offload tx queue */ 212 int nofldrxq; /* # of offload rx queues */ 213 int first_ofld_rxq; /* index of first offload rx queue */ 214 int nnmtxq; 215 int first_nm_txq; 216 int nnmrxq; 217 int first_nm_rxq; 218 int tmr_idx; 219 int ofld_tmr_idx; 220 int pktc_idx; 221 int ofld_pktc_idx; 222 int qsize_rxq; 223 int qsize_txq; 224 225 struct timeval last_refreshed; 226 struct fw_vi_stats_vf stats; 227 228 struct callout tick; 229 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 230 231 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 232}; 233 234struct tx_ch_rl_params { 235 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 236 uint32_t maxrate; 237}; 238 239enum { 240 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 241 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 242}; 243 244struct tx_cl_rl_params { 245 int refcount; 246 u_int flags; 247 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 248 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 249 enum fw_sched_params_mode mode; /* aggr or per-flow */ 250 uint32_t maxrate; 251 uint16_t pktsize; 252}; 253 254/* Tx scheduler parameters for a channel/port */ 255struct tx_sched_params { 256 /* Channel Rate Limiter */ 257 struct tx_ch_rl_params ch_rl; 258 259 /* Class WRR */ 260 /* XXX */ 261 262 /* Class Rate Limiter */ 263 struct tx_cl_rl_params cl_rl[]; 264}; 265 266struct port_info { 267 device_t dev; 268 struct adapter *adapter; 269 270 struct vi_info *vi; 271 int nvi; 272 int up_vis; 273 int uld_vis; 274 275 struct tx_sched_params *sched_params; 276 277 struct mtx pi_lock; 278 char lockname[16]; 279 unsigned long flags; 280 281 uint8_t lport; /* associated offload logical port */ 282 int8_t mdio_addr; 283 uint8_t port_type; 284 uint8_t mod_type; 285 uint8_t port_id; 286 uint8_t tx_chan; 287 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 288 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 289 290 struct link_config link_cfg; 291 struct link_config old_link_cfg; 292 struct ifmedia media; 293 294 struct timeval last_refreshed; 295 struct port_stats stats; 296 u_int tnl_cong_drops; 297 u_int tx_parse_error; 298 299 struct callout tick; 300}; 301 302#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 303 304/* Where the cluster came from, how it has been carved up. */ 305struct cluster_layout { 306 int8_t zidx; 307 int8_t hwidx; 308 uint16_t region1; /* mbufs laid out within this region */ 309 /* region2 is the DMA region */ 310 uint16_t region3; /* cluster_metadata within this region */ 311}; 312 313struct cluster_metadata { 314 u_int refcount; 315 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 316}; 317 318struct fl_sdesc { 319 caddr_t cl; 320 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 321 struct cluster_layout cll; 322}; 323 324struct tx_desc { 325 __be64 flit[8]; 326}; 327 328struct tx_sdesc { 329 struct mbuf *m; /* m_nextpkt linked chain of frames */ 330 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 331}; 332 333 334#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 335struct iq_desc { 336 struct rss_header rss; 337 uint8_t cpl[IQ_PAD]; 338 struct rsp_ctrl rsp; 339}; 340#undef IQ_PAD 341CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 342 343enum { 344 /* iq flags */ 345 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 346 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 347 /* 1 << 2 Used to be IQ_INTR */ 348 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 349 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 350 351 /* iq state */ 352 IQS_DISABLED = 0, 353 IQS_BUSY = 1, 354 IQS_IDLE = 2, 355 356 /* netmap related flags */ 357 NM_OFF = 0, 358 NM_ON = 1, 359 NM_BUSY = 2, 360}; 361 362struct sge_iq; 363struct rss_header; 364typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 365 struct mbuf *); 366typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 367typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 368 369/* 370 * Ingress Queue: T4 is producer, driver is consumer. 371 */ 372struct sge_iq { 373 uint32_t flags; 374 volatile int state; 375 struct adapter *adapter; 376 cpl_handler_t set_tcb_rpl; 377 cpl_handler_t l2t_write_rpl; 378 struct iq_desc *desc; /* KVA of descriptor ring */ 379 int8_t intr_pktc_idx; /* packet count threshold index */ 380 uint8_t gen; /* generation bit */ 381 uint8_t intr_params; /* interrupt holdoff parameters */ 382 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 383 uint16_t qsize; /* size (# of entries) of the queue */ 384 uint16_t sidx; /* index of the entry with the status page */ 385 uint16_t cidx; /* consumer index */ 386 uint16_t cntxt_id; /* SGE context id for the iq */ 387 uint16_t abs_id; /* absolute SGE id for the iq */ 388 389 STAILQ_ENTRY(sge_iq) link; 390 391 bus_dma_tag_t desc_tag; 392 bus_dmamap_t desc_map; 393 bus_addr_t ba; /* bus address of descriptor ring */ 394}; 395 396enum { 397 EQ_CTRL = 1, 398 EQ_ETH = 2, 399 EQ_OFLD = 3, 400 401 /* eq flags */ 402 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 403 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 404 EQ_ENABLED = (1 << 3), /* open for business */ 405 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 406}; 407 408/* Listed in order of preference. Update t4_sysctls too if you change these */ 409enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 410 411/* 412 * Egress Queue: driver is producer, T4 is consumer. 413 * 414 * Note: A free list is an egress queue (driver produces the buffers and T4 415 * consumes them) but it's special enough to have its own struct (see sge_fl). 416 */ 417struct sge_eq { 418 unsigned int flags; /* MUST be first */ 419 unsigned int cntxt_id; /* SGE context id for the eq */ 420 unsigned int abs_id; /* absolute SGE id for the eq */ 421 struct mtx eq_lock; 422 423 struct tx_desc *desc; /* KVA of descriptor ring */ 424 uint16_t doorbells; 425 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 426 u_int udb_qid; /* relative qid within the doorbell page */ 427 uint16_t sidx; /* index of the entry with the status page */ 428 uint16_t cidx; /* consumer idx (desc idx) */ 429 uint16_t pidx; /* producer idx (desc idx) */ 430 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 431 uint16_t dbidx; /* pidx of the most recent doorbell */ 432 uint16_t iqid; /* iq that gets egr_update for the eq */ 433 uint8_t tx_chan; /* tx channel used by the eq */ 434 volatile u_int equiq; /* EQUIQ outstanding */ 435 436 bus_dma_tag_t desc_tag; 437 bus_dmamap_t desc_map; 438 bus_addr_t ba; /* bus address of descriptor ring */ 439 char lockname[16]; 440}; 441 442struct sw_zone_info { 443 uma_zone_t zone; /* zone that this cluster comes from */ 444 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 445 int type; /* EXT_xxx type of the cluster */ 446 int8_t head_hwidx; 447 int8_t tail_hwidx; 448}; 449 450struct hw_buf_info { 451 int8_t zidx; /* backpointer to zone; -ve means unused */ 452 int8_t next; /* next hwidx for this zone; -1 means no more */ 453 int size; 454}; 455 456enum { 457 NUM_MEMWIN = 3, 458 459 MEMWIN0_APERTURE = 2048, 460 MEMWIN0_BASE = 0x1b800, 461 462 MEMWIN1_APERTURE = 32768, 463 MEMWIN1_BASE = 0x28000, 464 465 MEMWIN2_APERTURE_T4 = 65536, 466 MEMWIN2_BASE_T4 = 0x30000, 467 468 MEMWIN2_APERTURE_T5 = 128 * 1024, 469 MEMWIN2_BASE_T5 = 0x60000, 470}; 471 472struct memwin { 473 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 474 uint32_t mw_base; /* constant after setup_memwin */ 475 uint32_t mw_aperture; /* ditto */ 476 uint32_t mw_curpos; /* protected by mw_lock */ 477}; 478 479enum { 480 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 481 FL_DOOMED = (1 << 1), /* about to be destroyed */ 482 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 483 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 484}; 485 486#define FL_RUNNING_LOW(fl) \ 487 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 488#define FL_NOT_RUNNING_LOW(fl) \ 489 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 490 491struct sge_fl { 492 struct mtx fl_lock; 493 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 494 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 495 struct cluster_layout cll_def; /* default refill zone, layout */ 496 uint16_t lowat; /* # of buffers <= this means fl needs help */ 497 int flags; 498 uint16_t buf_boundary; 499 500 /* The 16b idx all deal with hw descriptors */ 501 uint16_t dbidx; /* hw pidx after last doorbell */ 502 uint16_t sidx; /* index of status page */ 503 volatile uint16_t hw_cidx; 504 505 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 506 uint32_t cidx; /* consumer index */ 507 uint32_t pidx; /* producer index */ 508 509 uint32_t dbval; 510 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 511 volatile uint32_t *udb; 512 513 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 514 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 515 uint64_t cl_allocated; /* # of clusters allocated */ 516 uint64_t cl_recycled; /* # of clusters recycled */ 517 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 518 519 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 520 struct mbuf *m0; 521 struct mbuf **pnext; 522 u_int remaining; 523 524 uint16_t qsize; /* # of hw descriptors (status page included) */ 525 uint16_t cntxt_id; /* SGE context id for the freelist */ 526 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 527 bus_dma_tag_t desc_tag; 528 bus_dmamap_t desc_map; 529 char lockname[16]; 530 bus_addr_t ba; /* bus address of descriptor ring */ 531 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 532}; 533 534struct mp_ring; 535 536/* txq: SGE egress queue + what's needed for Ethernet NIC */ 537struct sge_txq { 538 struct sge_eq eq; /* MUST be first */ 539 540 struct ifnet *ifp; /* the interface this txq belongs to */ 541 struct mp_ring *r; /* tx software ring */ 542 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 543 struct sglist *gl; 544 __be32 cpl_ctrl0; /* for convenience */ 545 int tc_idx; /* traffic class */ 546 547 struct task tx_reclaim_task; 548 /* stats for common events first */ 549 550 uint64_t txcsum; /* # of times hardware assisted with checksum */ 551 uint64_t tso_wrs; /* # of TSO work requests */ 552 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 553 uint64_t imm_wrs; /* # of work requests with immediate data */ 554 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 555 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 556 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 557 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 558 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 559 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 560 561 /* stats for not-that-common events */ 562} __aligned(CACHE_LINE_SIZE); 563 564/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 565struct sge_rxq { 566 struct sge_iq iq; /* MUST be first */ 567 struct sge_fl fl; /* MUST follow iq */ 568 569 struct ifnet *ifp; /* the interface this rxq belongs to */ 570#if defined(INET) || defined(INET6) 571 struct lro_ctrl lro; /* LRO state */ 572#endif 573 574 /* stats for common events first */ 575 576 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 577 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 578 579 /* stats for not-that-common events */ 580 581} __aligned(CACHE_LINE_SIZE); 582 583static inline struct sge_rxq * 584iq_to_rxq(struct sge_iq *iq) 585{ 586 587 return (__containerof(iq, struct sge_rxq, iq)); 588} 589 590 591/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 592struct sge_ofld_rxq { 593 struct sge_iq iq; /* MUST be first */ 594 struct sge_fl fl; /* MUST follow iq */ 595} __aligned(CACHE_LINE_SIZE); 596 597static inline struct sge_ofld_rxq * 598iq_to_ofld_rxq(struct sge_iq *iq) 599{ 600 601 return (__containerof(iq, struct sge_ofld_rxq, iq)); 602} 603 604struct wrqe { 605 STAILQ_ENTRY(wrqe) link; 606 struct sge_wrq *wrq; 607 int wr_len; 608 char wr[] __aligned(16); 609}; 610 611struct wrq_cookie { 612 TAILQ_ENTRY(wrq_cookie) link; 613 int ndesc; 614 int pidx; 615}; 616 617/* 618 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 619 * and offload tx queues are of this type. 620 */ 621struct sge_wrq { 622 struct sge_eq eq; /* MUST be first */ 623 624 struct adapter *adapter; 625 struct task wrq_tx_task; 626 627 /* Tx desc reserved but WR not "committed" yet. */ 628 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 629 630 /* List of WRs ready to go out as soon as descriptors are available. */ 631 STAILQ_HEAD(, wrqe) wr_list; 632 u_int nwr_pending; 633 u_int ndesc_needed; 634 635 /* stats for common events first */ 636 637 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 638 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 639 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 640 641 /* stats for not-that-common events */ 642 643 /* 644 * Scratch space for work requests that wrap around after reaching the 645 * status page, and some information about the last WR that used it. 646 */ 647 uint16_t ss_pidx; 648 uint16_t ss_len; 649 uint8_t ss[SGE_MAX_WR_LEN]; 650 651} __aligned(CACHE_LINE_SIZE); 652 653 654struct sge_nm_rxq { 655 struct vi_info *vi; 656 657 struct iq_desc *iq_desc; 658 uint16_t iq_abs_id; 659 uint16_t iq_cntxt_id; 660 uint16_t iq_cidx; 661 uint16_t iq_sidx; 662 uint8_t iq_gen; 663 664 __be64 *fl_desc; 665 uint16_t fl_cntxt_id; 666 uint32_t fl_cidx; 667 uint32_t fl_pidx; 668 uint32_t fl_sidx; 669 uint32_t fl_db_val; 670 u_int fl_hwidx:4; 671 672 u_int nid; /* netmap ring # for this queue */ 673 674 /* infrequently used items after this */ 675 676 bus_dma_tag_t iq_desc_tag; 677 bus_dmamap_t iq_desc_map; 678 bus_addr_t iq_ba; 679 int intr_idx; 680 681 bus_dma_tag_t fl_desc_tag; 682 bus_dmamap_t fl_desc_map; 683 bus_addr_t fl_ba; 684} __aligned(CACHE_LINE_SIZE); 685 686struct sge_nm_txq { 687 struct tx_desc *desc; 688 uint16_t cidx; 689 uint16_t pidx; 690 uint16_t sidx; 691 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 692 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 693 uint16_t dbidx; /* pidx of the most recent doorbell */ 694 uint16_t doorbells; 695 volatile uint32_t *udb; 696 u_int udb_qid; 697 u_int cntxt_id; 698 __be32 cpl_ctrl0; /* for convenience */ 699 u_int nid; /* netmap ring # for this queue */ 700 701 /* infrequently used items after this */ 702 703 bus_dma_tag_t desc_tag; 704 bus_dmamap_t desc_map; 705 bus_addr_t ba; 706 int iqidx; 707} __aligned(CACHE_LINE_SIZE); 708 709struct sge { 710 int nrxq; /* total # of Ethernet rx queues */ 711 int ntxq; /* total # of Ethernet tx queues */ 712 int nofldrxq; /* total # of TOE rx queues */ 713 int nofldtxq; /* total # of TOE tx queues */ 714 int nnmrxq; /* total # of netmap rx queues */ 715 int nnmtxq; /* total # of netmap tx queues */ 716 int niq; /* total # of ingress queues */ 717 int neq; /* total # of egress queues */ 718 719 struct sge_iq fwq; /* Firmware event queue */ 720 struct sge_wrq mgmtq; /* Management queue (control queue) */ 721 struct sge_wrq *ctrlq; /* Control queues */ 722 struct sge_txq *txq; /* NIC tx queues */ 723 struct sge_rxq *rxq; /* NIC rx queues */ 724 struct sge_wrq *ofld_txq; /* TOE tx queues */ 725 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 726 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 727 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 728 729 uint16_t iq_start; /* first cntxt_id */ 730 uint16_t iq_base; /* first abs_id */ 731 int eq_start; /* first cntxt_id */ 732 int eq_base; /* first abs_id */ 733 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 734 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 735 736 int8_t safe_hwidx1; /* may not have room for metadata */ 737 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 738 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 739 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 740}; 741 742struct devnames { 743 const char *nexus_name; 744 const char *ifnet_name; 745 const char *vi_ifnet_name; 746 const char *pf03_drv_name; 747 const char *vf_nexus_name; 748 const char *vf_ifnet_name; 749}; 750 751struct adapter { 752 SLIST_ENTRY(adapter) link; 753 device_t dev; 754 struct cdev *cdev; 755 const struct devnames *names; 756 757 /* PCIe register resources */ 758 int regs_rid; 759 struct resource *regs_res; 760 int msix_rid; 761 struct resource *msix_res; 762 bus_space_handle_t bh; 763 bus_space_tag_t bt; 764 bus_size_t mmio_len; 765 int udbs_rid; 766 struct resource *udbs_res; 767 volatile uint8_t *udbs_base; 768 769 unsigned int pf; 770 unsigned int mbox; 771 unsigned int vpd_busy; 772 unsigned int vpd_flag; 773 774 /* Interrupt information */ 775 int intr_type; 776 int intr_count; 777 struct irq { 778 struct resource *res; 779 int rid; 780 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 781 void *tag; 782 struct sge_rxq *rxq; 783 struct sge_nm_rxq *nm_rxq; 784 } __aligned(CACHE_LINE_SIZE) *irq; 785 int sge_gts_reg; 786 int sge_kdoorbell_reg; 787 788 bus_dma_tag_t dmat; /* Parent DMA tag */ 789 790 struct sge sge; 791 int lro_timeout; 792 int sc_do_rxcopy; 793 794 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 795 struct port_info *port[MAX_NPORTS]; 796 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 797 798 void *tom_softc; /* (struct tom_data *) */ 799 struct tom_tunables tt; 800 struct iw_tunables iwt; 801 void *iwarp_softc; /* (struct c4iw_dev *) */ 802 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 803 struct l2t_data *l2t; /* L2 table */ 804 struct tid_info tids; 805 806 uint16_t doorbells; 807 int offload_map; /* ports with IFCAP_TOE enabled */ 808 int active_ulds; /* ULDs activated on this adapter */ 809 int flags; 810 int debug_flags; 811 812 char ifp_lockname[16]; 813 struct mtx ifp_lock; 814 struct ifnet *ifp; /* tracer ifp */ 815 struct ifmedia media; 816 int traceq; /* iq used by all tracers, -1 if none */ 817 int tracer_valid; /* bitmap of valid tracers */ 818 int tracer_enabled; /* bitmap of enabled tracers */ 819 820 char fw_version[16]; 821 char tp_version[16]; 822 char er_version[16]; 823 char bs_version[16]; 824 char cfg_file[32]; 825 u_int cfcsum; 826 struct adapter_params params; 827 const struct chip_params *chip_params; 828 struct t4_virt_res vres; 829 830 uint16_t nbmcaps; 831 uint16_t linkcaps; 832 uint16_t switchcaps; 833 uint16_t niccaps; 834 uint16_t toecaps; 835 uint16_t rdmacaps; 836 uint16_t cryptocaps; 837 uint16_t iscsicaps; 838 uint16_t fcoecaps; 839 840 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 841 842 struct mtx sc_lock; 843 char lockname[16]; 844 845 /* Starving free lists */ 846 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 847 TAILQ_HEAD(, sge_fl) sfl; 848 struct callout sfl_callout; 849 850 struct mtx reg_lock; /* for indirect register access */ 851 852 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 853 854 struct mtx tc_lock; 855 struct task tc_task; 856 857 const char *last_op; 858 const void *last_op_thr; 859 int last_op_flags; 860}; 861 862#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 863#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 864#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 865#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 866 867#define ASSERT_SYNCHRONIZED_OP(sc) \ 868 KASSERT(IS_BUSY(sc) && \ 869 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 870 ("%s: operation not synchronized.", __func__)) 871 872#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 873#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 874#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 875#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 876 877#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 878#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 879#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 880#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 881#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 882 883#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 884#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 885#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 886#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 887 888#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 889#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 890#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 891#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 892#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 893 894#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 895#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 896#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 897#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 898#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 899 900#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 901 do { \ 902 if (sc->debug_flags & DF_DUMP_MBOX) { \ 903 log(LOG_NOTICE, \ 904 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 905 "%016llx %016llx %016llx %016llx\n", \ 906 device_get_nameunit(sc->dev), mbox, \ 907 (unsigned long long)t4_read_reg64(sc, data_reg), \ 908 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 909 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 910 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 911 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 912 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 913 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 914 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 915 } \ 916 } while (0) 917 918#define for_each_txq(vi, iter, q) \ 919 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 920 iter < vi->ntxq; ++iter, ++q) 921#define for_each_rxq(vi, iter, q) \ 922 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 923 iter < vi->nrxq; ++iter, ++q) 924#define for_each_ofld_txq(vi, iter, q) \ 925 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 926 iter < vi->nofldtxq; ++iter, ++q) 927#define for_each_ofld_rxq(vi, iter, q) \ 928 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 929 iter < vi->nofldrxq; ++iter, ++q) 930#define for_each_nm_txq(vi, iter, q) \ 931 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 932 iter < vi->nnmtxq; ++iter, ++q) 933#define for_each_nm_rxq(vi, iter, q) \ 934 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 935 iter < vi->nnmrxq; ++iter, ++q) 936#define for_each_vi(_pi, _iter, _vi) \ 937 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 938 ++(_iter), ++(_vi)) 939 940#define IDXINCR(idx, incr, wrap) do { \ 941 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 942} while (0) 943#define IDXDIFF(head, tail, wrap) \ 944 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 945 946/* One for errors, one for firmware events */ 947#define T4_EXTRA_INTR 2 948 949/* One for firmware events */ 950#define T4VF_EXTRA_INTR 1 951 952static inline int 953forwarding_intr_to_fwq(struct adapter *sc) 954{ 955 956 return (sc->intr_count == 1); 957} 958 959static inline uint32_t 960t4_read_reg(struct adapter *sc, uint32_t reg) 961{ 962 963 return bus_space_read_4(sc->bt, sc->bh, reg); 964} 965 966static inline void 967t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 968{ 969 970 bus_space_write_4(sc->bt, sc->bh, reg, val); 971} 972 973static inline uint64_t 974t4_read_reg64(struct adapter *sc, uint32_t reg) 975{ 976 977#ifdef __LP64__ 978 return bus_space_read_8(sc->bt, sc->bh, reg); 979#else 980 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 981 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 982 983#endif 984} 985 986static inline void 987t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 988{ 989 990#ifdef __LP64__ 991 bus_space_write_8(sc->bt, sc->bh, reg, val); 992#else 993 bus_space_write_4(sc->bt, sc->bh, reg, val); 994 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 995#endif 996} 997 998static inline void 999t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1000{ 1001 1002 *val = pci_read_config(sc->dev, reg, 1); 1003} 1004 1005static inline void 1006t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1007{ 1008 1009 pci_write_config(sc->dev, reg, val, 1); 1010} 1011 1012static inline void 1013t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1014{ 1015 1016 *val = pci_read_config(sc->dev, reg, 2); 1017} 1018 1019static inline void 1020t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1021{ 1022 1023 pci_write_config(sc->dev, reg, val, 2); 1024} 1025 1026static inline void 1027t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1028{ 1029 1030 *val = pci_read_config(sc->dev, reg, 4); 1031} 1032 1033static inline void 1034t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1035{ 1036 1037 pci_write_config(sc->dev, reg, val, 4); 1038} 1039 1040static inline struct port_info * 1041adap2pinfo(struct adapter *sc, int idx) 1042{ 1043 1044 return (sc->port[idx]); 1045} 1046 1047static inline void 1048t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1049{ 1050 1051 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1052} 1053 1054static inline bool 1055is_10G_port(const struct port_info *pi) 1056{ 1057 1058 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1059} 1060 1061static inline bool 1062is_25G_port(const struct port_info *pi) 1063{ 1064 1065 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1066} 1067 1068static inline bool 1069is_40G_port(const struct port_info *pi) 1070{ 1071 1072 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1073} 1074 1075static inline bool 1076is_100G_port(const struct port_info *pi) 1077{ 1078 1079 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1080} 1081 1082static inline int 1083port_top_speed(const struct port_info *pi) 1084{ 1085 1086 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1087 return (100); 1088 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1089 return (40); 1090 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1091 return (25); 1092 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1093 return (10); 1094 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1095 return (1); 1096 1097 return (0); 1098} 1099 1100static inline int 1101tx_resume_threshold(struct sge_eq *eq) 1102{ 1103 1104 /* not quite the same as qsize / 4, but this will do. */ 1105 return (eq->sidx / 4); 1106} 1107 1108static inline int 1109t4_use_ldst(struct adapter *sc) 1110{ 1111 1112#ifdef notyet 1113 return (sc->flags & FW_OK || !sc->use_bd); 1114#else 1115 return (0); 1116#endif 1117} 1118 1119/* t4_main.c */ 1120extern int t4_ntxq; 1121extern int t4_nrxq; 1122extern int t4_intr_types; 1123extern int t4_tmr_idx; 1124extern int t4_pktc_idx; 1125extern unsigned int t4_qsize_rxq; 1126extern unsigned int t4_qsize_txq; 1127extern device_method_t cxgbe_methods[]; 1128 1129int t4_os_find_pci_capability(struct adapter *, int); 1130int t4_os_pci_save_state(struct adapter *); 1131int t4_os_pci_restore_state(struct adapter *); 1132void t4_os_portmod_changed(struct port_info *); 1133void t4_os_link_changed(struct port_info *); 1134void t4_iterate(void (*)(struct adapter *, void *), void *); 1135void t4_init_devnames(struct adapter *); 1136void t4_add_adapter(struct adapter *); 1137int t4_detach_common(device_t); 1138int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1139int t4_map_bars_0_and_4(struct adapter *); 1140int t4_map_bar_2(struct adapter *); 1141int t4_setup_intr_handlers(struct adapter *); 1142void t4_sysctls(struct adapter *); 1143int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1144void doom_vi(struct adapter *, struct vi_info *); 1145void end_synchronized_op(struct adapter *, int); 1146int update_mac_settings(struct ifnet *, int); 1147int adapter_full_init(struct adapter *); 1148int adapter_full_uninit(struct adapter *); 1149uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1150int vi_full_init(struct vi_info *); 1151int vi_full_uninit(struct vi_info *); 1152void vi_sysctls(struct vi_info *); 1153void vi_tick(void *); 1154 1155#ifdef DEV_NETMAP 1156/* t4_netmap.c */ 1157void cxgbe_nm_attach(struct vi_info *); 1158void cxgbe_nm_detach(struct vi_info *); 1159void t4_nm_intr(void *); 1160#endif 1161 1162/* t4_sge.c */ 1163void t4_sge_modload(void); 1164void t4_sge_modunload(void); 1165uint64_t t4_sge_extfree_refs(void); 1166void t4_tweak_chip_settings(struct adapter *); 1167int t4_read_chip_settings(struct adapter *); 1168int t4_create_dma_tag(struct adapter *); 1169void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1170 struct sysctl_oid_list *); 1171int t4_destroy_dma_tag(struct adapter *); 1172int t4_setup_adapter_queues(struct adapter *); 1173int t4_teardown_adapter_queues(struct adapter *); 1174int t4_setup_vi_queues(struct vi_info *); 1175int t4_teardown_vi_queues(struct vi_info *); 1176void t4_intr_all(void *); 1177void t4_intr(void *); 1178void t4_vi_intr(void *); 1179void t4_intr_err(void *); 1180void t4_intr_evt(void *); 1181void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1182void t4_update_fl_bufsize(struct ifnet *); 1183int parse_pkt(struct adapter *, struct mbuf **); 1184void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1185void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1186int tnl_cong(struct port_info *, int); 1187int t4_register_an_handler(an_handler_t); 1188int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1189int t4_register_cpl_handler(int, cpl_handler_t); 1190 1191/* t4_tracer.c */ 1192struct t4_tracer; 1193void t4_tracer_modload(void); 1194void t4_tracer_modunload(void); 1195void t4_tracer_port_detach(struct adapter *); 1196int t4_get_tracer(struct adapter *, struct t4_tracer *); 1197int t4_set_tracer(struct adapter *, struct t4_tracer *); 1198int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1199int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1200 1201/* t4_sched.c */ 1202int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1203int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1204int t4_init_tx_sched(struct adapter *); 1205int t4_free_tx_sched(struct adapter *); 1206void t4_update_tx_sched(struct adapter *); 1207int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1208void t4_release_cl_rl_kbps(struct adapter *, int, int); 1209 1210static inline struct wrqe * 1211alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1212{ 1213 int len = offsetof(struct wrqe, wr) + wr_len; 1214 struct wrqe *wr; 1215 1216 wr = malloc(len, M_CXGBE, M_NOWAIT); 1217 if (__predict_false(wr == NULL)) 1218 return (NULL); 1219 wr->wr_len = wr_len; 1220 wr->wrq = wrq; 1221 return (wr); 1222} 1223 1224static inline void * 1225wrtod(struct wrqe *wr) 1226{ 1227 return (&wr->wr[0]); 1228} 1229 1230static inline void 1231free_wrqe(struct wrqe *wr) 1232{ 1233 free(wr, M_CXGBE); 1234} 1235 1236static inline void 1237t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1238{ 1239 struct sge_wrq *wrq = wr->wrq; 1240 1241 TXQ_LOCK(wrq); 1242 t4_wrq_tx_locked(sc, wrq, wr); 1243 TXQ_UNLOCK(wrq); 1244} 1245 1246#endif 1247