1/*- 2 * Dallas DS2153, DS21x54 single-chip E1 tranceiver registers. 3 * 4 * Copyright (C) 1996 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * This software is distributed with NO WARRANTIES, not even the implied 8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9 * 10 * Authors grant any other persons or organisations permission to use 11 * or modify this software as long as this message is kept with the software, 12 * all derivative works or modified versions. 13 * 14 * Cronyx Id: ds2153.h,v 1.2.4.1 2003/11/12 17:22:33 rik Exp $ 15 * $FreeBSD$ 16 */ 17 18/* 19 * Control and test registers 20 */ 21#define DS_RCR1 0x10 /* rw - receive control 1 */ 22#define DS_RCR2 0x11 /* rw - receive control 2 */ 23#define DS_TCR1 0x12 /* rw - transmit control 1 */ 24#define DS_TCR2 0x13 /* rw - transmit control 2 */ 25#define DS_CCR1 0x14 /* rw - common control 1 */ 26#define DS_CCR2 0x1a /* rw - common control 2 */ 27#define DS_CCR3 0x1b /* rw - common control 3 */ 28#define DS_LICR 0x18 /* rw - line interface control */ 29#define DS_IMR1 0x16 /* rw - interrupt mask 1 */ 30#define DS_IMR2 0x17 /* rw - interrupt mask 2 */ 31#define DS_TEST1 0x15 /* rw - test 1 */ 32#define DS_TEST2 0x19 /* rw - test 2 */ 33 34/* 35 * Status and information registers 36 */ 37#define DS_RIR 0x08 /* r - receive information */ 38#define DS_SSR 0x1e /* r - synchronizer status */ 39#define DS_SR1 0x06 /* r - status 1 */ 40#define DS_SR2 0x07 /* r - status 2 */ 41 42/* 43 * Error count registers 44 */ 45#define DS_VCR1 0x00 /* r - BPV or code violation count 1 */ 46#define DS_VCR2 0x01 /* r - BPV or code violation count 2 */ 47#define DS_CRCCR1 0x02 /* r - CRC4 error count 1 */ 48#define DS_CRCCR2 0x03 /* r - CRC4 error count 2 */ 49#define DS_EBCR1 0x04 /* r - E-bit count 1 */ 50#define DS_EBCR2 0x05 /* r - E-bit count 2 */ 51#define DS_FASCR1 0x02 /* r - FAS error count 1 */ 52#define DS_FASCR2 0x04 /* r - FAS error count 2 */ 53 54/* 55 * Signaling registers 56 */ 57#define DS_RS 0x30 /* r - receive signaling 1..16 */ 58#define DS_TS 0x40 /* rw - transmit signaling 1..16 */ 59 60/* 61 * Transmit idle registers 62 */ 63#define DS_TIR 0x26 /* rw - transmit idle 1..4 */ 64#define DS_TIDR 0x2a /* rw - transmit idle definition */ 65 66/* 67 * Clock blocking registers 68 */ 69#define DS_RCBR 0x2b /* rw - receive channel blocking 1..4 */ 70#define DS_TCBR 0x22 /* rw - transmit channel blocking 1..4 */ 71 72/* 73 * Slot 0 registers 74 */ 75#define DS_RAF 0x2f /* r - receive align frame */ 76#define DS_RNAF 0x1f /* r - receive non-align frame */ 77#define DS_TAF 0x20 /* rw - transmit align frame */ 78#define DS_TNAF 0x21 /* rw - transmit non-align frame */ 79 80/*---------------------------------------------- 81 * Receive control register 1 82 */ 83#define RCR1_RSO 0x00 /* RSYNC outputs frame boundaries */ 84#define RCR1_RSI 0x20 /* RSYNC is input (elastic store) */ 85#define RCR1_RSO_CAS 0x40 /* RSYNC outputs CAS multiframe boundaries */ 86#define RCR1_RSO_CRC4 0xc0 /* RSYNC outputs CRC4 multiframe boundaries */ 87 88#define RCR1_FRC 0x04 /* frame resync criteria */ 89#define RCR1_SYNCD 0x02 /* auto resync disable */ 90#define RCR1_RESYNC 0x01 /* force resync */ 91 92/* 93 * Receive control register 2 94 */ 95#define RCR2_SA_8 0x80 /* output Sa8 bit at RLINK pin */ 96#define RCR2_SA_7 0x40 /* output Sa7 bit at RLINK pin */ 97#define RCR2_SA_6 0x20 /* output Sa6 bit at RLINK pin */ 98#define RCR2_SA_5 0x10 /* output Sa5 bit at RLINK pin */ 99#define RCR2_SA_4 0x08 /* output Sa4 bit at RLINK pin */ 100#define RCR2_RSCLKM 0x04 /* receive side SYSCLK mode 2048 */ 101#define RCR2_RESE 0x02 /* receive side elastic store enable */ 102 103/* 104 * Transmit control register 1 105 */ 106#define TCR1_TFPT 0x40 /* source timeslot 0 from TSER pin */ 107#define TCR1_T16S 0x20 /* source timeslot 16 from TS1..TS16 regs */ 108#define TCR1_TUA1 0x10 /* transmit unframed all ones */ 109#define TCR1_TSIS 0x08 /* source Si bits from TAF/TNAF registers */ 110#define TCR1_TSA1 0x04 /* transmit timeslot 16 all ones */ 111 112#define TCR1_TSI 0x00 /* TSYNC is input */ 113#define TCR1_TSO 0x01 /* TSYNC outputs frame boundaries */ 114#define TCR1_TSO_MF 0x03 /* TSYNC outputs CAS/CRC4 m/f boundaries */ 115 116/* 117 * Transmit control register 2 118 */ 119#define TCR2_SA_8 0x80 /* source Sa8 bit from TLINK pin */ 120#define TCR2_SA_7 0x40 /* source Sa7 bit from TLINK pin */ 121#define TCR2_SA_6 0x20 /* source Sa6 bit from TLINK pin */ 122#define TCR2_SA_5 0x10 /* source Sa5 bit from TLINK pin */ 123#define TCR2_SA_4 0x08 /* source Sa4 bit from TLINK pin */ 124#define TCR2_AEBE 0x02 /* automatic E-bit enable */ 125#define TCR2_P16F 0x01 /* pin 16 is Loss of Transmit Clock */ 126 127/* 128 * Common control register 1 129 */ 130#define CCR1_FLOOP 0x80 /* enable framer loopback */ 131#define CCR1_THDB3 0x40 /* enable transmit HDB3 */ 132#define CCR1_TG802 0x20 /* enable transmit G.802 */ 133#define CCR1_TCRC4 0x10 /* enable transmit CRC4 */ 134#define CCR1_CCS 0x08 /* common channel signaling mode */ 135#define CCR1_RHDB3 0x04 /* enable receive HDB3 */ 136#define CCR1_RG802 0x02 /* enable receive G.802 */ 137#define CCR1_RCRC4 0x01 /* enable receive CRC4 */ 138 139/* 140 * Common control register 2 141 */ 142#define CCR2_EC625 0x80 /* update error counters every 62.5 ms */ 143#define CCR2_CNTCV 0x40 /* count code violations */ 144#define CCR2_AUTOAIS 0x20 /* automatic AIS generation */ 145#define CCR2_AUTORA 0x10 /* automatic remote alarm generation */ 146#define CCR2_LOFA1 0x08 /* force RSER to 1 under loss of frame align */ 147#define CCR2_TRCLK 0x04 /* switch transmitter to RCLK if TCLK stops */ 148#define CCR2_RLOOP 0x02 /* enable remote loopback */ 149#define CCR2_LLOOP 0x01 /* enable local loopback */ 150 151/* 152 * Common control register 3 153 */ 154#define CCR3_TESE 0x80 /* enable transmit elastic store */ 155#define CCR3_TCBFS 0x40 /* TCBRs define signaling bits to insert */ 156#define CCR3_TIRSER 0x20 /* TIRs define data channels from RSER pin */ 157#define CCR3_ESRESET 0x10 /* elastic store reset */ 158#define CCR3_LIRESET 0x08 /* line interface reset */ 159#define CCR3_THSE 0x04 /* insert signaling from TSIG into TSER */ 160#define CCR3_TSCLKM 0x02 /* transmit backplane clock 2048 */ 161 162/* 163 * Line interface control register 164 */ 165#define LICR_DB21 0x80 /* return loss 21 dB */ 166 167#define LICR_LB75 0x00 /* 75 Ohm normal */ 168#define LICR_LB120 0x20 /* 120 Ohm normal */ 169#define LICR_LB75P 0x40 /* 75 Ohm protected */ 170#define LICR_LB120P 0x60 /* 120 Ohm protected */ 171 172#define LICR_HIGAIN 0x10 /* receive gain 30 dB */ 173#define LICR_JA_TX 0x08 /* transmit side jitter attenuator select */ 174#define LICR_JA_LOW 0x04 /* low jitter attenuator depth (32 bits) */ 175#define LICR_JA_DISABLE 0x02 /* disable jitter attenuator */ 176#define LICR_POWERDOWN 0x01 /* transmit power down */ 177 178/*---------------------------------------------- 179 * Receive information register 180 */ 181#define RIR_TES_FULL 0x80 /* transmit elastic store full */ 182#define RIR_TES_EMPTY 0x40 /* transmit elastic store empty */ 183#define RIR_JALT 0x20 /* jitter attenuation limit trip */ 184#define RIR_ES_FULL 0x10 /* elastic store full */ 185#define RIR_ES_EMPTY 0x08 /* elastic store empty */ 186#define RIR_RESYNC_CRC 0x04 /* CRC4 resync (915/1000 errors) */ 187#define RIR_RESYNC 0x02 /* frame resync (three consec errors) */ 188#define RIR_RESYNC_CAS 0x01 /* CAS resync (two consec errors) */ 189 190/* 191 * Synchronizer status register 192 */ 193#define SSR_CSC(v) (((v) >> 2) & 0x3c | ((v) >> 3) & 1) 194 /* CRC4 sync counter (6 bits, bit 1 n/a) */ 195#define SSR_SYNC 0x04 /* frame alignment sync active */ 196#define SSR_SYNC_CAS 0x02 /* CAS multiframe sync active */ 197#define SSR_SYNC_CRC4 0x01 /* CRC4 multiframe sync active */ 198 199/* 200 * Status register 1 201 */ 202#define SR1_RSA1 0x80 /* receive signaling all ones */ 203#define SR1_RDMA 0x40 /* receive distant multiframe alarm */ 204#define SR1_RSA0 0x20 /* receive signaling all zeros */ 205#define SR1_RSLIP 0x10 /* receive elastic store slip event */ 206#define SR1_RUA1 0x08 /* receive unframed all ones */ 207#define SR1_RRA 0x04 /* receive remote alarm */ 208#define SR1_RCL 0x02 /* receive carrier loss */ 209#define SR1_RLOS 0x01 /* receive loss of sync */ 210 211/* 212 * Status register 2 213 */ 214#define SR2_RMF 0x80 /* receive CAS multiframe (every 2 ms) */ 215#define SR2_RAF 0x40 /* receive align frame (every 250 us) */ 216#define SR2_TMF 0x20 /* transmit multiframe (every 2 ms) */ 217#define SR2_SEC 0x10 /* one second timer (or 62.5 ms) */ 218#define SR2_TAF 0x08 /* transmit align frame (every 250 us) */ 219#define SR2_LOTC 0x04 /* loss of transmit clock */ 220#define SR2_RCMF 0x02 /* receive CRC4 multiframe (every 2 ms) */ 221#define SR2_TSLIP 0x01 /* transmit elastic store slip event */ 222 223/* 224 * Error count registers 225 */ 226#define VCR(h,l) (((short) (h) << 8) | (l)) /* 16-bit code violation */ 227#define CRCCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit CRC4 error count */ 228#define EBCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit E-bit count */ 229#define FASCR(h,l) (((short) (h) << 4 & 0xfc0) | (l) >> 2) /* 12-bit FAS error count */ 230 231#define FASCRH(h) ((h) << 4) /* 12-bit FAS error count */ 232#define FASCRL(l) ((l) >> 2) /* 12-bit FAS error count */ 233 234/* 235 * DS21x54 additional registers 236 */ 237#define DS_IDR 0x0f /* r - device id */ 238#define DS_TSACR 0x1c /* rw - transmit Sa bit control */ 239#define DS_CCR6 0x1d /* rw - common control 6 */ 240 241#define DS_TSIAF 0x50 /* rw - transmit Si bits align frame */ 242#define DS_TSINAF 0x51 /* rw - transmit Si bits non-align frame */ 243#define DS_TRA 0x52 /* rw - transmit remote alarm bits */ 244#define DS_TSA4 0x53 /* rw - transmit Sa4 bits */ 245#define DS_TSA5 0x54 /* rw - transmit Sa5 bits */ 246#define DS_TSA6 0x55 /* rw - transmit Sa6 bits */ 247#define DS_TSA7 0x56 /* rw - transmit Sa7 bits */ 248#define DS_TSA8 0x57 /* rw - transmit Sa8 bits */ 249#define DS_RSIAF 0x58 /* r - receive Si bits align frame */ 250#define DS_RSINAF 0x59 /* r - receive Si bits non-align frame */ 251#define DS_RRA 0x5a /* r - receive remote alarm bits */ 252#define DS_RSA4 0x5b /* r - receive Sa4 bits */ 253#define DS_RSA5 0x5c /* r - receive Sa5 bits */ 254#define DS_RSA6 0x5d /* r - receive Sa6 bits */ 255#define DS_RSA7 0x5e /* r - receive Sa7 bits */ 256#define DS_RSA8 0x5f /* r - receive Sa8 bits */ 257 258#define DS_TCC1 0xa0 /* rw - transmit channel control 1 */ 259#define DS_TCC2 0xa1 /* rw - transmit channel control 2 */ 260#define DS_TCC3 0xa2 /* rw - transmit channel control 3 */ 261#define DS_TCC4 0xa3 /* rw - transmit channel control 4 */ 262#define DS_RCC1 0xa4 /* rw - receive channel control 1 */ 263#define DS_RCC2 0xa5 /* rw - receive channel control 2 */ 264#define DS_RCC3 0xa6 /* rw - receive channel control 3 */ 265#define DS_RCC4 0xa7 /* rw - receive channel control 4 */ 266 267#define DS_CCR4 0xa8 /* rw - common control 4 */ 268#define DS_TDS0M 0xa9 /* r - transmit ds0 monitor */ 269#define DS_CCR5 0xaa /* rw - common control 5 */ 270#define DS_RDS0M 0xab /* r - receive ds0 monitor */ 271#define DS_TEST3 0xac /* rw - test 3, set to 00h */ 272 273#define DS_HCR 0xb0 /* rw - hdlc control */ 274#define DS_HSR 0xb1 /* rw - hdlc status */ 275#define DS_HIMR 0xb2 /* rw - hdlc interrupt mask */ 276#define DS_RHIR 0xb3 /* rw - receive hdlc information */ 277#define DS_RHFR 0xb4 /* rw - receive hdlc fifo */ 278#define DS_IBO 0xb5 /* rw - interleave bus operation */ 279#define DS_THIR 0xb6 /* rw - transmit hdlc information */ 280#define DS_THFR 0xb7 /* rw - transmit hdlc fifo */ 281#define DS_RDC1 0xb8 /* rw - receive hdlc ds0 control 1 */ 282#define DS_RDC2 0xb9 /* rw - receive hdlc ds0 control 2 */ 283#define DS_TDC1 0xba /* rw - transmit hdlc ds0 control 1 */ 284#define DS_TDC2 0xbb /* rw - transmit hdlc ds0 control 2 */ 285 286#define CCR4_RLB 0x80 /* enable remote loopback */ 287#define CCR4_LLB 0x40 /* enable local loopback */ 288#define CCR5_LIRST 0x80 /* line interface reset */ 289#define CCR6_RESR 0x02 /* receive elastic store reset */ 290#define CCR6_TESR 0x01 /* transmit elastic store reset */ 291