1/*- 2 * AMD Am83C30 serial communication controller registers. 3 * 4 * Copyright (C) 1996 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * This software is distributed with NO WARRANTIES, not even the implied 8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9 * 10 * Authors grant any other persons or organisations permission to use 11 * or modify this software as long as this message is kept with the software, 12 * all derivative works or modified versions. 13 * 14 * Cronyx Id: am8530.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $ 15 * $FreeBSD$ 16 */ 17 18/* 19 * Read/write registers. 20 */ 21#define AM_IVR 2 /* rw2 - interrupt vector register */ 22#define AM_DAT 8 /* rw8 - data buffer register */ 23#define AM_TCL 12 /* rw12 - time constant low */ 24#define AM_TCH 13 /* rw13 - time constant high */ 25#define AM_SICR 15 /* rw15 - status interrupt control reg */ 26 27/* 28 * Write only registers. 29 */ 30#define AM_CR 0 /* w0 - command register */ 31#define AM_IMR 1 /* w1 - interrupt mode register */ 32#define AM_RCR 3 /* w3 - receive control register */ 33#define AM_PMR 4 /* w4 - tx/rx parameters and modes reg */ 34#define AM_TCR 5 /* w5 - transmit control register */ 35#define AM_SAF 6 /* w6 - sync address field */ 36#define AM_SFR 7 /* w7 - sync flag register */ 37#define AM_MICR 9 /* w9 - master interrupt control reg */ 38#define AM_MCR 10 /* w10 - misc control register */ 39#define AM_CMR 11 /* w11 - clock mode register */ 40#define AM_BCR 14 /* w14 - baud rate control register */ 41 42/* 43 * Read only registers. 44 */ 45#define AM_SR 0 /* r0 - status register */ 46#define AM_RSR 1 /* r1 - receive status register */ 47#define AM_IPR 3 /* r3 - interrupt pending register */ 48#define AM_MSR 10 /* r10 - misc status register */ 49 50/* 51 * Enhanced mode registers. 52 * In enhanced mode registers PMR(w4), TCR(w5) become readable. 53 */ 54#define AM_FBCL 6 /* r6 - frame byte count low */ 55#define AM_FBCH 7 /* r7 - frame byte count high */ 56#define AM_RCR_R 9 /* r9 - read RCR(w3) */ 57#define AM_MCR_R 11 /* r11 - read MCR(w10) */ 58#define AM_SFR_R 14 /* r14 - read SFR(w7') */ 59 60#define AM_A 32 /* channel A offset */ 61 62/* 63 * Interrupt vector register 64 */ 65#define IVR_A 0x08 /* channel A status */ 66#define IVR_REASON 0x06 /* interrupt reason mask */ 67#define IVR_TXRDY 0x00 /* transmit buffer empty */ 68#define IVR_STATUS 0x02 /* external status interrupt */ 69#define IVR_RX 0x04 /* receive character available */ 70#define IVR_RXERR 0x06 /* special receive condition */ 71 72/* 73 * Interrupt mask register 74 */ 75#define IMR_EXT 0x01 /* ext interrupt enable */ 76#define IMR_TX 0x02 /* ext interrupt enable */ 77#define IMR_PARITY 0x04 /* ext interrupt enable */ 78 79#define IMR_RX_FIRST 0x08 /* ext interrupt enable */ 80#define IMR_RX_ALL 0x10 /* ext interrupt enable */ 81#define IMR_RX_ERR 0x18 /* ext interrupt enable */ 82 83#define IMR_WD_RX 0x20 /* wait/request follows receiver fifo */ 84#define IMR_WD_REQ 0x40 /* wait/request function as request */ 85#define IMR_WD_ENABLE 0x80 /* wait/request pin enable */ 86 87/* 88 * Master interrupt control register 89 */ 90#define MICR_VIS 0x01 /* vector includes status */ 91#define MICR_NV 0x02 /* no interrupt vector */ 92#define MICR_DLC 0x04 /* disable lower chain */ 93#define MICR_MIE 0x08 /* master interrupt enable */ 94#define MICR_HIGH 0x10 /* status high */ 95#define MICR_NINTACK 0x20 /* interrupt masking without INTACK */ 96 97#define MICR_RESET_A 0x80 /* channel reset A */ 98#define MICR_RESET_B 0x40 /* channel reset B */ 99#define MICR_RESET_HW 0xc0 /* force hardware reset */ 100 101/* 102 * Receive status register 103 */ 104#define RSR_FRME 0x10 /* framing error */ 105#define RSR_RXOVRN 0x20 /* rx overrun error */ 106 107/* 108 * Command register 109 */ 110#define CR_RST_EXTINT 0x10 /* reset external/status irq */ 111#define CR_TX_ABORT 0x18 /* send abort (SDLC) */ 112#define CR_RX_NXTINT 0x20 /* enable irq on next rx character */ 113#define CR_RST_TXINT 0x28 /* reset tx irq pending */ 114#define CR_RST_ERROR 0x30 /* error reset */ 115#define CR_RST_HIUS 0x38 /* reset highest irq under service */ 116