if_csreg.h revision 37785
1/* 2 * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29/* 30 * $Id: if_csreg.h,v 1.7 1998/07/19 16:13:39 root Exp root $ 31 */ 32 33#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ 34 /* offset 2h -> Model/Product Number */ 35 /* offset 3h -> Chip Revision Number */ 36 37#define PP_ISAIOB 0x0020 /* IO base address */ 38#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ 39#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ 40#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ 41#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ 42#define PP_ISASOF 0x0026 /* ISA DMA offset */ 43#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ 44#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ 45#define PP_CS8920_ISAMemB 0x0348 /* Memory base */ 46 47/* EEPROM data and command registers */ 48#define PP_EECMD 0x0040 /* NVR Interface Command register */ 49#define PP_EEData 0x0042 /* NVR Interface Data Register */ 50#define PP_DebugReg 0x0044 /* Debug Register */ 51 52#define PP_RxCFG 0x0102 /* Rx Bus config */ 53#define PP_RxCTL 0x0104 /* Receive Control Register */ 54#define PP_TxCFG 0x0106 /* Transmit Config Register */ 55#define PP_TxCMD 0x0108 /* Transmit Command Register */ 56#define PP_BufCFG 0x010A /* Bus configuration Register */ 57#define PP_LineCTL 0x0112 /* Line Config Register */ 58#define PP_SelfCTL 0x0114 /* Self Command Register */ 59#define PP_BusCTL 0x0116 /* ISA bus control Register */ 60#define PP_TestCTL 0x0118 /* Test Register */ 61#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ 62 63#define PP_ISQ 0x0120 /* Interrupt Status */ 64#define PP_RxEvent 0x0124 /* Rx Event Register */ 65#define PP_TxEvent 0x0128 /* Tx Event Register */ 66#define PP_BufEvent 0x012C /* Bus Event Register */ 67#define PP_RxMiss 0x0130 /* Receive Miss Count */ 68#define PP_TxCol 0x0132 /* Transmit Collision Count */ 69#define PP_LineST 0x0134 /* Line State Register */ 70#define PP_SelfST 0x0136 /* Self State register */ 71#define PP_BusST 0x0138 /* Bus Status */ 72#define PP_TDR 0x013C /* Time Domain Reflectometry */ 73#define PP_AutoNegST 0x013E /* Auto Neg Status */ 74#define PP_TxCommand 0x0144 /* Tx Command */ 75#define PP_TxLength 0x0146 /* Tx Length */ 76#define PP_LAF 0x0150 /* Hash Table */ 77#define PP_IA 0x0158 /* Physical Address Register */ 78 79#define PP_RxStatus 0x0400 /* Receive start of frame */ 80#define PP_RxLength 0x0402 /* Receive Length of frame */ 81#define PP_RxFrame 0x0404 /* Receive frame pointer */ 82#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ 83 84/* 85 * Primary I/O Base Address. If no I/O base is supplied by the user, then this 86 * can be used as the default I/O base to access the PacketPage Area. 87 */ 88#define DEFAULTIOBASE 0x0300 89#define FIRST_IO 0x020C /* First I/O port to check */ 90#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ 91#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ 92#define ADD_SIG 0x3000 /* Expected ID signature */ 93 94#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ 95 96#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ 97 98/* Mask to find out the types of registers */ 99#define REG_TYPE_MASK 0x001F 100 101/* Eeprom Commands */ 102#define ERSE_WR_ENBL 0x00F0 103#define ERSE_WR_DISABLE 0x0000 104 105/* Defines Control/Config register quintuplet numbers */ 106#define RX_BUF_CFG 0x0003 107#define RX_CONTROL 0x0005 108#define TX_CFG 0x0007 109#define TX_COMMAND 0x0009 110#define BUF_CFG 0x000B 111#define LINE_CONTROL 0x0013 112#define SELF_CONTROL 0x0015 113#define BUS_CONTROL 0x0017 114#define TEST_CONTROL 0x0019 115 116/* Defines Status/Count registers quintuplet numbers */ 117#define RX_EVENT 0x0004 118#define TX_EVENT 0x0008 119#define BUF_EVENT 0x000C 120#define RX_MISS_COUNT 0x0010 121#define TX_COL_COUNT 0x0012 122#define LINE_STATUS 0x0014 123#define SELF_STATUS 0x0016 124#define BUS_STATUS 0x0018 125#define TDR 0x001C 126 127/* 128 * PP_RxCFG - Receive Configuration and Interrupt Mask 129 * bit definition - Read/write 130 */ 131#define SKIP_1 0x0040 132#define RX_STREAM_ENBL 0x0080 133#define RX_OK_ENBL 0x0100 134#define RX_DMA_ONLY 0x0200 135#define AUTO_RX_DMA 0x0400 136#define BUFFER_CRC 0x0800 137#define RX_CRC_ERROR_ENBL 0x1000 138#define RX_RUNT_ENBL 0x2000 139#define RX_EXTRA_DATA_ENBL 0x4000 140 141/* PP_RxCTL - Receive Control bit definition - Read/write */ 142#define RX_IA_HASH_ACCEPT 0x0040 143#define RX_PROM_ACCEPT 0x0080 144#define RX_OK_ACCEPT 0x0100 145#define RX_MULTCAST_ACCEPT 0x0200 146#define RX_IA_ACCEPT 0x0400 147#define RX_BROADCAST_ACCEPT 0x0800 148#define RX_BAD_CRC_ACCEPT 0x1000 149#define RX_RUNT_ACCEPT 0x2000 150#define RX_EXTRA_DATA_ACCEPT 0x4000 151#define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \ 152 RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT) 153/* 154 * Default receive mode - individually addressed, broadcast, and error free 155 */ 156#define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) 157 158/* 159 * PP_TxCFG - Transmit Configuration Interrupt Mask 160 * bit definition - Read/write 161 */ 162#define TX_LOST_CRS_ENBL 0x0040 163#define TX_SQE_ERROR_ENBL 0x0080 164#define TX_OK_ENBL 0x0100 165#define TX_LATE_COL_ENBL 0x0200 166#define TX_JBR_ENBL 0x0400 167#define TX_ANY_COL_ENBL 0x0800 168#define TX_16_COL_ENBL 0x8000 169 170/* 171 * PP_TxCMD - Transmit Command bit definition - Read-only 172 */ 173#define TX_START_4_BYTES 0x0000 174#define TX_START_64_BYTES 0x0040 175#define TX_START_128_BYTES 0x0080 176#define TX_START_ALL_BYTES 0x00C0 177#define TX_FORCE 0x0100 178#define TX_ONE_COL 0x0200 179#define TX_TWO_PART_DEFF_DISABLE 0x0400 180#define TX_NO_CRC 0x1000 181#define TX_RUNT 0x2000 182 183/* 184 * PP_BufCFG - Buffer Configuration Interrupt Mask 185 * bit definition - Read/write 186 */ 187#define GENERATE_SW_INTERRUPT 0x0040 188#define RX_DMA_ENBL 0x0080 189#define READY_FOR_TX_ENBL 0x0100 190#define TX_UNDERRUN_ENBL 0x0200 191#define RX_MISS_ENBL 0x0400 192#define RX_128_BYTE_ENBL 0x0800 193#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 194#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 195#define RX_DEST_MATCH_ENBL 0x8000 196 197/* 198 * PP_LineCTL - Line Control bit definition - Read/write 199 */ 200#define SERIAL_RX_ON 0x0040 201#define SERIAL_TX_ON 0x0080 202#define AUI_ONLY 0x0100 203#define AUTO_AUI_10BASET 0x0200 204#define MODIFIED_BACKOFF 0x0800 205#define NO_AUTO_POLARITY 0x1000 206#define TWO_PART_DEFDIS 0x2000 207#define LOW_RX_SQUELCH 0x4000 208 209/* 210 * PP_SelfCTL - Software Self Control bit definition - Read/write 211 */ 212#define POWER_ON_RESET 0x0040 213#define SW_STOP 0x0100 214#define SLEEP_ON 0x0200 215#define AUTO_WAKEUP 0x0400 216#define HCB0_ENBL 0x1000 217#define HCB1_ENBL 0x2000 218#define HCB0 0x4000 219#define HCB1 0x8000 220 221/* 222 * PP_BusCTL - ISA Bus Control bit definition - Read/write 223 */ 224#define RESET_RX_DMA 0x0040 225#define MEMORY_ON 0x0400 226#define DMA_BURST_MODE 0x0800 227#define IO_CHANNEL_READY_ON 0x1000 228#define RX_DMA_SIZE_64Ks 0x2000 229#define ENABLE_IRQ 0x8000 230 231/* 232 * PP_TestCTL - Test Control bit definition - Read/write 233 */ 234#define LINK_OFF 0x0080 235#define ENDEC_LOOPBACK 0x0200 236#define AUI_LOOPBACK 0x0400 237#define BACKOFF_OFF 0x0800 238#define FAST_TEST 0x8000 239 240/* 241 * PP_RxEvent - Receive Event Bit definition - Read-only 242 */ 243#define RX_IA_HASHED 0x0040 244#define RX_DRIBBLE 0x0080 245#define RX_OK 0x0100 246#define RX_HASHED 0x0200 247#define RX_IA 0x0400 248#define RX_BROADCAST 0x0800 249#define RX_CRC_ERROR 0x1000 250#define RX_RUNT 0x2000 251#define RX_EXTRA_DATA 0x4000 252 253#define HASH_INDEX_MASK 0x0FC00 254 255/* 256 * PP_TxEvent - Transmit Event Bit definition - Read-only 257 */ 258#define TX_LOST_CRS 0x0040 259#define TX_SQE_ERROR 0x0080 260#define TX_OK 0x0100 261#define TX_LATE_COL 0x0200 262#define TX_JBR 0x0400 263#define TX_16_COL 0x8000 264#define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS) 265#define TX_COL_COUNT_MASK 0x7800 266 267/* 268 * PP_BufEvent - Buffer Event Bit definition - Read-only 269 */ 270#define SW_INTERRUPT 0x0040 271#define RX_DMA 0x0080 272#define READY_FOR_TX 0x0100 273#define TX_UNDERRUN 0x0200 274#define RX_MISS 0x0400 275#define RX_128_BYTE 0x0800 276#define TX_COL_OVRFLW 0x1000 277#define RX_MISS_OVRFLW 0x2000 278#define RX_DEST_MATCH 0x8000 279 280/* 281 * PP_LineST - Ethernet Line Status bit definition - Read-only 282 */ 283#define LINK_OK 0x0080 284#define AUI_ON 0x0100 285#define TENBASET_ON 0x0200 286#define POLARITY_OK 0x1000 287#define CRS_OK 0x4000 288 289/* 290 * PP_SelfST - Chip Software Status bit definition 291 */ 292#define ACTIVE_33V 0x0040 293#define INIT_DONE 0x0080 294#define SI_BUSY 0x0100 295#define EEPROM_PRESENT 0x0200 296#define EEPROM_OK 0x0400 297#define EL_PRESENT 0x0800 298#define EE_SIZE_64 0x1000 299 300/* 301 * PP_BusST - ISA Bus Status bit definition 302 */ 303#define TX_BID_ERROR 0x0080 304#define READY_FOR_TX_NOW 0x0100 305 306/* 307 * PP_AutoNegCTL - Auto Negotiation Control bit definition 308 */ 309#define RE_NEG_NOW 0x0040 310#define ALLOW_FDX 0x0080 311#define AUTO_NEG_ENABLE 0x0100 312#define NLP_ENABLE 0x0200 313#define FORCE_FDX 0x8000 314#define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE) 315#define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \ 316 ALLOW_FDX | RE_NEG_NOW) 317 318/* 319 * PP_AutoNegST - Auto Negotiation Status bit definition 320 */ 321#define AUTO_NEG_BUSY 0x0080 322#define FLP_LINK 0x0100 323#define FLP_LINK_GOOD 0x0800 324#define LINK_FAULT 0x1000 325#define HDX_ACTIVE 0x4000 326#define FDX_ACTIVE 0x8000 327 328/* 329 * The following block defines the ISQ event types 330 */ 331#define ISQ_RECEIVER_EVENT 0x04 332#define ISQ_TRANSMITTER_EVENT 0x08 333#define ISQ_BUFFER_EVENT 0x0c 334#define ISQ_RX_MISS_EVENT 0x10 335#define ISQ_TX_COL_EVENT 0x12 336 337#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ 338#define ISQ_HIST 16 /* small history buffer */ 339#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ 340 341#define TXRXBUFSIZE 0x0600 342#define RXDMABUFSIZE 0x8000 343#define RXDMASIZE 0x4000 344#define TXRX_LENGTH_MASK 0x07FF 345 346/* rx options bits */ 347#define RCV_WITH_RXON 1 /* Set SerRx ON */ 348#define RCV_COUNTS 2 /* Use Framecnt1 */ 349#define RCV_PONG 4 /* Pong respondent */ 350#define RCV_DONG 8 /* Dong operation */ 351#define RCV_POLLING 0x10 /* Poll RxEvent */ 352#define RCV_ISQ 0x20 /* Use ISQ, int */ 353#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ 354#define RCV_DMA 0x200 /* Set RxDMA only */ 355#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ 356#define RCV_FIXED_DATA 0x800 /* Every frame same */ 357#define RCV_IO 0x1000 /* Use ISA IO only */ 358#define RCV_MEMORY 0x2000 /* Use ISA Memory */ 359 360#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ 361#define PKT_START PP_TxFrame /* Start of packet RAM */ 362 363#define RX_FRAME_PORT 0x0000 364#define TX_FRAME_PORT RX_FRAME_PORT 365#define TX_CMD_PORT 0x0004 366#define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */ 367#define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */ 368#define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */ 369#define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */ 370#define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ 371#define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */ 372#define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */ 373#define TX_LEN_PORT 0x0006 374#define ISQ_PORT 0x0008 375#define ADD_PORT 0x000A 376#define DATA_PORT 0x000C 377 378#define EEPROM_WRITE_EN 0x00F0 379#define EEPROM_WRITE_DIS 0x0000 380#define EEPROM_WRITE_CMD 0x0100 381#define EEPROM_READ_CMD 0x0200 382 383/* Receive Header 384 * Description of header of each packet in receive area of memory 385 */ 386#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ 387#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ 388#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ 389#define RBUF_LEN_HI 3 /* Length of received data - high byte */ 390#define RBUF_HEAD_LEN 4 /* Length of this header */ 391 392#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ 393#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ 394 395/* for bios scan */ 396/* */ 397#ifdef CSDEBUG 398/* use these values for debugging bios scan */ 399#define BIOS_START_SEG 0x00000 400#define BIOS_OFFSET_INC 0x0010 401#else 402#define BIOS_START_SEG 0x0c000 403#define BIOS_OFFSET_INC 0x0200 404#endif 405 406#define BIOS_LAST_OFFSET 0x0fc00 407 408/* 409 * Byte offsets into the EEPROM configuration buffer 410 */ 411#define ISA_CNF_OFFSET 0x6 412#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ 413#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ 414 415/* 416 * the assumption here is that the bits in the eeprom are generally 417 * in the same position as those in the autonegctl register. 418 * Of course the IMM bit is not in that register so it must be 419 * masked out 420 */ 421#define EE_FORCE_FDX 0x8000 422#define EE_NLP_ENABLE 0x0200 423#define EE_AUTO_NEG_ENABLE 0x0100 424#define EE_ALLOW_FDX 0x0080 425#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \ 426 EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX) 427 428#define IMM_BIT 0x0040 /* ignore missing media */ 429 430#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) 431#define A_CNF_MEDIA 0x0007 432#define A_CNF_10B_T 0x0001 433#define A_CNF_AUI 0x0002 434#define A_CNF_10B_2 0x0004 435#define A_CNF_MEDIA_TYPE 0x0060 436#define A_CNF_MEDIA_AUTO 0x0000 437#define A_CNF_MEDIA_10B_T 0x0020 438#define A_CNF_MEDIA_AUI 0x0040 439#define A_CNF_MEDIA_10B_2 0x0060 440#define A_CNF_DC_DC_POLARITY 0x0080 441#define A_CNF_NO_AUTO_POLARITY 0x2000 442#define A_CNF_LOW_RX_SQUELCH 0x4000 443#define A_CNF_EXTND_10B_2 0x8000 444 445#define PACKET_PAGE_OFFSET 0x8 446 447/* 448 * Bit definitions for the ISA configuration word from the EEPROM 449 */ 450#define INT_NO_MASK 0x000F 451#define DMA_NO_MASK 0x0070 452#define ISA_DMA_SIZE 0x0200 453#define ISA_AUTO_RxDMA 0x0400 454#define ISA_RxDMA 0x0800 455#define DMA_BURST 0x1000 456#define STREAM_TRANSFER 0x2000 457#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) 458 459/* DMA controller registers */ 460#define DMA_BASE 0x00 /* DMA controller base */ 461#define DMA_BASE_2 0x0C0 /* DMA controller base */ 462 463#define DMA_STAT 0x0D0 /* DMA controller status register */ 464#define DMA_MASK 0x0D4 /* DMA controller mask register */ 465#define DMA_MODE 0x0D6 /* DMA controller mode register */ 466#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ 467 468/* DMA data */ 469#define DMA_DISABLE 0x04 /* Disable channel n */ 470#define DMA_ENABLE 0x00 /* Enable channel n */ 471/* Demand transfers, incr. address, auto init, writes, ch. n */ 472#define DMA_RX_MODE 0x14 473/* Demand transfers, incr. address, auto init, reads, ch. n */ 474#define DMA_TX_MODE 0x18 475 476#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ 477 478#define CS8900 0x0000 479#define CS8920 0x4000 480#define CS8920M 0x6000 481#define REVISON_BITS 0x1F00 482#define EEVER_NUMBER 0x12 483#define CHKSUM_LEN 0x14 484#define CHKSUM_VAL 0x0000 485#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ 486#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ 487#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ 488#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ 489#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ 490 491#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ 492 493#define PNP_ADD_PORT 0x0279 494#define PNP_WRITE_PORT 0x0A79 495 496#define GET_PNP_ISA_STRUCT 0x40 497#define PNP_ISA_STRUCT_LEN 0x06 498#define PNP_CSN_CNT_OFF 0x01 499#define PNP_RD_PORT_OFF 0x02 500#define PNP_FUNCTION_OK 0x00 501#define PNP_WAKE 0x03 502#define PNP_RSRC_DATA 0x04 503#define PNP_RSRC_READY 0x01 504#define PNP_STATUS 0x05 505#define PNP_ACTIVATE 0x30 506#define PNP_CNF_IO_H 0x60 507#define PNP_CNF_IO_L 0x61 508#define PNP_CNF_INT 0x70 509#define PNP_CNF_DMA 0x74 510#define PNP_CNF_MEM 0x48 511 512#define BIT0 1 513#define BIT15 0x8000 514 515#define CS_DUPLEX_AUTO 0 516#define CS_DUPLEX_FULL 1 517#define CS_DUPLEX_HALF 2 518 519/* Device name */ 520#define CS_NAME "cs" 521 522#define cs_readreg(iobase, portno) \ 523 (outw((iobase) + ADD_PORT, (portno)), \ 524 inw((iobase) + DATA_PORT)) 525#define cs_writereg(iobase, portno, value) \ 526 (outw((iobase) + ADD_PORT, (portno)), \ 527 outw((iobase) + DATA_PORT, (value))) 528#define cs_readword(iobase, portno) \ 529 (inw((iobase) + (portno))) 530#define cs_writeword(iobase, portno, value) \ 531 (outw((iobase) + (portno), (value))) 532 533#define reset_chip(nic_addr) \ 534 cs_writereg(nic_addr, PP_SelfCTL, cs_readreg(ioaddr, PP_SelfCTL) | POWER_ON_RESET), \ 535 DELAY(30000) 536 537#define cs_duplex_full(sc) \ 538 (cs_writereg(sc->nic_addr, PP_AutoNegCTL, FORCE_FDX)) 539 540#define cs_duplex_half(sc) \ 541 (cs_writereg(sc->nic_addr, PP_AutoNegCTL, NLP_ENABLE)) 542 543