1/*- 2 * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29/* 30 * $FreeBSD$ 31 */ 32 33#include <sys/rman.h> 34 35#define CS_89x0_IO_PORTS 0x0020 36 37#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ 38 /* offset 2h -> Model/Product Number */ 39 /* offset 3h -> Chip Revision Number */ 40 41#define PP_ISAIOB 0x0020 /* IO base address */ 42#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ 43#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ 44#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ 45#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ 46#define PP_ISASOF 0x0026 /* ISA DMA offset */ 47#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ 48#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ 49#define PP_CS8920_ISAMemB 0x0348 /* Memory base */ 50 51/* EEPROM data and command registers */ 52#define PP_EECMD 0x0040 /* NVR Interface Command register */ 53#define PP_EEData 0x0042 /* NVR Interface Data Register */ 54#define PP_DebugReg 0x0044 /* Debug Register */ 55 56#define PP_RxCFG 0x0102 /* Rx Bus config */ 57#define PP_RxCTL 0x0104 /* Receive Control Register */ 58#define PP_TxCFG 0x0106 /* Transmit Config Register */ 59#define PP_TxCMD 0x0108 /* Transmit Command Register */ 60#define PP_BufCFG 0x010A /* Bus configuration Register */ 61#define PP_LineCTL 0x0112 /* Line Config Register */ 62#define PP_SelfCTL 0x0114 /* Self Command Register */ 63#define PP_BusCTL 0x0116 /* ISA bus control Register */ 64#define PP_TestCTL 0x0118 /* Test Register */ 65#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ 66 67#define PP_ISQ 0x0120 /* Interrupt Status */ 68#define PP_RxEvent 0x0124 /* Rx Event Register */ 69#define PP_TxEvent 0x0128 /* Tx Event Register */ 70#define PP_BufEvent 0x012C /* Bus Event Register */ 71#define PP_RxMiss 0x0130 /* Receive Miss Count */ 72#define PP_TxCol 0x0132 /* Transmit Collision Count */ 73#define PP_LineST 0x0134 /* Line State Register */ 74#define PP_SelfST 0x0136 /* Self State register */ 75#define PP_BusST 0x0138 /* Bus Status */ 76#define PP_TDR 0x013C /* Time Domain Reflectometry */ 77#define PP_AutoNegST 0x013E /* Auto Neg Status */ 78#define PP_TxCommand 0x0144 /* Tx Command */ 79#define PP_TxLength 0x0146 /* Tx Length */ 80#define PP_LAF 0x0150 /* Hash Table */ 81#define PP_IA 0x0158 /* Physical Address Register */ 82 83#define PP_RxStatus 0x0400 /* Receive start of frame */ 84#define PP_RxLength 0x0402 /* Receive Length of frame */ 85#define PP_RxFrame 0x0404 /* Receive frame pointer */ 86#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ 87 88/* 89 * Primary I/O Base Address. If no I/O base is supplied by the user, then this 90 * can be used as the default I/O base to access the PacketPage Area. 91 */ 92#define DEFAULTIOBASE 0x0300 93#define FIRST_IO 0x020C /* First I/O port to check */ 94#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ 95#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ 96#define ADD_SIG 0x3000 /* Expected ID signature */ 97 98#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ 99 100#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ 101 102/* Mask to find out the types of registers */ 103#define REG_TYPE_MASK 0x001F 104 105/* Eeprom Commands */ 106#define ERSE_WR_ENBL 0x00F0 107#define ERSE_WR_DISABLE 0x0000 108 109/* Defines Control/Config register quintuplet numbers */ 110#define RX_BUF_CFG 0x0003 111#define RX_CONTROL 0x0005 112#define TX_CFG 0x0007 113#define TX_COMMAND 0x0009 114#define BUF_CFG 0x000B 115#define LINE_CONTROL 0x0013 116#define SELF_CONTROL 0x0015 117#define BUS_CONTROL 0x0017 118#define TEST_CONTROL 0x0019 119 120/* Defines Status/Count registers quintuplet numbers */ 121#define RX_EVENT 0x0004 122#define TX_EVENT 0x0008 123#define BUF_EVENT 0x000C 124#define RX_MISS_COUNT 0x0010 125#define TX_COL_COUNT 0x0012 126#define LINE_STATUS 0x0014 127#define SELF_STATUS 0x0016 128#define BUS_STATUS 0x0018 129#define TDR 0x001C 130 131/* 132 * PP_RxCFG - Receive Configuration and Interrupt Mask 133 * bit definition - Read/write 134 */ 135#define SKIP_1 0x0040 136#define RX_STREAM_ENBL 0x0080 137#define RX_OK_ENBL 0x0100 138#define RX_DMA_ONLY 0x0200 139#define AUTO_RX_DMA 0x0400 140#define BUFFER_CRC 0x0800 141#define RX_CRC_ERROR_ENBL 0x1000 142#define RX_RUNT_ENBL 0x2000 143#define RX_EXTRA_DATA_ENBL 0x4000 144 145/* PP_RxCTL - Receive Control bit definition - Read/write */ 146#define RX_IA_HASH_ACCEPT 0x0040 147#define RX_PROM_ACCEPT 0x0080 148#define RX_OK_ACCEPT 0x0100 149#define RX_MULTCAST_ACCEPT 0x0200 150#define RX_IA_ACCEPT 0x0400 151#define RX_BROADCAST_ACCEPT 0x0800 152#define RX_BAD_CRC_ACCEPT 0x1000 153#define RX_RUNT_ACCEPT 0x2000 154#define RX_EXTRA_DATA_ACCEPT 0x4000 155#define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \ 156 RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT) 157/* 158 * Default receive mode - individually addressed, broadcast, and error free 159 */ 160#define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) 161 162/* 163 * PP_TxCFG - Transmit Configuration Interrupt Mask 164 * bit definition - Read/write 165 */ 166#define TX_LOST_CRS_ENBL 0x0040 167#define TX_SQE_ERROR_ENBL 0x0080 168#define TX_OK_ENBL 0x0100 169#define TX_LATE_COL_ENBL 0x0200 170#define TX_JBR_ENBL 0x0400 171#define TX_ANY_COL_ENBL 0x0800 172#define TX_16_COL_ENBL 0x8000 173 174/* 175 * PP_TxCMD - Transmit Command bit definition - Read-only 176 */ 177#define TX_START_4_BYTES 0x0000 178#define TX_START_64_BYTES 0x0040 179#define TX_START_128_BYTES 0x0080 180#define TX_START_ALL_BYTES 0x00C0 181#define TX_FORCE 0x0100 182#define TX_ONE_COL 0x0200 183#define TX_TWO_PART_DEFF_DISABLE 0x0400 184#define TX_NO_CRC 0x1000 185#define TX_RUNT 0x2000 186 187/* 188 * PP_BufCFG - Buffer Configuration Interrupt Mask 189 * bit definition - Read/write 190 */ 191#define GENERATE_SW_INTERRUPT 0x0040 192#define RX_DMA_ENBL 0x0080 193#define READY_FOR_TX_ENBL 0x0100 194#define TX_UNDERRUN_ENBL 0x0200 195#define RX_MISS_ENBL 0x0400 196#define RX_128_BYTE_ENBL 0x0800 197#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 198#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 199#define RX_DEST_MATCH_ENBL 0x8000 200 201/* 202 * PP_LineCTL - Line Control bit definition - Read/write 203 */ 204#define SERIAL_RX_ON 0x0040 205#define SERIAL_TX_ON 0x0080 206#define AUI_ONLY 0x0100 207#define AUTO_AUI_10BASET 0x0200 208#define MODIFIED_BACKOFF 0x0800 209#define NO_AUTO_POLARITY 0x1000 210#define TWO_PART_DEFDIS 0x2000 211#define LOW_RX_SQUELCH 0x4000 212 213/* 214 * PP_SelfCTL - Software Self Control bit definition - Read/write 215 */ 216#define POWER_ON_RESET 0x0040 217#define SW_STOP 0x0100 218#define SLEEP_ON 0x0200 219#define AUTO_WAKEUP 0x0400 220#define HCB0_ENBL 0x1000 221#define HCB1_ENBL 0x2000 222#define HCB0 0x4000 223#define HCB1 0x8000 224 225/* 226 * PP_BusCTL - ISA Bus Control bit definition - Read/write 227 */ 228#define RESET_RX_DMA 0x0040 229#define MEMORY_ON 0x0400 230#define DMA_BURST_MODE 0x0800 231#define IO_CHANNEL_READY_ON 0x1000 232#define RX_DMA_SIZE_64Ks 0x2000 233#define ENABLE_IRQ 0x8000 234 235/* 236 * PP_TestCTL - Test Control bit definition - Read/write 237 */ 238#define LINK_OFF 0x0080 239#define ENDEC_LOOPBACK 0x0200 240#define AUI_LOOPBACK 0x0400 241#define BACKOFF_OFF 0x0800 242#define FAST_TEST 0x8000 243 244/* 245 * PP_RxEvent - Receive Event Bit definition - Read-only 246 */ 247#define RX_IA_HASHED 0x0040 248#define RX_DRIBBLE 0x0080 249#define RX_OK 0x0100 250#define RX_HASHED 0x0200 251#define RX_IA 0x0400 252#define RX_BROADCAST 0x0800 253#define RX_CRC_ERROR 0x1000 254#define RX_RUNT 0x2000 255#define RX_EXTRA_DATA 0x4000 256 257#define HASH_INDEX_MASK 0x0FC00 258 259/* 260 * PP_TxEvent - Transmit Event Bit definition - Read-only 261 */ 262#define TX_LOST_CRS 0x0040 263#define TX_SQE_ERROR 0x0080 264#define TX_OK 0x0100 265#define TX_LATE_COL 0x0200 266#define TX_JBR 0x0400 267#define TX_16_COL 0x8000 268#define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS) 269#define TX_COL_COUNT_MASK 0x7800 270 271/* 272 * PP_BufEvent - Buffer Event Bit definition - Read-only 273 */ 274#define SW_INTERRUPT 0x0040 275#define RX_DMA 0x0080 276#define READY_FOR_TX 0x0100 277#define TX_UNDERRUN 0x0200 278#define RX_MISS 0x0400 279#define RX_128_BYTE 0x0800 280#define TX_COL_OVRFLW 0x1000 281#define RX_MISS_OVRFLW 0x2000 282#define RX_DEST_MATCH 0x8000 283 284/* 285 * PP_LineST - Ethernet Line Status bit definition - Read-only 286 */ 287#define LINK_OK 0x0080 288#define AUI_ON 0x0100 289#define TENBASET_ON 0x0200 290#define POLARITY_OK 0x1000 291#define CRS_OK 0x4000 292 293/* 294 * PP_SelfST - Chip Software Status bit definition 295 */ 296#define ACTIVE_33V 0x0040 297#define INIT_DONE 0x0080 298#define SI_BUSY 0x0100 299#define EEPROM_PRESENT 0x0200 300#define EEPROM_OK 0x0400 301#define EL_PRESENT 0x0800 302#define EE_SIZE_64 0x1000 303 304/* 305 * PP_BusST - ISA Bus Status bit definition 306 */ 307#define TX_BID_ERROR 0x0080 308#define READY_FOR_TX_NOW 0x0100 309 310/* 311 * PP_AutoNegCTL - Auto Negotiation Control bit definition 312 */ 313#define RE_NEG_NOW 0x0040 314#define ALLOW_FDX 0x0080 315#define AUTO_NEG_ENABLE 0x0100 316#define NLP_ENABLE 0x0200 317#define FORCE_FDX 0x8000 318#define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE) 319#define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \ 320 ALLOW_FDX | RE_NEG_NOW) 321 322/* 323 * PP_AutoNegST - Auto Negotiation Status bit definition 324 */ 325#define AUTO_NEG_BUSY 0x0080 326#define FLP_LINK 0x0100 327#define FLP_LINK_GOOD 0x0800 328#define LINK_FAULT 0x1000 329#define HDX_ACTIVE 0x4000 330#define FDX_ACTIVE 0x8000 331 332/* 333 * The following block defines the ISQ event types 334 */ 335#define ISQ_RECEIVER_EVENT 0x04 336#define ISQ_TRANSMITTER_EVENT 0x08 337#define ISQ_BUFFER_EVENT 0x0c 338#define ISQ_RX_MISS_EVENT 0x10 339#define ISQ_TX_COL_EVENT 0x12 340 341#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ 342#define ISQ_HIST 16 /* small history buffer */ 343#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ 344 345#define TXRXBUFSIZE 0x0600 346#define RXDMABUFSIZE 0x8000 347#define RXDMASIZE 0x4000 348#define TXRX_LENGTH_MASK 0x07FF 349 350/* rx options bits */ 351#define RCV_WITH_RXON 1 /* Set SerRx ON */ 352#define RCV_COUNTS 2 /* Use Framecnt1 */ 353#define RCV_PONG 4 /* Pong respondent */ 354#define RCV_DONG 8 /* Dong operation */ 355#define RCV_POLLING 0x10 /* Poll RxEvent */ 356#define RCV_ISQ 0x20 /* Use ISQ, int */ 357#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ 358#define RCV_DMA 0x200 /* Set RxDMA only */ 359#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ 360#define RCV_FIXED_DATA 0x800 /* Every frame same */ 361#define RCV_IO 0x1000 /* Use ISA IO only */ 362#define RCV_MEMORY 0x2000 /* Use ISA Memory */ 363 364#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ 365#define PKT_START PP_TxFrame /* Start of packet RAM */ 366 367#define RX_FRAME_PORT 0x0000 368#define TX_FRAME_PORT RX_FRAME_PORT 369#define TX_CMD_PORT 0x0004 370#define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */ 371#define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */ 372#define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */ 373#define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */ 374#define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ 375#define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */ 376#define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */ 377#define TX_LEN_PORT 0x0006 378#define ISQ_PORT 0x0008 379#define ADD_PORT 0x000A 380#define DATA_PORT 0x000C 381 382#define EEPROM_WRITE_EN 0x00F0 383#define EEPROM_WRITE_DIS 0x0000 384#define EEPROM_WRITE_CMD 0x0100 385#define EEPROM_READ_CMD 0x0200 386 387/* Receive Header 388 * Description of header of each packet in receive area of memory 389 */ 390#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ 391#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ 392#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ 393#define RBUF_LEN_HI 3 /* Length of received data - high byte */ 394#define RBUF_HEAD_LEN 4 /* Length of this header */ 395 396#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ 397#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ 398 399/* for bios scan */ 400/* */ 401#ifdef CSDEBUG 402/* use these values for debugging bios scan */ 403#define BIOS_START_SEG 0x00000 404#define BIOS_OFFSET_INC 0x0010 405#else 406#define BIOS_START_SEG 0x0c000 407#define BIOS_OFFSET_INC 0x0200 408#endif 409 410#define BIOS_LAST_OFFSET 0x0fc00 411 412/* 413 * Word offsets into the EEPROM configuration buffer 414 */ 415#define ISA_CNF_OFFSET 0x3 416#define INT_NO_MASK 0x000F 417#define DMA_NO_MASK 0x0070 418#define USE_SA 0x0080 419#define IOCHRDY_ENABLE 0x0100 420#define ISA_DMA_SIZE 0x0200 /* 0 16k 1 64k */ 421#define ISA_AUTO_RxDMA 0x0400 422#define ISA_RxDMA 0x0800 423#define DMA_BURST 0x1000 424#define STREAM_TRANSFER 0x2000 425#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) 426#define BOOT_PROM_FLAG 0x4000 427#define MEMORY_MODE 0x8000 428 429#define PACKET_PAGE_BASE (ISA_CNF_OFFSET + 1) 430#define BOOT_ROM_BASE (ISA_CNF_OFFSET + 2) 431#define BOOT_PROM_MASK (ISA_CNF_OFFSET + 3) 432 433#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 4) /* 8900 eeprom */ 434#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 4) /* 8920 eeprom */ 435 /* 436 * the assumption here is that the bits in the eeprom are generally 437 * in the same position as those in the autonegctl register. 438 * Of course the IMM bit is not in that register so it must be 439 * masked out 440 */ 441#define EE_FORCE_FDX 0x8000 442#define EE_NLP_ENABLE 0x0200 443#define EE_AUTO_NEG_ENABLE 0x0100 444#define EE_ALLOW_FDX 0x0080 445#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \ 446 EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX) 447#define IMM_BIT 0x0040 /* ignore missing media */ 448 449#define ADAPTER_CNF_OFFSET (ISA_CNF_OFFSET + 5) 450#define A_CNF_MEDIA 0x0007 451#define A_CNF_10B_T 0x0001 452#define A_CNF_AUI 0x0002 453#define A_CNF_10B_2 0x0004 454#define A_CNF_MEDIA_TYPE 0x0060 455#define A_CNF_MEDIA_AUTO 0x0000 456#define A_CNF_MEDIA_10B_T 0x0020 457#define A_CNF_MEDIA_AUI 0x0040 458#define A_CNF_MEDIA_10B_2 0x0060 459#define A_CNF_DC_DC_POLARITY 0x0080 460#define A_CNF_WAKE_ENABLED 0x0100 461#define A_CNF_WAKE_CFG 0x0200 462#define A_CNF_CAN_WAKE 0x0400 463#define A_CNF_OPT_FLAGS 0x1800 /* 00 server, 01 DOS 10 multi-user */ 464#define A_CNF_NO_AUTO_POLARITY 0x2000 465#define A_CNF_LOW_RX_SQUELCH 0x4000 466#define A_CNF_EXTND_10B_2 0x8000 467 468#define MFG_DATE_OFFSET (ISA_CNF_OFFSET + 8) 469 470#define PACKET_PAGE_OFFSET 0x8 471 472/* DMA controller registers */ 473#define DMA_BASE 0x00 /* DMA controller base */ 474#define DMA_BASE_2 0x0C0 /* DMA controller base */ 475 476#define DMA_STAT 0x0D0 /* DMA controller status register */ 477#define DMA_MASK 0x0D4 /* DMA controller mask register */ 478#define DMA_MODE 0x0D6 /* DMA controller mode register */ 479#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ 480 481/* DMA data */ 482#define DMA_DISABLE 0x04 /* Disable channel n */ 483#define DMA_ENABLE 0x00 /* Enable channel n */ 484/* Demand transfers, incr. address, auto init, writes, ch. n */ 485#define DMA_RX_MODE 0x14 486/* Demand transfers, incr. address, auto init, reads, ch. n */ 487#define DMA_TX_MODE 0x18 488 489#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ 490 491#define CS8900 0x0000 492#define CS8920 0x4000 493#define CS8920M 0x6000 494#define REVISON_BITS 0x1F00 495#define EEVER_NUMBER 0x12 496#define CHKSUM_LEN 0x14 497#define CHKSUM_VAL 0x0000 498#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ 499#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ 500#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ 501#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ 502#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ 503 504#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ 505 506#define PNP_ADD_PORT 0x0279 507#define PNP_WRITE_PORT 0x0A79 508 509#define GET_PNP_ISA_STRUCT 0x40 510#define PNP_ISA_STRUCT_LEN 0x06 511#define PNP_CSN_CNT_OFF 0x01 512#define PNP_RD_PORT_OFF 0x02 513#define PNP_FUNCTION_OK 0x00 514#define PNP_WAKE 0x03 515#define PNP_RSRC_DATA 0x04 516#define PNP_RSRC_READY 0x01 517#define PNP_STATUS 0x05 518#define PNP_ACTIVATE 0x30 519#define PNP_CNF_IO_H 0x60 520#define PNP_CNF_IO_L 0x61 521#define PNP_CNF_INT 0x70 522#define PNP_CNF_DMA 0x74 523#define PNP_CNF_MEM 0x48 524 525#define BIT0 1 526#define BIT15 0x8000 527 528#define CS_DUPLEX_AUTO 0 529#define CS_DUPLEX_FULL 1 530#define CS_DUPLEX_HALF 2 531 532/* 533 * It would appear that for pccards (well, the IBM EtherJet PCMCIA card) that 534 * are connected to card bus bridges there's a problem. For reading the 535 * value back you have to go into 8 bit mode. The Linux driver also uses 536 * this trick. This may be a bug in the card and how it handles fast 16-bit 537 * read after a write. 538 */ 539#define HACK_FOR_CARDBUS_BRIDGE_PROBLEM 540#ifdef HACK_FOR_CARDBUS_BRIDGE_PROBLEM 541static __inline uint16_t 542cs_inw(struct cs_softc *sc, int off) 543{ 544 if (off & 1) 545 device_printf(sc->dev, "BUG: inw to an odd address.\n"); 546 return ((bus_read_1(sc->port_res, off)) | 547 (bus_read_1(sc->port_res, off + 1) << 8)); 548} 549#else 550static __inline uint16_t 551cs_inw(struct cs_softc *sc, int off) 552{ 553 return (bus_read_2(sc->port_res, off)); 554} 555#endif 556 557static __inline void 558cs_outw(struct cs_softc *sc, int off, uint16_t val) 559{ 560 bus_write_2(sc->port_res, off, val); 561} 562 563static __inline uint16_t 564cs_readreg(struct cs_softc *sc, uint16_t port) 565{ 566 cs_outw(sc, ADD_PORT, port); 567 return (cs_inw(sc, DATA_PORT)); 568} 569static __inline void 570cs_writereg(struct cs_softc *sc, uint16_t port, uint16_t val) 571{ 572 cs_outw(sc, ADD_PORT, port); 573 cs_outw(sc, DATA_PORT, val); 574} 575 576static __inline void 577reset_chip(struct cs_softc *sc) 578{ 579 cs_writereg(sc, PP_SelfCTL, 580 cs_readreg(sc, PP_SelfCTL) | POWER_ON_RESET); 581} 582 583#define cs_duplex_full(sc) \ 584 (cs_writereg(sc, PP_AutoNegCTL, FORCE_FDX)) 585 586#define cs_duplex_half(sc) \ 587 (cs_writereg(sc, PP_AutoNegCTL, NLP_ENABLE)) 588 589