if_csreg.h revision 179591
1/*- 2 * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29/* 30 * $FreeBSD: head/sys/dev/cs/if_csreg.h 179591 2008-06-06 04:56:27Z imp $ 31 */ 32 33#define CS_89x0_IO_PORTS 0x0020 34 35#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ 36 /* offset 2h -> Model/Product Number */ 37 /* offset 3h -> Chip Revision Number */ 38 39#define PP_ISAIOB 0x0020 /* IO base address */ 40#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ 41#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ 42#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ 43#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ 44#define PP_ISASOF 0x0026 /* ISA DMA offset */ 45#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ 46#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ 47#define PP_CS8920_ISAMemB 0x0348 /* Memory base */ 48 49/* EEPROM data and command registers */ 50#define PP_EECMD 0x0040 /* NVR Interface Command register */ 51#define PP_EEData 0x0042 /* NVR Interface Data Register */ 52#define PP_DebugReg 0x0044 /* Debug Register */ 53 54#define PP_RxCFG 0x0102 /* Rx Bus config */ 55#define PP_RxCTL 0x0104 /* Receive Control Register */ 56#define PP_TxCFG 0x0106 /* Transmit Config Register */ 57#define PP_TxCMD 0x0108 /* Transmit Command Register */ 58#define PP_BufCFG 0x010A /* Bus configuration Register */ 59#define PP_LineCTL 0x0112 /* Line Config Register */ 60#define PP_SelfCTL 0x0114 /* Self Command Register */ 61#define PP_BusCTL 0x0116 /* ISA bus control Register */ 62#define PP_TestCTL 0x0118 /* Test Register */ 63#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ 64 65#define PP_ISQ 0x0120 /* Interrupt Status */ 66#define PP_RxEvent 0x0124 /* Rx Event Register */ 67#define PP_TxEvent 0x0128 /* Tx Event Register */ 68#define PP_BufEvent 0x012C /* Bus Event Register */ 69#define PP_RxMiss 0x0130 /* Receive Miss Count */ 70#define PP_TxCol 0x0132 /* Transmit Collision Count */ 71#define PP_LineST 0x0134 /* Line State Register */ 72#define PP_SelfST 0x0136 /* Self State register */ 73#define PP_BusST 0x0138 /* Bus Status */ 74#define PP_TDR 0x013C /* Time Domain Reflectometry */ 75#define PP_AutoNegST 0x013E /* Auto Neg Status */ 76#define PP_TxCommand 0x0144 /* Tx Command */ 77#define PP_TxLength 0x0146 /* Tx Length */ 78#define PP_LAF 0x0150 /* Hash Table */ 79#define PP_IA 0x0158 /* Physical Address Register */ 80 81#define PP_RxStatus 0x0400 /* Receive start of frame */ 82#define PP_RxLength 0x0402 /* Receive Length of frame */ 83#define PP_RxFrame 0x0404 /* Receive frame pointer */ 84#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ 85 86/* 87 * Primary I/O Base Address. If no I/O base is supplied by the user, then this 88 * can be used as the default I/O base to access the PacketPage Area. 89 */ 90#define DEFAULTIOBASE 0x0300 91#define FIRST_IO 0x020C /* First I/O port to check */ 92#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ 93#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ 94#define ADD_SIG 0x3000 /* Expected ID signature */ 95 96#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ 97 98#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ 99 100/* Mask to find out the types of registers */ 101#define REG_TYPE_MASK 0x001F 102 103/* Eeprom Commands */ 104#define ERSE_WR_ENBL 0x00F0 105#define ERSE_WR_DISABLE 0x0000 106 107/* Defines Control/Config register quintuplet numbers */ 108#define RX_BUF_CFG 0x0003 109#define RX_CONTROL 0x0005 110#define TX_CFG 0x0007 111#define TX_COMMAND 0x0009 112#define BUF_CFG 0x000B 113#define LINE_CONTROL 0x0013 114#define SELF_CONTROL 0x0015 115#define BUS_CONTROL 0x0017 116#define TEST_CONTROL 0x0019 117 118/* Defines Status/Count registers quintuplet numbers */ 119#define RX_EVENT 0x0004 120#define TX_EVENT 0x0008 121#define BUF_EVENT 0x000C 122#define RX_MISS_COUNT 0x0010 123#define TX_COL_COUNT 0x0012 124#define LINE_STATUS 0x0014 125#define SELF_STATUS 0x0016 126#define BUS_STATUS 0x0018 127#define TDR 0x001C 128 129/* 130 * PP_RxCFG - Receive Configuration and Interrupt Mask 131 * bit definition - Read/write 132 */ 133#define SKIP_1 0x0040 134#define RX_STREAM_ENBL 0x0080 135#define RX_OK_ENBL 0x0100 136#define RX_DMA_ONLY 0x0200 137#define AUTO_RX_DMA 0x0400 138#define BUFFER_CRC 0x0800 139#define RX_CRC_ERROR_ENBL 0x1000 140#define RX_RUNT_ENBL 0x2000 141#define RX_EXTRA_DATA_ENBL 0x4000 142 143/* PP_RxCTL - Receive Control bit definition - Read/write */ 144#define RX_IA_HASH_ACCEPT 0x0040 145#define RX_PROM_ACCEPT 0x0080 146#define RX_OK_ACCEPT 0x0100 147#define RX_MULTCAST_ACCEPT 0x0200 148#define RX_IA_ACCEPT 0x0400 149#define RX_BROADCAST_ACCEPT 0x0800 150#define RX_BAD_CRC_ACCEPT 0x1000 151#define RX_RUNT_ACCEPT 0x2000 152#define RX_EXTRA_DATA_ACCEPT 0x4000 153#define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \ 154 RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT) 155/* 156 * Default receive mode - individually addressed, broadcast, and error free 157 */ 158#define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) 159 160/* 161 * PP_TxCFG - Transmit Configuration Interrupt Mask 162 * bit definition - Read/write 163 */ 164#define TX_LOST_CRS_ENBL 0x0040 165#define TX_SQE_ERROR_ENBL 0x0080 166#define TX_OK_ENBL 0x0100 167#define TX_LATE_COL_ENBL 0x0200 168#define TX_JBR_ENBL 0x0400 169#define TX_ANY_COL_ENBL 0x0800 170#define TX_16_COL_ENBL 0x8000 171 172/* 173 * PP_TxCMD - Transmit Command bit definition - Read-only 174 */ 175#define TX_START_4_BYTES 0x0000 176#define TX_START_64_BYTES 0x0040 177#define TX_START_128_BYTES 0x0080 178#define TX_START_ALL_BYTES 0x00C0 179#define TX_FORCE 0x0100 180#define TX_ONE_COL 0x0200 181#define TX_TWO_PART_DEFF_DISABLE 0x0400 182#define TX_NO_CRC 0x1000 183#define TX_RUNT 0x2000 184 185/* 186 * PP_BufCFG - Buffer Configuration Interrupt Mask 187 * bit definition - Read/write 188 */ 189#define GENERATE_SW_INTERRUPT 0x0040 190#define RX_DMA_ENBL 0x0080 191#define READY_FOR_TX_ENBL 0x0100 192#define TX_UNDERRUN_ENBL 0x0200 193#define RX_MISS_ENBL 0x0400 194#define RX_128_BYTE_ENBL 0x0800 195#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 196#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 197#define RX_DEST_MATCH_ENBL 0x8000 198 199/* 200 * PP_LineCTL - Line Control bit definition - Read/write 201 */ 202#define SERIAL_RX_ON 0x0040 203#define SERIAL_TX_ON 0x0080 204#define AUI_ONLY 0x0100 205#define AUTO_AUI_10BASET 0x0200 206#define MODIFIED_BACKOFF 0x0800 207#define NO_AUTO_POLARITY 0x1000 208#define TWO_PART_DEFDIS 0x2000 209#define LOW_RX_SQUELCH 0x4000 210 211/* 212 * PP_SelfCTL - Software Self Control bit definition - Read/write 213 */ 214#define POWER_ON_RESET 0x0040 215#define SW_STOP 0x0100 216#define SLEEP_ON 0x0200 217#define AUTO_WAKEUP 0x0400 218#define HCB0_ENBL 0x1000 219#define HCB1_ENBL 0x2000 220#define HCB0 0x4000 221#define HCB1 0x8000 222 223/* 224 * PP_BusCTL - ISA Bus Control bit definition - Read/write 225 */ 226#define RESET_RX_DMA 0x0040 227#define MEMORY_ON 0x0400 228#define DMA_BURST_MODE 0x0800 229#define IO_CHANNEL_READY_ON 0x1000 230#define RX_DMA_SIZE_64Ks 0x2000 231#define ENABLE_IRQ 0x8000 232 233/* 234 * PP_TestCTL - Test Control bit definition - Read/write 235 */ 236#define LINK_OFF 0x0080 237#define ENDEC_LOOPBACK 0x0200 238#define AUI_LOOPBACK 0x0400 239#define BACKOFF_OFF 0x0800 240#define FAST_TEST 0x8000 241 242/* 243 * PP_RxEvent - Receive Event Bit definition - Read-only 244 */ 245#define RX_IA_HASHED 0x0040 246#define RX_DRIBBLE 0x0080 247#define RX_OK 0x0100 248#define RX_HASHED 0x0200 249#define RX_IA 0x0400 250#define RX_BROADCAST 0x0800 251#define RX_CRC_ERROR 0x1000 252#define RX_RUNT 0x2000 253#define RX_EXTRA_DATA 0x4000 254 255#define HASH_INDEX_MASK 0x0FC00 256 257/* 258 * PP_TxEvent - Transmit Event Bit definition - Read-only 259 */ 260#define TX_LOST_CRS 0x0040 261#define TX_SQE_ERROR 0x0080 262#define TX_OK 0x0100 263#define TX_LATE_COL 0x0200 264#define TX_JBR 0x0400 265#define TX_16_COL 0x8000 266#define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS) 267#define TX_COL_COUNT_MASK 0x7800 268 269/* 270 * PP_BufEvent - Buffer Event Bit definition - Read-only 271 */ 272#define SW_INTERRUPT 0x0040 273#define RX_DMA 0x0080 274#define READY_FOR_TX 0x0100 275#define TX_UNDERRUN 0x0200 276#define RX_MISS 0x0400 277#define RX_128_BYTE 0x0800 278#define TX_COL_OVRFLW 0x1000 279#define RX_MISS_OVRFLW 0x2000 280#define RX_DEST_MATCH 0x8000 281 282/* 283 * PP_LineST - Ethernet Line Status bit definition - Read-only 284 */ 285#define LINK_OK 0x0080 286#define AUI_ON 0x0100 287#define TENBASET_ON 0x0200 288#define POLARITY_OK 0x1000 289#define CRS_OK 0x4000 290 291/* 292 * PP_SelfST - Chip Software Status bit definition 293 */ 294#define ACTIVE_33V 0x0040 295#define INIT_DONE 0x0080 296#define SI_BUSY 0x0100 297#define EEPROM_PRESENT 0x0200 298#define EEPROM_OK 0x0400 299#define EL_PRESENT 0x0800 300#define EE_SIZE_64 0x1000 301 302/* 303 * PP_BusST - ISA Bus Status bit definition 304 */ 305#define TX_BID_ERROR 0x0080 306#define READY_FOR_TX_NOW 0x0100 307 308/* 309 * PP_AutoNegCTL - Auto Negotiation Control bit definition 310 */ 311#define RE_NEG_NOW 0x0040 312#define ALLOW_FDX 0x0080 313#define AUTO_NEG_ENABLE 0x0100 314#define NLP_ENABLE 0x0200 315#define FORCE_FDX 0x8000 316#define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE) 317#define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \ 318 ALLOW_FDX | RE_NEG_NOW) 319 320/* 321 * PP_AutoNegST - Auto Negotiation Status bit definition 322 */ 323#define AUTO_NEG_BUSY 0x0080 324#define FLP_LINK 0x0100 325#define FLP_LINK_GOOD 0x0800 326#define LINK_FAULT 0x1000 327#define HDX_ACTIVE 0x4000 328#define FDX_ACTIVE 0x8000 329 330/* 331 * The following block defines the ISQ event types 332 */ 333#define ISQ_RECEIVER_EVENT 0x04 334#define ISQ_TRANSMITTER_EVENT 0x08 335#define ISQ_BUFFER_EVENT 0x0c 336#define ISQ_RX_MISS_EVENT 0x10 337#define ISQ_TX_COL_EVENT 0x12 338 339#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ 340#define ISQ_HIST 16 /* small history buffer */ 341#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ 342 343#define TXRXBUFSIZE 0x0600 344#define RXDMABUFSIZE 0x8000 345#define RXDMASIZE 0x4000 346#define TXRX_LENGTH_MASK 0x07FF 347 348/* rx options bits */ 349#define RCV_WITH_RXON 1 /* Set SerRx ON */ 350#define RCV_COUNTS 2 /* Use Framecnt1 */ 351#define RCV_PONG 4 /* Pong respondent */ 352#define RCV_DONG 8 /* Dong operation */ 353#define RCV_POLLING 0x10 /* Poll RxEvent */ 354#define RCV_ISQ 0x20 /* Use ISQ, int */ 355#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ 356#define RCV_DMA 0x200 /* Set RxDMA only */ 357#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ 358#define RCV_FIXED_DATA 0x800 /* Every frame same */ 359#define RCV_IO 0x1000 /* Use ISA IO only */ 360#define RCV_MEMORY 0x2000 /* Use ISA Memory */ 361 362#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ 363#define PKT_START PP_TxFrame /* Start of packet RAM */ 364 365#define RX_FRAME_PORT 0x0000 366#define TX_FRAME_PORT RX_FRAME_PORT 367#define TX_CMD_PORT 0x0004 368#define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */ 369#define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */ 370#define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */ 371#define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */ 372#define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ 373#define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */ 374#define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */ 375#define TX_LEN_PORT 0x0006 376#define ISQ_PORT 0x0008 377#define ADD_PORT 0x000A 378#define DATA_PORT 0x000C 379 380#define EEPROM_WRITE_EN 0x00F0 381#define EEPROM_WRITE_DIS 0x0000 382#define EEPROM_WRITE_CMD 0x0100 383#define EEPROM_READ_CMD 0x0200 384 385/* Receive Header 386 * Description of header of each packet in receive area of memory 387 */ 388#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ 389#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ 390#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ 391#define RBUF_LEN_HI 3 /* Length of received data - high byte */ 392#define RBUF_HEAD_LEN 4 /* Length of this header */ 393 394#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ 395#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ 396 397/* for bios scan */ 398/* */ 399#ifdef CSDEBUG 400/* use these values for debugging bios scan */ 401#define BIOS_START_SEG 0x00000 402#define BIOS_OFFSET_INC 0x0010 403#else 404#define BIOS_START_SEG 0x0c000 405#define BIOS_OFFSET_INC 0x0200 406#endif 407 408#define BIOS_LAST_OFFSET 0x0fc00 409 410/* 411 * Byte offsets into the EEPROM configuration buffer 412 */ 413#define ISA_CNF_OFFSET 0x6 414#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ 415#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ 416 417/* 418 * the assumption here is that the bits in the eeprom are generally 419 * in the same position as those in the autonegctl register. 420 * Of course the IMM bit is not in that register so it must be 421 * masked out 422 */ 423#define EE_FORCE_FDX 0x8000 424#define EE_NLP_ENABLE 0x0200 425#define EE_AUTO_NEG_ENABLE 0x0100 426#define EE_ALLOW_FDX 0x0080 427#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \ 428 EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX) 429 430#define IMM_BIT 0x0040 /* ignore missing media */ 431 432#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) 433#define A_CNF_MEDIA 0x0007 434#define A_CNF_10B_T 0x0001 435#define A_CNF_AUI 0x0002 436#define A_CNF_10B_2 0x0004 437#define A_CNF_MEDIA_TYPE 0x0060 438#define A_CNF_MEDIA_AUTO 0x0000 439#define A_CNF_MEDIA_10B_T 0x0020 440#define A_CNF_MEDIA_AUI 0x0040 441#define A_CNF_MEDIA_10B_2 0x0060 442#define A_CNF_DC_DC_POLARITY 0x0080 443#define A_CNF_NO_AUTO_POLARITY 0x2000 444#define A_CNF_LOW_RX_SQUELCH 0x4000 445#define A_CNF_EXTND_10B_2 0x8000 446 447#define PACKET_PAGE_OFFSET 0x8 448 449/* 450 * Bit definitions for the ISA configuration word from the EEPROM 451 */ 452#define INT_NO_MASK 0x000F 453#define DMA_NO_MASK 0x0070 454#define ISA_DMA_SIZE 0x0200 455#define ISA_AUTO_RxDMA 0x0400 456#define ISA_RxDMA 0x0800 457#define DMA_BURST 0x1000 458#define STREAM_TRANSFER 0x2000 459#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) 460 461/* DMA controller registers */ 462#define DMA_BASE 0x00 /* DMA controller base */ 463#define DMA_BASE_2 0x0C0 /* DMA controller base */ 464 465#define DMA_STAT 0x0D0 /* DMA controller status register */ 466#define DMA_MASK 0x0D4 /* DMA controller mask register */ 467#define DMA_MODE 0x0D6 /* DMA controller mode register */ 468#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ 469 470/* DMA data */ 471#define DMA_DISABLE 0x04 /* Disable channel n */ 472#define DMA_ENABLE 0x00 /* Enable channel n */ 473/* Demand transfers, incr. address, auto init, writes, ch. n */ 474#define DMA_RX_MODE 0x14 475/* Demand transfers, incr. address, auto init, reads, ch. n */ 476#define DMA_TX_MODE 0x18 477 478#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ 479 480#define CS8900 0x0000 481#define CS8920 0x4000 482#define CS8920M 0x6000 483#define REVISON_BITS 0x1F00 484#define EEVER_NUMBER 0x12 485#define CHKSUM_LEN 0x14 486#define CHKSUM_VAL 0x0000 487#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ 488#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ 489#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ 490#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ 491#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ 492 493#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ 494 495#define PNP_ADD_PORT 0x0279 496#define PNP_WRITE_PORT 0x0A79 497 498#define GET_PNP_ISA_STRUCT 0x40 499#define PNP_ISA_STRUCT_LEN 0x06 500#define PNP_CSN_CNT_OFF 0x01 501#define PNP_RD_PORT_OFF 0x02 502#define PNP_FUNCTION_OK 0x00 503#define PNP_WAKE 0x03 504#define PNP_RSRC_DATA 0x04 505#define PNP_RSRC_READY 0x01 506#define PNP_STATUS 0x05 507#define PNP_ACTIVATE 0x30 508#define PNP_CNF_IO_H 0x60 509#define PNP_CNF_IO_L 0x61 510#define PNP_CNF_INT 0x70 511#define PNP_CNF_DMA 0x74 512#define PNP_CNF_MEM 0x48 513 514#define BIT0 1 515#define BIT15 0x8000 516 517#define CS_DUPLEX_AUTO 0 518#define CS_DUPLEX_FULL 1 519#define CS_DUPLEX_HALF 2 520 521/* 522 * It would appear that for pccards (well, the IBM EtherJet PCMCIA card) that 523 * are connected to card bus bridges there's a problem. For reading the 524 * value back you have to go into 8 bit mode. The Linux driver also uses 525 * this trick. This may be a bug in the card and how it handles fast 16-bit 526 * read after a write. 527 */ 528#define HACK_FOR_CARDBUS_BRIDGE_PROBLEM 529#ifdef HACK_FOR_CARDBUS_BRIDGE_PROBLEM 530static __inline uint16_t 531cs_inw(struct cs_softc *sc, int off) 532{ 533 return ((inb(sc->nic_addr + off) & 0xff) | 534 (inb(sc->nic_addr + off + 1) << 8)); 535} 536#else 537static __inline uint16_t 538cs_inw(struct cs_softc *sc, int off) 539{ 540 return (inw(sc->nic_addr + off)); 541} 542#endif 543 544static __inline void 545cs_outw(struct cs_softc *sc, int off, uint16_t val) 546{ 547 outw(sc->nic_addr + off, val); 548} 549 550static __inline uint16_t 551cs_readreg(struct cs_softc *sc, uint16_t port) 552{ 553 cs_outw(sc, ADD_PORT, port); 554 return (cs_inw(sc, DATA_PORT)); 555} 556static __inline void 557cs_writereg(struct cs_softc *sc, uint16_t port, uint16_t val) 558{ 559 cs_outw(sc, ADD_PORT, port); 560 cs_outw(sc, DATA_PORT, val); 561} 562 563static __inline void 564reset_chip(struct cs_softc *sc) 565{ 566 cs_writereg(sc, PP_SelfCTL, 567 cs_readreg(sc, PP_SelfCTL) | POWER_ON_RESET); 568} 569 570#define cs_duplex_full(sc) \ 571 (cs_writereg(sc, PP_AutoNegCTL, FORCE_FDX)) 572 573#define cs_duplex_half(sc) \ 574 (cs_writereg(sc, PP_AutoNegCTL, NLP_ENABLE)) 575 576