if_csreg.h revision 58816
137785Smsmith/* 237785Smsmith * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko. 337785Smsmith * All rights reserved. 437785Smsmith * 537785Smsmith * Redistribution and use in source and binary forms, with or without 637785Smsmith * modification, are permitted provided that the following conditions 737785Smsmith * are met: 837785Smsmith * 1. Redistributions of source code must retain the above copyright 937785Smsmith * notice unmodified, this list of conditions, and the following 1037785Smsmith * disclaimer. 1137785Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1237785Smsmith * notice, this list of conditions and the following disclaimer in the 1337785Smsmith * documentation and/or other materials provided with the distribution. 1437785Smsmith * 1537785Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1637785Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1737785Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1837785Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1937785Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2037785Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2137785Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2237785Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2337785Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2437785Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2537785Smsmith * SUCH DAMAGE. 2637785Smsmith * 2737785Smsmith */ 2837785Smsmith 2937785Smsmith/* 3050477Speter * $FreeBSD: head/sys/dev/cs/if_csreg.h 58816 2000-03-30 05:16:16Z imp $ 3137785Smsmith */ 3237785Smsmith 3358816Simp#define CS_89x0_IO_PORTS 0x0020 3458816Simp 3537785Smsmith#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ 3637785Smsmith /* offset 2h -> Model/Product Number */ 3737785Smsmith /* offset 3h -> Chip Revision Number */ 3837785Smsmith 3937785Smsmith#define PP_ISAIOB 0x0020 /* IO base address */ 4037785Smsmith#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ 4137785Smsmith#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ 4237785Smsmith#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ 4337785Smsmith#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ 4437785Smsmith#define PP_ISASOF 0x0026 /* ISA DMA offset */ 4537785Smsmith#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ 4637785Smsmith#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ 4737785Smsmith#define PP_CS8920_ISAMemB 0x0348 /* Memory base */ 4837785Smsmith 4937785Smsmith/* EEPROM data and command registers */ 5037785Smsmith#define PP_EECMD 0x0040 /* NVR Interface Command register */ 5137785Smsmith#define PP_EEData 0x0042 /* NVR Interface Data Register */ 5237785Smsmith#define PP_DebugReg 0x0044 /* Debug Register */ 5337785Smsmith 5437785Smsmith#define PP_RxCFG 0x0102 /* Rx Bus config */ 5537785Smsmith#define PP_RxCTL 0x0104 /* Receive Control Register */ 5637785Smsmith#define PP_TxCFG 0x0106 /* Transmit Config Register */ 5737785Smsmith#define PP_TxCMD 0x0108 /* Transmit Command Register */ 5837785Smsmith#define PP_BufCFG 0x010A /* Bus configuration Register */ 5937785Smsmith#define PP_LineCTL 0x0112 /* Line Config Register */ 6037785Smsmith#define PP_SelfCTL 0x0114 /* Self Command Register */ 6137785Smsmith#define PP_BusCTL 0x0116 /* ISA bus control Register */ 6237785Smsmith#define PP_TestCTL 0x0118 /* Test Register */ 6337785Smsmith#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ 6437785Smsmith 6537785Smsmith#define PP_ISQ 0x0120 /* Interrupt Status */ 6637785Smsmith#define PP_RxEvent 0x0124 /* Rx Event Register */ 6737785Smsmith#define PP_TxEvent 0x0128 /* Tx Event Register */ 6837785Smsmith#define PP_BufEvent 0x012C /* Bus Event Register */ 6937785Smsmith#define PP_RxMiss 0x0130 /* Receive Miss Count */ 7037785Smsmith#define PP_TxCol 0x0132 /* Transmit Collision Count */ 7137785Smsmith#define PP_LineST 0x0134 /* Line State Register */ 7237785Smsmith#define PP_SelfST 0x0136 /* Self State register */ 7337785Smsmith#define PP_BusST 0x0138 /* Bus Status */ 7437785Smsmith#define PP_TDR 0x013C /* Time Domain Reflectometry */ 7537785Smsmith#define PP_AutoNegST 0x013E /* Auto Neg Status */ 7637785Smsmith#define PP_TxCommand 0x0144 /* Tx Command */ 7737785Smsmith#define PP_TxLength 0x0146 /* Tx Length */ 7837785Smsmith#define PP_LAF 0x0150 /* Hash Table */ 7937785Smsmith#define PP_IA 0x0158 /* Physical Address Register */ 8037785Smsmith 8137785Smsmith#define PP_RxStatus 0x0400 /* Receive start of frame */ 8237785Smsmith#define PP_RxLength 0x0402 /* Receive Length of frame */ 8337785Smsmith#define PP_RxFrame 0x0404 /* Receive frame pointer */ 8437785Smsmith#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ 8537785Smsmith 8637785Smsmith/* 8737785Smsmith * Primary I/O Base Address. If no I/O base is supplied by the user, then this 8837785Smsmith * can be used as the default I/O base to access the PacketPage Area. 8937785Smsmith */ 9037785Smsmith#define DEFAULTIOBASE 0x0300 9137785Smsmith#define FIRST_IO 0x020C /* First I/O port to check */ 9237785Smsmith#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ 9337785Smsmith#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ 9437785Smsmith#define ADD_SIG 0x3000 /* Expected ID signature */ 9537785Smsmith 9637785Smsmith#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ 9737785Smsmith 9837785Smsmith#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ 9937785Smsmith 10037785Smsmith/* Mask to find out the types of registers */ 10137785Smsmith#define REG_TYPE_MASK 0x001F 10237785Smsmith 10337785Smsmith/* Eeprom Commands */ 10437785Smsmith#define ERSE_WR_ENBL 0x00F0 10537785Smsmith#define ERSE_WR_DISABLE 0x0000 10637785Smsmith 10737785Smsmith/* Defines Control/Config register quintuplet numbers */ 10837785Smsmith#define RX_BUF_CFG 0x0003 10937785Smsmith#define RX_CONTROL 0x0005 11037785Smsmith#define TX_CFG 0x0007 11137785Smsmith#define TX_COMMAND 0x0009 11237785Smsmith#define BUF_CFG 0x000B 11337785Smsmith#define LINE_CONTROL 0x0013 11437785Smsmith#define SELF_CONTROL 0x0015 11537785Smsmith#define BUS_CONTROL 0x0017 11637785Smsmith#define TEST_CONTROL 0x0019 11737785Smsmith 11837785Smsmith/* Defines Status/Count registers quintuplet numbers */ 11937785Smsmith#define RX_EVENT 0x0004 12037785Smsmith#define TX_EVENT 0x0008 12137785Smsmith#define BUF_EVENT 0x000C 12237785Smsmith#define RX_MISS_COUNT 0x0010 12337785Smsmith#define TX_COL_COUNT 0x0012 12437785Smsmith#define LINE_STATUS 0x0014 12537785Smsmith#define SELF_STATUS 0x0016 12637785Smsmith#define BUS_STATUS 0x0018 12737785Smsmith#define TDR 0x001C 12837785Smsmith 12937785Smsmith/* 13037785Smsmith * PP_RxCFG - Receive Configuration and Interrupt Mask 13137785Smsmith * bit definition - Read/write 13237785Smsmith */ 13337785Smsmith#define SKIP_1 0x0040 13437785Smsmith#define RX_STREAM_ENBL 0x0080 13537785Smsmith#define RX_OK_ENBL 0x0100 13637785Smsmith#define RX_DMA_ONLY 0x0200 13737785Smsmith#define AUTO_RX_DMA 0x0400 13837785Smsmith#define BUFFER_CRC 0x0800 13937785Smsmith#define RX_CRC_ERROR_ENBL 0x1000 14037785Smsmith#define RX_RUNT_ENBL 0x2000 14137785Smsmith#define RX_EXTRA_DATA_ENBL 0x4000 14237785Smsmith 14337785Smsmith/* PP_RxCTL - Receive Control bit definition - Read/write */ 14437785Smsmith#define RX_IA_HASH_ACCEPT 0x0040 14537785Smsmith#define RX_PROM_ACCEPT 0x0080 14637785Smsmith#define RX_OK_ACCEPT 0x0100 14737785Smsmith#define RX_MULTCAST_ACCEPT 0x0200 14837785Smsmith#define RX_IA_ACCEPT 0x0400 14937785Smsmith#define RX_BROADCAST_ACCEPT 0x0800 15037785Smsmith#define RX_BAD_CRC_ACCEPT 0x1000 15137785Smsmith#define RX_RUNT_ACCEPT 0x2000 15237785Smsmith#define RX_EXTRA_DATA_ACCEPT 0x4000 15337785Smsmith#define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \ 15437785Smsmith RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT) 15537785Smsmith/* 15637785Smsmith * Default receive mode - individually addressed, broadcast, and error free 15737785Smsmith */ 15837785Smsmith#define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) 15937785Smsmith 16037785Smsmith/* 16137785Smsmith * PP_TxCFG - Transmit Configuration Interrupt Mask 16237785Smsmith * bit definition - Read/write 16337785Smsmith */ 16437785Smsmith#define TX_LOST_CRS_ENBL 0x0040 16537785Smsmith#define TX_SQE_ERROR_ENBL 0x0080 16637785Smsmith#define TX_OK_ENBL 0x0100 16737785Smsmith#define TX_LATE_COL_ENBL 0x0200 16837785Smsmith#define TX_JBR_ENBL 0x0400 16937785Smsmith#define TX_ANY_COL_ENBL 0x0800 17037785Smsmith#define TX_16_COL_ENBL 0x8000 17137785Smsmith 17237785Smsmith/* 17337785Smsmith * PP_TxCMD - Transmit Command bit definition - Read-only 17437785Smsmith */ 17537785Smsmith#define TX_START_4_BYTES 0x0000 17637785Smsmith#define TX_START_64_BYTES 0x0040 17737785Smsmith#define TX_START_128_BYTES 0x0080 17837785Smsmith#define TX_START_ALL_BYTES 0x00C0 17937785Smsmith#define TX_FORCE 0x0100 18037785Smsmith#define TX_ONE_COL 0x0200 18137785Smsmith#define TX_TWO_PART_DEFF_DISABLE 0x0400 18237785Smsmith#define TX_NO_CRC 0x1000 18337785Smsmith#define TX_RUNT 0x2000 18437785Smsmith 18537785Smsmith/* 18637785Smsmith * PP_BufCFG - Buffer Configuration Interrupt Mask 18737785Smsmith * bit definition - Read/write 18837785Smsmith */ 18937785Smsmith#define GENERATE_SW_INTERRUPT 0x0040 19037785Smsmith#define RX_DMA_ENBL 0x0080 19137785Smsmith#define READY_FOR_TX_ENBL 0x0100 19237785Smsmith#define TX_UNDERRUN_ENBL 0x0200 19337785Smsmith#define RX_MISS_ENBL 0x0400 19437785Smsmith#define RX_128_BYTE_ENBL 0x0800 19537785Smsmith#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 19637785Smsmith#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 19737785Smsmith#define RX_DEST_MATCH_ENBL 0x8000 19837785Smsmith 19937785Smsmith/* 20037785Smsmith * PP_LineCTL - Line Control bit definition - Read/write 20137785Smsmith */ 20237785Smsmith#define SERIAL_RX_ON 0x0040 20337785Smsmith#define SERIAL_TX_ON 0x0080 20437785Smsmith#define AUI_ONLY 0x0100 20537785Smsmith#define AUTO_AUI_10BASET 0x0200 20637785Smsmith#define MODIFIED_BACKOFF 0x0800 20737785Smsmith#define NO_AUTO_POLARITY 0x1000 20837785Smsmith#define TWO_PART_DEFDIS 0x2000 20937785Smsmith#define LOW_RX_SQUELCH 0x4000 21037785Smsmith 21137785Smsmith/* 21237785Smsmith * PP_SelfCTL - Software Self Control bit definition - Read/write 21337785Smsmith */ 21437785Smsmith#define POWER_ON_RESET 0x0040 21537785Smsmith#define SW_STOP 0x0100 21637785Smsmith#define SLEEP_ON 0x0200 21737785Smsmith#define AUTO_WAKEUP 0x0400 21837785Smsmith#define HCB0_ENBL 0x1000 21937785Smsmith#define HCB1_ENBL 0x2000 22037785Smsmith#define HCB0 0x4000 22137785Smsmith#define HCB1 0x8000 22237785Smsmith 22337785Smsmith/* 22437785Smsmith * PP_BusCTL - ISA Bus Control bit definition - Read/write 22537785Smsmith */ 22637785Smsmith#define RESET_RX_DMA 0x0040 22737785Smsmith#define MEMORY_ON 0x0400 22837785Smsmith#define DMA_BURST_MODE 0x0800 22937785Smsmith#define IO_CHANNEL_READY_ON 0x1000 23037785Smsmith#define RX_DMA_SIZE_64Ks 0x2000 23137785Smsmith#define ENABLE_IRQ 0x8000 23237785Smsmith 23337785Smsmith/* 23437785Smsmith * PP_TestCTL - Test Control bit definition - Read/write 23537785Smsmith */ 23637785Smsmith#define LINK_OFF 0x0080 23737785Smsmith#define ENDEC_LOOPBACK 0x0200 23837785Smsmith#define AUI_LOOPBACK 0x0400 23937785Smsmith#define BACKOFF_OFF 0x0800 24037785Smsmith#define FAST_TEST 0x8000 24137785Smsmith 24237785Smsmith/* 24337785Smsmith * PP_RxEvent - Receive Event Bit definition - Read-only 24437785Smsmith */ 24537785Smsmith#define RX_IA_HASHED 0x0040 24637785Smsmith#define RX_DRIBBLE 0x0080 24737785Smsmith#define RX_OK 0x0100 24837785Smsmith#define RX_HASHED 0x0200 24937785Smsmith#define RX_IA 0x0400 25037785Smsmith#define RX_BROADCAST 0x0800 25137785Smsmith#define RX_CRC_ERROR 0x1000 25237785Smsmith#define RX_RUNT 0x2000 25337785Smsmith#define RX_EXTRA_DATA 0x4000 25437785Smsmith 25537785Smsmith#define HASH_INDEX_MASK 0x0FC00 25637785Smsmith 25737785Smsmith/* 25837785Smsmith * PP_TxEvent - Transmit Event Bit definition - Read-only 25937785Smsmith */ 26037785Smsmith#define TX_LOST_CRS 0x0040 26137785Smsmith#define TX_SQE_ERROR 0x0080 26237785Smsmith#define TX_OK 0x0100 26337785Smsmith#define TX_LATE_COL 0x0200 26437785Smsmith#define TX_JBR 0x0400 26537785Smsmith#define TX_16_COL 0x8000 26637785Smsmith#define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS) 26737785Smsmith#define TX_COL_COUNT_MASK 0x7800 26837785Smsmith 26937785Smsmith/* 27037785Smsmith * PP_BufEvent - Buffer Event Bit definition - Read-only 27137785Smsmith */ 27237785Smsmith#define SW_INTERRUPT 0x0040 27337785Smsmith#define RX_DMA 0x0080 27437785Smsmith#define READY_FOR_TX 0x0100 27537785Smsmith#define TX_UNDERRUN 0x0200 27637785Smsmith#define RX_MISS 0x0400 27737785Smsmith#define RX_128_BYTE 0x0800 27837785Smsmith#define TX_COL_OVRFLW 0x1000 27937785Smsmith#define RX_MISS_OVRFLW 0x2000 28037785Smsmith#define RX_DEST_MATCH 0x8000 28137785Smsmith 28237785Smsmith/* 28337785Smsmith * PP_LineST - Ethernet Line Status bit definition - Read-only 28437785Smsmith */ 28537785Smsmith#define LINK_OK 0x0080 28637785Smsmith#define AUI_ON 0x0100 28737785Smsmith#define TENBASET_ON 0x0200 28837785Smsmith#define POLARITY_OK 0x1000 28937785Smsmith#define CRS_OK 0x4000 29037785Smsmith 29137785Smsmith/* 29237785Smsmith * PP_SelfST - Chip Software Status bit definition 29337785Smsmith */ 29437785Smsmith#define ACTIVE_33V 0x0040 29537785Smsmith#define INIT_DONE 0x0080 29637785Smsmith#define SI_BUSY 0x0100 29737785Smsmith#define EEPROM_PRESENT 0x0200 29837785Smsmith#define EEPROM_OK 0x0400 29937785Smsmith#define EL_PRESENT 0x0800 30037785Smsmith#define EE_SIZE_64 0x1000 30137785Smsmith 30237785Smsmith/* 30337785Smsmith * PP_BusST - ISA Bus Status bit definition 30437785Smsmith */ 30537785Smsmith#define TX_BID_ERROR 0x0080 30637785Smsmith#define READY_FOR_TX_NOW 0x0100 30737785Smsmith 30837785Smsmith/* 30937785Smsmith * PP_AutoNegCTL - Auto Negotiation Control bit definition 31037785Smsmith */ 31137785Smsmith#define RE_NEG_NOW 0x0040 31237785Smsmith#define ALLOW_FDX 0x0080 31337785Smsmith#define AUTO_NEG_ENABLE 0x0100 31437785Smsmith#define NLP_ENABLE 0x0200 31537785Smsmith#define FORCE_FDX 0x8000 31637785Smsmith#define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE) 31737785Smsmith#define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \ 31837785Smsmith ALLOW_FDX | RE_NEG_NOW) 31937785Smsmith 32037785Smsmith/* 32137785Smsmith * PP_AutoNegST - Auto Negotiation Status bit definition 32237785Smsmith */ 32337785Smsmith#define AUTO_NEG_BUSY 0x0080 32437785Smsmith#define FLP_LINK 0x0100 32537785Smsmith#define FLP_LINK_GOOD 0x0800 32637785Smsmith#define LINK_FAULT 0x1000 32737785Smsmith#define HDX_ACTIVE 0x4000 32837785Smsmith#define FDX_ACTIVE 0x8000 32937785Smsmith 33037785Smsmith/* 33137785Smsmith * The following block defines the ISQ event types 33237785Smsmith */ 33337785Smsmith#define ISQ_RECEIVER_EVENT 0x04 33437785Smsmith#define ISQ_TRANSMITTER_EVENT 0x08 33537785Smsmith#define ISQ_BUFFER_EVENT 0x0c 33637785Smsmith#define ISQ_RX_MISS_EVENT 0x10 33737785Smsmith#define ISQ_TX_COL_EVENT 0x12 33837785Smsmith 33937785Smsmith#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ 34037785Smsmith#define ISQ_HIST 16 /* small history buffer */ 34137785Smsmith#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ 34237785Smsmith 34337785Smsmith#define TXRXBUFSIZE 0x0600 34437785Smsmith#define RXDMABUFSIZE 0x8000 34537785Smsmith#define RXDMASIZE 0x4000 34637785Smsmith#define TXRX_LENGTH_MASK 0x07FF 34737785Smsmith 34837785Smsmith/* rx options bits */ 34937785Smsmith#define RCV_WITH_RXON 1 /* Set SerRx ON */ 35037785Smsmith#define RCV_COUNTS 2 /* Use Framecnt1 */ 35137785Smsmith#define RCV_PONG 4 /* Pong respondent */ 35237785Smsmith#define RCV_DONG 8 /* Dong operation */ 35337785Smsmith#define RCV_POLLING 0x10 /* Poll RxEvent */ 35437785Smsmith#define RCV_ISQ 0x20 /* Use ISQ, int */ 35537785Smsmith#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ 35637785Smsmith#define RCV_DMA 0x200 /* Set RxDMA only */ 35737785Smsmith#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ 35837785Smsmith#define RCV_FIXED_DATA 0x800 /* Every frame same */ 35937785Smsmith#define RCV_IO 0x1000 /* Use ISA IO only */ 36037785Smsmith#define RCV_MEMORY 0x2000 /* Use ISA Memory */ 36137785Smsmith 36237785Smsmith#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ 36337785Smsmith#define PKT_START PP_TxFrame /* Start of packet RAM */ 36437785Smsmith 36537785Smsmith#define RX_FRAME_PORT 0x0000 36637785Smsmith#define TX_FRAME_PORT RX_FRAME_PORT 36737785Smsmith#define TX_CMD_PORT 0x0004 36837785Smsmith#define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */ 36937785Smsmith#define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */ 37037785Smsmith#define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */ 37137785Smsmith#define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */ 37237785Smsmith#define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ 37337785Smsmith#define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */ 37437785Smsmith#define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */ 37537785Smsmith#define TX_LEN_PORT 0x0006 37637785Smsmith#define ISQ_PORT 0x0008 37737785Smsmith#define ADD_PORT 0x000A 37837785Smsmith#define DATA_PORT 0x000C 37937785Smsmith 38037785Smsmith#define EEPROM_WRITE_EN 0x00F0 38137785Smsmith#define EEPROM_WRITE_DIS 0x0000 38237785Smsmith#define EEPROM_WRITE_CMD 0x0100 38337785Smsmith#define EEPROM_READ_CMD 0x0200 38437785Smsmith 38537785Smsmith/* Receive Header 38637785Smsmith * Description of header of each packet in receive area of memory 38737785Smsmith */ 38837785Smsmith#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ 38937785Smsmith#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ 39037785Smsmith#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ 39137785Smsmith#define RBUF_LEN_HI 3 /* Length of received data - high byte */ 39237785Smsmith#define RBUF_HEAD_LEN 4 /* Length of this header */ 39337785Smsmith 39437785Smsmith#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ 39537785Smsmith#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ 39637785Smsmith 39737785Smsmith/* for bios scan */ 39837785Smsmith/* */ 39937785Smsmith#ifdef CSDEBUG 40037785Smsmith/* use these values for debugging bios scan */ 40137785Smsmith#define BIOS_START_SEG 0x00000 40237785Smsmith#define BIOS_OFFSET_INC 0x0010 40337785Smsmith#else 40437785Smsmith#define BIOS_START_SEG 0x0c000 40537785Smsmith#define BIOS_OFFSET_INC 0x0200 40637785Smsmith#endif 40737785Smsmith 40837785Smsmith#define BIOS_LAST_OFFSET 0x0fc00 40937785Smsmith 41037785Smsmith/* 41137785Smsmith * Byte offsets into the EEPROM configuration buffer 41237785Smsmith */ 41337785Smsmith#define ISA_CNF_OFFSET 0x6 41437785Smsmith#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ 41537785Smsmith#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ 41637785Smsmith 41737785Smsmith/* 41837785Smsmith * the assumption here is that the bits in the eeprom are generally 41937785Smsmith * in the same position as those in the autonegctl register. 42037785Smsmith * Of course the IMM bit is not in that register so it must be 42137785Smsmith * masked out 42237785Smsmith */ 42337785Smsmith#define EE_FORCE_FDX 0x8000 42437785Smsmith#define EE_NLP_ENABLE 0x0200 42537785Smsmith#define EE_AUTO_NEG_ENABLE 0x0100 42637785Smsmith#define EE_ALLOW_FDX 0x0080 42737785Smsmith#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \ 42837785Smsmith EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX) 42937785Smsmith 43037785Smsmith#define IMM_BIT 0x0040 /* ignore missing media */ 43137785Smsmith 43237785Smsmith#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) 43337785Smsmith#define A_CNF_MEDIA 0x0007 43437785Smsmith#define A_CNF_10B_T 0x0001 43537785Smsmith#define A_CNF_AUI 0x0002 43637785Smsmith#define A_CNF_10B_2 0x0004 43737785Smsmith#define A_CNF_MEDIA_TYPE 0x0060 43837785Smsmith#define A_CNF_MEDIA_AUTO 0x0000 43937785Smsmith#define A_CNF_MEDIA_10B_T 0x0020 44037785Smsmith#define A_CNF_MEDIA_AUI 0x0040 44137785Smsmith#define A_CNF_MEDIA_10B_2 0x0060 44237785Smsmith#define A_CNF_DC_DC_POLARITY 0x0080 44337785Smsmith#define A_CNF_NO_AUTO_POLARITY 0x2000 44437785Smsmith#define A_CNF_LOW_RX_SQUELCH 0x4000 44537785Smsmith#define A_CNF_EXTND_10B_2 0x8000 44637785Smsmith 44737785Smsmith#define PACKET_PAGE_OFFSET 0x8 44837785Smsmith 44937785Smsmith/* 45037785Smsmith * Bit definitions for the ISA configuration word from the EEPROM 45137785Smsmith */ 45237785Smsmith#define INT_NO_MASK 0x000F 45337785Smsmith#define DMA_NO_MASK 0x0070 45437785Smsmith#define ISA_DMA_SIZE 0x0200 45537785Smsmith#define ISA_AUTO_RxDMA 0x0400 45637785Smsmith#define ISA_RxDMA 0x0800 45737785Smsmith#define DMA_BURST 0x1000 45837785Smsmith#define STREAM_TRANSFER 0x2000 45937785Smsmith#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) 46037785Smsmith 46137785Smsmith/* DMA controller registers */ 46237785Smsmith#define DMA_BASE 0x00 /* DMA controller base */ 46337785Smsmith#define DMA_BASE_2 0x0C0 /* DMA controller base */ 46437785Smsmith 46537785Smsmith#define DMA_STAT 0x0D0 /* DMA controller status register */ 46637785Smsmith#define DMA_MASK 0x0D4 /* DMA controller mask register */ 46737785Smsmith#define DMA_MODE 0x0D6 /* DMA controller mode register */ 46837785Smsmith#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ 46937785Smsmith 47037785Smsmith/* DMA data */ 47137785Smsmith#define DMA_DISABLE 0x04 /* Disable channel n */ 47237785Smsmith#define DMA_ENABLE 0x00 /* Enable channel n */ 47337785Smsmith/* Demand transfers, incr. address, auto init, writes, ch. n */ 47437785Smsmith#define DMA_RX_MODE 0x14 47537785Smsmith/* Demand transfers, incr. address, auto init, reads, ch. n */ 47637785Smsmith#define DMA_TX_MODE 0x18 47737785Smsmith 47837785Smsmith#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ 47937785Smsmith 48037785Smsmith#define CS8900 0x0000 48137785Smsmith#define CS8920 0x4000 48237785Smsmith#define CS8920M 0x6000 48337785Smsmith#define REVISON_BITS 0x1F00 48437785Smsmith#define EEVER_NUMBER 0x12 48537785Smsmith#define CHKSUM_LEN 0x14 48637785Smsmith#define CHKSUM_VAL 0x0000 48737785Smsmith#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ 48837785Smsmith#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ 48937785Smsmith#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ 49037785Smsmith#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ 49137785Smsmith#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ 49237785Smsmith 49337785Smsmith#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ 49437785Smsmith 49537785Smsmith#define PNP_ADD_PORT 0x0279 49637785Smsmith#define PNP_WRITE_PORT 0x0A79 49737785Smsmith 49837785Smsmith#define GET_PNP_ISA_STRUCT 0x40 49937785Smsmith#define PNP_ISA_STRUCT_LEN 0x06 50037785Smsmith#define PNP_CSN_CNT_OFF 0x01 50137785Smsmith#define PNP_RD_PORT_OFF 0x02 50237785Smsmith#define PNP_FUNCTION_OK 0x00 50337785Smsmith#define PNP_WAKE 0x03 50437785Smsmith#define PNP_RSRC_DATA 0x04 50537785Smsmith#define PNP_RSRC_READY 0x01 50637785Smsmith#define PNP_STATUS 0x05 50737785Smsmith#define PNP_ACTIVATE 0x30 50837785Smsmith#define PNP_CNF_IO_H 0x60 50937785Smsmith#define PNP_CNF_IO_L 0x61 51037785Smsmith#define PNP_CNF_INT 0x70 51137785Smsmith#define PNP_CNF_DMA 0x74 51237785Smsmith#define PNP_CNF_MEM 0x48 51337785Smsmith 51437785Smsmith#define BIT0 1 51537785Smsmith#define BIT15 0x8000 51637785Smsmith 51737785Smsmith#define CS_DUPLEX_AUTO 0 51837785Smsmith#define CS_DUPLEX_FULL 1 51937785Smsmith#define CS_DUPLEX_HALF 2 52037785Smsmith 52137785Smsmith/* Device name */ 52237785Smsmith#define CS_NAME "cs" 52337785Smsmith 52437785Smsmith#define cs_readreg(iobase, portno) \ 52537785Smsmith (outw((iobase) + ADD_PORT, (portno)), \ 52637785Smsmith inw((iobase) + DATA_PORT)) 52737785Smsmith#define cs_writereg(iobase, portno, value) \ 52837785Smsmith (outw((iobase) + ADD_PORT, (portno)), \ 52937785Smsmith outw((iobase) + DATA_PORT, (value))) 53037785Smsmith#define cs_readword(iobase, portno) \ 53137785Smsmith (inw((iobase) + (portno))) 53237785Smsmith#define cs_writeword(iobase, portno, value) \ 53337785Smsmith (outw((iobase) + (portno), (value))) 53437785Smsmith 53537785Smsmith#define reset_chip(nic_addr) \ 53637785Smsmith cs_writereg(nic_addr, PP_SelfCTL, cs_readreg(ioaddr, PP_SelfCTL) | POWER_ON_RESET), \ 53737785Smsmith DELAY(30000) 53837785Smsmith 53937785Smsmith#define cs_duplex_full(sc) \ 54037785Smsmith (cs_writereg(sc->nic_addr, PP_AutoNegCTL, FORCE_FDX)) 54137785Smsmith 54237785Smsmith#define cs_duplex_half(sc) \ 54337785Smsmith (cs_writereg(sc->nic_addr, PP_AutoNegCTL, NLP_ENABLE)) 54437785Smsmith 545