1/*- 2 * Cronyx Tau-PCI DDK definitions. 3 * 4 * Copyright (C) 1999-2003 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * Copyright (C) 2000-2004 Cronyx Engineering. 8 * Author: Roman Kurakin, <rik@cronyx.ru> 9 * 10 * This software is distributed with NO WARRANTIES, not even the implied 11 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 * 13 * Authors grant any other persons or organisations a permission to use, 14 * modify and redistribute this software in source and binary forms, 15 * as long as this message is kept with the software, all derivative 16 * works or modified versions. 17 * 18 * $Cronyx: cpddk.h,v 1.8.4.20 2004/12/06 16:21:06 rik Exp $ 19 * $FreeBSD$ 20 */ 21#define NBRD 6 /* the maximum number of installed boards */ 22#define NCHAN 4 /* the number of channels on the board */ 23#define NRBUF 64 /* the number of receive buffers per channel, 24 min 2 */ 25#define NTBUF 4 /* the number of transmit buffers per channel */ 26#define BUFSZ 1664 /* i/o buffer size (26*64, min 1601) */ 27#define QSZ 128 /* intr queue size (multiple of 32, min 32) */ 28 29#ifndef CPDDK_COBF_SAFE 30#pragma pack(4) 31 32typedef struct { 33 unsigned long bpv; /* bipolar violations */ 34 unsigned long fse; /* frame sync errors */ 35 unsigned long crce; /* CRC errors */ 36 unsigned long rcrce; /* remote CRC errors (E-bit) */ 37 unsigned long uas; /* unavailable seconds */ 38 unsigned long les; /* line errored seconds */ 39 unsigned long es; /* errored seconds */ 40 unsigned long bes; /* bursty errored seconds */ 41 unsigned long ses; /* severely errored seconds */ 42 unsigned long oofs; /* out of frame seconds */ 43 unsigned long css; /* controlled slip seconds */ 44 unsigned long dm; /* degraded minutes */ 45} cp_gstat_t; 46 47typedef struct { /* cross-connector parameters */ 48 unsigned char ts [32]; /* timeslot number */ 49 unsigned char link [32]; /* E1 link number */ 50} cp_dxc_t; 51 52typedef struct { 53 unsigned long len; /* data buffer length, fe, hold, hi */ 54#define DESC_FE 0x80000000 55#define DESC_HOLD 0x40000000 56#define DESC_HI 0x20000000 57#define DESC_LEN(v) ((v) >> 16 & 0x1fff) 58 59 unsigned long next; /* next descriptor pointer */ 60 unsigned long data; /* pointer to data buffer */ 61 unsigned long status; /* complete, receive abort, fe, len */ 62#define DESC_RA 0x00000200 63#define DESC_C 0x40000000 64 65 unsigned long fe; /* pointer to frame end descriptor */ 66} cp_desc_t; 67 68typedef struct { 69 cp_desc_t tdesc [NTBUF]; /* transmit buffer descriptors */ 70 cp_desc_t rdesc [NRBUF]; /* receive buffer descriptors */ 71 unsigned char tbuffer [NTBUF] [BUFSZ]; /* transmit buffers */ 72 unsigned char rbuffer [NRBUF] [BUFSZ]; /* receive buffers */ 73} cp_buf_t; 74 75typedef struct { 76 unsigned long iqrx [NCHAN] [QSZ]; /* rx intr queue */ 77 unsigned long iqtx [NCHAN] [QSZ]; /* tx intr queue */ 78 unsigned long iqlx [QSZ]; /* LBI intr queue */ 79} cp_qbuf_t; 80 81typedef struct _cp_chan_t { 82 unsigned char *regs; /* base addr of channel registers */ 83 volatile unsigned long *RXBAR, *TXBAR, *CFG; 84 volatile unsigned long *BRDA, *FRDA, *LRDA, *BTDA, *FTDA, *LTDA; 85 unsigned char CCR, CSR, GMD, GLS, E1CS, E1CR, E1EPS; 86 87 unsigned char num; /* channel number, 0..1 */ 88 unsigned char type; /* channel type */ 89#define T_NONE 0 /* no channel */ 90#define T_SERIAL 1 /* V.35/RS */ 91#define T_G703 2 /* G.703 */ 92#define T_E1 3 /* E1 */ 93#define T_E3 4 /* E3 */ 94#define T_HSSI 5 /* HSSI */ 95#define T_DATA 6 /* no physical interface */ 96#define T_T3 7 /* T3 */ 97#define T_STS1 8 /* STS1 */ 98 99 struct _cp_board_t *board; /* board pointer */ 100 101 unsigned char dtr; /* DTR signal value */ 102 unsigned char rts; /* RTS signal value */ 103 unsigned long baud; /* data rate, bps */ 104 unsigned char dpll; /* dpll mode */ 105 unsigned char nrzi; /* nrzi mode */ 106 unsigned char invtxc; /* invert tx clock */ 107 unsigned char invrxc; /* invert rx clock */ 108 unsigned char lloop; /* local loopback mode */ 109 unsigned char rloop; /* remote loopback mode */ 110 unsigned char gsyn; /* G.703 clock mode */ 111#define GSYN_INT 0 /* internal transmit clock source */ 112#define GSYN_RCV 1 /* transmit clock source = receive */ 113#define GSYN_RCV0 2 /* tclk = rclk from channel 0 */ 114#define GSYN_RCV1 3 /* ...from channel 1 */ 115#define GSYN_RCV2 4 /* ...from channel 2 */ 116#define GSYN_RCV3 5 /* ...from channel 3 */ 117 118 unsigned char scrambler; /* G.703 scrambler enable */ 119 120 unsigned long ts; /* E1 timeslot mask */ 121 unsigned char higain; /* E1 high gain mode */ 122 unsigned char use16; /* E1 use ts 16 */ 123 unsigned char crc4; /* E1 enable CRC4 */ 124 unsigned char phony; /* E1 phony mode */ 125 unsigned char unfram; /* E1 unframed mode */ 126 unsigned char monitor; /* E1 monitoring mode */ 127 unsigned char dir; /* E1 direction mode */ 128 cp_dxc_t dxc; /* E1 cross-connect params */ 129 130 unsigned char ais; /* E3 AIS */ 131 unsigned char losais; /* E3 AIS on LOS*/ 132 unsigned char ber; /* E3 BER */ 133 unsigned char cablen; /* E3 cable length */ 134 unsigned char e3cr1; /* e3cr1 clone */ 135 136 unsigned char scc_ien; /* SCC Interrupts enabled */ 137 unsigned char ds_ien; /* DS Interrupts enabled */ 138 139 unsigned long imr; 140 unsigned char ccr; /* CCR image */ 141 unsigned long ccr0; /* CCR0 clone */ 142 unsigned long ccr1; /* CCR1 clone */ 143 unsigned long ccr2; /* CCR2 clone */ 144 unsigned char gmd; /* G.703 MDi register image */ 145 unsigned char e1cr; /* E1 CR register image */ 146 unsigned char ds21x54; /* new tranceiver flag */ 147 148 unsigned long rintr; /* receive interrupts */ 149 unsigned long tintr; /* transmit interrupts */ 150 ulong64 ibytes; /* input bytes */ 151 ulong64 obytes; /* output bytes */ 152 unsigned long ipkts; /* input packets */ 153 unsigned long opkts; /* output packets */ 154 unsigned long underrun; /* output underrun errors */ 155 unsigned long overrun; /* input overrun errors */ 156 unsigned long frame; /* input frame errors */ 157 unsigned long crc; /* input crc errors */ 158 159 unsigned short status; /* E1/G.703 line status bit mask */ 160#define ESTS_NOALARM 0x0001 /* no alarm present */ 161#define ESTS_FARLOF 0x0002 /* receiving far loss of framing */ 162#define ESTS_AIS 0x0008 /* receiving all ones */ 163#define ESTS_LOF 0x0020 /* loss of framing */ 164#define ESTS_LOS 0x0040 /* loss of signal */ 165#define ESTS_AIS16 0x0100 /* receiving all ones in timeslot 16 */ 166#define ESTS_FARLOMF 0x0200 /* receiving alarm in timeslot 16 */ 167#define ESTS_LOMF 0x0400 /* loss of multiframe sync */ 168#define ESTS_TSTREQ 0x0800 /* test code detected */ 169#define ESTS_TSTERR 0x1000 /* test error */ 170 171 unsigned long totsec; /* total seconds elapsed */ 172 unsigned long cursec; /* current seconds elapsed */ 173 unsigned long degsec; /* degraded seconds */ 174 unsigned long degerr; /* errors during degraded seconds */ 175 cp_gstat_t currnt; /* current 15-min interval data */ 176 cp_gstat_t total; /* total statistics data */ 177 cp_gstat_t interval [48]; /* 12 hour period data */ 178 unsigned long e3status; /* E3 status */ 179#define E3STS_LOS 0x00000002 /* Lost of synchronization */ 180#define E3STS_TXE 0x00000004 /* Transmit error */ 181#define E3STS_AIS 0x00000008 /* Transmit error */ 182 unsigned long e3csec_5; /* 1/5 of second counter */ 183 unsigned long e3tsec; /* total seconds coounter */ 184 unsigned long e3ccv; /* E3 current 15-min cv errors */ 185 unsigned long e3tcv; /* E3 total cv errors */ 186 unsigned long e3icv[48]; /* E3 12 hour period cv errors */ 187 188 unsigned long *iqrx; /* rx intr queue */ 189 unsigned long *iqtx; /* tx intr queue */ 190 int irn, itn; 191 192 unsigned char *tbuf [NTBUF]; /* transmit buffers */ 193 cp_desc_t *tdesc; /* transmit buffer descriptors */ 194 unsigned long tphys [NTBUF]; /* transmit buffer phys address */ 195 unsigned long tdphys [NTBUF]; /* transmit descr phys addresses */ 196 int tn; /* first active transmit buffer */ 197 int te; /* first empty transmit buffer */ 198 199 unsigned char *rbuf [NRBUF]; /* receive buffers */ 200 cp_desc_t *rdesc; /* receive buffer descriptors */ 201 unsigned long rphys [NRBUF]; /* receive buffer phys address */ 202 unsigned long rdphys [NRBUF]; /* receive descr phys addresses */ 203 int rn; /* first active receive buffer */ 204 205 void *tag [NTBUF]; /* system dependent data per buffer */ 206 void *sys; /* system dependent data per channel */ 207 unsigned char debug; /* debug level, 0..2 */ 208 unsigned char debug_shadow; /* debug shadow */ 209 210 void (*transmit) (struct _cp_chan_t *c, void *tag, int len); 211 void (*receive) (struct _cp_chan_t *c, unsigned char *data, int len); 212 void (*error) (struct _cp_chan_t *c, int reason); 213#define CP_FRAME 1 214#define CP_CRC 2 215#define CP_UNDERRUN 3 216#define CP_OVERRUN 4 217#define CP_OVERFLOW 5 218} cp_chan_t; 219 220typedef struct _cp_board_t { 221 unsigned char *base; /* base address of adapter registers */ 222 unsigned char num; /* board number, 0..5 */ 223 unsigned char type; /* board type Tau/TauE1/TauG703 */ 224#define B_TAUPCI 1 /* 2 channels V.35/RS */ 225#define B_TAUPCI_E3 2 /* 1 channel E3 */ 226#define B_TAUPCI_HSSI 3 /* 1 channel HSSI */ 227#define B_TAUPCI_G703 4 /* 2 channels G703 */ 228#define B_TAUPCI_E1 5 /* 2 channels E1 */ 229#define B_TAUPCI4 6 /* 4 channels V.35/RS */ 230#define B_TAUPCI4_G703 7 /* 2 channels G.703 + 2 channels V.35/RS */ 231#define B_TAUPCI4_4G703 8 /* 4 channels G.703 */ 232#define B_TAUPCI_2E1 9 /* 2 channels E1, 4 data ports */ 233#define B_TAUPCI4_E1 10 /* 2 channels E1 + 2 channels V.35/RS */ 234#define B_TAUPCI4_4E1 11 /* 4 channels E1 */ 235#define B_TAUPCI_L 12 /* 1 channel V.35/RS */ 236 237 unsigned long osc; /* oscillator frequency */ 238 char name[16]; /* board version name */ 239 cp_chan_t chan[NCHAN]; /* channel structures */ 240 unsigned char mux; /* E1 mux mode */ 241 unsigned char dxc_cas; /* CAS cross-connection */ 242 unsigned char bcr; /* BCR image */ 243 unsigned char e1cfg; /* E1 CFG register image */ 244 unsigned char gpidle; /* idle bits of gp port */ 245 unsigned char E1DATA; 246 unsigned long intr; /* interrupt counter */ 247 unsigned long *iqlx; /* LBI intr queue */ 248 int iln; 249 unsigned char fw_type; /* firmware type */ 250#define FW_TAUPCI_NONE 0 251#define FW_TAUPCI_E3_B 1 252#define FW_TAUPCI_2E1_B 2 253#define FW_TAUPCI_2E1_A 3 254#define FW_TAUPCI_4E1_B 6 255#define FW_TAUPCI_4E1_A 7 256 unsigned char *firmware[8]; /* external firmware */ 257 void *sys; 258} cp_board_t; 259 260#pragma pack() 261 262/* PCI device identifiers. */ 263extern unsigned short cp_vendor_id; 264extern unsigned short cp_device_id; 265 266/* Initialization. */ 267unsigned short cp_init (cp_board_t *b, int num, unsigned char *base); 268void cp_reset (cp_board_t *b, cp_qbuf_t *buf, unsigned long phys); 269void cp_hard_reset (cp_board_t *b); 270unsigned long cp_regio (cp_chan_t *c, int op, int reg, unsigned long val); 271#define REGIO_INB 0 272#define REGIO_IN 1 273#define REGIO_INS 2 274#define REGIO_INX 3 275#define REGIO_INB_OUTB 4 276#define REGIO_OUTB 5 277#define REGIO_OUTX 6 278#define REGIO_R_W 7 279#define REGIO_OUT_IN 8 280#define REGIO_OUTB_INB 9 281 282/* Callback registration. */ 283void cp_register_transmit (cp_chan_t *c, void (*func) (cp_chan_t*, void*, int)); 284void cp_register_receive (cp_chan_t *c, void (*func) (cp_chan_t*, 285 unsigned char*, int)); 286void cp_register_error (cp_chan_t *c, void (*func) (cp_chan_t*, int)); 287 288/* Data transmittion. */ 289void cp_start_chan (cp_chan_t *c, int tx, int rx, cp_buf_t *cb, unsigned long phys); 290void cp_stop_chan (cp_chan_t *c); 291void cp_start_e1 (cp_chan_t *c); 292void cp_stop_e1 (cp_chan_t *c); 293int cp_transmit_space (cp_chan_t *c); 294int cp_send_packet (cp_chan_t *c, unsigned char *data, int len, void *tag); 295 296/* Interrupt control. */ 297int cp_interrupt (cp_board_t *b); 298int cp_interrupt_poll (cp_board_t *b, int ack); 299void cp_handle_interrupt (cp_board_t *b); 300void cp_enable_interrupt (cp_board_t *b, int on); 301 302/* G.703 timer. */ 303void cp_g703_timer (cp_chan_t *c); 304 305/* E1 timer. */ 306void cp_e1_timer (cp_chan_t *c); 307 308/* E3 timer. */ 309void cp_e3_timer (cp_chan_t *c); 310 311/* LED control. */ 312void cp_led (cp_board_t *b, int on); 313 314/* Modem signals. */ 315void cp_set_dtr (cp_chan_t *c, int on); 316void cp_set_rts (cp_chan_t *c, int on); 317int cp_get_dsr (cp_chan_t *c); 318int cp_get_cd (cp_chan_t *c); 319int cp_get_cts (cp_chan_t *c); 320int cp_get_txcerr (cp_chan_t *c); 321int cp_get_rxcerr (cp_chan_t *c); 322 323/* HDLC parameters. */ 324void cp_set_baud (cp_chan_t *c, int baud); 325void cp_set_dpll (cp_chan_t *c, int on); 326void cp_set_nrzi (cp_chan_t *c, int on); 327void cp_set_invtxc (cp_chan_t *c, int on); 328void cp_set_invrxc (cp_chan_t *c, int on); 329void cp_set_lloop (cp_chan_t *c, int on); 330 331/* Channel status, cable type. */ 332int cp_get_rloop (cp_chan_t *c); 333int cp_get_lq (cp_chan_t *c); 334int cp_get_cable (cp_chan_t *c); 335#define CABLE_RS232 0 336#define CABLE_V35 1 337#define CABLE_RS530 2 338#define CABLE_X21 3 339#define CABLE_RS485 4 340#define CABLE_NOT_ATTACHED 9 341#define CABLE_COAX 10 342#define CABLE_TP 11 343 344/* E1/G.703 parameters. */ 345void cp_set_gsyn (cp_chan_t *c, int syn); 346void cp_set_ts (cp_chan_t *c, unsigned long ts); 347void cp_set_dir (cp_chan_t *c, int dir); 348void cp_set_mux (cp_board_t *b, int on); 349void cp_dxc_cas_enable (cp_board_t *b, int on); 350void cp_set_dxc (cp_chan_t *c, cp_dxc_t *param); 351void cp_set_higain (cp_chan_t *c, int on); 352void cp_set_use16 (cp_chan_t *c, int on); 353void cp_set_crc4 (cp_chan_t *c, int on); 354void cp_set_phony (cp_chan_t *c, int on); 355void cp_set_unfram (cp_chan_t *c, int on); 356void cp_set_scrambler (cp_chan_t *c, int on); 357void cp_set_monitor (cp_chan_t *c, int on); 358 359/* E3 parameters. */ 360void cp_set_rloop (cp_chan_t *c, int on); 361void cp_set_ber (cp_chan_t *c, int on); 362void cp_set_cablen (cp_chan_t *c, int on); 363void cp_set_losais (cp_chan_t *c, int on); 364 365#endif /* CPDDK_COBF_SAFE */ 366