if_cas.c revision 227843
1194246Smarius/*- 2194246Smarius * Copyright (C) 2001 Eduardo Horvath. 3194246Smarius * Copyright (c) 2001-2003 Thomas Moestl 4194246Smarius * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5194246Smarius * All rights reserved. 6194246Smarius * 7194246Smarius * Redistribution and use in source and binary forms, with or without 8194246Smarius * modification, are permitted provided that the following conditions 9194246Smarius * are met: 10194246Smarius * 1. Redistributions of source code must retain the above copyright 11194246Smarius * notice, this list of conditions and the following disclaimer. 12194246Smarius * 2. Redistributions in binary form must reproduce the above copyright 13194246Smarius * notice, this list of conditions and the following disclaimer in the 14194246Smarius * documentation and/or other materials provided with the distribution. 15194246Smarius * 16194246Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17194246Smarius * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18194246Smarius * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19194246Smarius * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20194246Smarius * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21194246Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22194246Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23194246Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24194246Smarius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25194246Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26194246Smarius * SUCH DAMAGE. 27194246Smarius * 28194246Smarius * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29194246Smarius * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30194246Smarius */ 31194246Smarius 32194246Smarius#include <sys/cdefs.h> 33194246Smarius__FBSDID("$FreeBSD: head/sys/dev/cas/if_cas.c 227843 2011-11-22 21:28:20Z marius $"); 34194246Smarius 35194246Smarius/* 36194246Smarius * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37194246Smarius * Saturn Gigabit Ethernet controllers 38194246Smarius */ 39194246Smarius 40194246Smarius#if 0 41194246Smarius#define CAS_DEBUG 42194246Smarius#endif 43194246Smarius 44194246Smarius#include <sys/param.h> 45194246Smarius#include <sys/systm.h> 46194246Smarius#include <sys/bus.h> 47194246Smarius#include <sys/callout.h> 48194246Smarius#include <sys/endian.h> 49194246Smarius#include <sys/mbuf.h> 50194246Smarius#include <sys/malloc.h> 51194246Smarius#include <sys/kernel.h> 52194246Smarius#include <sys/lock.h> 53194246Smarius#include <sys/module.h> 54194246Smarius#include <sys/mutex.h> 55194246Smarius#include <sys/refcount.h> 56194246Smarius#include <sys/resource.h> 57194246Smarius#include <sys/rman.h> 58194246Smarius#include <sys/socket.h> 59194246Smarius#include <sys/sockio.h> 60194904Smarius#include <sys/taskqueue.h> 61194246Smarius 62194246Smarius#include <net/bpf.h> 63194246Smarius#include <net/ethernet.h> 64194246Smarius#include <net/if.h> 65194246Smarius#include <net/if_arp.h> 66194246Smarius#include <net/if_dl.h> 67194246Smarius#include <net/if_media.h> 68194246Smarius#include <net/if_types.h> 69194246Smarius#include <net/if_vlan_var.h> 70194246Smarius 71194246Smarius#include <netinet/in.h> 72194246Smarius#include <netinet/in_systm.h> 73194246Smarius#include <netinet/ip.h> 74194246Smarius#include <netinet/tcp.h> 75194246Smarius#include <netinet/udp.h> 76194246Smarius 77194246Smarius#include <machine/bus.h> 78194246Smarius#if defined(__powerpc__) || defined(__sparc64__) 79207585Smarius#include <dev/ofw/ofw_bus.h> 80194246Smarius#include <dev/ofw/openfirm.h> 81194246Smarius#include <machine/ofw_machdep.h> 82194246Smarius#endif 83194246Smarius#include <machine/resource.h> 84194246Smarius 85194246Smarius#include <dev/mii/mii.h> 86194246Smarius#include <dev/mii/miivar.h> 87194246Smarius 88194246Smarius#include <dev/cas/if_casreg.h> 89194246Smarius#include <dev/cas/if_casvar.h> 90194246Smarius 91194246Smarius#include <dev/pci/pcireg.h> 92194246Smarius#include <dev/pci/pcivar.h> 93194246Smarius 94194246Smarius#include "miibus_if.h" 95194246Smarius 96194246Smarius#define RINGASSERT(n , min, max) \ 97194246Smarius CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 98194246Smarius 99194246SmariusRINGASSERT(CAS_NRXCOMP, 128, 32768); 100194246SmariusRINGASSERT(CAS_NRXDESC, 32, 8192); 101194246SmariusRINGASSERT(CAS_NRXDESC2, 32, 8192); 102194246SmariusRINGASSERT(CAS_NTXDESC, 32, 8192); 103194246Smarius 104194246Smarius#undef RINGASSERT 105194246Smarius 106194246Smarius#define CCDASSERT(m, a) \ 107194246Smarius CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 108194246Smarius 109194246SmariusCCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 110194246SmariusCCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 111194246SmariusCCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 112194246Smarius 113194246Smarius#undef CCDASSERT 114194246Smarius 115194246Smarius#define CAS_TRIES 10000 116194246Smarius 117194246Smarius/* 118194246Smarius * According to documentation, the hardware has support for basic TCP 119194246Smarius * checksum offloading only, in practice this can be also used for UDP 120194246Smarius * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 121194246Smarius * is not converted to 0xffff no longer exists). 122194246Smarius */ 123194246Smarius#define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 124194246Smarius 125194246Smariusstatic inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 126194246Smariusstatic int cas_attach(struct cas_softc *sc); 127194246Smariusstatic int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 128194246Smarius uint32_t set); 129194246Smariusstatic void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 130194246Smarius int nsegs, int error); 131194246Smariusstatic void cas_detach(struct cas_softc *sc); 132194246Smariusstatic int cas_disable_rx(struct cas_softc *sc); 133194246Smariusstatic int cas_disable_tx(struct cas_softc *sc); 134194246Smariusstatic void cas_eint(struct cas_softc *sc, u_int status); 135194246Smariusstatic void cas_free(void *arg1, void* arg2); 136194246Smariusstatic void cas_init(void *xsc); 137194246Smariusstatic void cas_init_locked(struct cas_softc *sc); 138194246Smariusstatic void cas_init_regs(struct cas_softc *sc); 139194904Smariusstatic int cas_intr(void *v); 140194904Smariusstatic void cas_intr_task(void *arg, int pending __unused); 141194246Smariusstatic int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142194246Smariusstatic int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 143194246Smariusstatic int cas_mediachange(struct ifnet *ifp); 144194246Smariusstatic void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 145194246Smariusstatic void cas_meminit(struct cas_softc *sc); 146194246Smariusstatic void cas_mifinit(struct cas_softc *sc); 147194246Smariusstatic int cas_mii_readreg(device_t dev, int phy, int reg); 148194246Smariusstatic void cas_mii_statchg(device_t dev); 149194246Smariusstatic int cas_mii_writereg(device_t dev, int phy, int reg, int val); 150194246Smariusstatic void cas_reset(struct cas_softc *sc); 151194246Smariusstatic int cas_reset_rx(struct cas_softc *sc); 152194246Smariusstatic int cas_reset_tx(struct cas_softc *sc); 153194246Smariusstatic void cas_resume(struct cas_softc *sc); 154194246Smariusstatic u_int cas_descsize(u_int sz); 155194246Smariusstatic void cas_rint(struct cas_softc *sc); 156194246Smariusstatic void cas_rint_timeout(void *arg); 157194246Smariusstatic inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 158194246Smariusstatic inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 159194246Smariusstatic u_int cas_rxcompsize(u_int sz); 160194246Smariusstatic void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 161194246Smarius int nsegs, int error); 162194246Smariusstatic void cas_setladrf(struct cas_softc *sc); 163194246Smariusstatic void cas_start(struct ifnet *ifp); 164194246Smariusstatic void cas_stop(struct ifnet *ifp); 165194246Smariusstatic void cas_suspend(struct cas_softc *sc); 166194246Smariusstatic void cas_tick(void *arg); 167194246Smariusstatic void cas_tint(struct cas_softc *sc); 168194904Smariusstatic void cas_tx_task(void *arg, int pending __unused); 169194246Smariusstatic inline void cas_txkick(struct cas_softc *sc); 170194904Smariusstatic void cas_watchdog(struct cas_softc *sc); 171194246Smarius 172194246Smariusstatic devclass_t cas_devclass; 173194246Smarius 174194246SmariusMODULE_DEPEND(cas, ether, 1, 1, 1); 175194246SmariusMODULE_DEPEND(cas, miibus, 1, 1, 1); 176194246Smarius 177194246Smarius#ifdef CAS_DEBUG 178194246Smarius#include <sys/ktr.h> 179210334Sattilio#define KTR_CAS KTR_SPARE2 180194246Smarius#endif 181194246Smarius 182194246Smariusstatic int 183194246Smariuscas_attach(struct cas_softc *sc) 184194246Smarius{ 185194246Smarius struct cas_txsoft *txs; 186194246Smarius struct ifnet *ifp; 187194246Smarius int error, i; 188194246Smarius uint32_t v; 189194246Smarius 190194246Smarius /* Set up ifnet structure. */ 191194246Smarius ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 192194246Smarius if (ifp == NULL) 193194246Smarius return (ENOSPC); 194194246Smarius ifp->if_softc = sc; 195194246Smarius if_initname(ifp, device_get_name(sc->sc_dev), 196194246Smarius device_get_unit(sc->sc_dev)); 197194246Smarius ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 198194246Smarius ifp->if_start = cas_start; 199194246Smarius ifp->if_ioctl = cas_ioctl; 200194246Smarius ifp->if_init = cas_init; 201194246Smarius IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 202194246Smarius ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 203194246Smarius IFQ_SET_READY(&ifp->if_snd); 204194246Smarius 205194246Smarius callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 206223986Smarius callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 207194904Smarius /* Create local taskq. */ 208194904Smarius TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 209194904Smarius TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 210194904Smarius sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 211194904Smarius taskqueue_thread_enqueue, &sc->sc_tq); 212194904Smarius if (sc->sc_tq == NULL) { 213194904Smarius device_printf(sc->sc_dev, "could not create taskqueue\n"); 214194904Smarius error = ENXIO; 215194904Smarius goto fail_ifnet; 216194904Smarius } 217194904Smarius taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 218194904Smarius device_get_nameunit(sc->sc_dev)); 219194246Smarius 220194246Smarius /* Make sure the chip is stopped. */ 221194246Smarius cas_reset(sc); 222194246Smarius 223194246Smarius error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 224194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 225194246Smarius BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 226194246Smarius &sc->sc_pdmatag); 227194246Smarius if (error != 0) 228194904Smarius goto fail_taskq; 229194246Smarius 230194246Smarius error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 231194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 232194246Smarius CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 233194246Smarius if (error != 0) 234194246Smarius goto fail_ptag; 235194246Smarius 236194246Smarius error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 237194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 238194246Smarius MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 239194246Smarius BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 240194246Smarius if (error != 0) 241194246Smarius goto fail_rtag; 242194246Smarius 243194246Smarius error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 244194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 245194246Smarius sizeof(struct cas_control_data), 1, 246194246Smarius sizeof(struct cas_control_data), 0, 247194246Smarius NULL, NULL, &sc->sc_cdmatag); 248194246Smarius if (error != 0) 249194246Smarius goto fail_ttag; 250194246Smarius 251194246Smarius /* 252194246Smarius * Allocate the control data structures, create and load the 253194246Smarius * DMA map for it. 254194246Smarius */ 255194246Smarius if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 256194246Smarius (void **)&sc->sc_control_data, 257194246Smarius BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 258194246Smarius &sc->sc_cddmamap)) != 0) { 259194246Smarius device_printf(sc->sc_dev, 260194246Smarius "unable to allocate control data, error = %d\n", error); 261194246Smarius goto fail_ctag; 262194246Smarius } 263194246Smarius 264194246Smarius sc->sc_cddma = 0; 265194246Smarius if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 266194246Smarius sc->sc_control_data, sizeof(struct cas_control_data), 267194246Smarius cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 268194246Smarius device_printf(sc->sc_dev, 269194246Smarius "unable to load control data DMA map, error = %d\n", 270194246Smarius error); 271194246Smarius goto fail_cmem; 272194246Smarius } 273194246Smarius 274194246Smarius /* 275194246Smarius * Initialize the transmit job descriptors. 276194246Smarius */ 277194246Smarius STAILQ_INIT(&sc->sc_txfreeq); 278194246Smarius STAILQ_INIT(&sc->sc_txdirtyq); 279194246Smarius 280194246Smarius /* 281194246Smarius * Create the transmit buffer DMA maps. 282194246Smarius */ 283194246Smarius error = ENOMEM; 284194246Smarius for (i = 0; i < CAS_TXQUEUELEN; i++) { 285194246Smarius txs = &sc->sc_txsoft[i]; 286194246Smarius txs->txs_mbuf = NULL; 287194246Smarius txs->txs_ndescs = 0; 288194246Smarius if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 289194246Smarius &txs->txs_dmamap)) != 0) { 290194246Smarius device_printf(sc->sc_dev, 291194246Smarius "unable to create TX DMA map %d, error = %d\n", 292194246Smarius i, error); 293194246Smarius goto fail_txd; 294194246Smarius } 295194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 296194246Smarius } 297194246Smarius 298194246Smarius /* 299194246Smarius * Allocate the receive buffers, create and load the DMA maps 300194246Smarius * for them. 301194246Smarius */ 302194246Smarius for (i = 0; i < CAS_NRXDESC; i++) { 303194246Smarius if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 304194246Smarius &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 305194246Smarius &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 306194246Smarius device_printf(sc->sc_dev, 307194246Smarius "unable to allocate RX buffer %d, error = %d\n", 308194246Smarius i, error); 309194246Smarius goto fail_rxmem; 310194246Smarius } 311194246Smarius 312194246Smarius sc->sc_rxdptr = i; 313194246Smarius sc->sc_rxdsoft[i].rxds_paddr = 0; 314194246Smarius if ((error = bus_dmamap_load(sc->sc_rdmatag, 315194246Smarius sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 316194246Smarius CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 317194246Smarius sc->sc_rxdsoft[i].rxds_paddr == 0) { 318194246Smarius device_printf(sc->sc_dev, 319194246Smarius "unable to load RX DMA map %d, error = %d\n", 320194246Smarius i, error); 321194246Smarius goto fail_rxmap; 322194246Smarius } 323194246Smarius } 324194246Smarius 325207585Smarius if ((sc->sc_flags & CAS_SERDES) == 0) { 326207585Smarius CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 327207585Smarius CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 328207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 329207585Smarius cas_mifinit(sc); 330207585Smarius /* 331207585Smarius * Look for an external PHY. 332207585Smarius */ 333207585Smarius error = ENXIO; 334207585Smarius v = CAS_READ_4(sc, CAS_MIF_CONF); 335207585Smarius if ((v & CAS_MIF_CONF_MDI1) != 0) { 336207585Smarius v |= CAS_MIF_CONF_PHY_SELECT; 337207585Smarius CAS_WRITE_4(sc, CAS_MIF_CONF, v); 338207585Smarius CAS_BARRIER(sc, CAS_MIF_CONF, 4, 339207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 340207585Smarius /* Enable/unfreeze the GMII pins of Saturn. */ 341207585Smarius if (sc->sc_variant == CAS_SATURN) { 342207585Smarius CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 343207585Smarius CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 344207585Smarius BUS_SPACE_BARRIER_READ | 345207585Smarius BUS_SPACE_BARRIER_WRITE); 346207585Smarius } 347213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 348213893Smarius cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 349215721Smarius MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 350194246Smarius } 351207585Smarius /* 352207585Smarius * Fall back on an internal PHY if no external PHY was found. 353207585Smarius */ 354207585Smarius if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 355207585Smarius v &= ~CAS_MIF_CONF_PHY_SELECT; 356207585Smarius CAS_WRITE_4(sc, CAS_MIF_CONF, v); 357207585Smarius CAS_BARRIER(sc, CAS_MIF_CONF, 4, 358207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 359207585Smarius /* Freeze the GMII pins of Saturn for saving power. */ 360207585Smarius if (sc->sc_variant == CAS_SATURN) { 361207585Smarius CAS_WRITE_4(sc, CAS_SATURN_PCFG, 362207585Smarius CAS_SATURN_PCFG_FSI); 363207585Smarius CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 364207585Smarius BUS_SPACE_BARRIER_READ | 365207585Smarius BUS_SPACE_BARRIER_WRITE); 366207585Smarius } 367213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 368213893Smarius cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 369215721Smarius MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 370194246Smarius } 371207585Smarius } else { 372207585Smarius /* 373207585Smarius * Use the external PCS SERDES. 374207585Smarius */ 375194246Smarius CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 376207585Smarius CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 377207585Smarius /* Enable/unfreeze the SERDES pins of Saturn. */ 378207585Smarius if (sc->sc_variant == CAS_SATURN) { 379207585Smarius CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 380207585Smarius CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 381207585Smarius BUS_SPACE_BARRIER_WRITE); 382207585Smarius } 383194246Smarius CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 384207585Smarius CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 385207585Smarius BUS_SPACE_BARRIER_WRITE); 386207585Smarius CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 387207585Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 388207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 389213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 390213893Smarius cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 391215721Smarius CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 392194246Smarius } 393194246Smarius if (error != 0) { 394213893Smarius device_printf(sc->sc_dev, "attaching PHYs failed\n"); 395194246Smarius goto fail_rxmap; 396194246Smarius } 397194246Smarius sc->sc_mii = device_get_softc(sc->sc_miibus); 398194246Smarius 399194246Smarius /* 400194246Smarius * From this point forward, the attachment cannot fail. A failure 401194246Smarius * before this point releases all resources that may have been 402194246Smarius * allocated. 403194246Smarius */ 404194246Smarius 405194246Smarius /* Announce FIFO sizes. */ 406194246Smarius v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 407194246Smarius device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 408194246Smarius CAS_RX_FIFO_SIZE / 1024, v / 16); 409194246Smarius 410194246Smarius /* Attach the interface. */ 411194246Smarius ether_ifattach(ifp, sc->sc_enaddr); 412194246Smarius 413194246Smarius /* 414194246Smarius * Tell the upper layer(s) we support long frames/checksum offloads. 415194246Smarius */ 416194246Smarius ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 417194246Smarius ifp->if_capabilities = IFCAP_VLAN_MTU; 418194246Smarius if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 419194246Smarius ifp->if_capabilities |= IFCAP_HWCSUM; 420194246Smarius ifp->if_hwassist = CAS_CSUM_FEATURES; 421194246Smarius } 422194246Smarius ifp->if_capenable = ifp->if_capabilities; 423194246Smarius 424194246Smarius return (0); 425194246Smarius 426194246Smarius /* 427194246Smarius * Free any resources we've allocated during the failed attach 428194246Smarius * attempt. Do this in reverse order and fall through. 429194246Smarius */ 430194246Smarius fail_rxmap: 431194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 432194246Smarius if (sc->sc_rxdsoft[i].rxds_paddr != 0) 433194246Smarius bus_dmamap_unload(sc->sc_rdmatag, 434194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 435194246Smarius fail_rxmem: 436194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 437194246Smarius if (sc->sc_rxdsoft[i].rxds_buf != NULL) 438194246Smarius bus_dmamem_free(sc->sc_rdmatag, 439194246Smarius sc->sc_rxdsoft[i].rxds_buf, 440194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 441194246Smarius fail_txd: 442194246Smarius for (i = 0; i < CAS_TXQUEUELEN; i++) 443194246Smarius if (sc->sc_txsoft[i].txs_dmamap != NULL) 444194246Smarius bus_dmamap_destroy(sc->sc_tdmatag, 445194246Smarius sc->sc_txsoft[i].txs_dmamap); 446194246Smarius bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 447194246Smarius fail_cmem: 448194246Smarius bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 449194246Smarius sc->sc_cddmamap); 450194246Smarius fail_ctag: 451194246Smarius bus_dma_tag_destroy(sc->sc_cdmatag); 452194246Smarius fail_ttag: 453194246Smarius bus_dma_tag_destroy(sc->sc_tdmatag); 454194246Smarius fail_rtag: 455194246Smarius bus_dma_tag_destroy(sc->sc_rdmatag); 456194246Smarius fail_ptag: 457194246Smarius bus_dma_tag_destroy(sc->sc_pdmatag); 458194904Smarius fail_taskq: 459194904Smarius taskqueue_free(sc->sc_tq); 460194246Smarius fail_ifnet: 461194246Smarius if_free(ifp); 462194246Smarius return (error); 463194246Smarius} 464194246Smarius 465194246Smariusstatic void 466194246Smariuscas_detach(struct cas_softc *sc) 467194246Smarius{ 468194246Smarius struct ifnet *ifp = sc->sc_ifp; 469194246Smarius int i; 470194246Smarius 471194904Smarius ether_ifdetach(ifp); 472194246Smarius CAS_LOCK(sc); 473194246Smarius cas_stop(ifp); 474194246Smarius CAS_UNLOCK(sc); 475194246Smarius callout_drain(&sc->sc_tick_ch); 476194246Smarius callout_drain(&sc->sc_rx_ch); 477194904Smarius taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 478194904Smarius taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 479194246Smarius if_free(ifp); 480194904Smarius taskqueue_free(sc->sc_tq); 481194246Smarius device_delete_child(sc->sc_dev, sc->sc_miibus); 482194246Smarius 483194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 484194246Smarius if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 485194246Smarius bus_dmamap_sync(sc->sc_rdmatag, 486194246Smarius sc->sc_rxdsoft[i].rxds_dmamap, 487194246Smarius BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 488194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 489194246Smarius if (sc->sc_rxdsoft[i].rxds_paddr != 0) 490194246Smarius bus_dmamap_unload(sc->sc_rdmatag, 491194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 492194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 493194246Smarius if (sc->sc_rxdsoft[i].rxds_buf != NULL) 494194246Smarius bus_dmamem_free(sc->sc_rdmatag, 495194246Smarius sc->sc_rxdsoft[i].rxds_buf, 496194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 497194246Smarius for (i = 0; i < CAS_TXQUEUELEN; i++) 498194246Smarius if (sc->sc_txsoft[i].txs_dmamap != NULL) 499194246Smarius bus_dmamap_destroy(sc->sc_tdmatag, 500194246Smarius sc->sc_txsoft[i].txs_dmamap); 501194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 502194246Smarius bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 503194246Smarius bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 504194246Smarius sc->sc_cddmamap); 505194246Smarius bus_dma_tag_destroy(sc->sc_cdmatag); 506194246Smarius bus_dma_tag_destroy(sc->sc_tdmatag); 507194246Smarius bus_dma_tag_destroy(sc->sc_rdmatag); 508194246Smarius bus_dma_tag_destroy(sc->sc_pdmatag); 509194246Smarius} 510194246Smarius 511194246Smariusstatic void 512194246Smariuscas_suspend(struct cas_softc *sc) 513194246Smarius{ 514194246Smarius struct ifnet *ifp = sc->sc_ifp; 515194246Smarius 516194246Smarius CAS_LOCK(sc); 517194246Smarius cas_stop(ifp); 518194246Smarius CAS_UNLOCK(sc); 519194246Smarius} 520194246Smarius 521194246Smariusstatic void 522194246Smariuscas_resume(struct cas_softc *sc) 523194246Smarius{ 524194246Smarius struct ifnet *ifp = sc->sc_ifp; 525194246Smarius 526194246Smarius CAS_LOCK(sc); 527194246Smarius /* 528194246Smarius * On resume all registers have to be initialized again like 529194246Smarius * after power-on. 530194246Smarius */ 531194246Smarius sc->sc_flags &= ~CAS_INITED; 532194246Smarius if (ifp->if_flags & IFF_UP) 533194246Smarius cas_init_locked(sc); 534194246Smarius CAS_UNLOCK(sc); 535194246Smarius} 536194246Smarius 537194246Smariusstatic inline void 538194246Smariuscas_rxcksum(struct mbuf *m, uint16_t cksum) 539194246Smarius{ 540194246Smarius struct ether_header *eh; 541194246Smarius struct ip *ip; 542194246Smarius struct udphdr *uh; 543194246Smarius uint16_t *opts; 544194246Smarius int32_t hlen, len, pktlen; 545194246Smarius uint32_t temp32; 546194246Smarius 547194246Smarius pktlen = m->m_pkthdr.len; 548194246Smarius if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 549194246Smarius return; 550194246Smarius eh = mtod(m, struct ether_header *); 551194246Smarius if (eh->ether_type != htons(ETHERTYPE_IP)) 552194246Smarius return; 553194246Smarius ip = (struct ip *)(eh + 1); 554194246Smarius if (ip->ip_v != IPVERSION) 555194246Smarius return; 556194246Smarius 557194246Smarius hlen = ip->ip_hl << 2; 558194246Smarius pktlen -= sizeof(struct ether_header); 559194246Smarius if (hlen < sizeof(struct ip)) 560194246Smarius return; 561194246Smarius if (ntohs(ip->ip_len) < hlen) 562194246Smarius return; 563194246Smarius if (ntohs(ip->ip_len) != pktlen) 564194246Smarius return; 565194246Smarius if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 566194246Smarius return; /* Cannot handle fragmented packet. */ 567194246Smarius 568194246Smarius switch (ip->ip_p) { 569194246Smarius case IPPROTO_TCP: 570194246Smarius if (pktlen < (hlen + sizeof(struct tcphdr))) 571194246Smarius return; 572194246Smarius break; 573194246Smarius case IPPROTO_UDP: 574194246Smarius if (pktlen < (hlen + sizeof(struct udphdr))) 575194246Smarius return; 576194246Smarius uh = (struct udphdr *)((uint8_t *)ip + hlen); 577194246Smarius if (uh->uh_sum == 0) 578194246Smarius return; /* no checksum */ 579194246Smarius break; 580194246Smarius default: 581194246Smarius return; 582194246Smarius } 583194246Smarius 584194246Smarius cksum = ~cksum; 585194246Smarius /* checksum fixup for IP options */ 586194246Smarius len = hlen - sizeof(struct ip); 587194246Smarius if (len > 0) { 588194246Smarius opts = (uint16_t *)(ip + 1); 589194246Smarius for (; len > 0; len -= sizeof(uint16_t), opts++) { 590194246Smarius temp32 = cksum - *opts; 591194246Smarius temp32 = (temp32 >> 16) + (temp32 & 65535); 592194246Smarius cksum = temp32 & 65535; 593194246Smarius } 594194246Smarius } 595194246Smarius m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 596194246Smarius m->m_pkthdr.csum_data = cksum; 597194246Smarius} 598194246Smarius 599194246Smariusstatic void 600194246Smariuscas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 601194246Smarius{ 602194246Smarius struct cas_softc *sc = xsc; 603194246Smarius 604194246Smarius if (error != 0) 605194246Smarius return; 606194246Smarius if (nsegs != 1) 607194246Smarius panic("%s: bad control buffer segment count", __func__); 608194246Smarius sc->sc_cddma = segs[0].ds_addr; 609194246Smarius} 610194246Smarius 611194246Smariusstatic void 612194246Smariuscas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 613194246Smarius{ 614194246Smarius struct cas_softc *sc = xsc; 615194246Smarius 616194246Smarius if (error != 0) 617194246Smarius return; 618194246Smarius if (nsegs != 1) 619194246Smarius panic("%s: bad RX buffer segment count", __func__); 620194246Smarius sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 621194246Smarius} 622194246Smarius 623194246Smariusstatic void 624194246Smariuscas_tick(void *arg) 625194246Smarius{ 626194246Smarius struct cas_softc *sc = arg; 627194904Smarius struct ifnet *ifp = sc->sc_ifp; 628194246Smarius uint32_t v; 629194246Smarius 630194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 631194246Smarius 632194246Smarius /* 633194246Smarius * Unload collision and error counters. 634194246Smarius */ 635194246Smarius ifp->if_collisions += 636194246Smarius CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 637194246Smarius CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT); 638194246Smarius v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 639194246Smarius CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 640194246Smarius ifp->if_collisions += v; 641194246Smarius ifp->if_oerrors += v; 642194246Smarius ifp->if_ierrors += 643194246Smarius CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 644194246Smarius CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 645194246Smarius CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 646194246Smarius CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL); 647194246Smarius 648194246Smarius /* 649194246Smarius * Then clear the hardware counters. 650194246Smarius */ 651194246Smarius CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 652194246Smarius CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 653194246Smarius CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 654194246Smarius CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 655194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 656194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 657194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 658194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 659194246Smarius 660194246Smarius mii_tick(sc->sc_mii); 661194246Smarius 662194904Smarius if (sc->sc_txfree != CAS_MAXTXFREE) 663194904Smarius cas_tint(sc); 664194246Smarius 665194904Smarius cas_watchdog(sc); 666194904Smarius 667194246Smarius callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 668194246Smarius} 669194246Smarius 670194246Smariusstatic int 671194246Smariuscas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 672194246Smarius{ 673194246Smarius int i; 674194246Smarius uint32_t reg; 675194246Smarius 676194246Smarius for (i = CAS_TRIES; i--; DELAY(100)) { 677194246Smarius reg = CAS_READ_4(sc, r); 678194246Smarius if ((reg & clr) == 0 && (reg & set) == set) 679194246Smarius return (1); 680194246Smarius } 681194246Smarius return (0); 682194246Smarius} 683194246Smarius 684194246Smariusstatic void 685194246Smariuscas_reset(struct cas_softc *sc) 686194246Smarius{ 687194246Smarius 688194246Smarius#ifdef CAS_DEBUG 689194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 690194246Smarius#endif 691194246Smarius /* Disable all interrupts in order to avoid spurious ones. */ 692194246Smarius CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 693194246Smarius 694194246Smarius cas_reset_rx(sc); 695194246Smarius cas_reset_tx(sc); 696194246Smarius 697194246Smarius /* 698194246Smarius * Do a full reset modulo the result of the last auto-negotiation 699194246Smarius * when using the SERDES. 700194246Smarius */ 701194246Smarius CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 702194246Smarius ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 703194246Smarius CAS_BARRIER(sc, CAS_RESET, 4, 704194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 705194246Smarius DELAY(3000); 706194246Smarius if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 707194246Smarius device_printf(sc->sc_dev, "cannot reset device\n"); 708194246Smarius} 709194246Smarius 710194246Smariusstatic void 711194246Smariuscas_stop(struct ifnet *ifp) 712194246Smarius{ 713194246Smarius struct cas_softc *sc = ifp->if_softc; 714194246Smarius struct cas_txsoft *txs; 715194246Smarius 716194246Smarius#ifdef CAS_DEBUG 717194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 718194246Smarius#endif 719194246Smarius 720194246Smarius callout_stop(&sc->sc_tick_ch); 721194246Smarius callout_stop(&sc->sc_rx_ch); 722194246Smarius 723194246Smarius /* Disable all interrupts in order to avoid spurious ones. */ 724194246Smarius CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 725194246Smarius 726194246Smarius cas_reset_tx(sc); 727194246Smarius cas_reset_rx(sc); 728194246Smarius 729194246Smarius /* 730194246Smarius * Release any queued transmit buffers. 731194246Smarius */ 732194246Smarius while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 733194246Smarius STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 734194246Smarius if (txs->txs_ndescs != 0) { 735194246Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 736194246Smarius BUS_DMASYNC_POSTWRITE); 737194246Smarius bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 738194246Smarius if (txs->txs_mbuf != NULL) { 739194246Smarius m_freem(txs->txs_mbuf); 740194246Smarius txs->txs_mbuf = NULL; 741194246Smarius } 742194246Smarius } 743194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 744194246Smarius } 745194246Smarius 746194246Smarius /* 747194246Smarius * Mark the interface down and cancel the watchdog timer. 748194246Smarius */ 749194246Smarius ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 750194246Smarius sc->sc_flags &= ~CAS_LINK; 751194246Smarius sc->sc_wdog_timer = 0; 752194246Smarius} 753194246Smarius 754194246Smariusstatic int 755194246Smariuscas_reset_rx(struct cas_softc *sc) 756194246Smarius{ 757194246Smarius 758194246Smarius /* 759194246Smarius * Resetting while DMA is in progress can cause a bus hang, so we 760194246Smarius * disable DMA first. 761194246Smarius */ 762223951Smarius (void)cas_disable_rx(sc); 763194246Smarius CAS_WRITE_4(sc, CAS_RX_CONF, 0); 764194246Smarius CAS_BARRIER(sc, CAS_RX_CONF, 4, 765194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 766194246Smarius if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 767194246Smarius device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 768194246Smarius 769194246Smarius /* Finally, reset the ERX. */ 770194246Smarius CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 771194246Smarius ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 772194246Smarius CAS_BARRIER(sc, CAS_RESET, 4, 773194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 774223951Smarius if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 775194246Smarius device_printf(sc->sc_dev, "cannot reset receiver\n"); 776194246Smarius return (1); 777194246Smarius } 778194246Smarius return (0); 779194246Smarius} 780194246Smarius 781194246Smariusstatic int 782194246Smariuscas_reset_tx(struct cas_softc *sc) 783194246Smarius{ 784194246Smarius 785194246Smarius /* 786194246Smarius * Resetting while DMA is in progress can cause a bus hang, so we 787194246Smarius * disable DMA first. 788194246Smarius */ 789223951Smarius (void)cas_disable_tx(sc); 790194246Smarius CAS_WRITE_4(sc, CAS_TX_CONF, 0); 791194246Smarius CAS_BARRIER(sc, CAS_TX_CONF, 4, 792194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 793194246Smarius if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 794194246Smarius device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 795194246Smarius 796194246Smarius /* Finally, reset the ETX. */ 797194246Smarius CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 798194246Smarius ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 799194246Smarius CAS_BARRIER(sc, CAS_RESET, 4, 800194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 801223951Smarius if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 802194246Smarius device_printf(sc->sc_dev, "cannot reset transmitter\n"); 803194246Smarius return (1); 804194246Smarius } 805194246Smarius return (0); 806194246Smarius} 807194246Smarius 808194246Smariusstatic int 809194246Smariuscas_disable_rx(struct cas_softc *sc) 810194246Smarius{ 811194246Smarius 812194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 813194246Smarius CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 814194246Smarius CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 815194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 816223951Smarius if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 817223951Smarius return (1); 818223951Smarius device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 819223951Smarius return (0); 820194246Smarius} 821194246Smarius 822194246Smariusstatic int 823194246Smariuscas_disable_tx(struct cas_softc *sc) 824194246Smarius{ 825194246Smarius 826194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 827194246Smarius CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 828194246Smarius CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 829194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 830223951Smarius if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 831223951Smarius return (1); 832223951Smarius device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 833223951Smarius return (0); 834194246Smarius} 835194246Smarius 836194246Smariusstatic inline void 837194246Smariuscas_rxcompinit(struct cas_rx_comp *rxcomp) 838194246Smarius{ 839194246Smarius 840194246Smarius rxcomp->crc_word1 = 0; 841194246Smarius rxcomp->crc_word2 = 0; 842194246Smarius rxcomp->crc_word3 = 843194246Smarius htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 844194246Smarius rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 845194246Smarius} 846194246Smarius 847194246Smariusstatic void 848194246Smariuscas_meminit(struct cas_softc *sc) 849194246Smarius{ 850194246Smarius int i; 851194246Smarius 852194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 853194246Smarius 854194246Smarius /* 855194246Smarius * Initialize the transmit descriptor ring. 856194246Smarius */ 857194246Smarius for (i = 0; i < CAS_NTXDESC; i++) { 858194246Smarius sc->sc_txdescs[i].cd_flags = 0; 859194246Smarius sc->sc_txdescs[i].cd_buf_ptr = 0; 860194246Smarius } 861194246Smarius sc->sc_txfree = CAS_MAXTXFREE; 862194246Smarius sc->sc_txnext = 0; 863194246Smarius sc->sc_txwin = 0; 864194246Smarius 865194246Smarius /* 866194246Smarius * Initialize the receive completion ring. 867194246Smarius */ 868194246Smarius for (i = 0; i < CAS_NRXCOMP; i++) 869194246Smarius cas_rxcompinit(&sc->sc_rxcomps[i]); 870194246Smarius sc->sc_rxcptr = 0; 871194246Smarius 872194246Smarius /* 873194246Smarius * Initialize the first receive descriptor ring. We leave 874194246Smarius * the second one zeroed as we don't actually use it. 875194246Smarius */ 876194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 877194246Smarius CAS_INIT_RXDESC(sc, i, i); 878194246Smarius sc->sc_rxdptr = 0; 879194246Smarius 880194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 881194246Smarius} 882194246Smarius 883194246Smariusstatic u_int 884194246Smariuscas_descsize(u_int sz) 885194246Smarius{ 886194246Smarius 887194246Smarius switch (sz) { 888194246Smarius case 32: 889194246Smarius return (CAS_DESC_32); 890194246Smarius case 64: 891194246Smarius return (CAS_DESC_64); 892194246Smarius case 128: 893194246Smarius return (CAS_DESC_128); 894194246Smarius case 256: 895194246Smarius return (CAS_DESC_256); 896194246Smarius case 512: 897194246Smarius return (CAS_DESC_512); 898194246Smarius case 1024: 899194246Smarius return (CAS_DESC_1K); 900194246Smarius case 2048: 901194246Smarius return (CAS_DESC_2K); 902194246Smarius case 4096: 903194246Smarius return (CAS_DESC_4K); 904194246Smarius case 8192: 905194246Smarius return (CAS_DESC_8K); 906194246Smarius default: 907194246Smarius printf("%s: invalid descriptor ring size %d\n", __func__, sz); 908194246Smarius return (CAS_DESC_32); 909194246Smarius } 910194246Smarius} 911194246Smarius 912194246Smariusstatic u_int 913194246Smariuscas_rxcompsize(u_int sz) 914194246Smarius{ 915194246Smarius 916194246Smarius switch (sz) { 917194246Smarius case 128: 918194246Smarius return (CAS_RX_CONF_COMP_128); 919194246Smarius case 256: 920194246Smarius return (CAS_RX_CONF_COMP_256); 921194246Smarius case 512: 922194246Smarius return (CAS_RX_CONF_COMP_512); 923194246Smarius case 1024: 924194246Smarius return (CAS_RX_CONF_COMP_1K); 925194246Smarius case 2048: 926194246Smarius return (CAS_RX_CONF_COMP_2K); 927194246Smarius case 4096: 928194246Smarius return (CAS_RX_CONF_COMP_4K); 929194246Smarius case 8192: 930194246Smarius return (CAS_RX_CONF_COMP_8K); 931194246Smarius case 16384: 932194246Smarius return (CAS_RX_CONF_COMP_16K); 933194246Smarius case 32768: 934194246Smarius return (CAS_RX_CONF_COMP_32K); 935194246Smarius default: 936194246Smarius printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 937194246Smarius return (CAS_RX_CONF_COMP_128); 938194246Smarius } 939194246Smarius} 940194246Smarius 941194246Smariusstatic void 942194246Smariuscas_init(void *xsc) 943194246Smarius{ 944194246Smarius struct cas_softc *sc = xsc; 945194246Smarius 946194246Smarius CAS_LOCK(sc); 947194246Smarius cas_init_locked(sc); 948194246Smarius CAS_UNLOCK(sc); 949194246Smarius} 950194246Smarius 951194246Smarius/* 952194246Smarius * Initialization of interface; set up initialization block 953194246Smarius * and transmit/receive descriptor rings. 954194246Smarius */ 955194246Smariusstatic void 956194246Smariuscas_init_locked(struct cas_softc *sc) 957194246Smarius{ 958194246Smarius struct ifnet *ifp = sc->sc_ifp; 959194246Smarius uint32_t v; 960194246Smarius 961194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 962194246Smarius 963194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 964194904Smarius return; 965194904Smarius 966194246Smarius#ifdef CAS_DEBUG 967194246Smarius CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 968194246Smarius __func__); 969194246Smarius#endif 970194246Smarius /* 971194246Smarius * Initialization sequence. The numbered steps below correspond 972194246Smarius * to the sequence outlined in section 6.3.5.1 in the Ethernet 973194246Smarius * Channel Engine manual (part of the PCIO manual). 974194246Smarius * See also the STP2002-STQ document from Sun Microsystems. 975194246Smarius */ 976194246Smarius 977194246Smarius /* step 1 & 2. Reset the Ethernet Channel. */ 978194246Smarius cas_stop(ifp); 979194246Smarius cas_reset(sc); 980194246Smarius#ifdef CAS_DEBUG 981194246Smarius CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 982194246Smarius __func__); 983194246Smarius#endif 984194246Smarius 985207585Smarius if ((sc->sc_flags & CAS_SERDES) == 0) 986207585Smarius /* Re-initialize the MIF. */ 987207585Smarius cas_mifinit(sc); 988194246Smarius 989194246Smarius /* step 3. Setup data structures in host memory. */ 990194246Smarius cas_meminit(sc); 991194246Smarius 992194246Smarius /* step 4. TX MAC registers & counters */ 993194246Smarius cas_init_regs(sc); 994194246Smarius 995194246Smarius /* step 5. RX MAC registers & counters */ 996194246Smarius 997194246Smarius /* step 6 & 7. Program Ring Base Addresses. */ 998194246Smarius CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 999194246Smarius (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1000194246Smarius CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1001194246Smarius CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1002194246Smarius 1003194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1004194246Smarius (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1005194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1006194246Smarius CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1007194246Smarius 1008194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1009194246Smarius (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1010194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1011194246Smarius CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1012194246Smarius 1013194246Smarius if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1014194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1015194246Smarius (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1016194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1017194246Smarius CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1018194246Smarius } 1019194246Smarius 1020194246Smarius#ifdef CAS_DEBUG 1021194246Smarius CTR5(KTR_CAS, 1022194246Smarius "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1023194246Smarius CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1024194246Smarius CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1025194246Smarius#endif 1026194246Smarius 1027194246Smarius /* step 8. Global Configuration & Interrupt Masks */ 1028194246Smarius 1029194246Smarius /* Disable weighted round robin. */ 1030194246Smarius CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1031194246Smarius 1032194246Smarius /* 1033194246Smarius * Enable infinite bursts for revisions without PCI issues if 1034194246Smarius * applicable. Doing so greatly improves the TX performance on 1035194246Smarius * !__sparc64__. 1036194246Smarius */ 1037194246Smarius CAS_WRITE_4(sc, CAS_INF_BURST, 1038194246Smarius#if !defined(__sparc64__) 1039194246Smarius (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1040194246Smarius#endif 1041194246Smarius 0); 1042194246Smarius 1043194246Smarius /* Set up interrupts. */ 1044194246Smarius CAS_WRITE_4(sc, CAS_INTMASK, 1045194904Smarius ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1046194246Smarius CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1047194246Smarius CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1048194246Smarius CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1049194246Smarius CAS_INTR_PCI_ERROR_INT 1050194246Smarius#ifdef CAS_DEBUG 1051194246Smarius | CAS_INTR_PCS_INT | CAS_INTR_MIF 1052194246Smarius#endif 1053194246Smarius )); 1054194904Smarius /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1055194904Smarius CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1056194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1057194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1058194246Smarius ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1059194246Smarius#ifdef CAS_DEBUG 1060194246Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1061194246Smarius ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1062194246Smarius CAS_MAC_CTRL_NON_PAUSE)); 1063194246Smarius#else 1064194246Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1065194246Smarius CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1066194246Smarius CAS_MAC_CTRL_NON_PAUSE); 1067194246Smarius#endif 1068194246Smarius 1069194246Smarius /* Enable PCI error interrupts. */ 1070194246Smarius CAS_WRITE_4(sc, CAS_ERROR_MASK, 1071194246Smarius ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1072194246Smarius CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1073194246Smarius 1074194246Smarius /* Enable PCI error interrupts in BIM configuration. */ 1075194246Smarius CAS_WRITE_4(sc, CAS_BIM_CONF, 1076194246Smarius CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1077194246Smarius 1078194246Smarius /* 1079194246Smarius * step 9. ETX Configuration: encode receive descriptor ring size, 1080194246Smarius * enable DMA and disable pre-interrupt writeback completion. 1081194246Smarius */ 1082194246Smarius v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1083194246Smarius CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1084194246Smarius CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1085194246Smarius 1086194246Smarius /* step 10. ERX Configuration */ 1087194246Smarius 1088194246Smarius /* 1089194246Smarius * Encode receive completion and descriptor ring sizes, set the 1090194246Smarius * swivel offset. 1091194246Smarius */ 1092194246Smarius v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1093194246Smarius v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1094194246Smarius if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1095194246Smarius v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1096194246Smarius CAS_WRITE_4(sc, CAS_RX_CONF, 1097194246Smarius v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1098194246Smarius 1099194246Smarius /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1100194246Smarius CAS_WRITE_4(sc, CAS_RX_PTHRS, 1101215721Smarius (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1102194246Smarius 1103194246Smarius /* RX blanking */ 1104194246Smarius CAS_WRITE_4(sc, CAS_RX_BLANK, 1105194246Smarius (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1106194246Smarius 1107194246Smarius /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1108194246Smarius CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1109194246Smarius (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1110194246Smarius 1111194246Smarius /* Initialize the RX page size register as appropriate for 8k. */ 1112194246Smarius CAS_WRITE_4(sc, CAS_RX_PSZ, 1113194246Smarius (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1114194246Smarius (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1115194246Smarius (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1116194246Smarius (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1117194246Smarius 1118194246Smarius /* Disable RX random early detection. */ 1119194246Smarius CAS_WRITE_4(sc, CAS_RX_RED, 0); 1120194246Smarius 1121194246Smarius /* Zero the RX reassembly DMA table. */ 1122194246Smarius for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1123194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1124194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1125194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1126194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1127194246Smarius } 1128194246Smarius 1129194246Smarius /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1130194246Smarius CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1131194246Smarius CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1132194246Smarius 1133194246Smarius /* Finally, enable RX DMA. */ 1134194246Smarius CAS_WRITE_4(sc, CAS_RX_CONF, 1135194246Smarius CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1136194246Smarius 1137194246Smarius /* step 11. Configure Media. */ 1138194246Smarius 1139194246Smarius /* step 12. RX_MAC Configuration Register */ 1140223951Smarius v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1141223951Smarius v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1142223951Smarius v |= CAS_MAC_RX_CONF_STRPFCS; 1143223951Smarius sc->sc_mac_rxcfg = v; 1144223951Smarius /* 1145223951Smarius * Clear the RX filter and reprogram it. This will also set the 1146223951Smarius * current RX MAC configuration and enable it. 1147223951Smarius */ 1148223951Smarius cas_setladrf(sc); 1149194246Smarius 1150194246Smarius /* step 13. TX_MAC Configuration Register */ 1151194246Smarius v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1152194246Smarius v |= CAS_MAC_TX_CONF_EN; 1153223951Smarius (void)cas_disable_tx(sc); 1154194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1155194246Smarius 1156194246Smarius /* step 14. Issue Transmit Pending command. */ 1157194246Smarius 1158220943Smarius /* step 15. Give the receiver a swift kick. */ 1159194246Smarius CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1160194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1161194246Smarius if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1162194246Smarius CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1163194246Smarius 1164194246Smarius ifp->if_drv_flags |= IFF_DRV_RUNNING; 1165194246Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1166194246Smarius 1167194246Smarius mii_mediachg(sc->sc_mii); 1168194246Smarius 1169194246Smarius /* Start the one second timer. */ 1170194246Smarius sc->sc_wdog_timer = 0; 1171194246Smarius callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1172194246Smarius} 1173194246Smarius 1174194246Smariusstatic int 1175194246Smariuscas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1176194246Smarius{ 1177194246Smarius bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1178194246Smarius struct cas_txsoft *txs; 1179194246Smarius struct ip *ip; 1180194246Smarius struct mbuf *m; 1181194246Smarius uint64_t cflags; 1182194246Smarius int error, nexttx, nsegs, offset, seg; 1183194246Smarius 1184194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1185194246Smarius 1186194246Smarius /* Get a work queue entry. */ 1187194246Smarius if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1188194246Smarius /* Ran out of descriptors. */ 1189194246Smarius return (ENOBUFS); 1190194246Smarius } 1191194246Smarius 1192194246Smarius cflags = 0; 1193194246Smarius if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1194194246Smarius if (M_WRITABLE(*m_head) == 0) { 1195194246Smarius m = m_dup(*m_head, M_DONTWAIT); 1196194246Smarius m_freem(*m_head); 1197194246Smarius *m_head = m; 1198194246Smarius if (m == NULL) 1199194246Smarius return (ENOBUFS); 1200194246Smarius } 1201194246Smarius offset = sizeof(struct ether_header); 1202194246Smarius m = m_pullup(*m_head, offset + sizeof(struct ip)); 1203194246Smarius if (m == NULL) { 1204194246Smarius *m_head = NULL; 1205194246Smarius return (ENOBUFS); 1206194246Smarius } 1207194246Smarius ip = (struct ip *)(mtod(m, caddr_t) + offset); 1208194246Smarius offset += (ip->ip_hl << 2); 1209194246Smarius cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1210194246Smarius ((offset + m->m_pkthdr.csum_data) << 1211194246Smarius CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1212194246Smarius *m_head = m; 1213194246Smarius } 1214194246Smarius 1215194246Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1216194246Smarius *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1217194246Smarius if (error == EFBIG) { 1218194246Smarius m = m_collapse(*m_head, M_DONTWAIT, CAS_NTXSEGS); 1219194246Smarius if (m == NULL) { 1220194246Smarius m_freem(*m_head); 1221194246Smarius *m_head = NULL; 1222194246Smarius return (ENOBUFS); 1223194246Smarius } 1224194246Smarius *m_head = m; 1225194246Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1226194246Smarius txs->txs_dmamap, *m_head, txsegs, &nsegs, 1227194246Smarius BUS_DMA_NOWAIT); 1228194246Smarius if (error != 0) { 1229194246Smarius m_freem(*m_head); 1230194246Smarius *m_head = NULL; 1231194246Smarius return (error); 1232194246Smarius } 1233194246Smarius } else if (error != 0) 1234194246Smarius return (error); 1235194246Smarius /* If nsegs is wrong then the stack is corrupt. */ 1236194246Smarius KASSERT(nsegs <= CAS_NTXSEGS, 1237194246Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1238194246Smarius if (nsegs == 0) { 1239194246Smarius m_freem(*m_head); 1240194246Smarius *m_head = NULL; 1241194246Smarius return (EIO); 1242194246Smarius } 1243194246Smarius 1244194246Smarius /* 1245194246Smarius * Ensure we have enough descriptors free to describe 1246194246Smarius * the packet. Note, we always reserve one descriptor 1247194246Smarius * at the end of the ring as a termination point, in 1248194246Smarius * order to prevent wrap-around. 1249194246Smarius */ 1250194246Smarius if (nsegs > sc->sc_txfree - 1) { 1251194246Smarius txs->txs_ndescs = 0; 1252194246Smarius bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1253194246Smarius return (ENOBUFS); 1254194246Smarius } 1255194246Smarius 1256194246Smarius txs->txs_ndescs = nsegs; 1257194246Smarius txs->txs_firstdesc = sc->sc_txnext; 1258194246Smarius nexttx = txs->txs_firstdesc; 1259194246Smarius for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1260194246Smarius#ifdef CAS_DEBUG 1261194246Smarius CTR6(KTR_CAS, 1262194246Smarius "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1263194246Smarius __func__, seg, nexttx, txsegs[seg].ds_len, 1264194246Smarius txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1265194246Smarius#endif 1266194246Smarius sc->sc_txdescs[nexttx].cd_buf_ptr = 1267194246Smarius htole64(txsegs[seg].ds_addr); 1268194246Smarius KASSERT(txsegs[seg].ds_len < 1269194246Smarius CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1270194246Smarius ("%s: segment size too large!", __func__)); 1271194246Smarius sc->sc_txdescs[nexttx].cd_flags = 1272194246Smarius htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1273194246Smarius txs->txs_lastdesc = nexttx; 1274194246Smarius } 1275194246Smarius 1276194246Smarius /* Set EOF on the last descriptor. */ 1277194246Smarius#ifdef CAS_DEBUG 1278194246Smarius CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1279194246Smarius __func__, seg, nexttx); 1280194246Smarius#endif 1281194246Smarius sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1282194246Smarius htole64(CAS_TD_END_OF_FRAME); 1283194246Smarius 1284194246Smarius /* Lastly set SOF on the first descriptor. */ 1285194246Smarius#ifdef CAS_DEBUG 1286194246Smarius CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1287194246Smarius __func__, seg, nexttx); 1288194246Smarius#endif 1289194904Smarius if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1290194246Smarius sc->sc_txwin = 0; 1291194246Smarius sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1292194246Smarius htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1293194246Smarius } else 1294194246Smarius sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1295194246Smarius htole64(cflags | CAS_TD_START_OF_FRAME); 1296194246Smarius 1297194246Smarius /* Sync the DMA map. */ 1298194246Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1299194246Smarius BUS_DMASYNC_PREWRITE); 1300194246Smarius 1301194246Smarius#ifdef CAS_DEBUG 1302194246Smarius CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1303194246Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1304194246Smarius txs->txs_ndescs); 1305194246Smarius#endif 1306194246Smarius STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1307194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1308194246Smarius txs->txs_mbuf = *m_head; 1309194246Smarius 1310194246Smarius sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1311194246Smarius sc->sc_txfree -= txs->txs_ndescs; 1312194246Smarius 1313194246Smarius return (0); 1314194246Smarius} 1315194246Smarius 1316194246Smariusstatic void 1317194246Smariuscas_init_regs(struct cas_softc *sc) 1318194246Smarius{ 1319194246Smarius int i; 1320194246Smarius const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1321194246Smarius 1322194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1323194246Smarius 1324194246Smarius /* These registers are not cleared on reset. */ 1325194246Smarius if ((sc->sc_flags & CAS_INITED) == 0) { 1326194246Smarius /* magic values */ 1327194246Smarius CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1328194246Smarius CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1329194246Smarius CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1330194246Smarius 1331194246Smarius /* min frame length */ 1332194246Smarius CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1333194246Smarius /* max frame length and max burst size */ 1334194246Smarius CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1335194246Smarius ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1336194246Smarius CAS_MAC_MAX_BF_FRM_SHFT) | 1337194246Smarius (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1338194246Smarius 1339194246Smarius /* more magic values */ 1340194246Smarius CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1341194246Smarius CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1342194246Smarius CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1343215721Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1344194246Smarius 1345194246Smarius /* random number seed */ 1346194246Smarius CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1347194246Smarius ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1348194246Smarius 1349194246Smarius /* secondary MAC addresses: 0:0:0:0:0:0 */ 1350194246Smarius for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1351194246Smarius i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1352194246Smarius CAS_WRITE_4(sc, i, 0); 1353194246Smarius 1354194246Smarius /* MAC control address: 01:80:c2:00:00:01 */ 1355194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1356194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1357194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1358194246Smarius 1359194246Smarius /* MAC filter address: 0:0:0:0:0:0 */ 1360194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1361194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1362194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1363194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1364194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1365194246Smarius 1366194246Smarius /* Zero the hash table. */ 1367194246Smarius for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1368194246Smarius i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1369194246Smarius CAS_WRITE_4(sc, i, 0); 1370194246Smarius 1371194246Smarius sc->sc_flags |= CAS_INITED; 1372194246Smarius } 1373194246Smarius 1374194246Smarius /* Counters need to be zeroed. */ 1375194246Smarius CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1376194246Smarius CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1377194246Smarius CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1378194246Smarius CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1379194246Smarius CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1380194246Smarius CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1381194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1382194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1383194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1384194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1385194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1386194246Smarius 1387194246Smarius /* Set XOFF PAUSE time. */ 1388194246Smarius CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1389194246Smarius 1390194246Smarius /* Set the station address. */ 1391194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1392194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1393194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1394194246Smarius 1395194246Smarius /* Enable MII outputs. */ 1396194246Smarius CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1397194246Smarius} 1398194246Smarius 1399194246Smariusstatic void 1400194904Smariuscas_tx_task(void *arg, int pending __unused) 1401194246Smarius{ 1402194904Smarius struct ifnet *ifp; 1403194246Smarius 1404194904Smarius ifp = (struct ifnet *)arg; 1405194904Smarius cas_start(ifp); 1406194246Smarius} 1407194246Smarius 1408194246Smariusstatic inline void 1409194246Smariuscas_txkick(struct cas_softc *sc) 1410194246Smarius{ 1411194246Smarius 1412194246Smarius /* 1413194246Smarius * Update the TX kick register. This register has to point to the 1414194246Smarius * descriptor after the last valid one and for optimum performance 1415194246Smarius * should be incremented in multiples of 4 (the DMA engine fetches/ 1416194246Smarius * updates descriptors in batches of 4). 1417194246Smarius */ 1418194246Smarius#ifdef CAS_DEBUG 1419194246Smarius CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1420194246Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1421194246Smarius#endif 1422194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1423194246Smarius CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1424194246Smarius} 1425194246Smarius 1426194246Smariusstatic void 1427194904Smariuscas_start(struct ifnet *ifp) 1428194246Smarius{ 1429194246Smarius struct cas_softc *sc = ifp->if_softc; 1430194246Smarius struct mbuf *m; 1431194246Smarius int kicked, ntx; 1432194246Smarius 1433194904Smarius CAS_LOCK(sc); 1434194246Smarius 1435194246Smarius if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1436194904Smarius IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1437194904Smarius CAS_UNLOCK(sc); 1438194246Smarius return; 1439194904Smarius } 1440194246Smarius 1441194904Smarius if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1442194904Smarius cas_tint(sc); 1443194904Smarius 1444194246Smarius#ifdef CAS_DEBUG 1445194246Smarius CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1446194246Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1447194246Smarius sc->sc_txnext); 1448194246Smarius#endif 1449194246Smarius ntx = 0; 1450194246Smarius kicked = 0; 1451194246Smarius for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1452194246Smarius IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1453194246Smarius if (m == NULL) 1454194246Smarius break; 1455194246Smarius if (cas_load_txmbuf(sc, &m) != 0) { 1456194246Smarius if (m == NULL) 1457194246Smarius break; 1458194246Smarius ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1459194246Smarius IFQ_DRV_PREPEND(&ifp->if_snd, m); 1460194246Smarius break; 1461194246Smarius } 1462194246Smarius if ((sc->sc_txnext % 4) == 0) { 1463194246Smarius cas_txkick(sc); 1464194246Smarius kicked = 1; 1465194246Smarius } else 1466194246Smarius kicked = 0; 1467194246Smarius ntx++; 1468194246Smarius BPF_MTAP(ifp, m); 1469194246Smarius } 1470194246Smarius 1471194246Smarius if (ntx > 0) { 1472194246Smarius if (kicked == 0) 1473194246Smarius cas_txkick(sc); 1474194246Smarius#ifdef CAS_DEBUG 1475194246Smarius CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1476194246Smarius device_get_name(sc->sc_dev), sc->sc_txnext); 1477194246Smarius#endif 1478194246Smarius 1479194246Smarius /* Set a watchdog timer in case the chip flakes out. */ 1480194246Smarius sc->sc_wdog_timer = 5; 1481194246Smarius#ifdef CAS_DEBUG 1482194246Smarius CTR3(KTR_CAS, "%s: %s: watchdog %d", 1483194246Smarius device_get_name(sc->sc_dev), __func__, 1484194246Smarius sc->sc_wdog_timer); 1485194246Smarius#endif 1486194246Smarius } 1487194904Smarius 1488194904Smarius CAS_UNLOCK(sc); 1489194246Smarius} 1490194246Smarius 1491194246Smariusstatic void 1492194246Smariuscas_tint(struct cas_softc *sc) 1493194246Smarius{ 1494194246Smarius struct ifnet *ifp = sc->sc_ifp; 1495194246Smarius struct cas_txsoft *txs; 1496194246Smarius int progress; 1497194246Smarius uint32_t txlast; 1498194246Smarius#ifdef CAS_DEBUG 1499194246Smarius int i; 1500194246Smarius 1501194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1502194246Smarius 1503194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1504194246Smarius#endif 1505194246Smarius 1506194246Smarius /* 1507194246Smarius * Go through our TX list and free mbufs for those 1508194246Smarius * frames that have been transmitted. 1509194246Smarius */ 1510194246Smarius progress = 0; 1511194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1512194246Smarius while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1513194246Smarius#ifdef CAS_DEBUG 1514194246Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1515194246Smarius printf(" txsoft %p transmit chain:\n", txs); 1516194246Smarius for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1517194246Smarius printf("descriptor %d: ", i); 1518194246Smarius printf("cd_flags: 0x%016llx\t", 1519194246Smarius (long long)le64toh( 1520194246Smarius sc->sc_txdescs[i].cd_flags)); 1521194246Smarius printf("cd_buf_ptr: 0x%016llx\n", 1522194246Smarius (long long)le64toh( 1523194246Smarius sc->sc_txdescs[i].cd_buf_ptr)); 1524194246Smarius if (i == txs->txs_lastdesc) 1525194246Smarius break; 1526194246Smarius } 1527194246Smarius } 1528194246Smarius#endif 1529194246Smarius 1530194246Smarius /* 1531194246Smarius * In theory, we could harvest some descriptors before 1532194246Smarius * the ring is empty, but that's a bit complicated. 1533194246Smarius * 1534194246Smarius * CAS_TX_COMPn points to the last descriptor 1535194246Smarius * processed + 1. 1536194246Smarius */ 1537194246Smarius txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1538194246Smarius#ifdef CAS_DEBUG 1539194246Smarius CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1540194246Smarius "txs->txs_lastdesc = %d, txlast = %d", 1541194246Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1542194246Smarius#endif 1543194246Smarius if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1544194246Smarius if ((txlast >= txs->txs_firstdesc) && 1545194246Smarius (txlast <= txs->txs_lastdesc)) 1546194246Smarius break; 1547194246Smarius } else { 1548194246Smarius /* Ick -- this command wraps. */ 1549194246Smarius if ((txlast >= txs->txs_firstdesc) || 1550194246Smarius (txlast <= txs->txs_lastdesc)) 1551194246Smarius break; 1552194246Smarius } 1553194246Smarius 1554194246Smarius#ifdef CAS_DEBUG 1555194246Smarius CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1556194246Smarius#endif 1557194246Smarius STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1558194246Smarius 1559194246Smarius sc->sc_txfree += txs->txs_ndescs; 1560194246Smarius 1561194246Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1562194246Smarius BUS_DMASYNC_POSTWRITE); 1563194246Smarius bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1564194246Smarius if (txs->txs_mbuf != NULL) { 1565194246Smarius m_freem(txs->txs_mbuf); 1566194246Smarius txs->txs_mbuf = NULL; 1567194246Smarius } 1568194246Smarius 1569194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1570194246Smarius 1571194246Smarius ifp->if_opackets++; 1572194246Smarius progress = 1; 1573194246Smarius } 1574194246Smarius 1575194246Smarius#ifdef CAS_DEBUG 1576215721Smarius CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1577194246Smarius "CAS_TX_COMP3 %x", 1578215721Smarius __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1579215721Smarius ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1580215721Smarius CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1581194246Smarius CAS_READ_4(sc, CAS_TX_COMP3)); 1582194246Smarius#endif 1583194246Smarius 1584194246Smarius if (progress) { 1585194904Smarius /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1586194246Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1587194246Smarius if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1588194246Smarius sc->sc_wdog_timer = 0; 1589194246Smarius } 1590194246Smarius 1591194246Smarius#ifdef CAS_DEBUG 1592194246Smarius CTR3(KTR_CAS, "%s: %s: watchdog %d", 1593194246Smarius device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1594194246Smarius#endif 1595194246Smarius} 1596194246Smarius 1597194246Smariusstatic void 1598194246Smariuscas_rint_timeout(void *arg) 1599194246Smarius{ 1600194246Smarius struct cas_softc *sc = arg; 1601194246Smarius 1602223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1603194246Smarius 1604194246Smarius cas_rint(sc); 1605194246Smarius} 1606194246Smarius 1607194246Smariusstatic void 1608194246Smariuscas_rint(struct cas_softc *sc) 1609194246Smarius{ 1610194246Smarius struct cas_rxdsoft *rxds, *rxds2; 1611194246Smarius struct ifnet *ifp = sc->sc_ifp; 1612194246Smarius struct mbuf *m, *m2; 1613194246Smarius uint64_t word1, word2, word3, word4; 1614194246Smarius uint32_t rxhead; 1615194246Smarius u_int idx, idx2, len, off, skip; 1616194246Smarius 1617223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1618194246Smarius 1619194246Smarius callout_stop(&sc->sc_rx_ch); 1620194246Smarius 1621194246Smarius#ifdef CAS_DEBUG 1622194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1623194246Smarius#endif 1624194246Smarius 1625194246Smarius#define PRINTWORD(n, delimiter) \ 1626194246Smarius printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1627194246Smarius 1628194246Smarius#define SKIPASSERT(n) \ 1629194246Smarius KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1630194246Smarius ("%s: word ## n not 0", __func__)) 1631194246Smarius 1632194246Smarius#define WORDTOH(n) \ 1633194246Smarius word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1634194246Smarius 1635194246Smarius /* 1636194246Smarius * Read the completion head register once. This limits 1637194246Smarius * how long the following loop can execute. 1638194246Smarius */ 1639194246Smarius rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1640194246Smarius#ifdef CAS_DEBUG 1641194246Smarius CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1642215721Smarius __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1643194246Smarius#endif 1644194246Smarius skip = 0; 1645194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1646194246Smarius for (; sc->sc_rxcptr != rxhead; 1647194246Smarius sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1648194246Smarius if (skip != 0) { 1649194246Smarius SKIPASSERT(1); 1650194246Smarius SKIPASSERT(2); 1651194246Smarius SKIPASSERT(3); 1652194246Smarius 1653194246Smarius --skip; 1654194246Smarius goto skip; 1655194246Smarius } 1656194246Smarius 1657194246Smarius WORDTOH(1); 1658194246Smarius WORDTOH(2); 1659194246Smarius WORDTOH(3); 1660194246Smarius WORDTOH(4); 1661194246Smarius 1662194246Smarius#ifdef CAS_DEBUG 1663194246Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1664194246Smarius printf(" completion %d: ", sc->sc_rxcptr); 1665194246Smarius PRINTWORD(1, '\t'); 1666194246Smarius PRINTWORD(2, '\t'); 1667194246Smarius PRINTWORD(3, '\t'); 1668194246Smarius PRINTWORD(4, '\n'); 1669194246Smarius } 1670194246Smarius#endif 1671194246Smarius 1672194246Smarius if (__predict_false( 1673194246Smarius (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1674194246Smarius (word4 & CAS_RC4_ZERO) != 0)) { 1675194246Smarius /* 1676194246Smarius * The descriptor is still marked as owned, although 1677194246Smarius * it is supposed to have completed. This has been 1678194246Smarius * observed on some machines. Just exiting here 1679194246Smarius * might leave the packet sitting around until another 1680194246Smarius * one arrives to trigger a new interrupt, which is 1681194246Smarius * generally undesirable, so set up a timeout. 1682194246Smarius */ 1683194246Smarius callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1684194246Smarius cas_rint_timeout, sc); 1685194246Smarius break; 1686194246Smarius } 1687194246Smarius 1688194246Smarius if (__predict_false( 1689194246Smarius (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1690194246Smarius ifp->if_ierrors++; 1691194246Smarius device_printf(sc->sc_dev, 1692194246Smarius "receive error: CRC error\n"); 1693194246Smarius continue; 1694194246Smarius } 1695194246Smarius 1696194246Smarius KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1697194246Smarius CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1698194246Smarius ("%s: data and header present", __func__)); 1699194246Smarius KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1700194246Smarius CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1701194246Smarius ("%s: split and header present", __func__)); 1702194246Smarius KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1703194246Smarius (word1 & CAS_RC1_RELEASE_HDR) == 0, 1704194246Smarius ("%s: data present but header release", __func__)); 1705194246Smarius KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1706194246Smarius (word1 & CAS_RC1_RELEASE_DATA) == 0, 1707194246Smarius ("%s: header present but data release", __func__)); 1708194246Smarius 1709194246Smarius if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1710194246Smarius idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1711194246Smarius off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1712194246Smarius#ifdef CAS_DEBUG 1713194246Smarius CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1714194246Smarius __func__, idx, off, len); 1715194246Smarius#endif 1716194246Smarius rxds = &sc->sc_rxdsoft[idx]; 1717194246Smarius MGETHDR(m, M_DONTWAIT, MT_DATA); 1718194246Smarius if (m != NULL) { 1719194246Smarius refcount_acquire(&rxds->rxds_refcount); 1720194246Smarius bus_dmamap_sync(sc->sc_rdmatag, 1721194246Smarius rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1722194973Smarius#if __FreeBSD_version < 800016 1723194246Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + 1724194246Smarius off * 256 + ETHER_ALIGN, len, cas_free, 1725194973Smarius rxds, M_RDONLY, EXT_NET_DRV); 1726194246Smarius#else 1727194973Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + 1728194973Smarius off * 256 + ETHER_ALIGN, len, cas_free, 1729194246Smarius sc, (void *)(uintptr_t)idx, 1730194973Smarius M_RDONLY, EXT_NET_DRV); 1731194246Smarius#endif 1732194246Smarius if ((m->m_flags & M_EXT) == 0) { 1733194246Smarius m_freem(m); 1734194246Smarius m = NULL; 1735194246Smarius } 1736194246Smarius } 1737194246Smarius if (m != NULL) { 1738194246Smarius m->m_pkthdr.rcvif = ifp; 1739194246Smarius m->m_pkthdr.len = m->m_len = len; 1740194246Smarius ifp->if_ipackets++; 1741194246Smarius if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1742194246Smarius cas_rxcksum(m, CAS_GET(word4, 1743194246Smarius CAS_RC4_TCP_CSUM)); 1744194246Smarius /* Pass it on. */ 1745223986Smarius CAS_UNLOCK(sc); 1746194246Smarius (*ifp->if_input)(ifp, m); 1747223986Smarius CAS_LOCK(sc); 1748194246Smarius } else 1749223951Smarius ifp->if_iqdrops++; 1750194246Smarius 1751194246Smarius if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1752194246Smarius refcount_release(&rxds->rxds_refcount) != 0) 1753194246Smarius cas_add_rxdesc(sc, idx); 1754194246Smarius } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1755194246Smarius idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1756194246Smarius off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1757194246Smarius#ifdef CAS_DEBUG 1758194246Smarius CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1759194246Smarius __func__, idx, off, len); 1760194246Smarius#endif 1761194246Smarius rxds = &sc->sc_rxdsoft[idx]; 1762194246Smarius MGETHDR(m, M_DONTWAIT, MT_DATA); 1763194246Smarius if (m != NULL) { 1764194246Smarius refcount_acquire(&rxds->rxds_refcount); 1765194246Smarius off += ETHER_ALIGN; 1766194246Smarius m->m_len = min(CAS_PAGE_SIZE - off, len); 1767194246Smarius bus_dmamap_sync(sc->sc_rdmatag, 1768194246Smarius rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1769194973Smarius#if __FreeBSD_version < 800016 1770194246Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1771194973Smarius m->m_len, cas_free, rxds, M_RDONLY, 1772194973Smarius EXT_NET_DRV); 1773194246Smarius#else 1774194973Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1775194973Smarius m->m_len, cas_free, sc, 1776194973Smarius (void *)(uintptr_t)idx, M_RDONLY, 1777194973Smarius EXT_NET_DRV); 1778194246Smarius#endif 1779194246Smarius if ((m->m_flags & M_EXT) == 0) { 1780194246Smarius m_freem(m); 1781194246Smarius m = NULL; 1782194246Smarius } 1783194246Smarius } 1784194246Smarius idx2 = 0; 1785208776Smarius m2 = NULL; 1786194246Smarius rxds2 = NULL; 1787194246Smarius if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1788194246Smarius KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1789194246Smarius ("%s: split but no release next", 1790194246Smarius __func__)); 1791194246Smarius 1792194246Smarius idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1793194246Smarius#ifdef CAS_DEBUG 1794194246Smarius CTR2(KTR_CAS, "%s: split at idx %d", 1795194246Smarius __func__, idx2); 1796194246Smarius#endif 1797194246Smarius rxds2 = &sc->sc_rxdsoft[idx2]; 1798208776Smarius if (m != NULL) { 1799208776Smarius MGET(m2, M_DONTWAIT, MT_DATA); 1800208776Smarius if (m2 != NULL) { 1801208776Smarius refcount_acquire( 1802208776Smarius &rxds2->rxds_refcount); 1803208776Smarius m2->m_len = len - m->m_len; 1804208776Smarius bus_dmamap_sync( 1805208776Smarius sc->sc_rdmatag, 1806208776Smarius rxds2->rxds_dmamap, 1807208776Smarius BUS_DMASYNC_POSTREAD); 1808194973Smarius#if __FreeBSD_version < 800016 1809208776Smarius MEXTADD(m2, 1810208776Smarius (caddr_t)rxds2->rxds_buf, 1811208776Smarius m2->m_len, cas_free, 1812208776Smarius rxds2, M_RDONLY, 1813208776Smarius EXT_NET_DRV); 1814194973Smarius#else 1815208776Smarius MEXTADD(m2, 1816208776Smarius (caddr_t)rxds2->rxds_buf, 1817208776Smarius m2->m_len, cas_free, sc, 1818208776Smarius (void *)(uintptr_t)idx2, 1819208776Smarius M_RDONLY, EXT_NET_DRV); 1820194246Smarius#endif 1821208776Smarius if ((m2->m_flags & M_EXT) == 1822208776Smarius 0) { 1823208776Smarius m_freem(m2); 1824208776Smarius m2 = NULL; 1825208776Smarius } 1826194246Smarius } 1827194246Smarius } 1828194246Smarius if (m2 != NULL) 1829194246Smarius m->m_next = m2; 1830208776Smarius else if (m != NULL) { 1831194246Smarius m_freem(m); 1832194246Smarius m = NULL; 1833194246Smarius } 1834194246Smarius } 1835194246Smarius if (m != NULL) { 1836194246Smarius m->m_pkthdr.rcvif = ifp; 1837194246Smarius m->m_pkthdr.len = len; 1838194246Smarius ifp->if_ipackets++; 1839194246Smarius if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1840194246Smarius cas_rxcksum(m, CAS_GET(word4, 1841194246Smarius CAS_RC4_TCP_CSUM)); 1842194246Smarius /* Pass it on. */ 1843223986Smarius CAS_UNLOCK(sc); 1844194246Smarius (*ifp->if_input)(ifp, m); 1845223986Smarius CAS_LOCK(sc); 1846194246Smarius } else 1847223951Smarius ifp->if_iqdrops++; 1848194246Smarius 1849194246Smarius if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1850194246Smarius refcount_release(&rxds->rxds_refcount) != 0) 1851194246Smarius cas_add_rxdesc(sc, idx); 1852194246Smarius if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1853194246Smarius refcount_release(&rxds2->rxds_refcount) != 0) 1854194246Smarius cas_add_rxdesc(sc, idx2); 1855194246Smarius } 1856194246Smarius 1857194246Smarius skip = CAS_GET(word1, CAS_RC1_SKIP); 1858194246Smarius 1859194246Smarius skip: 1860194246Smarius cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1861194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1862194904Smarius break; 1863194246Smarius } 1864194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1865194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1866194246Smarius 1867194246Smarius#undef PRINTWORD 1868194246Smarius#undef SKIPASSERT 1869194246Smarius#undef WORDTOH 1870194246Smarius 1871194246Smarius#ifdef CAS_DEBUG 1872194246Smarius CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1873215721Smarius __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1874194246Smarius CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1875194246Smarius#endif 1876194246Smarius} 1877194246Smarius 1878194246Smariusstatic void 1879194246Smariuscas_free(void *arg1, void *arg2) 1880194246Smarius{ 1881194246Smarius struct cas_rxdsoft *rxds; 1882194246Smarius struct cas_softc *sc; 1883223986Smarius u_int idx, locked; 1884194246Smarius 1885194246Smarius#if __FreeBSD_version < 800016 1886194246Smarius rxds = arg2; 1887194246Smarius sc = rxds->rxds_sc; 1888194246Smarius idx = rxds->rxds_idx; 1889194246Smarius#else 1890194246Smarius sc = arg1; 1891194246Smarius idx = (uintptr_t)arg2; 1892194246Smarius rxds = &sc->sc_rxdsoft[idx]; 1893194246Smarius#endif 1894194246Smarius if (refcount_release(&rxds->rxds_refcount) == 0) 1895194246Smarius return; 1896194246Smarius 1897194246Smarius /* 1898194246Smarius * NB: this function can be called via m_freem(9) within 1899194246Smarius * this driver! 1900194246Smarius */ 1901223986Smarius if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1902223986Smarius CAS_LOCK(sc); 1903194246Smarius cas_add_rxdesc(sc, idx); 1904223986Smarius if (locked == 0) 1905223986Smarius CAS_UNLOCK(sc); 1906194246Smarius} 1907194246Smarius 1908194246Smariusstatic inline void 1909194246Smariuscas_add_rxdesc(struct cas_softc *sc, u_int idx) 1910194246Smarius{ 1911194246Smarius 1912223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1913194246Smarius 1914194246Smarius bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1915194246Smarius BUS_DMASYNC_PREREAD); 1916194246Smarius CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1917194246Smarius sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1918194246Smarius 1919194246Smarius /* 1920194246Smarius * Update the RX kick register. This register has to point to the 1921194246Smarius * descriptor after the last valid one (before the current batch) 1922194246Smarius * and for optimum performance should be incremented in multiples 1923194246Smarius * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1924194246Smarius */ 1925194246Smarius if ((sc->sc_rxdptr % 4) == 0) { 1926194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1927194246Smarius CAS_WRITE_4(sc, CAS_RX_KICK, 1928194246Smarius (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1929194246Smarius } 1930194246Smarius} 1931194246Smarius 1932194246Smariusstatic void 1933194246Smariuscas_eint(struct cas_softc *sc, u_int status) 1934194246Smarius{ 1935194904Smarius struct ifnet *ifp = sc->sc_ifp; 1936194246Smarius 1937223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1938194246Smarius 1939194904Smarius ifp->if_ierrors++; 1940194904Smarius 1941194246Smarius device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1942194246Smarius if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1943194246Smarius status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1944194246Smarius printf(", PCI bus error 0x%x", status); 1945194246Smarius if ((status & CAS_ERROR_OTHER) != 0) { 1946194246Smarius status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1947194246Smarius printf(", PCI status 0x%x", status); 1948194246Smarius pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1949194246Smarius } 1950194246Smarius } 1951194246Smarius printf("\n"); 1952194246Smarius 1953194904Smarius ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1954223986Smarius cas_init_locked(sc); 1955194904Smarius if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1956194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1957194246Smarius} 1958194246Smarius 1959194904Smariusstatic int 1960194246Smariuscas_intr(void *v) 1961194246Smarius{ 1962194246Smarius struct cas_softc *sc = v; 1963194904Smarius 1964194904Smarius if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1965194904Smarius CAS_INTR_SUMMARY) == 0)) 1966194904Smarius return (FILTER_STRAY); 1967194904Smarius 1968194904Smarius /* Disable interrupts. */ 1969194904Smarius CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1970194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1971194904Smarius 1972194904Smarius return (FILTER_HANDLED); 1973194904Smarius} 1974194904Smarius 1975194904Smariusstatic void 1976194904Smariuscas_intr_task(void *arg, int pending __unused) 1977194904Smarius{ 1978194904Smarius struct cas_softc *sc = arg; 1979194904Smarius struct ifnet *ifp = sc->sc_ifp; 1980194246Smarius uint32_t status, status2; 1981194246Smarius 1982194904Smarius CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1983194904Smarius 1984194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1985194904Smarius return; 1986194904Smarius 1987194246Smarius status = CAS_READ_4(sc, CAS_STATUS); 1988194246Smarius if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1989194904Smarius goto done; 1990194246Smarius 1991223986Smarius CAS_LOCK(sc); 1992194246Smarius#ifdef CAS_DEBUG 1993194246Smarius CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1994194246Smarius device_get_name(sc->sc_dev), __func__, 1995215721Smarius (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 1996194246Smarius 1997194246Smarius /* 1998194246Smarius * PCS interrupts must be cleared, otherwise no traffic is passed! 1999194246Smarius */ 2000194246Smarius if ((status & CAS_INTR_PCS_INT) != 0) { 2001194246Smarius status2 = 2002194246Smarius CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 2003194246Smarius CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 2004194246Smarius if ((status2 & CAS_PCS_INTR_LINK) != 0) 2005194246Smarius device_printf(sc->sc_dev, 2006194246Smarius "%s: PCS link status changed\n", __func__); 2007194246Smarius } 2008194246Smarius if ((status & CAS_MAC_CTRL_STATUS) != 0) { 2009194246Smarius status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 2010194246Smarius if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2011194246Smarius device_printf(sc->sc_dev, 2012194246Smarius "%s: PAUSE received (PAUSE time %d slots)\n", 2013194246Smarius __func__, 2014194246Smarius (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2015194246Smarius CAS_MAC_CTRL_STATUS_PT_SHFT); 2016194246Smarius if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2017194246Smarius device_printf(sc->sc_dev, 2018194246Smarius "%s: transited to PAUSE state\n", __func__); 2019194246Smarius if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2020194246Smarius device_printf(sc->sc_dev, 2021194246Smarius "%s: transited to non-PAUSE state\n", __func__); 2022194246Smarius } 2023194246Smarius if ((status & CAS_INTR_MIF) != 0) 2024194246Smarius device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2025194246Smarius#endif 2026194246Smarius 2027194246Smarius if (__predict_false((status & 2028194246Smarius (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2029194246Smarius CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2030194246Smarius cas_eint(sc, status); 2031223986Smarius CAS_UNLOCK(sc); 2032194246Smarius return; 2033194246Smarius } 2034194246Smarius 2035194246Smarius if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2036194246Smarius status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2037194246Smarius if ((status2 & 2038194246Smarius (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2039223986Smarius ifp->if_oerrors++; 2040194246Smarius else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2041194246Smarius device_printf(sc->sc_dev, 2042194246Smarius "MAC TX fault, status %x\n", status2); 2043194246Smarius } 2044194246Smarius 2045194246Smarius if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2046194246Smarius status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2047194246Smarius if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2048223986Smarius ifp->if_ierrors++; 2049194246Smarius else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2050194246Smarius device_printf(sc->sc_dev, 2051194246Smarius "MAC RX fault, status %x\n", status2); 2052194246Smarius } 2053194246Smarius 2054194246Smarius if ((status & 2055194246Smarius (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2056194246Smarius CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2057194246Smarius cas_rint(sc); 2058194904Smarius#ifdef CAS_DEBUG 2059194246Smarius if (__predict_false((status & 2060194246Smarius (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2061194246Smarius CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2062194246Smarius device_printf(sc->sc_dev, 2063194246Smarius "RX fault, status %x\n", status); 2064194904Smarius#endif 2065194246Smarius } 2066194246Smarius 2067194246Smarius if ((status & 2068223986Smarius (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2069194246Smarius cas_tint(sc); 2070223986Smarius 2071223986Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2072194904Smarius CAS_UNLOCK(sc); 2073194904Smarius return; 2074223986Smarius } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2075194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2076223986Smarius CAS_UNLOCK(sc); 2077194904Smarius 2078194904Smarius status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2079194904Smarius if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2080194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2081194904Smarius return; 2082194904Smarius } 2083194904Smarius 2084194904Smarius done: 2085194904Smarius /* Re-enable interrupts. */ 2086194904Smarius CAS_WRITE_4(sc, CAS_INTMASK, 2087194904Smarius ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2088194904Smarius CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2089194904Smarius CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2090194904Smarius CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2091194904Smarius CAS_INTR_PCI_ERROR_INT 2092194904Smarius#ifdef CAS_DEBUG 2093194904Smarius | CAS_INTR_PCS_INT | CAS_INTR_MIF 2094194904Smarius#endif 2095194904Smarius )); 2096194246Smarius} 2097194246Smarius 2098194904Smariusstatic void 2099194246Smariuscas_watchdog(struct cas_softc *sc) 2100194246Smarius{ 2101194246Smarius struct ifnet *ifp = sc->sc_ifp; 2102194246Smarius 2103194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 2104194246Smarius 2105194246Smarius#ifdef CAS_DEBUG 2106194246Smarius CTR4(KTR_CAS, 2107215721Smarius "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2108215721Smarius __func__, CAS_READ_4(sc, CAS_RX_CONF), 2109194246Smarius CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2110215721Smarius CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2111194246Smarius CTR4(KTR_CAS, 2112215721Smarius "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2113215721Smarius __func__, CAS_READ_4(sc, CAS_TX_CONF), 2114194246Smarius CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2115215721Smarius CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2116194246Smarius#endif 2117194246Smarius 2118194246Smarius if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2119194904Smarius return; 2120194246Smarius 2121194246Smarius if ((sc->sc_flags & CAS_LINK) != 0) 2122194246Smarius device_printf(sc->sc_dev, "device timeout\n"); 2123194246Smarius else if (bootverbose) 2124194246Smarius device_printf(sc->sc_dev, "device timeout (no link)\n"); 2125194246Smarius ++ifp->if_oerrors; 2126194246Smarius 2127194246Smarius /* Try to get more packets going. */ 2128194904Smarius ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2129194246Smarius cas_init_locked(sc); 2130194904Smarius if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2131194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2132194246Smarius} 2133194246Smarius 2134194246Smariusstatic void 2135194246Smariuscas_mifinit(struct cas_softc *sc) 2136194246Smarius{ 2137194246Smarius 2138194246Smarius /* Configure the MIF in frame mode. */ 2139194246Smarius CAS_WRITE_4(sc, CAS_MIF_CONF, 2140194246Smarius CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2141207585Smarius CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2142207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2143194246Smarius} 2144194246Smarius 2145194246Smarius/* 2146194246Smarius * MII interface 2147194246Smarius * 2148194246Smarius * The MII interface supports at least three different operating modes: 2149194246Smarius * 2150194246Smarius * Bitbang mode is implemented using data, clock and output enable registers. 2151194246Smarius * 2152194246Smarius * Frame mode is implemented by loading a complete frame into the frame 2153194246Smarius * register and polling the valid bit for completion. 2154194246Smarius * 2155194246Smarius * Polling mode uses the frame register but completion is indicated by 2156194246Smarius * an interrupt. 2157194246Smarius * 2158194246Smarius */ 2159194246Smariusstatic int 2160194246Smariuscas_mii_readreg(device_t dev, int phy, int reg) 2161194246Smarius{ 2162194246Smarius struct cas_softc *sc; 2163194246Smarius int n; 2164194246Smarius uint32_t v; 2165194246Smarius 2166194246Smarius#ifdef CAS_DEBUG_PHY 2167194246Smarius printf("%s: phy %d reg %d\n", __func__, phy, reg); 2168194246Smarius#endif 2169194246Smarius 2170194246Smarius sc = device_get_softc(dev); 2171194246Smarius if ((sc->sc_flags & CAS_SERDES) != 0) { 2172194246Smarius switch (reg) { 2173194246Smarius case MII_BMCR: 2174194246Smarius reg = CAS_PCS_CTRL; 2175194246Smarius break; 2176194246Smarius case MII_BMSR: 2177194246Smarius reg = CAS_PCS_STATUS; 2178194246Smarius break; 2179194246Smarius case MII_PHYIDR1: 2180194246Smarius case MII_PHYIDR2: 2181194246Smarius return (0); 2182194246Smarius case MII_ANAR: 2183194246Smarius reg = CAS_PCS_ANAR; 2184194246Smarius break; 2185194246Smarius case MII_ANLPAR: 2186194246Smarius reg = CAS_PCS_ANLPAR; 2187194246Smarius break; 2188194246Smarius case MII_EXTSR: 2189194246Smarius return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2190194246Smarius default: 2191194246Smarius device_printf(sc->sc_dev, 2192194246Smarius "%s: unhandled register %d\n", __func__, reg); 2193194246Smarius return (0); 2194194246Smarius } 2195194246Smarius return (CAS_READ_4(sc, reg)); 2196194246Smarius } 2197194246Smarius 2198194246Smarius /* Construct the frame command. */ 2199194246Smarius v = CAS_MIF_FRAME_READ | 2200194246Smarius (phy << CAS_MIF_FRAME_PHY_SHFT) | 2201194246Smarius (reg << CAS_MIF_FRAME_REG_SHFT); 2202194246Smarius 2203194246Smarius CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2204194246Smarius CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2205194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2206194246Smarius for (n = 0; n < 100; n++) { 2207194246Smarius DELAY(1); 2208194246Smarius v = CAS_READ_4(sc, CAS_MIF_FRAME); 2209194246Smarius if (v & CAS_MIF_FRAME_TA_LSB) 2210194246Smarius return (v & CAS_MIF_FRAME_DATA); 2211194246Smarius } 2212194246Smarius 2213194246Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2214194246Smarius return (0); 2215194246Smarius} 2216194246Smarius 2217194246Smariusstatic int 2218194246Smariuscas_mii_writereg(device_t dev, int phy, int reg, int val) 2219194246Smarius{ 2220194246Smarius struct cas_softc *sc; 2221194246Smarius int n; 2222194246Smarius uint32_t v; 2223194246Smarius 2224194246Smarius#ifdef CAS_DEBUG_PHY 2225194246Smarius printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2226194246Smarius#endif 2227194246Smarius 2228194246Smarius sc = device_get_softc(dev); 2229194246Smarius if ((sc->sc_flags & CAS_SERDES) != 0) { 2230194246Smarius switch (reg) { 2231194246Smarius case MII_BMSR: 2232194246Smarius reg = CAS_PCS_STATUS; 2233194246Smarius break; 2234194246Smarius case MII_BMCR: 2235194246Smarius reg = CAS_PCS_CTRL; 2236194246Smarius if ((val & CAS_PCS_CTRL_RESET) == 0) 2237194246Smarius break; 2238194246Smarius CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2239194246Smarius CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2240194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2241194246Smarius if (!cas_bitwait(sc, CAS_PCS_CTRL, 2242194246Smarius CAS_PCS_CTRL_RESET, 0)) 2243194246Smarius device_printf(sc->sc_dev, 2244194246Smarius "cannot reset PCS\n"); 2245194246Smarius /* FALLTHROUGH */ 2246194246Smarius case MII_ANAR: 2247194246Smarius CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2248194246Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2249194246Smarius BUS_SPACE_BARRIER_WRITE); 2250194246Smarius CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2251207585Smarius CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2252207585Smarius BUS_SPACE_BARRIER_WRITE); 2253194246Smarius CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2254194246Smarius CAS_PCS_SERDES_CTRL_ESD); 2255207585Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2256207585Smarius BUS_SPACE_BARRIER_WRITE); 2257194246Smarius CAS_WRITE_4(sc, CAS_PCS_CONF, 2258194246Smarius CAS_PCS_CONF_EN); 2259207585Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2260207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2261194246Smarius return (0); 2262194246Smarius case MII_ANLPAR: 2263194246Smarius reg = CAS_PCS_ANLPAR; 2264194246Smarius break; 2265194246Smarius default: 2266194246Smarius device_printf(sc->sc_dev, 2267194246Smarius "%s: unhandled register %d\n", __func__, reg); 2268194246Smarius return (0); 2269194246Smarius } 2270194246Smarius CAS_WRITE_4(sc, reg, val); 2271207585Smarius CAS_BARRIER(sc, reg, 4, 2272207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2273194246Smarius return (0); 2274194246Smarius } 2275194246Smarius 2276194246Smarius /* Construct the frame command. */ 2277194246Smarius v = CAS_MIF_FRAME_WRITE | 2278194246Smarius (phy << CAS_MIF_FRAME_PHY_SHFT) | 2279194246Smarius (reg << CAS_MIF_FRAME_REG_SHFT) | 2280194246Smarius (val & CAS_MIF_FRAME_DATA); 2281194246Smarius 2282194246Smarius CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2283194246Smarius CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2284194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2285194246Smarius for (n = 0; n < 100; n++) { 2286194246Smarius DELAY(1); 2287194246Smarius v = CAS_READ_4(sc, CAS_MIF_FRAME); 2288194246Smarius if (v & CAS_MIF_FRAME_TA_LSB) 2289194246Smarius return (1); 2290194246Smarius } 2291194246Smarius 2292194246Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2293194246Smarius return (0); 2294194246Smarius} 2295194246Smarius 2296194246Smariusstatic void 2297194246Smariuscas_mii_statchg(device_t dev) 2298194246Smarius{ 2299194246Smarius struct cas_softc *sc; 2300194246Smarius struct ifnet *ifp; 2301194246Smarius int gigabit; 2302194246Smarius uint32_t rxcfg, txcfg, v; 2303194246Smarius 2304194246Smarius sc = device_get_softc(dev); 2305194246Smarius ifp = sc->sc_ifp; 2306194246Smarius 2307194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 2308194246Smarius 2309194246Smarius#ifdef CAS_DEBUG 2310194246Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) 2311213893Smarius device_printf(sc->sc_dev, "%s: status changen", __func__); 2312194246Smarius#endif 2313194246Smarius 2314194246Smarius if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2315194246Smarius IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2316194246Smarius sc->sc_flags |= CAS_LINK; 2317194246Smarius else 2318194246Smarius sc->sc_flags &= ~CAS_LINK; 2319194246Smarius 2320194246Smarius switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2321194246Smarius case IFM_1000_SX: 2322194246Smarius case IFM_1000_LX: 2323194246Smarius case IFM_1000_CX: 2324194246Smarius case IFM_1000_T: 2325194246Smarius gigabit = 1; 2326194246Smarius break; 2327194246Smarius default: 2328194246Smarius gigabit = 0; 2329194246Smarius } 2330194246Smarius 2331194246Smarius /* 2332194246Smarius * The configuration done here corresponds to the steps F) and 2333194246Smarius * G) and as far as enabling of RX and TX MAC goes also step H) 2334194246Smarius * of the initialization sequence outlined in section 11.2.1 of 2335194246Smarius * the Cassini+ ASIC Specification. 2336194246Smarius */ 2337194246Smarius 2338223951Smarius rxcfg = sc->sc_mac_rxcfg; 2339223951Smarius rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2340194246Smarius txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2341194246Smarius CAS_MAC_TX_CONF_NGUL; 2342194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2343194246Smarius txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2344194246Smarius else if (gigabit != 0) { 2345194246Smarius rxcfg |= CAS_MAC_RX_CONF_CARR; 2346194246Smarius txcfg |= CAS_MAC_TX_CONF_CARR; 2347194246Smarius } 2348223951Smarius (void)cas_disable_tx(sc); 2349194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2350223951Smarius (void)cas_disable_rx(sc); 2351194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2352194246Smarius 2353194246Smarius v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2354194246Smarius ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2355194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2356194246Smarius IFM_ETH_RXPAUSE) != 0) 2357194246Smarius v |= CAS_MAC_CTRL_CONF_RXP; 2358194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2359194246Smarius IFM_ETH_TXPAUSE) != 0) 2360194246Smarius v |= CAS_MAC_CTRL_CONF_TXP; 2361194246Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2362194246Smarius 2363194246Smarius /* 2364194246Smarius * All supported chips have a bug causing incorrect checksum 2365194246Smarius * to be calculated when letting them strip the FCS in half- 2366194246Smarius * duplex mode. In theory we could disable FCS stripping and 2367194246Smarius * manually adjust the checksum accordingly. It seems to make 2368194246Smarius * more sense to optimze for the common case and just disable 2369194246Smarius * hardware checksumming in half-duplex mode though. 2370194246Smarius */ 2371194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2372194246Smarius ifp->if_capenable &= ~IFCAP_HWCSUM; 2373194246Smarius ifp->if_hwassist = 0; 2374194246Smarius } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2375194246Smarius ifp->if_capenable = ifp->if_capabilities; 2376194246Smarius ifp->if_hwassist = CAS_CSUM_FEATURES; 2377194246Smarius } 2378194246Smarius 2379194246Smarius if (sc->sc_variant == CAS_SATURN) { 2380194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2381194246Smarius /* silicon bug workaround */ 2382194246Smarius CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2383194246Smarius else 2384194246Smarius CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2385194246Smarius } 2386194246Smarius 2387194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2388194246Smarius gigabit != 0) 2389194246Smarius CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2390194246Smarius CAS_MAC_SLOT_TIME_CARR); 2391194246Smarius else 2392194246Smarius CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2393194246Smarius CAS_MAC_SLOT_TIME_NORM); 2394194246Smarius 2395194246Smarius /* XIF Configuration */ 2396194246Smarius v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2397194246Smarius if ((sc->sc_flags & CAS_SERDES) == 0) { 2398194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2399194246Smarius v |= CAS_MAC_XIF_CONF_NOECHO; 2400194246Smarius v |= CAS_MAC_XIF_CONF_BUF_OE; 2401194246Smarius } 2402194246Smarius if (gigabit != 0) 2403194246Smarius v |= CAS_MAC_XIF_CONF_GMII; 2404194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2405194246Smarius v |= CAS_MAC_XIF_CONF_FDXLED; 2406194246Smarius CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2407194246Smarius 2408223951Smarius sc->sc_mac_rxcfg = rxcfg; 2409223986Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2410194246Smarius (sc->sc_flags & CAS_LINK) != 0) { 2411194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2412194246Smarius txcfg | CAS_MAC_TX_CONF_EN); 2413194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2414194246Smarius rxcfg | CAS_MAC_RX_CONF_EN); 2415194246Smarius } 2416194246Smarius} 2417194246Smarius 2418194246Smariusstatic int 2419194246Smariuscas_mediachange(struct ifnet *ifp) 2420194246Smarius{ 2421194246Smarius struct cas_softc *sc = ifp->if_softc; 2422194246Smarius int error; 2423194246Smarius 2424194246Smarius /* XXX add support for serial media. */ 2425194246Smarius 2426194246Smarius CAS_LOCK(sc); 2427194246Smarius error = mii_mediachg(sc->sc_mii); 2428194246Smarius CAS_UNLOCK(sc); 2429194246Smarius return (error); 2430194246Smarius} 2431194246Smarius 2432194246Smariusstatic void 2433194246Smariuscas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2434194246Smarius{ 2435194246Smarius struct cas_softc *sc = ifp->if_softc; 2436194246Smarius 2437194246Smarius CAS_LOCK(sc); 2438194246Smarius if ((ifp->if_flags & IFF_UP) == 0) { 2439194246Smarius CAS_UNLOCK(sc); 2440194246Smarius return; 2441194246Smarius } 2442194246Smarius 2443194246Smarius mii_pollstat(sc->sc_mii); 2444194246Smarius ifmr->ifm_active = sc->sc_mii->mii_media_active; 2445194246Smarius ifmr->ifm_status = sc->sc_mii->mii_media_status; 2446194246Smarius CAS_UNLOCK(sc); 2447194246Smarius} 2448194246Smarius 2449194246Smariusstatic int 2450194246Smariuscas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2451194246Smarius{ 2452194246Smarius struct cas_softc *sc = ifp->if_softc; 2453194246Smarius struct ifreq *ifr = (struct ifreq *)data; 2454194246Smarius int error; 2455194246Smarius 2456194246Smarius error = 0; 2457194246Smarius switch (cmd) { 2458194246Smarius case SIOCSIFFLAGS: 2459194246Smarius CAS_LOCK(sc); 2460194246Smarius if ((ifp->if_flags & IFF_UP) != 0) { 2461194246Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2462194246Smarius ((ifp->if_flags ^ sc->sc_ifflags) & 2463194246Smarius (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2464194246Smarius cas_setladrf(sc); 2465194246Smarius else 2466194246Smarius cas_init_locked(sc); 2467194246Smarius } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2468194246Smarius cas_stop(ifp); 2469194246Smarius sc->sc_ifflags = ifp->if_flags; 2470194246Smarius CAS_UNLOCK(sc); 2471194246Smarius break; 2472194246Smarius case SIOCSIFCAP: 2473194246Smarius CAS_LOCK(sc); 2474194246Smarius if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2475194246Smarius error = EINVAL; 2476194246Smarius CAS_UNLOCK(sc); 2477194246Smarius break; 2478194246Smarius } 2479194246Smarius ifp->if_capenable = ifr->ifr_reqcap; 2480194246Smarius if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2481194246Smarius ifp->if_hwassist = CAS_CSUM_FEATURES; 2482194246Smarius else 2483194246Smarius ifp->if_hwassist = 0; 2484194246Smarius CAS_UNLOCK(sc); 2485194246Smarius break; 2486194246Smarius case SIOCADDMULTI: 2487194246Smarius case SIOCDELMULTI: 2488194246Smarius CAS_LOCK(sc); 2489194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2490194904Smarius cas_setladrf(sc); 2491194246Smarius CAS_UNLOCK(sc); 2492194246Smarius break; 2493194246Smarius case SIOCSIFMTU: 2494194246Smarius if ((ifr->ifr_mtu < ETHERMIN) || 2495194246Smarius (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2496194246Smarius error = EINVAL; 2497194246Smarius else 2498194246Smarius ifp->if_mtu = ifr->ifr_mtu; 2499194246Smarius break; 2500194246Smarius case SIOCGIFMEDIA: 2501194246Smarius case SIOCSIFMEDIA: 2502194246Smarius error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2503194246Smarius break; 2504194246Smarius default: 2505194246Smarius error = ether_ioctl(ifp, cmd, data); 2506194246Smarius break; 2507194246Smarius } 2508194246Smarius 2509194246Smarius return (error); 2510194246Smarius} 2511194246Smarius 2512194246Smariusstatic void 2513194246Smariuscas_setladrf(struct cas_softc *sc) 2514194246Smarius{ 2515194246Smarius struct ifnet *ifp = sc->sc_ifp; 2516194246Smarius struct ifmultiaddr *inm; 2517194246Smarius int i; 2518194246Smarius uint32_t hash[16]; 2519194246Smarius uint32_t crc, v; 2520194246Smarius 2521194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 2522194246Smarius 2523194246Smarius /* 2524223951Smarius * Turn off the RX MAC and the hash filter as required by the Sun 2525223951Smarius * Cassini programming restrictions. 2526194246Smarius */ 2527223951Smarius v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2528223951Smarius CAS_MAC_RX_CONF_EN); 2529194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2530194246Smarius CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2531194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2532223951Smarius if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2533223951Smarius CAS_MAC_RX_CONF_EN, 0)) 2534223951Smarius device_printf(sc->sc_dev, 2535223951Smarius "cannot disable RX MAC or hash filter\n"); 2536194246Smarius 2537223951Smarius v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2538194246Smarius if ((ifp->if_flags & IFF_PROMISC) != 0) { 2539194246Smarius v |= CAS_MAC_RX_CONF_PROMISC; 2540194246Smarius goto chipit; 2541194246Smarius } 2542194246Smarius if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2543194246Smarius v |= CAS_MAC_RX_CONF_PGRP; 2544194246Smarius goto chipit; 2545194246Smarius } 2546194246Smarius 2547194246Smarius /* 2548194246Smarius * Set up multicast address filter by passing all multicast 2549194246Smarius * addresses through a crc generator, and then using the high 2550194246Smarius * order 8 bits as an index into the 256 bit logical address 2551194246Smarius * filter. The high order 4 bits selects the word, while the 2552194246Smarius * other 4 bits select the bit within the word (where bit 0 2553194246Smarius * is the MSB). 2554194246Smarius */ 2555194246Smarius 2556194246Smarius /* Clear the hash table. */ 2557194246Smarius memset(hash, 0, sizeof(hash)); 2558194246Smarius 2559195049Srwatson if_maddr_rlock(ifp); 2560194246Smarius TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2561194246Smarius if (inm->ifma_addr->sa_family != AF_LINK) 2562194246Smarius continue; 2563194246Smarius crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2564194246Smarius inm->ifma_addr), ETHER_ADDR_LEN); 2565194246Smarius 2566194246Smarius /* We just want the 8 most significant bits. */ 2567194246Smarius crc >>= 24; 2568194246Smarius 2569194246Smarius /* Set the corresponding bit in the filter. */ 2570194246Smarius hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2571194246Smarius } 2572195049Srwatson if_maddr_runlock(ifp); 2573194246Smarius 2574194246Smarius v |= CAS_MAC_RX_CONF_HFILTER; 2575194246Smarius 2576194246Smarius /* Now load the hash table into the chip (if we are using it). */ 2577194246Smarius for (i = 0; i < 16; i++) 2578194246Smarius CAS_WRITE_4(sc, 2579194246Smarius CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2580194246Smarius hash[i]); 2581194246Smarius 2582194246Smarius chipit: 2583223951Smarius sc->sc_mac_rxcfg = v; 2584223951Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2585194246Smarius} 2586194246Smarius 2587194246Smariusstatic int cas_pci_attach(device_t dev); 2588194246Smariusstatic int cas_pci_detach(device_t dev); 2589194246Smariusstatic int cas_pci_probe(device_t dev); 2590194246Smariusstatic int cas_pci_resume(device_t dev); 2591194246Smariusstatic int cas_pci_suspend(device_t dev); 2592194246Smarius 2593194246Smariusstatic device_method_t cas_pci_methods[] = { 2594194246Smarius /* Device interface */ 2595194246Smarius DEVMETHOD(device_probe, cas_pci_probe), 2596194246Smarius DEVMETHOD(device_attach, cas_pci_attach), 2597194246Smarius DEVMETHOD(device_detach, cas_pci_detach), 2598194246Smarius DEVMETHOD(device_suspend, cas_pci_suspend), 2599194246Smarius DEVMETHOD(device_resume, cas_pci_resume), 2600194246Smarius /* Use the suspend handler here, it is all that is required. */ 2601194246Smarius DEVMETHOD(device_shutdown, cas_pci_suspend), 2602194246Smarius 2603194246Smarius /* MII interface */ 2604194246Smarius DEVMETHOD(miibus_readreg, cas_mii_readreg), 2605194246Smarius DEVMETHOD(miibus_writereg, cas_mii_writereg), 2606194246Smarius DEVMETHOD(miibus_statchg, cas_mii_statchg), 2607194246Smarius 2608227843Smarius DEVMETHOD_END 2609194246Smarius}; 2610194246Smarius 2611194246Smariusstatic driver_t cas_pci_driver = { 2612194246Smarius "cas", 2613194246Smarius cas_pci_methods, 2614194246Smarius sizeof(struct cas_softc) 2615194246Smarius}; 2616194246Smarius 2617194246SmariusDRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2618194246SmariusDRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2619194246SmariusMODULE_DEPEND(cas, pci, 1, 1, 1); 2620194246Smarius 2621194246Smariusstatic const struct cas_pci_dev { 2622194246Smarius uint32_t cpd_devid; 2623194246Smarius uint8_t cpd_revid; 2624194246Smarius int cpd_variant; 2625194246Smarius const char *cpd_desc; 2626194246Smarius} const cas_pci_devlist[] = { 2627194246Smarius { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2628194246Smarius { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2629194246Smarius { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2630194246Smarius { 0, 0, 0, NULL } 2631194246Smarius}; 2632194246Smarius 2633194246Smariusstatic int 2634194246Smariuscas_pci_probe(device_t dev) 2635194246Smarius{ 2636194246Smarius int i; 2637194246Smarius 2638194246Smarius for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2639194246Smarius if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2640194246Smarius pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2641194246Smarius device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2642194246Smarius return (BUS_PROBE_DEFAULT); 2643194246Smarius } 2644194246Smarius } 2645194246Smarius 2646194246Smarius return (ENXIO); 2647194246Smarius} 2648194246Smarius 2649194246Smariusstatic struct resource_spec cas_pci_res_spec[] = { 2650194246Smarius { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2651194246Smarius { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2652194246Smarius { -1, 0 } 2653194246Smarius}; 2654194246Smarius 2655207585Smarius#define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2656207585Smarius#define CAS_PHY_INTERFACE "phy-interface" 2657207585Smarius#define CAS_PHY_TYPE "phy-type" 2658207585Smarius#define CAS_PHY_TYPE_PCS "pcs" 2659207585Smarius 2660194246Smariusstatic int 2661194246Smariuscas_pci_attach(device_t dev) 2662194246Smarius{ 2663207585Smarius char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2664194246Smarius struct cas_softc *sc; 2665194246Smarius int i; 2666194246Smarius#if !(defined(__powerpc__) || defined(__sparc64__)) 2667194246Smarius u_char enaddr[4][ETHER_ADDR_LEN]; 2668207585Smarius u_int j, k, lma, pcs[4], phy; 2669194246Smarius#endif 2670194246Smarius 2671194246Smarius sc = device_get_softc(dev); 2672194246Smarius sc->sc_variant = CAS_UNKNOWN; 2673194246Smarius for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2674194246Smarius if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2675194246Smarius pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2676194246Smarius sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2677194246Smarius break; 2678194246Smarius } 2679194246Smarius } 2680194246Smarius if (sc->sc_variant == CAS_UNKNOWN) { 2681194246Smarius device_printf(dev, "unknown adaptor\n"); 2682194246Smarius return (ENXIO); 2683194246Smarius } 2684194246Smarius 2685194246Smarius pci_enable_busmaster(dev); 2686194246Smarius 2687194246Smarius sc->sc_dev = dev; 2688194246Smarius if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2689194246Smarius /* Hardware checksumming may hang TX. */ 2690194246Smarius sc->sc_flags |= CAS_NO_CSUM; 2691194246Smarius if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2692194246Smarius sc->sc_flags |= CAS_REG_PLUS; 2693194246Smarius if (sc->sc_variant == CAS_CAS || 2694194246Smarius (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2695194246Smarius sc->sc_flags |= CAS_TABORT; 2696194246Smarius if (bootverbose) 2697194246Smarius device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2698194246Smarius 2699194246Smarius if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2700194246Smarius device_printf(dev, "failed to allocate resources\n"); 2701194246Smarius bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2702194246Smarius return (ENXIO); 2703194246Smarius } 2704194246Smarius 2705194246Smarius CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2706194246Smarius 2707194246Smarius#if defined(__powerpc__) || defined(__sparc64__) 2708194246Smarius OF_getetheraddr(dev, sc->sc_enaddr); 2709207585Smarius if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2710207585Smarius sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2711207585Smarius CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2712207585Smarius buf[sizeof(buf) - 1] = '\0'; 2713207585Smarius if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2714207585Smarius sc->sc_flags |= CAS_SERDES; 2715207585Smarius } 2716194246Smarius#else 2717194246Smarius /* 2718207585Smarius * Dig out VPD (vital product data) and read the MAC address as well 2719207585Smarius * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2720207585Smarius * FCode) and can't be accessed via the PCI capability pointer. 2721207585Smarius * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2722207585Smarius * in the free US Patent 7149820. 2723194246Smarius */ 2724194246Smarius 2725194246Smarius#define PCI_ROMHDR_SIZE 0x1c 2726194246Smarius#define PCI_ROMHDR_SIG 0x00 2727194246Smarius#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2728194246Smarius#define PCI_ROMHDR_PTR_DATA 0x18 2729194246Smarius#define PCI_ROM_SIZE 0x18 2730194246Smarius#define PCI_ROM_SIG 0x00 2731194246Smarius#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2732194246Smarius /* reversed */ 2733194246Smarius#define PCI_ROM_VENDOR 0x04 2734194246Smarius#define PCI_ROM_DEVICE 0x06 2735194246Smarius#define PCI_ROM_PTR_VPD 0x08 2736194246Smarius#define PCI_VPDRES_BYTE0 0x00 2737194246Smarius#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2738194246Smarius#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2739194246Smarius#define PCI_VPDRES_LARGE_LEN_LSB 0x01 2740194246Smarius#define PCI_VPDRES_LARGE_LEN_MSB 0x02 2741194246Smarius#define PCI_VPDRES_LARGE_SIZE 0x03 2742194246Smarius#define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2743194246Smarius#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2744194246Smarius#define PCI_VPD_KEY0 0x00 2745194246Smarius#define PCI_VPD_KEY1 0x01 2746194246Smarius#define PCI_VPD_LEN 0x02 2747194246Smarius#define PCI_VPD_SIZE 0x03 2748194246Smarius 2749194246Smarius#define CAS_ROM_READ_1(sc, offs) \ 2750194246Smarius CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2751194246Smarius#define CAS_ROM_READ_2(sc, offs) \ 2752194246Smarius CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2753194246Smarius#define CAS_ROM_READ_4(sc, offs) \ 2754194246Smarius CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2755194246Smarius 2756207585Smarius lma = phy = 0; 2757207585Smarius memset(enaddr, 0, sizeof(enaddr)); 2758207585Smarius memset(pcs, 0, sizeof(pcs)); 2759207585Smarius 2760194246Smarius /* Enable PCI Expansion ROM access. */ 2761194246Smarius CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2762194246Smarius CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2763194246Smarius 2764194246Smarius /* Read PCI Expansion ROM header. */ 2765194246Smarius if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2766194246Smarius (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2767194246Smarius PCI_ROMHDR_SIZE) { 2768194246Smarius device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2769194246Smarius goto fail_prom; 2770194246Smarius } 2771194246Smarius 2772194246Smarius /* Read PCI Expansion ROM data. */ 2773194246Smarius if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2774194246Smarius CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2775194246Smarius CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2776194246Smarius (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2777194246Smarius i + PCI_ROM_SIZE) { 2778194246Smarius device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2779194246Smarius goto fail_prom; 2780194246Smarius } 2781194246Smarius 2782194246Smarius /* Read PCI VPD. */ 2783194246Smarius next: 2784194246Smarius if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2785194246Smarius j + PCI_VPDRES_BYTE0)) == 0) { 2786194246Smarius device_printf(dev, "no large PCI VPD\n"); 2787194246Smarius goto fail_prom; 2788194246Smarius } 2789194246Smarius 2790194246Smarius i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2791194246Smarius CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2792194246Smarius switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2793194246Smarius j + PCI_VPDRES_BYTE0))) { 2794194246Smarius case PCI_VPDRES_TYPE_ID_STRING: 2795194246Smarius /* Skip identifier string. */ 2796194246Smarius j += PCI_VPDRES_LARGE_SIZE + i; 2797194246Smarius goto next; 2798194246Smarius case PCI_VPDRES_TYPE_VPD: 2799194246Smarius for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2800194246Smarius i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2801194246Smarius j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2802194246Smarius if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2803194246Smarius /* no Enhanced VPD */ 2804194246Smarius continue; 2805194246Smarius if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2806194246Smarius /* no instance property */ 2807194246Smarius continue; 2808207585Smarius if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2809207585Smarius /* byte array */ 2810207585Smarius if (CAS_ROM_READ_1(sc, 2811207585Smarius j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2812207585Smarius continue; 2813207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2814207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2815207585Smarius buf, sizeof(buf)); 2816207585Smarius buf[sizeof(buf) - 1] = '\0'; 2817207585Smarius if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2818207585Smarius continue; 2819207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2820207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2821207585Smarius 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2822207585Smarius enaddr[lma], sizeof(enaddr[lma])); 2823207585Smarius lma++; 2824207585Smarius if (lma == 4 && phy == 4) 2825207585Smarius break; 2826207585Smarius } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2827207585Smarius 'S') { 2828207585Smarius /* string */ 2829207585Smarius if (CAS_ROM_READ_1(sc, 2830207585Smarius j + PCI_VPD_SIZE + 4) != 2831207585Smarius sizeof(CAS_PHY_TYPE_PCS)) 2832207585Smarius continue; 2833207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2834207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2835207585Smarius buf, sizeof(buf)); 2836207585Smarius buf[sizeof(buf) - 1] = '\0'; 2837207585Smarius if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2838207585Smarius k = sizeof(CAS_PHY_INTERFACE); 2839207585Smarius else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2840207585Smarius k = sizeof(CAS_PHY_TYPE); 2841207585Smarius else 2842207585Smarius continue; 2843207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2844207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2845207585Smarius 5 + k, buf, sizeof(buf)); 2846207585Smarius buf[sizeof(buf) - 1] = '\0'; 2847207585Smarius if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2848207585Smarius pcs[phy] = 1; 2849207585Smarius phy++; 2850207585Smarius if (lma == 4 && phy == 4) 2851207585Smarius break; 2852207585Smarius } 2853194246Smarius } 2854194246Smarius break; 2855194246Smarius default: 2856194246Smarius device_printf(dev, "unexpected PCI VPD\n"); 2857194246Smarius goto fail_prom; 2858194246Smarius } 2859194246Smarius 2860194246Smarius fail_prom: 2861194246Smarius CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2862194246Smarius 2863207585Smarius if (lma == 0) { 2864194246Smarius device_printf(dev, "could not determine Ethernet address\n"); 2865194246Smarius goto fail; 2866194246Smarius } 2867194246Smarius i = 0; 2868207585Smarius if (lma > 1 && pci_get_slot(dev) < sizeof(enaddr) / sizeof(*enaddr)) 2869194246Smarius i = pci_get_slot(dev); 2870194246Smarius memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2871207585Smarius 2872207585Smarius if (phy == 0) { 2873207585Smarius device_printf(dev, "could not determine PHY type\n"); 2874207585Smarius goto fail; 2875207585Smarius } 2876207585Smarius i = 0; 2877207585Smarius if (phy > 1 && pci_get_slot(dev) < sizeof(pcs) / sizeof(*pcs)) 2878207585Smarius i = pci_get_slot(dev); 2879207585Smarius if (pcs[i] != 0) 2880207585Smarius sc->sc_flags |= CAS_SERDES; 2881194246Smarius#endif 2882194246Smarius 2883194246Smarius if (cas_attach(sc) != 0) { 2884194246Smarius device_printf(dev, "could not be attached\n"); 2885194246Smarius goto fail; 2886194246Smarius } 2887194246Smarius 2888194246Smarius if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2889194904Smarius INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2890194246Smarius device_printf(dev, "failed to set up interrupt\n"); 2891194246Smarius cas_detach(sc); 2892194246Smarius goto fail; 2893194246Smarius } 2894194246Smarius return (0); 2895194246Smarius 2896194246Smarius fail: 2897194246Smarius CAS_LOCK_DESTROY(sc); 2898194246Smarius bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2899194246Smarius return (ENXIO); 2900194246Smarius} 2901194246Smarius 2902194246Smariusstatic int 2903194246Smariuscas_pci_detach(device_t dev) 2904194246Smarius{ 2905194246Smarius struct cas_softc *sc; 2906194246Smarius 2907194246Smarius sc = device_get_softc(dev); 2908194246Smarius bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2909194246Smarius cas_detach(sc); 2910194246Smarius CAS_LOCK_DESTROY(sc); 2911194246Smarius bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2912194246Smarius return (0); 2913194246Smarius} 2914194246Smarius 2915194246Smariusstatic int 2916194246Smariuscas_pci_suspend(device_t dev) 2917194246Smarius{ 2918194246Smarius 2919194246Smarius cas_suspend(device_get_softc(dev)); 2920194246Smarius return (0); 2921194246Smarius} 2922194246Smarius 2923194246Smariusstatic int 2924194246Smariuscas_pci_resume(device_t dev) 2925194246Smarius{ 2926194246Smarius 2927194246Smarius cas_resume(device_get_softc(dev)); 2928194246Smarius return (0); 2929194246Smarius} 2930