1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35/* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40#if 0 41#define CAS_DEBUG 42#endif 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/callout.h> 48#include <sys/endian.h> 49#include <sys/mbuf.h> 50#include <sys/malloc.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/module.h> 54#include <sys/mutex.h> 55#include <sys/refcount.h> 56#include <sys/resource.h> 57#include <sys/rman.h> 58#include <sys/socket.h> 59#include <sys/sockio.h> 60#include <sys/taskqueue.h> 61 62#include <net/bpf.h> 63#include <net/ethernet.h> 64#include <net/if.h> 65#include <net/if_var.h> 66#include <net/if_arp.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_types.h> 70#include <net/if_vlan_var.h> 71 72#include <netinet/in.h> 73#include <netinet/in_systm.h> 74#include <netinet/ip.h> 75#include <netinet/tcp.h> 76#include <netinet/udp.h> 77 78#include <machine/bus.h> 79#if defined(__powerpc__) || defined(__sparc64__) 80#include <dev/ofw/ofw_bus.h> 81#include <dev/ofw/openfirm.h> 82#include <machine/ofw_machdep.h> 83#endif 84#include <machine/resource.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88 89#include <dev/cas/if_casreg.h> 90#include <dev/cas/if_casvar.h> 91 92#include <dev/pci/pcireg.h> 93#include <dev/pci/pcivar.h> 94 95#include "miibus_if.h" 96 97#define RINGASSERT(n , min, max) \ 98 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 99 100RINGASSERT(CAS_NRXCOMP, 128, 32768); 101RINGASSERT(CAS_NRXDESC, 32, 8192); 102RINGASSERT(CAS_NRXDESC2, 32, 8192); 103RINGASSERT(CAS_NTXDESC, 32, 8192); 104 105#undef RINGASSERT 106 107#define CCDASSERT(m, a) \ 108 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 109 110CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 111CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 112CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 113 114#undef CCDASSERT 115 116#define CAS_TRIES 10000 117 118/* 119 * According to documentation, the hardware has support for basic TCP 120 * checksum offloading only, in practice this can be also used for UDP 121 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 122 * is not converted to 0xffff no longer exists). 123 */ 124#define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 125 126static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 127static int cas_attach(struct cas_softc *sc); 128static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 129 uint32_t set); 130static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 131 int nsegs, int error); 132static void cas_detach(struct cas_softc *sc); 133static int cas_disable_rx(struct cas_softc *sc); 134static int cas_disable_tx(struct cas_softc *sc); 135static void cas_eint(struct cas_softc *sc, u_int status); 136static void cas_free(struct mbuf *m, void *arg1, void* arg2); 137static void cas_init(void *xsc); 138static void cas_init_locked(struct cas_softc *sc); 139static void cas_init_regs(struct cas_softc *sc); 140static int cas_intr(void *v); 141static void cas_intr_task(void *arg, int pending __unused); 142static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 143static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 144static int cas_mediachange(struct ifnet *ifp); 145static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 146static void cas_meminit(struct cas_softc *sc); 147static void cas_mifinit(struct cas_softc *sc); 148static int cas_mii_readreg(device_t dev, int phy, int reg); 149static void cas_mii_statchg(device_t dev); 150static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 151static void cas_reset(struct cas_softc *sc); 152static int cas_reset_rx(struct cas_softc *sc); 153static int cas_reset_tx(struct cas_softc *sc); 154static void cas_resume(struct cas_softc *sc); 155static u_int cas_descsize(u_int sz); 156static void cas_rint(struct cas_softc *sc); 157static void cas_rint_timeout(void *arg); 158static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 159static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 160static u_int cas_rxcompsize(u_int sz); 161static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 162 int nsegs, int error); 163static void cas_setladrf(struct cas_softc *sc); 164static void cas_start(struct ifnet *ifp); 165static void cas_stop(struct ifnet *ifp); 166static void cas_suspend(struct cas_softc *sc); 167static void cas_tick(void *arg); 168static void cas_tint(struct cas_softc *sc); 169static void cas_tx_task(void *arg, int pending __unused); 170static inline void cas_txkick(struct cas_softc *sc); 171static void cas_watchdog(struct cas_softc *sc); 172 173static devclass_t cas_devclass; 174 175MODULE_DEPEND(cas, ether, 1, 1, 1); 176MODULE_DEPEND(cas, miibus, 1, 1, 1); 177 178#ifdef CAS_DEBUG 179#include <sys/ktr.h> 180#define KTR_CAS KTR_SPARE2 181#endif 182 183static int 184cas_attach(struct cas_softc *sc) 185{ 186 struct cas_txsoft *txs; 187 struct ifnet *ifp; 188 int error, i; 189 uint32_t v; 190 191 /* Set up ifnet structure. */ 192 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 193 if (ifp == NULL) 194 return (ENOSPC); 195 ifp->if_softc = sc; 196 if_initname(ifp, device_get_name(sc->sc_dev), 197 device_get_unit(sc->sc_dev)); 198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 199 ifp->if_start = cas_start; 200 ifp->if_ioctl = cas_ioctl; 201 ifp->if_init = cas_init; 202 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 203 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 204 IFQ_SET_READY(&ifp->if_snd); 205 206 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 207 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 208 /* Create local taskq. */ 209 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 210 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 211 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 212 taskqueue_thread_enqueue, &sc->sc_tq); 213 if (sc->sc_tq == NULL) { 214 device_printf(sc->sc_dev, "could not create taskqueue\n"); 215 error = ENXIO; 216 goto fail_ifnet; 217 } 218 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 219 device_get_nameunit(sc->sc_dev)); 220 if (error != 0) { 221 device_printf(sc->sc_dev, "could not start threads\n"); 222 goto fail_taskq; 223 } 224 225 /* Make sure the chip is stopped. */ 226 cas_reset(sc); 227 228 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 229 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 230 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 231 &sc->sc_pdmatag); 232 if (error != 0) 233 goto fail_taskq; 234 235 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 237 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 238 if (error != 0) 239 goto fail_ptag; 240 241 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 242 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 243 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 244 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 245 if (error != 0) 246 goto fail_rtag; 247 248 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 249 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 250 sizeof(struct cas_control_data), 1, 251 sizeof(struct cas_control_data), 0, 252 NULL, NULL, &sc->sc_cdmatag); 253 if (error != 0) 254 goto fail_ttag; 255 256 /* 257 * Allocate the control data structures, create and load the 258 * DMA map for it. 259 */ 260 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 261 (void **)&sc->sc_control_data, 262 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 263 &sc->sc_cddmamap)) != 0) { 264 device_printf(sc->sc_dev, 265 "unable to allocate control data, error = %d\n", error); 266 goto fail_ctag; 267 } 268 269 sc->sc_cddma = 0; 270 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 271 sc->sc_control_data, sizeof(struct cas_control_data), 272 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 273 device_printf(sc->sc_dev, 274 "unable to load control data DMA map, error = %d\n", 275 error); 276 goto fail_cmem; 277 } 278 279 /* 280 * Initialize the transmit job descriptors. 281 */ 282 STAILQ_INIT(&sc->sc_txfreeq); 283 STAILQ_INIT(&sc->sc_txdirtyq); 284 285 /* 286 * Create the transmit buffer DMA maps. 287 */ 288 error = ENOMEM; 289 for (i = 0; i < CAS_TXQUEUELEN; i++) { 290 txs = &sc->sc_txsoft[i]; 291 txs->txs_mbuf = NULL; 292 txs->txs_ndescs = 0; 293 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 294 &txs->txs_dmamap)) != 0) { 295 device_printf(sc->sc_dev, 296 "unable to create TX DMA map %d, error = %d\n", 297 i, error); 298 goto fail_txd; 299 } 300 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 301 } 302 303 /* 304 * Allocate the receive buffers, create and load the DMA maps 305 * for them. 306 */ 307 for (i = 0; i < CAS_NRXDESC; i++) { 308 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 309 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 310 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 311 device_printf(sc->sc_dev, 312 "unable to allocate RX buffer %d, error = %d\n", 313 i, error); 314 goto fail_rxmem; 315 } 316 317 sc->sc_rxdptr = i; 318 sc->sc_rxdsoft[i].rxds_paddr = 0; 319 if ((error = bus_dmamap_load(sc->sc_rdmatag, 320 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 321 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 322 sc->sc_rxdsoft[i].rxds_paddr == 0) { 323 device_printf(sc->sc_dev, 324 "unable to load RX DMA map %d, error = %d\n", 325 i, error); 326 goto fail_rxmap; 327 } 328 } 329 330 if ((sc->sc_flags & CAS_SERDES) == 0) { 331 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 332 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 333 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 334 cas_mifinit(sc); 335 /* 336 * Look for an external PHY. 337 */ 338 error = ENXIO; 339 v = CAS_READ_4(sc, CAS_MIF_CONF); 340 if ((v & CAS_MIF_CONF_MDI1) != 0) { 341 v |= CAS_MIF_CONF_PHY_SELECT; 342 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 343 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 344 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 345 /* Enable/unfreeze the GMII pins of Saturn. */ 346 if (sc->sc_variant == CAS_SATURN) { 347 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 348 CAS_READ_4(sc, CAS_SATURN_PCFG) & 349 ~CAS_SATURN_PCFG_FSI); 350 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 351 BUS_SPACE_BARRIER_READ | 352 BUS_SPACE_BARRIER_WRITE); 353 DELAY(10000); 354 } 355 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 356 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 357 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 358 } 359 /* 360 * Fall back on an internal PHY if no external PHY was found. 361 */ 362 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 363 v &= ~CAS_MIF_CONF_PHY_SELECT; 364 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 365 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 366 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 367 /* Freeze the GMII pins of Saturn for saving power. */ 368 if (sc->sc_variant == CAS_SATURN) { 369 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 370 CAS_READ_4(sc, CAS_SATURN_PCFG) | 371 CAS_SATURN_PCFG_FSI); 372 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 373 BUS_SPACE_BARRIER_READ | 374 BUS_SPACE_BARRIER_WRITE); 375 DELAY(10000); 376 } 377 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 378 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 379 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 380 } 381 } else { 382 /* 383 * Use the external PCS SERDES. 384 */ 385 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 386 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 387 /* Enable/unfreeze the SERDES pins of Saturn. */ 388 if (sc->sc_variant == CAS_SATURN) { 389 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 390 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 391 BUS_SPACE_BARRIER_WRITE); 392 } 393 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 394 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 395 BUS_SPACE_BARRIER_WRITE); 396 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 397 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 398 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 399 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 400 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 401 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 402 } 403 if (error != 0) { 404 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 405 goto fail_rxmap; 406 } 407 sc->sc_mii = device_get_softc(sc->sc_miibus); 408 409 /* 410 * From this point forward, the attachment cannot fail. A failure 411 * before this point releases all resources that may have been 412 * allocated. 413 */ 414 415 /* Announce FIFO sizes. */ 416 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 417 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 418 CAS_RX_FIFO_SIZE / 1024, v / 16); 419 420 /* Attach the interface. */ 421 ether_ifattach(ifp, sc->sc_enaddr); 422 423 /* 424 * Tell the upper layer(s) we support long frames/checksum offloads. 425 */ 426 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 427 ifp->if_capabilities = IFCAP_VLAN_MTU; 428 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 429 ifp->if_capabilities |= IFCAP_HWCSUM; 430 ifp->if_hwassist = CAS_CSUM_FEATURES; 431 } 432 ifp->if_capenable = ifp->if_capabilities; 433 434 return (0); 435 436 /* 437 * Free any resources we've allocated during the failed attach 438 * attempt. Do this in reverse order and fall through. 439 */ 440 fail_rxmap: 441 for (i = 0; i < CAS_NRXDESC; i++) 442 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 443 bus_dmamap_unload(sc->sc_rdmatag, 444 sc->sc_rxdsoft[i].rxds_dmamap); 445 fail_rxmem: 446 for (i = 0; i < CAS_NRXDESC; i++) 447 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 448 bus_dmamem_free(sc->sc_rdmatag, 449 sc->sc_rxdsoft[i].rxds_buf, 450 sc->sc_rxdsoft[i].rxds_dmamap); 451 fail_txd: 452 for (i = 0; i < CAS_TXQUEUELEN; i++) 453 if (sc->sc_txsoft[i].txs_dmamap != NULL) 454 bus_dmamap_destroy(sc->sc_tdmatag, 455 sc->sc_txsoft[i].txs_dmamap); 456 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 457 fail_cmem: 458 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 459 sc->sc_cddmamap); 460 fail_ctag: 461 bus_dma_tag_destroy(sc->sc_cdmatag); 462 fail_ttag: 463 bus_dma_tag_destroy(sc->sc_tdmatag); 464 fail_rtag: 465 bus_dma_tag_destroy(sc->sc_rdmatag); 466 fail_ptag: 467 bus_dma_tag_destroy(sc->sc_pdmatag); 468 fail_taskq: 469 taskqueue_free(sc->sc_tq); 470 fail_ifnet: 471 if_free(ifp); 472 return (error); 473} 474 475static void 476cas_detach(struct cas_softc *sc) 477{ 478 struct ifnet *ifp = sc->sc_ifp; 479 int i; 480 481 ether_ifdetach(ifp); 482 CAS_LOCK(sc); 483 cas_stop(ifp); 484 CAS_UNLOCK(sc); 485 callout_drain(&sc->sc_tick_ch); 486 callout_drain(&sc->sc_rx_ch); 487 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 488 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 489 if_free(ifp); 490 taskqueue_free(sc->sc_tq); 491 device_delete_child(sc->sc_dev, sc->sc_miibus); 492 493 for (i = 0; i < CAS_NRXDESC; i++) 494 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 495 bus_dmamap_sync(sc->sc_rdmatag, 496 sc->sc_rxdsoft[i].rxds_dmamap, 497 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 498 for (i = 0; i < CAS_NRXDESC; i++) 499 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 500 bus_dmamap_unload(sc->sc_rdmatag, 501 sc->sc_rxdsoft[i].rxds_dmamap); 502 for (i = 0; i < CAS_NRXDESC; i++) 503 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 504 bus_dmamem_free(sc->sc_rdmatag, 505 sc->sc_rxdsoft[i].rxds_buf, 506 sc->sc_rxdsoft[i].rxds_dmamap); 507 for (i = 0; i < CAS_TXQUEUELEN; i++) 508 if (sc->sc_txsoft[i].txs_dmamap != NULL) 509 bus_dmamap_destroy(sc->sc_tdmatag, 510 sc->sc_txsoft[i].txs_dmamap); 511 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 512 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 513 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 514 sc->sc_cddmamap); 515 bus_dma_tag_destroy(sc->sc_cdmatag); 516 bus_dma_tag_destroy(sc->sc_tdmatag); 517 bus_dma_tag_destroy(sc->sc_rdmatag); 518 bus_dma_tag_destroy(sc->sc_pdmatag); 519} 520 521static void 522cas_suspend(struct cas_softc *sc) 523{ 524 struct ifnet *ifp = sc->sc_ifp; 525 526 CAS_LOCK(sc); 527 cas_stop(ifp); 528 CAS_UNLOCK(sc); 529} 530 531static void 532cas_resume(struct cas_softc *sc) 533{ 534 struct ifnet *ifp = sc->sc_ifp; 535 536 CAS_LOCK(sc); 537 /* 538 * On resume all registers have to be initialized again like 539 * after power-on. 540 */ 541 sc->sc_flags &= ~CAS_INITED; 542 if (ifp->if_flags & IFF_UP) 543 cas_init_locked(sc); 544 CAS_UNLOCK(sc); 545} 546 547static inline void 548cas_rxcksum(struct mbuf *m, uint16_t cksum) 549{ 550 struct ether_header *eh; 551 struct ip *ip; 552 struct udphdr *uh; 553 uint16_t *opts; 554 int32_t hlen, len, pktlen; 555 uint32_t temp32; 556 557 pktlen = m->m_pkthdr.len; 558 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 559 return; 560 eh = mtod(m, struct ether_header *); 561 if (eh->ether_type != htons(ETHERTYPE_IP)) 562 return; 563 ip = (struct ip *)(eh + 1); 564 if (ip->ip_v != IPVERSION) 565 return; 566 567 hlen = ip->ip_hl << 2; 568 pktlen -= sizeof(struct ether_header); 569 if (hlen < sizeof(struct ip)) 570 return; 571 if (ntohs(ip->ip_len) < hlen) 572 return; 573 if (ntohs(ip->ip_len) != pktlen) 574 return; 575 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 576 return; /* Cannot handle fragmented packet. */ 577 578 switch (ip->ip_p) { 579 case IPPROTO_TCP: 580 if (pktlen < (hlen + sizeof(struct tcphdr))) 581 return; 582 break; 583 case IPPROTO_UDP: 584 if (pktlen < (hlen + sizeof(struct udphdr))) 585 return; 586 uh = (struct udphdr *)((uint8_t *)ip + hlen); 587 if (uh->uh_sum == 0) 588 return; /* no checksum */ 589 break; 590 default: 591 return; 592 } 593 594 cksum = ~cksum; 595 /* checksum fixup for IP options */ 596 len = hlen - sizeof(struct ip); 597 if (len > 0) { 598 opts = (uint16_t *)(ip + 1); 599 for (; len > 0; len -= sizeof(uint16_t), opts++) { 600 temp32 = cksum - *opts; 601 temp32 = (temp32 >> 16) + (temp32 & 65535); 602 cksum = temp32 & 65535; 603 } 604 } 605 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 606 m->m_pkthdr.csum_data = cksum; 607} 608 609static void 610cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 611{ 612 struct cas_softc *sc = xsc; 613 614 if (error != 0) 615 return; 616 if (nsegs != 1) 617 panic("%s: bad control buffer segment count", __func__); 618 sc->sc_cddma = segs[0].ds_addr; 619} 620 621static void 622cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 623{ 624 struct cas_softc *sc = xsc; 625 626 if (error != 0) 627 return; 628 if (nsegs != 1) 629 panic("%s: bad RX buffer segment count", __func__); 630 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 631} 632 633static void 634cas_tick(void *arg) 635{ 636 struct cas_softc *sc = arg; 637 struct ifnet *ifp = sc->sc_ifp; 638 uint32_t v; 639 640 CAS_LOCK_ASSERT(sc, MA_OWNED); 641 642 /* 643 * Unload collision and error counters. 644 */ 645 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 646 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 647 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT)); 648 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 649 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 650 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v); 651 if_inc_counter(ifp, IFCOUNTER_OERRORS, v); 652 if_inc_counter(ifp, IFCOUNTER_IERRORS, 653 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 654 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 655 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 656 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL)); 657 658 /* 659 * Then clear the hardware counters. 660 */ 661 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 662 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 663 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 664 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 665 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 666 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 667 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 668 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 669 670 mii_tick(sc->sc_mii); 671 672 if (sc->sc_txfree != CAS_MAXTXFREE) 673 cas_tint(sc); 674 675 cas_watchdog(sc); 676 677 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 678} 679 680static int 681cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 682{ 683 int i; 684 uint32_t reg; 685 686 for (i = CAS_TRIES; i--; DELAY(100)) { 687 reg = CAS_READ_4(sc, r); 688 if ((reg & clr) == 0 && (reg & set) == set) 689 return (1); 690 } 691 return (0); 692} 693 694static void 695cas_reset(struct cas_softc *sc) 696{ 697 698#ifdef CAS_DEBUG 699 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 700#endif 701 /* Disable all interrupts in order to avoid spurious ones. */ 702 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 703 704 cas_reset_rx(sc); 705 cas_reset_tx(sc); 706 707 /* 708 * Do a full reset modulo the result of the last auto-negotiation 709 * when using the SERDES. 710 */ 711 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 712 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 713 CAS_BARRIER(sc, CAS_RESET, 4, 714 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 715 DELAY(3000); 716 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 717 device_printf(sc->sc_dev, "cannot reset device\n"); 718} 719 720static void 721cas_stop(struct ifnet *ifp) 722{ 723 struct cas_softc *sc = ifp->if_softc; 724 struct cas_txsoft *txs; 725 726#ifdef CAS_DEBUG 727 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 728#endif 729 730 callout_stop(&sc->sc_tick_ch); 731 callout_stop(&sc->sc_rx_ch); 732 733 /* Disable all interrupts in order to avoid spurious ones. */ 734 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 735 736 cas_reset_tx(sc); 737 cas_reset_rx(sc); 738 739 /* 740 * Release any queued transmit buffers. 741 */ 742 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 743 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 744 if (txs->txs_ndescs != 0) { 745 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 746 BUS_DMASYNC_POSTWRITE); 747 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 748 if (txs->txs_mbuf != NULL) { 749 m_freem(txs->txs_mbuf); 750 txs->txs_mbuf = NULL; 751 } 752 } 753 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 754 } 755 756 /* 757 * Mark the interface down and cancel the watchdog timer. 758 */ 759 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 760 sc->sc_flags &= ~CAS_LINK; 761 sc->sc_wdog_timer = 0; 762} 763 764static int 765cas_reset_rx(struct cas_softc *sc) 766{ 767 768 /* 769 * Resetting while DMA is in progress can cause a bus hang, so we 770 * disable DMA first. 771 */ 772 (void)cas_disable_rx(sc); 773 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 774 CAS_BARRIER(sc, CAS_RX_CONF, 4, 775 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 776 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 777 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 778 779 /* Finally, reset the ERX. */ 780 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 781 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 782 CAS_BARRIER(sc, CAS_RESET, 4, 783 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 784 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 785 device_printf(sc->sc_dev, "cannot reset receiver\n"); 786 return (1); 787 } 788 return (0); 789} 790 791static int 792cas_reset_tx(struct cas_softc *sc) 793{ 794 795 /* 796 * Resetting while DMA is in progress can cause a bus hang, so we 797 * disable DMA first. 798 */ 799 (void)cas_disable_tx(sc); 800 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 801 CAS_BARRIER(sc, CAS_TX_CONF, 4, 802 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 803 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 804 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 805 806 /* Finally, reset the ETX. */ 807 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 808 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 809 CAS_BARRIER(sc, CAS_RESET, 4, 810 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 811 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 812 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 813 return (1); 814 } 815 return (0); 816} 817 818static int 819cas_disable_rx(struct cas_softc *sc) 820{ 821 822 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 823 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 824 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 825 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 826 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 827 return (1); 828 if (bootverbose) 829 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 830 return (0); 831} 832 833static int 834cas_disable_tx(struct cas_softc *sc) 835{ 836 837 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 838 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 839 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 840 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 841 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 842 return (1); 843 if (bootverbose) 844 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 845 return (0); 846} 847 848static inline void 849cas_rxcompinit(struct cas_rx_comp *rxcomp) 850{ 851 852 rxcomp->crc_word1 = 0; 853 rxcomp->crc_word2 = 0; 854 rxcomp->crc_word3 = 855 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 856 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 857} 858 859static void 860cas_meminit(struct cas_softc *sc) 861{ 862 int i; 863 864 CAS_LOCK_ASSERT(sc, MA_OWNED); 865 866 /* 867 * Initialize the transmit descriptor ring. 868 */ 869 for (i = 0; i < CAS_NTXDESC; i++) { 870 sc->sc_txdescs[i].cd_flags = 0; 871 sc->sc_txdescs[i].cd_buf_ptr = 0; 872 } 873 sc->sc_txfree = CAS_MAXTXFREE; 874 sc->sc_txnext = 0; 875 sc->sc_txwin = 0; 876 877 /* 878 * Initialize the receive completion ring. 879 */ 880 for (i = 0; i < CAS_NRXCOMP; i++) 881 cas_rxcompinit(&sc->sc_rxcomps[i]); 882 sc->sc_rxcptr = 0; 883 884 /* 885 * Initialize the first receive descriptor ring. We leave 886 * the second one zeroed as we don't actually use it. 887 */ 888 for (i = 0; i < CAS_NRXDESC; i++) 889 CAS_INIT_RXDESC(sc, i, i); 890 sc->sc_rxdptr = 0; 891 892 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 893} 894 895static u_int 896cas_descsize(u_int sz) 897{ 898 899 switch (sz) { 900 case 32: 901 return (CAS_DESC_32); 902 case 64: 903 return (CAS_DESC_64); 904 case 128: 905 return (CAS_DESC_128); 906 case 256: 907 return (CAS_DESC_256); 908 case 512: 909 return (CAS_DESC_512); 910 case 1024: 911 return (CAS_DESC_1K); 912 case 2048: 913 return (CAS_DESC_2K); 914 case 4096: 915 return (CAS_DESC_4K); 916 case 8192: 917 return (CAS_DESC_8K); 918 default: 919 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 920 return (CAS_DESC_32); 921 } 922} 923 924static u_int 925cas_rxcompsize(u_int sz) 926{ 927 928 switch (sz) { 929 case 128: 930 return (CAS_RX_CONF_COMP_128); 931 case 256: 932 return (CAS_RX_CONF_COMP_256); 933 case 512: 934 return (CAS_RX_CONF_COMP_512); 935 case 1024: 936 return (CAS_RX_CONF_COMP_1K); 937 case 2048: 938 return (CAS_RX_CONF_COMP_2K); 939 case 4096: 940 return (CAS_RX_CONF_COMP_4K); 941 case 8192: 942 return (CAS_RX_CONF_COMP_8K); 943 case 16384: 944 return (CAS_RX_CONF_COMP_16K); 945 case 32768: 946 return (CAS_RX_CONF_COMP_32K); 947 default: 948 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 949 return (CAS_RX_CONF_COMP_128); 950 } 951} 952 953static void 954cas_init(void *xsc) 955{ 956 struct cas_softc *sc = xsc; 957 958 CAS_LOCK(sc); 959 cas_init_locked(sc); 960 CAS_UNLOCK(sc); 961} 962 963/* 964 * Initialization of interface; set up initialization block 965 * and transmit/receive descriptor rings. 966 */ 967static void 968cas_init_locked(struct cas_softc *sc) 969{ 970 struct ifnet *ifp = sc->sc_ifp; 971 uint32_t v; 972 973 CAS_LOCK_ASSERT(sc, MA_OWNED); 974 975 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 976 return; 977 978#ifdef CAS_DEBUG 979 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 980 __func__); 981#endif 982 /* 983 * Initialization sequence. The numbered steps below correspond 984 * to the sequence outlined in section 6.3.5.1 in the Ethernet 985 * Channel Engine manual (part of the PCIO manual). 986 * See also the STP2002-STQ document from Sun Microsystems. 987 */ 988 989 /* step 1 & 2. Reset the Ethernet Channel. */ 990 cas_stop(ifp); 991 cas_reset(sc); 992#ifdef CAS_DEBUG 993 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 994 __func__); 995#endif 996 997 if ((sc->sc_flags & CAS_SERDES) == 0) 998 /* Re-initialize the MIF. */ 999 cas_mifinit(sc); 1000 1001 /* step 3. Setup data structures in host memory. */ 1002 cas_meminit(sc); 1003 1004 /* step 4. TX MAC registers & counters */ 1005 cas_init_regs(sc); 1006 1007 /* step 5. RX MAC registers & counters */ 1008 1009 /* step 6 & 7. Program Ring Base Addresses. */ 1010 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1011 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1012 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1013 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1014 1015 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1016 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1017 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1018 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1019 1020 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1021 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1022 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1023 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1024 1025 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1026 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1027 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1028 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1029 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1030 } 1031 1032#ifdef CAS_DEBUG 1033 CTR5(KTR_CAS, 1034 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1035 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1036 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1037#endif 1038 1039 /* step 8. Global Configuration & Interrupt Masks */ 1040 1041 /* Disable weighted round robin. */ 1042 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1043 1044 /* 1045 * Enable infinite bursts for revisions without PCI issues if 1046 * applicable. Doing so greatly improves the TX performance on 1047 * !__sparc64__ (on sparc64, setting CAS_INF_BURST improves TX 1048 * performance only marginally but hurts RX throughput quite a bit). 1049 */ 1050 CAS_WRITE_4(sc, CAS_INF_BURST, 1051#if !defined(__sparc64__) 1052 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1053#endif 1054 0); 1055 1056 /* Set up interrupts. */ 1057 CAS_WRITE_4(sc, CAS_INTMASK, 1058 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1059 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1060 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1061 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1062 CAS_INTR_PCI_ERROR_INT 1063#ifdef CAS_DEBUG 1064 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1065#endif 1066 )); 1067 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1068 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1069 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1070 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1071 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1072#ifdef CAS_DEBUG 1073 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1074 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1075 CAS_MAC_CTRL_NON_PAUSE)); 1076#else 1077 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1078 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1079 CAS_MAC_CTRL_NON_PAUSE); 1080#endif 1081 1082 /* Enable PCI error interrupts. */ 1083 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1084 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1085 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1086 1087 /* Enable PCI error interrupts in BIM configuration. */ 1088 CAS_WRITE_4(sc, CAS_BIM_CONF, 1089 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1090 1091 /* 1092 * step 9. ETX Configuration: encode receive descriptor ring size, 1093 * enable DMA and disable pre-interrupt writeback completion. 1094 */ 1095 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1096 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1097 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1098 1099 /* step 10. ERX Configuration */ 1100 1101 /* 1102 * Encode receive completion and descriptor ring sizes, set the 1103 * swivel offset. 1104 */ 1105 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1106 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1107 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1108 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1109 CAS_WRITE_4(sc, CAS_RX_CONF, 1110 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1111 1112 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1113 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1114 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1115 1116 /* RX blanking */ 1117 CAS_WRITE_4(sc, CAS_RX_BLANK, 1118 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1119 1120 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1121 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1122 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1123 1124 /* Initialize the RX page size register as appropriate for 8k. */ 1125 CAS_WRITE_4(sc, CAS_RX_PSZ, 1126 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1127 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1128 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1129 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1130 1131 /* Disable RX random early detection. */ 1132 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1133 1134 /* Zero the RX reassembly DMA table. */ 1135 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1136 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1137 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1138 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1139 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1140 } 1141 1142 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1143 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1144 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1145 1146 /* Finally, enable RX DMA. */ 1147 CAS_WRITE_4(sc, CAS_RX_CONF, 1148 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1149 1150 /* step 11. Configure Media. */ 1151 1152 /* step 12. RX_MAC Configuration Register */ 1153 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1154 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1155 v |= CAS_MAC_RX_CONF_STRPFCS; 1156 sc->sc_mac_rxcfg = v; 1157 /* 1158 * Clear the RX filter and reprogram it. This will also set the 1159 * current RX MAC configuration and enable it. 1160 */ 1161 cas_setladrf(sc); 1162 1163 /* step 13. TX_MAC Configuration Register */ 1164 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1165 v |= CAS_MAC_TX_CONF_EN; 1166 (void)cas_disable_tx(sc); 1167 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1168 1169 /* step 14. Issue Transmit Pending command. */ 1170 1171 /* step 15. Give the receiver a swift kick. */ 1172 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1173 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1174 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1175 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1176 1177 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1178 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1179 1180 mii_mediachg(sc->sc_mii); 1181 1182 /* Start the one second timer. */ 1183 sc->sc_wdog_timer = 0; 1184 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1185} 1186 1187static int 1188cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1189{ 1190 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1191 struct cas_txsoft *txs; 1192 struct ip *ip; 1193 struct mbuf *m; 1194 uint64_t cflags; 1195 int error, nexttx, nsegs, offset, seg; 1196 1197 CAS_LOCK_ASSERT(sc, MA_OWNED); 1198 1199 /* Get a work queue entry. */ 1200 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1201 /* Ran out of descriptors. */ 1202 return (ENOBUFS); 1203 } 1204 1205 cflags = 0; 1206 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1207 if (M_WRITABLE(*m_head) == 0) { 1208 m = m_dup(*m_head, M_NOWAIT); 1209 m_freem(*m_head); 1210 *m_head = m; 1211 if (m == NULL) 1212 return (ENOBUFS); 1213 } 1214 offset = sizeof(struct ether_header); 1215 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1216 if (m == NULL) { 1217 *m_head = NULL; 1218 return (ENOBUFS); 1219 } 1220 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1221 offset += (ip->ip_hl << 2); 1222 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1223 ((offset + m->m_pkthdr.csum_data) << 1224 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1225 *m_head = m; 1226 } 1227 1228 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1229 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1230 if (error == EFBIG) { 1231 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS); 1232 if (m == NULL) { 1233 m_freem(*m_head); 1234 *m_head = NULL; 1235 return (ENOBUFS); 1236 } 1237 *m_head = m; 1238 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1239 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1240 BUS_DMA_NOWAIT); 1241 if (error != 0) { 1242 m_freem(*m_head); 1243 *m_head = NULL; 1244 return (error); 1245 } 1246 } else if (error != 0) 1247 return (error); 1248 /* If nsegs is wrong then the stack is corrupt. */ 1249 KASSERT(nsegs <= CAS_NTXSEGS, 1250 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1251 if (nsegs == 0) { 1252 m_freem(*m_head); 1253 *m_head = NULL; 1254 return (EIO); 1255 } 1256 1257 /* 1258 * Ensure we have enough descriptors free to describe 1259 * the packet. Note, we always reserve one descriptor 1260 * at the end of the ring as a termination point, in 1261 * order to prevent wrap-around. 1262 */ 1263 if (nsegs > sc->sc_txfree - 1) { 1264 txs->txs_ndescs = 0; 1265 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1266 return (ENOBUFS); 1267 } 1268 1269 txs->txs_ndescs = nsegs; 1270 txs->txs_firstdesc = sc->sc_txnext; 1271 nexttx = txs->txs_firstdesc; 1272 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1273#ifdef CAS_DEBUG 1274 CTR6(KTR_CAS, 1275 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1276 __func__, seg, nexttx, txsegs[seg].ds_len, 1277 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1278#endif 1279 sc->sc_txdescs[nexttx].cd_buf_ptr = 1280 htole64(txsegs[seg].ds_addr); 1281 KASSERT(txsegs[seg].ds_len < 1282 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1283 ("%s: segment size too large!", __func__)); 1284 sc->sc_txdescs[nexttx].cd_flags = 1285 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1286 txs->txs_lastdesc = nexttx; 1287 } 1288 1289 /* Set EOF on the last descriptor. */ 1290#ifdef CAS_DEBUG 1291 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1292 __func__, seg, nexttx); 1293#endif 1294 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1295 htole64(CAS_TD_END_OF_FRAME); 1296 1297 /* Lastly set SOF on the first descriptor. */ 1298#ifdef CAS_DEBUG 1299 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1300 __func__, seg, nexttx); 1301#endif 1302 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1303 sc->sc_txwin = 0; 1304 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1305 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1306 } else 1307 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1308 htole64(cflags | CAS_TD_START_OF_FRAME); 1309 1310 /* Sync the DMA map. */ 1311 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1312 BUS_DMASYNC_PREWRITE); 1313 1314#ifdef CAS_DEBUG 1315 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1316 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1317 txs->txs_ndescs); 1318#endif 1319 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1320 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1321 txs->txs_mbuf = *m_head; 1322 1323 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1324 sc->sc_txfree -= txs->txs_ndescs; 1325 1326 return (0); 1327} 1328 1329static void 1330cas_init_regs(struct cas_softc *sc) 1331{ 1332 int i; 1333 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1334 1335 CAS_LOCK_ASSERT(sc, MA_OWNED); 1336 1337 /* These registers are not cleared on reset. */ 1338 if ((sc->sc_flags & CAS_INITED) == 0) { 1339 /* magic values */ 1340 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1341 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1342 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1343 1344 /* min frame length */ 1345 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1346 /* max frame length and max burst size */ 1347 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1348 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1349 CAS_MAC_MAX_BF_FRM_SHFT) | 1350 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1351 1352 /* more magic values */ 1353 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1354 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1355 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1356 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1357 1358 /* random number seed */ 1359 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1360 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1361 1362 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1363 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1364 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1365 CAS_WRITE_4(sc, i, 0); 1366 1367 /* MAC control address: 01:80:c2:00:00:01 */ 1368 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1369 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1370 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1371 1372 /* MAC filter address: 0:0:0:0:0:0 */ 1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1374 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1376 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1377 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1378 1379 /* Zero the hash table. */ 1380 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1381 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1382 CAS_WRITE_4(sc, i, 0); 1383 1384 sc->sc_flags |= CAS_INITED; 1385 } 1386 1387 /* Counters need to be zeroed. */ 1388 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1389 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1390 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1391 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1392 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1393 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1394 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1395 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1396 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1397 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1398 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1399 1400 /* Set XOFF PAUSE time. */ 1401 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1402 1403 /* Set the station address. */ 1404 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1405 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1406 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1407 1408 /* Enable MII outputs. */ 1409 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1410} 1411 1412static void 1413cas_tx_task(void *arg, int pending __unused) 1414{ 1415 struct ifnet *ifp; 1416 1417 ifp = (struct ifnet *)arg; 1418 cas_start(ifp); 1419} 1420 1421static inline void 1422cas_txkick(struct cas_softc *sc) 1423{ 1424 1425 /* 1426 * Update the TX kick register. This register has to point to the 1427 * descriptor after the last valid one and for optimum performance 1428 * should be incremented in multiples of 4 (the DMA engine fetches/ 1429 * updates descriptors in batches of 4). 1430 */ 1431#ifdef CAS_DEBUG 1432 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1433 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1434#endif 1435 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1436 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1437} 1438 1439static void 1440cas_start(struct ifnet *ifp) 1441{ 1442 struct cas_softc *sc = ifp->if_softc; 1443 struct mbuf *m; 1444 int kicked, ntx; 1445 1446 CAS_LOCK(sc); 1447 1448 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1449 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1450 CAS_UNLOCK(sc); 1451 return; 1452 } 1453 1454 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1455 cas_tint(sc); 1456 1457#ifdef CAS_DEBUG 1458 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1459 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1460 sc->sc_txnext); 1461#endif 1462 ntx = 0; 1463 kicked = 0; 1464 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1465 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1466 if (m == NULL) 1467 break; 1468 if (cas_load_txmbuf(sc, &m) != 0) { 1469 if (m == NULL) 1470 break; 1471 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1472 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1473 break; 1474 } 1475 if ((sc->sc_txnext % 4) == 0) { 1476 cas_txkick(sc); 1477 kicked = 1; 1478 } else 1479 kicked = 0; 1480 ntx++; 1481 BPF_MTAP(ifp, m); 1482 } 1483 1484 if (ntx > 0) { 1485 if (kicked == 0) 1486 cas_txkick(sc); 1487#ifdef CAS_DEBUG 1488 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1489 device_get_name(sc->sc_dev), sc->sc_txnext); 1490#endif 1491 1492 /* Set a watchdog timer in case the chip flakes out. */ 1493 sc->sc_wdog_timer = 5; 1494#ifdef CAS_DEBUG 1495 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1496 device_get_name(sc->sc_dev), __func__, 1497 sc->sc_wdog_timer); 1498#endif 1499 } 1500 1501 CAS_UNLOCK(sc); 1502} 1503 1504static void 1505cas_tint(struct cas_softc *sc) 1506{ 1507 struct ifnet *ifp = sc->sc_ifp; 1508 struct cas_txsoft *txs; 1509 int progress; 1510 uint32_t txlast; 1511#ifdef CAS_DEBUG 1512 int i; 1513 1514 CAS_LOCK_ASSERT(sc, MA_OWNED); 1515 1516 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1517#endif 1518 1519 /* 1520 * Go through our TX list and free mbufs for those 1521 * frames that have been transmitted. 1522 */ 1523 progress = 0; 1524 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1525 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1526#ifdef CAS_DEBUG 1527 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1528 printf(" txsoft %p transmit chain:\n", txs); 1529 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1530 printf("descriptor %d: ", i); 1531 printf("cd_flags: 0x%016llx\t", 1532 (long long)le64toh( 1533 sc->sc_txdescs[i].cd_flags)); 1534 printf("cd_buf_ptr: 0x%016llx\n", 1535 (long long)le64toh( 1536 sc->sc_txdescs[i].cd_buf_ptr)); 1537 if (i == txs->txs_lastdesc) 1538 break; 1539 } 1540 } 1541#endif 1542 1543 /* 1544 * In theory, we could harvest some descriptors before 1545 * the ring is empty, but that's a bit complicated. 1546 * 1547 * CAS_TX_COMPn points to the last descriptor 1548 * processed + 1. 1549 */ 1550 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1551#ifdef CAS_DEBUG 1552 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1553 "txs->txs_lastdesc = %d, txlast = %d", 1554 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1555#endif 1556 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1557 if ((txlast >= txs->txs_firstdesc) && 1558 (txlast <= txs->txs_lastdesc)) 1559 break; 1560 } else { 1561 /* Ick -- this command wraps. */ 1562 if ((txlast >= txs->txs_firstdesc) || 1563 (txlast <= txs->txs_lastdesc)) 1564 break; 1565 } 1566 1567#ifdef CAS_DEBUG 1568 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1569#endif 1570 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1571 1572 sc->sc_txfree += txs->txs_ndescs; 1573 1574 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1575 BUS_DMASYNC_POSTWRITE); 1576 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1577 if (txs->txs_mbuf != NULL) { 1578 m_freem(txs->txs_mbuf); 1579 txs->txs_mbuf = NULL; 1580 } 1581 1582 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1583 1584 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1585 progress = 1; 1586 } 1587 1588#ifdef CAS_DEBUG 1589 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1590 "CAS_TX_COMP3 %x", 1591 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1592 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1593 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1594 CAS_READ_4(sc, CAS_TX_COMP3)); 1595#endif 1596 1597 if (progress) { 1598 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1599 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1600 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1601 sc->sc_wdog_timer = 0; 1602 } 1603 1604#ifdef CAS_DEBUG 1605 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1606 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1607#endif 1608} 1609 1610static void 1611cas_rint_timeout(void *arg) 1612{ 1613 struct cas_softc *sc = arg; 1614 1615 CAS_LOCK_ASSERT(sc, MA_OWNED); 1616 1617 cas_rint(sc); 1618} 1619 1620static void 1621cas_rint(struct cas_softc *sc) 1622{ 1623 struct cas_rxdsoft *rxds, *rxds2; 1624 struct ifnet *ifp = sc->sc_ifp; 1625 struct mbuf *m, *m2; 1626 uint64_t word1, word2, word3, word4; 1627 uint32_t rxhead; 1628 u_int idx, idx2, len, off, skip; 1629 1630 CAS_LOCK_ASSERT(sc, MA_OWNED); 1631 1632 callout_stop(&sc->sc_rx_ch); 1633 1634#ifdef CAS_DEBUG 1635 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1636#endif 1637 1638#define PRINTWORD(n, delimiter) \ 1639 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1640 1641#define SKIPASSERT(n) \ 1642 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1643 ("%s: word ## n not 0", __func__)) 1644 1645#define WORDTOH(n) \ 1646 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1647 1648 /* 1649 * Read the completion head register once. This limits 1650 * how long the following loop can execute. 1651 */ 1652 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1653#ifdef CAS_DEBUG 1654 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1655 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1656#endif 1657 skip = 0; 1658 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1659 for (; sc->sc_rxcptr != rxhead; 1660 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1661 if (skip != 0) { 1662 SKIPASSERT(1); 1663 SKIPASSERT(2); 1664 SKIPASSERT(3); 1665 1666 --skip; 1667 goto skip; 1668 } 1669 1670 WORDTOH(1); 1671 WORDTOH(2); 1672 WORDTOH(3); 1673 WORDTOH(4); 1674 1675#ifdef CAS_DEBUG 1676 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1677 printf(" completion %d: ", sc->sc_rxcptr); 1678 PRINTWORD(1, '\t'); 1679 PRINTWORD(2, '\t'); 1680 PRINTWORD(3, '\t'); 1681 PRINTWORD(4, '\n'); 1682 } 1683#endif 1684 1685 if (__predict_false( 1686 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1687 (word4 & CAS_RC4_ZERO) != 0)) { 1688 /* 1689 * The descriptor is still marked as owned, although 1690 * it is supposed to have completed. This has been 1691 * observed on some machines. Just exiting here 1692 * might leave the packet sitting around until another 1693 * one arrives to trigger a new interrupt, which is 1694 * generally undesirable, so set up a timeout. 1695 */ 1696 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1697 cas_rint_timeout, sc); 1698 break; 1699 } 1700 1701 if (__predict_false( 1702 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1703 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1704 device_printf(sc->sc_dev, 1705 "receive error: CRC error\n"); 1706 continue; 1707 } 1708 1709 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1710 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1711 ("%s: data and header present", __func__)); 1712 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1713 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1714 ("%s: split and header present", __func__)); 1715 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1716 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1717 ("%s: data present but header release", __func__)); 1718 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1719 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1720 ("%s: header present but data release", __func__)); 1721 1722 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1723 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1724 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1725#ifdef CAS_DEBUG 1726 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1727 __func__, idx, off, len); 1728#endif 1729 rxds = &sc->sc_rxdsoft[idx]; 1730 MGETHDR(m, M_NOWAIT, MT_DATA); 1731 if (m != NULL) { 1732 refcount_acquire(&rxds->rxds_refcount); 1733 bus_dmamap_sync(sc->sc_rdmatag, 1734 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1735#if __FreeBSD_version < 800016 1736 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1737 off * 256 + ETHER_ALIGN, len, cas_free, 1738 rxds, M_RDONLY, EXT_NET_DRV); 1739#else 1740 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1741 off * 256 + ETHER_ALIGN, len, cas_free, 1742 sc, (void *)(uintptr_t)idx, 1743 M_RDONLY, EXT_NET_DRV); 1744#endif 1745 if ((m->m_flags & M_EXT) == 0) { 1746 m_freem(m); 1747 m = NULL; 1748 } 1749 } 1750 if (m != NULL) { 1751 m->m_pkthdr.rcvif = ifp; 1752 m->m_pkthdr.len = m->m_len = len; 1753 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1754 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1755 cas_rxcksum(m, CAS_GET(word4, 1756 CAS_RC4_TCP_CSUM)); 1757 /* Pass it on. */ 1758 CAS_UNLOCK(sc); 1759 (*ifp->if_input)(ifp, m); 1760 CAS_LOCK(sc); 1761 } else 1762 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1763 1764 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1765 refcount_release(&rxds->rxds_refcount) != 0) 1766 cas_add_rxdesc(sc, idx); 1767 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1768 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1769 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1770#ifdef CAS_DEBUG 1771 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1772 __func__, idx, off, len); 1773#endif 1774 rxds = &sc->sc_rxdsoft[idx]; 1775 MGETHDR(m, M_NOWAIT, MT_DATA); 1776 if (m != NULL) { 1777 refcount_acquire(&rxds->rxds_refcount); 1778 off += ETHER_ALIGN; 1779 m->m_len = min(CAS_PAGE_SIZE - off, len); 1780 bus_dmamap_sync(sc->sc_rdmatag, 1781 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1782#if __FreeBSD_version < 800016 1783 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1784 m->m_len, cas_free, rxds, M_RDONLY, 1785 EXT_NET_DRV); 1786#else 1787 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1788 m->m_len, cas_free, sc, 1789 (void *)(uintptr_t)idx, M_RDONLY, 1790 EXT_NET_DRV); 1791#endif 1792 if ((m->m_flags & M_EXT) == 0) { 1793 m_freem(m); 1794 m = NULL; 1795 } 1796 } 1797 idx2 = 0; 1798 m2 = NULL; 1799 rxds2 = NULL; 1800 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1801 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1802 ("%s: split but no release next", 1803 __func__)); 1804 1805 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1806#ifdef CAS_DEBUG 1807 CTR2(KTR_CAS, "%s: split at idx %d", 1808 __func__, idx2); 1809#endif 1810 rxds2 = &sc->sc_rxdsoft[idx2]; 1811 if (m != NULL) { 1812 MGET(m2, M_NOWAIT, MT_DATA); 1813 if (m2 != NULL) { 1814 refcount_acquire( 1815 &rxds2->rxds_refcount); 1816 m2->m_len = len - m->m_len; 1817 bus_dmamap_sync( 1818 sc->sc_rdmatag, 1819 rxds2->rxds_dmamap, 1820 BUS_DMASYNC_POSTREAD); 1821#if __FreeBSD_version < 800016 1822 MEXTADD(m2, 1823 (caddr_t)rxds2->rxds_buf, 1824 m2->m_len, cas_free, 1825 rxds2, M_RDONLY, 1826 EXT_NET_DRV); 1827#else 1828 MEXTADD(m2, 1829 (caddr_t)rxds2->rxds_buf, 1830 m2->m_len, cas_free, sc, 1831 (void *)(uintptr_t)idx2, 1832 M_RDONLY, EXT_NET_DRV); 1833#endif 1834 if ((m2->m_flags & M_EXT) == 1835 0) { 1836 m_freem(m2); 1837 m2 = NULL; 1838 } 1839 } 1840 } 1841 if (m2 != NULL) 1842 m->m_next = m2; 1843 else if (m != NULL) { 1844 m_freem(m); 1845 m = NULL; 1846 } 1847 } 1848 if (m != NULL) { 1849 m->m_pkthdr.rcvif = ifp; 1850 m->m_pkthdr.len = len; 1851 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1852 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1853 cas_rxcksum(m, CAS_GET(word4, 1854 CAS_RC4_TCP_CSUM)); 1855 /* Pass it on. */ 1856 CAS_UNLOCK(sc); 1857 (*ifp->if_input)(ifp, m); 1858 CAS_LOCK(sc); 1859 } else 1860 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1861 1862 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1863 refcount_release(&rxds->rxds_refcount) != 0) 1864 cas_add_rxdesc(sc, idx); 1865 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1866 refcount_release(&rxds2->rxds_refcount) != 0) 1867 cas_add_rxdesc(sc, idx2); 1868 } 1869 1870 skip = CAS_GET(word1, CAS_RC1_SKIP); 1871 1872 skip: 1873 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1874 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1875 break; 1876 } 1877 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1879 1880#undef PRINTWORD 1881#undef SKIPASSERT 1882#undef WORDTOH 1883 1884#ifdef CAS_DEBUG 1885 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1886 __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1887 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1888#endif 1889} 1890 1891static void 1892cas_free(struct mbuf *m, void *arg1, void *arg2) 1893{ 1894 struct cas_rxdsoft *rxds; 1895 struct cas_softc *sc; 1896 u_int idx, locked; 1897 1898#if __FreeBSD_version < 800016 1899 rxds = arg2; 1900 sc = rxds->rxds_sc; 1901 idx = rxds->rxds_idx; 1902#else 1903 sc = arg1; 1904 idx = (uintptr_t)arg2; 1905 rxds = &sc->sc_rxdsoft[idx]; 1906#endif 1907 if (refcount_release(&rxds->rxds_refcount) == 0) 1908 return; 1909 1910 /* 1911 * NB: this function can be called via m_freem(9) within 1912 * this driver! 1913 */ 1914 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1915 CAS_LOCK(sc); 1916 cas_add_rxdesc(sc, idx); 1917 if (locked == 0) 1918 CAS_UNLOCK(sc); 1919} 1920 1921static inline void 1922cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1923{ 1924 1925 CAS_LOCK_ASSERT(sc, MA_OWNED); 1926 1927 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1928 BUS_DMASYNC_PREREAD); 1929 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1930 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1931 1932 /* 1933 * Update the RX kick register. This register has to point to the 1934 * descriptor after the last valid one (before the current batch) 1935 * and for optimum performance should be incremented in multiples 1936 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1937 */ 1938 if ((sc->sc_rxdptr % 4) == 0) { 1939 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1940 CAS_WRITE_4(sc, CAS_RX_KICK, 1941 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1942 } 1943} 1944 1945static void 1946cas_eint(struct cas_softc *sc, u_int status) 1947{ 1948 struct ifnet *ifp = sc->sc_ifp; 1949 1950 CAS_LOCK_ASSERT(sc, MA_OWNED); 1951 1952 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1953 1954 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1955 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1956 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1957 printf(", PCI bus error 0x%x", status); 1958 if ((status & CAS_ERROR_OTHER) != 0) { 1959 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1960 printf(", PCI status 0x%x", status); 1961 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1962 } 1963 } 1964 printf("\n"); 1965 1966 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1967 cas_init_locked(sc); 1968 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1969 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1970} 1971 1972static int 1973cas_intr(void *v) 1974{ 1975 struct cas_softc *sc = v; 1976 1977 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1978 CAS_INTR_SUMMARY) == 0)) 1979 return (FILTER_STRAY); 1980 1981 /* Disable interrupts. */ 1982 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1983 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1984 1985 return (FILTER_HANDLED); 1986} 1987 1988static void 1989cas_intr_task(void *arg, int pending __unused) 1990{ 1991 struct cas_softc *sc = arg; 1992 struct ifnet *ifp = sc->sc_ifp; 1993 uint32_t status, status2; 1994 1995 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1996 1997 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1998 return; 1999 2000 status = CAS_READ_4(sc, CAS_STATUS); 2001 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 2002 goto done; 2003 2004 CAS_LOCK(sc); 2005#ifdef CAS_DEBUG 2006 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 2007 device_get_name(sc->sc_dev), __func__, 2008 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 2009 2010 /* 2011 * PCS interrupts must be cleared, otherwise no traffic is passed! 2012 */ 2013 if ((status & CAS_INTR_PCS_INT) != 0) { 2014 status2 = 2015 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 2016 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 2017 if ((status2 & CAS_PCS_INTR_LINK) != 0) 2018 device_printf(sc->sc_dev, 2019 "%s: PCS link status changed\n", __func__); 2020 } 2021 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 2022 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 2023 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2024 device_printf(sc->sc_dev, 2025 "%s: PAUSE received (PAUSE time %d slots)\n", 2026 __func__, 2027 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2028 CAS_MAC_CTRL_STATUS_PT_SHFT); 2029 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2030 device_printf(sc->sc_dev, 2031 "%s: transited to PAUSE state\n", __func__); 2032 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2033 device_printf(sc->sc_dev, 2034 "%s: transited to non-PAUSE state\n", __func__); 2035 } 2036 if ((status & CAS_INTR_MIF) != 0) 2037 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2038#endif 2039 2040 if (__predict_false((status & 2041 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2042 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2043 cas_eint(sc, status); 2044 CAS_UNLOCK(sc); 2045 return; 2046 } 2047 2048 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2049 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2050 if ((status2 & 2051 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2052 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2053 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2054 device_printf(sc->sc_dev, 2055 "MAC TX fault, status %x\n", status2); 2056 } 2057 2058 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2059 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2060 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2061 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2062 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2063 device_printf(sc->sc_dev, 2064 "MAC RX fault, status %x\n", status2); 2065 } 2066 2067 if ((status & 2068 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2069 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2070 cas_rint(sc); 2071#ifdef CAS_DEBUG 2072 if (__predict_false((status & 2073 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2074 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2075 device_printf(sc->sc_dev, 2076 "RX fault, status %x\n", status); 2077#endif 2078 } 2079 2080 if ((status & 2081 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2082 cas_tint(sc); 2083 2084 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2085 CAS_UNLOCK(sc); 2086 return; 2087 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2088 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2089 CAS_UNLOCK(sc); 2090 2091 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2092 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2093 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2094 return; 2095 } 2096 2097 done: 2098 /* Re-enable interrupts. */ 2099 CAS_WRITE_4(sc, CAS_INTMASK, 2100 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2101 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2102 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2103 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2104 CAS_INTR_PCI_ERROR_INT 2105#ifdef CAS_DEBUG 2106 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2107#endif 2108 )); 2109} 2110 2111static void 2112cas_watchdog(struct cas_softc *sc) 2113{ 2114 struct ifnet *ifp = sc->sc_ifp; 2115 2116 CAS_LOCK_ASSERT(sc, MA_OWNED); 2117 2118#ifdef CAS_DEBUG 2119 CTR4(KTR_CAS, 2120 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2121 __func__, CAS_READ_4(sc, CAS_RX_CONF), 2122 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2123 CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2124 CTR4(KTR_CAS, 2125 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2126 __func__, CAS_READ_4(sc, CAS_TX_CONF), 2127 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2128 CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2129#endif 2130 2131 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2132 return; 2133 2134 if ((sc->sc_flags & CAS_LINK) != 0) 2135 device_printf(sc->sc_dev, "device timeout\n"); 2136 else if (bootverbose) 2137 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2138 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2139 2140 /* Try to get more packets going. */ 2141 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2142 cas_init_locked(sc); 2143 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2144 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2145} 2146 2147static void 2148cas_mifinit(struct cas_softc *sc) 2149{ 2150 2151 /* Configure the MIF in frame mode. */ 2152 CAS_WRITE_4(sc, CAS_MIF_CONF, 2153 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2154 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2155 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2156} 2157 2158/* 2159 * MII interface 2160 * 2161 * The MII interface supports at least three different operating modes: 2162 * 2163 * Bitbang mode is implemented using data, clock and output enable registers. 2164 * 2165 * Frame mode is implemented by loading a complete frame into the frame 2166 * register and polling the valid bit for completion. 2167 * 2168 * Polling mode uses the frame register but completion is indicated by 2169 * an interrupt. 2170 * 2171 */ 2172static int 2173cas_mii_readreg(device_t dev, int phy, int reg) 2174{ 2175 struct cas_softc *sc; 2176 int n; 2177 uint32_t v; 2178 2179#ifdef CAS_DEBUG_PHY 2180 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2181#endif 2182 2183 sc = device_get_softc(dev); 2184 if ((sc->sc_flags & CAS_SERDES) != 0) { 2185 switch (reg) { 2186 case MII_BMCR: 2187 reg = CAS_PCS_CTRL; 2188 break; 2189 case MII_BMSR: 2190 reg = CAS_PCS_STATUS; 2191 break; 2192 case MII_PHYIDR1: 2193 case MII_PHYIDR2: 2194 return (0); 2195 case MII_ANAR: 2196 reg = CAS_PCS_ANAR; 2197 break; 2198 case MII_ANLPAR: 2199 reg = CAS_PCS_ANLPAR; 2200 break; 2201 case MII_EXTSR: 2202 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2203 default: 2204 device_printf(sc->sc_dev, 2205 "%s: unhandled register %d\n", __func__, reg); 2206 return (0); 2207 } 2208 return (CAS_READ_4(sc, reg)); 2209 } 2210 2211 /* Construct the frame command. */ 2212 v = CAS_MIF_FRAME_READ | 2213 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2214 (reg << CAS_MIF_FRAME_REG_SHFT); 2215 2216 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2217 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2218 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2219 for (n = 0; n < 100; n++) { 2220 DELAY(1); 2221 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2222 if (v & CAS_MIF_FRAME_TA_LSB) 2223 return (v & CAS_MIF_FRAME_DATA); 2224 } 2225 2226 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2227 return (0); 2228} 2229 2230static int 2231cas_mii_writereg(device_t dev, int phy, int reg, int val) 2232{ 2233 struct cas_softc *sc; 2234 int n; 2235 uint32_t v; 2236 2237#ifdef CAS_DEBUG_PHY 2238 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2239#endif 2240 2241 sc = device_get_softc(dev); 2242 if ((sc->sc_flags & CAS_SERDES) != 0) { 2243 switch (reg) { 2244 case MII_BMSR: 2245 reg = CAS_PCS_STATUS; 2246 break; 2247 case MII_BMCR: 2248 reg = CAS_PCS_CTRL; 2249 if ((val & CAS_PCS_CTRL_RESET) == 0) 2250 break; 2251 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2252 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2253 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2254 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2255 CAS_PCS_CTRL_RESET, 0)) 2256 device_printf(sc->sc_dev, 2257 "cannot reset PCS\n"); 2258 /* FALLTHROUGH */ 2259 case MII_ANAR: 2260 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2261 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2262 BUS_SPACE_BARRIER_WRITE); 2263 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2264 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2265 BUS_SPACE_BARRIER_WRITE); 2266 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2267 CAS_PCS_SERDES_CTRL_ESD); 2268 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2269 BUS_SPACE_BARRIER_WRITE); 2270 CAS_WRITE_4(sc, CAS_PCS_CONF, 2271 CAS_PCS_CONF_EN); 2272 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2273 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2274 return (0); 2275 case MII_ANLPAR: 2276 reg = CAS_PCS_ANLPAR; 2277 break; 2278 default: 2279 device_printf(sc->sc_dev, 2280 "%s: unhandled register %d\n", __func__, reg); 2281 return (0); 2282 } 2283 CAS_WRITE_4(sc, reg, val); 2284 CAS_BARRIER(sc, reg, 4, 2285 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2286 return (0); 2287 } 2288 2289 /* Construct the frame command. */ 2290 v = CAS_MIF_FRAME_WRITE | 2291 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2292 (reg << CAS_MIF_FRAME_REG_SHFT) | 2293 (val & CAS_MIF_FRAME_DATA); 2294 2295 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2296 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2297 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2298 for (n = 0; n < 100; n++) { 2299 DELAY(1); 2300 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2301 if (v & CAS_MIF_FRAME_TA_LSB) 2302 return (1); 2303 } 2304 2305 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2306 return (0); 2307} 2308 2309static void 2310cas_mii_statchg(device_t dev) 2311{ 2312 struct cas_softc *sc; 2313 struct ifnet *ifp; 2314 int gigabit; 2315 uint32_t rxcfg, txcfg, v; 2316 2317 sc = device_get_softc(dev); 2318 ifp = sc->sc_ifp; 2319 2320 CAS_LOCK_ASSERT(sc, MA_OWNED); 2321 2322#ifdef CAS_DEBUG 2323 if ((ifp->if_flags & IFF_DEBUG) != 0) 2324 device_printf(sc->sc_dev, "%s: status changen", __func__); 2325#endif 2326 2327 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2328 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2329 sc->sc_flags |= CAS_LINK; 2330 else 2331 sc->sc_flags &= ~CAS_LINK; 2332 2333 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2334 case IFM_1000_SX: 2335 case IFM_1000_LX: 2336 case IFM_1000_CX: 2337 case IFM_1000_T: 2338 gigabit = 1; 2339 break; 2340 default: 2341 gigabit = 0; 2342 } 2343 2344 /* 2345 * The configuration done here corresponds to the steps F) and 2346 * G) and as far as enabling of RX and TX MAC goes also step H) 2347 * of the initialization sequence outlined in section 11.2.1 of 2348 * the Cassini+ ASIC Specification. 2349 */ 2350 2351 rxcfg = sc->sc_mac_rxcfg; 2352 rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2353 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2354 CAS_MAC_TX_CONF_NGUL; 2355 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2356 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2357 else if (gigabit != 0) { 2358 rxcfg |= CAS_MAC_RX_CONF_CARR; 2359 txcfg |= CAS_MAC_TX_CONF_CARR; 2360 } 2361 (void)cas_disable_tx(sc); 2362 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2363 (void)cas_disable_rx(sc); 2364 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2365 2366 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2367 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2368 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2369 IFM_ETH_RXPAUSE) != 0) 2370 v |= CAS_MAC_CTRL_CONF_RXP; 2371 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2372 IFM_ETH_TXPAUSE) != 0) 2373 v |= CAS_MAC_CTRL_CONF_TXP; 2374 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2375 2376 /* 2377 * All supported chips have a bug causing incorrect checksum 2378 * to be calculated when letting them strip the FCS in half- 2379 * duplex mode. In theory we could disable FCS stripping and 2380 * manually adjust the checksum accordingly. It seems to make 2381 * more sense to optimze for the common case and just disable 2382 * hardware checksumming in half-duplex mode though. 2383 */ 2384 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2385 ifp->if_capenable &= ~IFCAP_HWCSUM; 2386 ifp->if_hwassist = 0; 2387 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2388 ifp->if_capenable = ifp->if_capabilities; 2389 ifp->if_hwassist = CAS_CSUM_FEATURES; 2390 } 2391 2392 if (sc->sc_variant == CAS_SATURN) { 2393 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2394 /* silicon bug workaround */ 2395 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2396 else 2397 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2398 } 2399 2400 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2401 gigabit != 0) 2402 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2403 CAS_MAC_SLOT_TIME_CARR); 2404 else 2405 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2406 CAS_MAC_SLOT_TIME_NORM); 2407 2408 /* XIF Configuration */ 2409 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2410 if ((sc->sc_flags & CAS_SERDES) == 0) { 2411 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2412 v |= CAS_MAC_XIF_CONF_NOECHO; 2413 v |= CAS_MAC_XIF_CONF_BUF_OE; 2414 } 2415 if (gigabit != 0) 2416 v |= CAS_MAC_XIF_CONF_GMII; 2417 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2418 v |= CAS_MAC_XIF_CONF_FDXLED; 2419 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2420 2421 sc->sc_mac_rxcfg = rxcfg; 2422 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2423 (sc->sc_flags & CAS_LINK) != 0) { 2424 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2425 txcfg | CAS_MAC_TX_CONF_EN); 2426 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2427 rxcfg | CAS_MAC_RX_CONF_EN); 2428 } 2429} 2430 2431static int 2432cas_mediachange(struct ifnet *ifp) 2433{ 2434 struct cas_softc *sc = ifp->if_softc; 2435 int error; 2436 2437 /* XXX add support for serial media. */ 2438 2439 CAS_LOCK(sc); 2440 error = mii_mediachg(sc->sc_mii); 2441 CAS_UNLOCK(sc); 2442 return (error); 2443} 2444 2445static void 2446cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2447{ 2448 struct cas_softc *sc = ifp->if_softc; 2449 2450 CAS_LOCK(sc); 2451 if ((ifp->if_flags & IFF_UP) == 0) { 2452 CAS_UNLOCK(sc); 2453 return; 2454 } 2455 2456 mii_pollstat(sc->sc_mii); 2457 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2458 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2459 CAS_UNLOCK(sc); 2460} 2461 2462static int 2463cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2464{ 2465 struct cas_softc *sc = ifp->if_softc; 2466 struct ifreq *ifr = (struct ifreq *)data; 2467 int error; 2468 2469 error = 0; 2470 switch (cmd) { 2471 case SIOCSIFFLAGS: 2472 CAS_LOCK(sc); 2473 if ((ifp->if_flags & IFF_UP) != 0) { 2474 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2475 ((ifp->if_flags ^ sc->sc_ifflags) & 2476 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2477 cas_setladrf(sc); 2478 else 2479 cas_init_locked(sc); 2480 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2481 cas_stop(ifp); 2482 sc->sc_ifflags = ifp->if_flags; 2483 CAS_UNLOCK(sc); 2484 break; 2485 case SIOCSIFCAP: 2486 CAS_LOCK(sc); 2487 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2488 error = EINVAL; 2489 CAS_UNLOCK(sc); 2490 break; 2491 } 2492 ifp->if_capenable = ifr->ifr_reqcap; 2493 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2494 ifp->if_hwassist = CAS_CSUM_FEATURES; 2495 else 2496 ifp->if_hwassist = 0; 2497 CAS_UNLOCK(sc); 2498 break; 2499 case SIOCADDMULTI: 2500 case SIOCDELMULTI: 2501 CAS_LOCK(sc); 2502 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2503 cas_setladrf(sc); 2504 CAS_UNLOCK(sc); 2505 break; 2506 case SIOCSIFMTU: 2507 if ((ifr->ifr_mtu < ETHERMIN) || 2508 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2509 error = EINVAL; 2510 else 2511 ifp->if_mtu = ifr->ifr_mtu; 2512 break; 2513 case SIOCGIFMEDIA: 2514 case SIOCSIFMEDIA: 2515 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2516 break; 2517 default: 2518 error = ether_ioctl(ifp, cmd, data); 2519 break; 2520 } 2521 2522 return (error); 2523} 2524 2525static void 2526cas_setladrf(struct cas_softc *sc) 2527{ 2528 struct ifnet *ifp = sc->sc_ifp; 2529 struct ifmultiaddr *inm; 2530 int i; 2531 uint32_t hash[16]; 2532 uint32_t crc, v; 2533 2534 CAS_LOCK_ASSERT(sc, MA_OWNED); 2535 2536 /* 2537 * Turn off the RX MAC and the hash filter as required by the Sun 2538 * Cassini programming restrictions. 2539 */ 2540 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2541 CAS_MAC_RX_CONF_EN); 2542 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2543 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2544 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2545 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2546 CAS_MAC_RX_CONF_EN, 0)) 2547 device_printf(sc->sc_dev, 2548 "cannot disable RX MAC or hash filter\n"); 2549 2550 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2551 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2552 v |= CAS_MAC_RX_CONF_PROMISC; 2553 goto chipit; 2554 } 2555 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2556 v |= CAS_MAC_RX_CONF_PGRP; 2557 goto chipit; 2558 } 2559 2560 /* 2561 * Set up multicast address filter by passing all multicast 2562 * addresses through a crc generator, and then using the high 2563 * order 8 bits as an index into the 256 bit logical address 2564 * filter. The high order 4 bits selects the word, while the 2565 * other 4 bits select the bit within the word (where bit 0 2566 * is the MSB). 2567 */ 2568 2569 /* Clear the hash table. */ 2570 memset(hash, 0, sizeof(hash)); 2571 2572 if_maddr_rlock(ifp); 2573 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2574 if (inm->ifma_addr->sa_family != AF_LINK) 2575 continue; 2576 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2577 inm->ifma_addr), ETHER_ADDR_LEN); 2578 2579 /* We just want the 8 most significant bits. */ 2580 crc >>= 24; 2581 2582 /* Set the corresponding bit in the filter. */ 2583 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2584 } 2585 if_maddr_runlock(ifp); 2586 2587 v |= CAS_MAC_RX_CONF_HFILTER; 2588 2589 /* Now load the hash table into the chip (if we are using it). */ 2590 for (i = 0; i < 16; i++) 2591 CAS_WRITE_4(sc, 2592 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2593 hash[i]); 2594 2595 chipit: 2596 sc->sc_mac_rxcfg = v; 2597 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2598} 2599 2600static int cas_pci_attach(device_t dev); 2601static int cas_pci_detach(device_t dev); 2602static int cas_pci_probe(device_t dev); 2603static int cas_pci_resume(device_t dev); 2604static int cas_pci_suspend(device_t dev); 2605 2606static device_method_t cas_pci_methods[] = { 2607 /* Device interface */ 2608 DEVMETHOD(device_probe, cas_pci_probe), 2609 DEVMETHOD(device_attach, cas_pci_attach), 2610 DEVMETHOD(device_detach, cas_pci_detach), 2611 DEVMETHOD(device_suspend, cas_pci_suspend), 2612 DEVMETHOD(device_resume, cas_pci_resume), 2613 /* Use the suspend handler here, it is all that is required. */ 2614 DEVMETHOD(device_shutdown, cas_pci_suspend), 2615 2616 /* MII interface */ 2617 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2618 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2619 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2620 2621 DEVMETHOD_END 2622}; 2623 2624static driver_t cas_pci_driver = { 2625 "cas", 2626 cas_pci_methods, 2627 sizeof(struct cas_softc) 2628}; 2629 2630DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2631DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2632MODULE_DEPEND(cas, pci, 1, 1, 1); 2633 2634static const struct cas_pci_dev { 2635 uint32_t cpd_devid; 2636 uint8_t cpd_revid; 2637 int cpd_variant; 2638 const char *cpd_desc; 2639} cas_pci_devlist[] = { 2640 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2641 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2642 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2643 { 0, 0, 0, NULL } 2644}; 2645 2646static int 2647cas_pci_probe(device_t dev) 2648{ 2649 int i; 2650 2651 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2652 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2653 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2654 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2655 return (BUS_PROBE_DEFAULT); 2656 } 2657 } 2658 2659 return (ENXIO); 2660} 2661 2662static struct resource_spec cas_pci_res_spec[] = { 2663 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2664 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2665 { -1, 0 } 2666}; 2667 2668#define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2669#define CAS_PHY_INTERFACE "phy-interface" 2670#define CAS_PHY_TYPE "phy-type" 2671#define CAS_PHY_TYPE_PCS "pcs" 2672 2673static int 2674cas_pci_attach(device_t dev) 2675{ 2676 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2677 struct cas_softc *sc; 2678 int i; 2679#if !(defined(__powerpc__) || defined(__sparc64__)) 2680 u_char enaddr[4][ETHER_ADDR_LEN]; 2681 u_int j, k, lma, pcs[4], phy; 2682#endif 2683 2684 sc = device_get_softc(dev); 2685 sc->sc_variant = CAS_UNKNOWN; 2686 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2687 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2688 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2689 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2690 break; 2691 } 2692 } 2693 if (sc->sc_variant == CAS_UNKNOWN) { 2694 device_printf(dev, "unknown adaptor\n"); 2695 return (ENXIO); 2696 } 2697 2698 /* PCI configuration */ 2699 pci_write_config(dev, PCIR_COMMAND, 2700 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN | 2701 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2); 2702 2703 sc->sc_dev = dev; 2704 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2705 /* Hardware checksumming may hang TX. */ 2706 sc->sc_flags |= CAS_NO_CSUM; 2707 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2708 sc->sc_flags |= CAS_REG_PLUS; 2709 if (sc->sc_variant == CAS_CAS || 2710 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2711 sc->sc_flags |= CAS_TABORT; 2712 if (bootverbose) 2713 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2714 2715 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2716 device_printf(dev, "failed to allocate resources\n"); 2717 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2718 return (ENXIO); 2719 } 2720 2721 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2722 2723#if defined(__powerpc__) || defined(__sparc64__) 2724 OF_getetheraddr(dev, sc->sc_enaddr); 2725 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2726 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2727 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2728 buf[sizeof(buf) - 1] = '\0'; 2729 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2730 sc->sc_flags |= CAS_SERDES; 2731 } 2732#else 2733 /* 2734 * Dig out VPD (vital product data) and read the MAC address as well 2735 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2736 * FCode) and can't be accessed via the PCI capability pointer. 2737 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2738 * in the free US Patent 7149820. 2739 */ 2740 2741#define PCI_ROMHDR_SIZE 0x1c 2742#define PCI_ROMHDR_SIG 0x00 2743#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2744#define PCI_ROMHDR_PTR_DATA 0x18 2745#define PCI_ROM_SIZE 0x18 2746#define PCI_ROM_SIG 0x00 2747#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2748 /* reversed */ 2749#define PCI_ROM_VENDOR 0x04 2750#define PCI_ROM_DEVICE 0x06 2751#define PCI_ROM_PTR_VPD 0x08 2752#define PCI_VPDRES_BYTE0 0x00 2753#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2754#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2755#define PCI_VPDRES_LARGE_LEN_LSB 0x01 2756#define PCI_VPDRES_LARGE_LEN_MSB 0x02 2757#define PCI_VPDRES_LARGE_SIZE 0x03 2758#define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2759#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2760#define PCI_VPD_KEY0 0x00 2761#define PCI_VPD_KEY1 0x01 2762#define PCI_VPD_LEN 0x02 2763#define PCI_VPD_SIZE 0x03 2764 2765#define CAS_ROM_READ_1(sc, offs) \ 2766 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2767#define CAS_ROM_READ_2(sc, offs) \ 2768 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2769#define CAS_ROM_READ_4(sc, offs) \ 2770 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2771 2772 lma = phy = 0; 2773 memset(enaddr, 0, sizeof(enaddr)); 2774 memset(pcs, 0, sizeof(pcs)); 2775 2776 /* Enable PCI Expansion ROM access. */ 2777 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2778 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2779 2780 /* Read PCI Expansion ROM header. */ 2781 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2782 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2783 PCI_ROMHDR_SIZE) { 2784 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2785 goto fail_prom; 2786 } 2787 2788 /* Read PCI Expansion ROM data. */ 2789 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2790 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2791 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2792 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2793 i + PCI_ROM_SIZE) { 2794 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2795 goto fail_prom; 2796 } 2797 2798 /* Read PCI VPD. */ 2799 next: 2800 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2801 j + PCI_VPDRES_BYTE0)) == 0) { 2802 device_printf(dev, "no large PCI VPD\n"); 2803 goto fail_prom; 2804 } 2805 2806 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2807 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2808 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2809 j + PCI_VPDRES_BYTE0))) { 2810 case PCI_VPDRES_TYPE_ID_STRING: 2811 /* Skip identifier string. */ 2812 j += PCI_VPDRES_LARGE_SIZE + i; 2813 goto next; 2814 case PCI_VPDRES_TYPE_VPD: 2815 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2816 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2817 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2818 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2819 /* no Enhanced VPD */ 2820 continue; 2821 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2822 /* no instance property */ 2823 continue; 2824 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2825 /* byte array */ 2826 if (CAS_ROM_READ_1(sc, 2827 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2828 continue; 2829 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2830 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2831 buf, sizeof(buf)); 2832 buf[sizeof(buf) - 1] = '\0'; 2833 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2834 continue; 2835 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2836 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2837 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2838 enaddr[lma], sizeof(enaddr[lma])); 2839 lma++; 2840 if (lma == 4 && phy == 4) 2841 break; 2842 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2843 'S') { 2844 /* string */ 2845 if (CAS_ROM_READ_1(sc, 2846 j + PCI_VPD_SIZE + 4) != 2847 sizeof(CAS_PHY_TYPE_PCS)) 2848 continue; 2849 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2850 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2851 buf, sizeof(buf)); 2852 buf[sizeof(buf) - 1] = '\0'; 2853 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2854 k = sizeof(CAS_PHY_INTERFACE); 2855 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2856 k = sizeof(CAS_PHY_TYPE); 2857 else 2858 continue; 2859 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2860 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2861 5 + k, buf, sizeof(buf)); 2862 buf[sizeof(buf) - 1] = '\0'; 2863 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2864 pcs[phy] = 1; 2865 phy++; 2866 if (lma == 4 && phy == 4) 2867 break; 2868 } 2869 } 2870 break; 2871 default: 2872 device_printf(dev, "unexpected PCI VPD\n"); 2873 goto fail_prom; 2874 } 2875 2876 fail_prom: 2877 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2878 2879 if (lma == 0) { 2880 device_printf(dev, "could not determine Ethernet address\n"); 2881 goto fail; 2882 } 2883 i = 0; 2884 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr)) 2885 i = pci_get_slot(dev); 2886 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2887 2888 if (phy == 0) { 2889 device_printf(dev, "could not determine PHY type\n"); 2890 goto fail; 2891 } 2892 i = 0; 2893 if (phy > 1 && pci_get_slot(dev) < nitems(pcs)) 2894 i = pci_get_slot(dev); 2895 if (pcs[i] != 0) 2896 sc->sc_flags |= CAS_SERDES; 2897#endif 2898 2899 if (cas_attach(sc) != 0) { 2900 device_printf(dev, "could not be attached\n"); 2901 goto fail; 2902 } 2903 2904 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2905 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2906 device_printf(dev, "failed to set up interrupt\n"); 2907 cas_detach(sc); 2908 goto fail; 2909 } 2910 return (0); 2911 2912 fail: 2913 CAS_LOCK_DESTROY(sc); 2914 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2915 return (ENXIO); 2916} 2917 2918static int 2919cas_pci_detach(device_t dev) 2920{ 2921 struct cas_softc *sc; 2922 2923 sc = device_get_softc(dev); 2924 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2925 cas_detach(sc); 2926 CAS_LOCK_DESTROY(sc); 2927 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2928 return (0); 2929} 2930 2931static int 2932cas_pci_suspend(device_t dev) 2933{ 2934 2935 cas_suspend(device_get_softc(dev)); 2936 return (0); 2937} 2938 2939static int 2940cas_pci_resume(device_t dev) 2941{ 2942 2943 cas_resume(device_get_softc(dev)); 2944 return (0); 2945} 2946