if_cas.c revision 213893
1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/dev/cas/if_cas.c 213893 2010-10-15 14:52:11Z marius $"); 34 35/* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40#if 0 41#define CAS_DEBUG 42#endif 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/callout.h> 48#include <sys/endian.h> 49#include <sys/mbuf.h> 50#include <sys/malloc.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/module.h> 54#include <sys/mutex.h> 55#include <sys/refcount.h> 56#include <sys/resource.h> 57#include <sys/rman.h> 58#include <sys/socket.h> 59#include <sys/sockio.h> 60#include <sys/taskqueue.h> 61 62#include <net/bpf.h> 63#include <net/ethernet.h> 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68#include <net/if_types.h> 69#include <net/if_vlan_var.h> 70 71#include <netinet/in.h> 72#include <netinet/in_systm.h> 73#include <netinet/ip.h> 74#include <netinet/tcp.h> 75#include <netinet/udp.h> 76 77#include <machine/bus.h> 78#if defined(__powerpc__) || defined(__sparc64__) 79#include <dev/ofw/ofw_bus.h> 80#include <dev/ofw/openfirm.h> 81#include <machine/ofw_machdep.h> 82#endif 83#include <machine/resource.h> 84 85#include <dev/mii/mii.h> 86#include <dev/mii/miivar.h> 87 88#include <dev/cas/if_casreg.h> 89#include <dev/cas/if_casvar.h> 90 91#include <dev/pci/pcireg.h> 92#include <dev/pci/pcivar.h> 93 94#include "miibus_if.h" 95 96#define RINGASSERT(n , min, max) \ 97 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 98 99RINGASSERT(CAS_NRXCOMP, 128, 32768); 100RINGASSERT(CAS_NRXDESC, 32, 8192); 101RINGASSERT(CAS_NRXDESC2, 32, 8192); 102RINGASSERT(CAS_NTXDESC, 32, 8192); 103 104#undef RINGASSERT 105 106#define CCDASSERT(m, a) \ 107 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 108 109CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 110CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 111CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 112 113#undef CCDASSERT 114 115#define CAS_TRIES 10000 116 117/* 118 * According to documentation, the hardware has support for basic TCP 119 * checksum offloading only, in practice this can be also used for UDP 120 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 121 * is not converted to 0xffff no longer exists). 122 */ 123#define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 124 125static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 126static int cas_attach(struct cas_softc *sc); 127static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 128 uint32_t set); 129static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 130 int nsegs, int error); 131static void cas_detach(struct cas_softc *sc); 132static int cas_disable_rx(struct cas_softc *sc); 133static int cas_disable_tx(struct cas_softc *sc); 134static void cas_eint(struct cas_softc *sc, u_int status); 135static void cas_free(void *arg1, void* arg2); 136static void cas_init(void *xsc); 137static void cas_init_locked(struct cas_softc *sc); 138static void cas_init_regs(struct cas_softc *sc); 139static int cas_intr(void *v); 140static void cas_intr_task(void *arg, int pending __unused); 141static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 143static int cas_mediachange(struct ifnet *ifp); 144static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 145static void cas_meminit(struct cas_softc *sc); 146static void cas_mifinit(struct cas_softc *sc); 147static int cas_mii_readreg(device_t dev, int phy, int reg); 148static void cas_mii_statchg(device_t dev); 149static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 150static void cas_reset(struct cas_softc *sc); 151static int cas_reset_rx(struct cas_softc *sc); 152static int cas_reset_tx(struct cas_softc *sc); 153static void cas_resume(struct cas_softc *sc); 154static u_int cas_descsize(u_int sz); 155static void cas_rint(struct cas_softc *sc); 156static void cas_rint_timeout(void *arg); 157static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 158static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 159static u_int cas_rxcompsize(u_int sz); 160static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 161 int nsegs, int error); 162static void cas_setladrf(struct cas_softc *sc); 163static void cas_start(struct ifnet *ifp); 164static void cas_stop(struct ifnet *ifp); 165static void cas_suspend(struct cas_softc *sc); 166static void cas_tick(void *arg); 167static void cas_tint(struct cas_softc *sc); 168static void cas_tx_task(void *arg, int pending __unused); 169static inline void cas_txkick(struct cas_softc *sc); 170static void cas_watchdog(struct cas_softc *sc); 171 172static devclass_t cas_devclass; 173 174MODULE_DEPEND(cas, ether, 1, 1, 1); 175MODULE_DEPEND(cas, miibus, 1, 1, 1); 176 177#ifdef CAS_DEBUG 178#include <sys/ktr.h> 179#define KTR_CAS KTR_SPARE2 180#endif 181 182static int 183cas_attach(struct cas_softc *sc) 184{ 185 struct cas_txsoft *txs; 186 struct ifnet *ifp; 187 int error, i; 188 uint32_t v; 189 190 /* Set up ifnet structure. */ 191 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 192 if (ifp == NULL) 193 return (ENOSPC); 194 ifp->if_softc = sc; 195 if_initname(ifp, device_get_name(sc->sc_dev), 196 device_get_unit(sc->sc_dev)); 197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 198 ifp->if_start = cas_start; 199 ifp->if_ioctl = cas_ioctl; 200 ifp->if_init = cas_init; 201 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 202 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 203 IFQ_SET_READY(&ifp->if_snd); 204 205 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 206 callout_init(&sc->sc_rx_ch, 1); 207 /* Create local taskq. */ 208 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 209 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 210 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 211 taskqueue_thread_enqueue, &sc->sc_tq); 212 if (sc->sc_tq == NULL) { 213 device_printf(sc->sc_dev, "could not create taskqueue\n"); 214 error = ENXIO; 215 goto fail_ifnet; 216 } 217 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 218 device_get_nameunit(sc->sc_dev)); 219 220 /* Make sure the chip is stopped. */ 221 cas_reset(sc); 222 223 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 225 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 226 &sc->sc_pdmatag); 227 if (error != 0) 228 goto fail_taskq; 229 230 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 232 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 233 if (error != 0) 234 goto fail_ptag; 235 236 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 238 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 239 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 240 if (error != 0) 241 goto fail_rtag; 242 243 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 245 sizeof(struct cas_control_data), 1, 246 sizeof(struct cas_control_data), 0, 247 NULL, NULL, &sc->sc_cdmatag); 248 if (error != 0) 249 goto fail_ttag; 250 251 /* 252 * Allocate the control data structures, create and load the 253 * DMA map for it. 254 */ 255 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 256 (void **)&sc->sc_control_data, 257 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 258 &sc->sc_cddmamap)) != 0) { 259 device_printf(sc->sc_dev, 260 "unable to allocate control data, error = %d\n", error); 261 goto fail_ctag; 262 } 263 264 sc->sc_cddma = 0; 265 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 266 sc->sc_control_data, sizeof(struct cas_control_data), 267 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 268 device_printf(sc->sc_dev, 269 "unable to load control data DMA map, error = %d\n", 270 error); 271 goto fail_cmem; 272 } 273 274 /* 275 * Initialize the transmit job descriptors. 276 */ 277 STAILQ_INIT(&sc->sc_txfreeq); 278 STAILQ_INIT(&sc->sc_txdirtyq); 279 280 /* 281 * Create the transmit buffer DMA maps. 282 */ 283 error = ENOMEM; 284 for (i = 0; i < CAS_TXQUEUELEN; i++) { 285 txs = &sc->sc_txsoft[i]; 286 txs->txs_mbuf = NULL; 287 txs->txs_ndescs = 0; 288 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 289 &txs->txs_dmamap)) != 0) { 290 device_printf(sc->sc_dev, 291 "unable to create TX DMA map %d, error = %d\n", 292 i, error); 293 goto fail_txd; 294 } 295 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 296 } 297 298 /* 299 * Allocate the receive buffers, create and load the DMA maps 300 * for them. 301 */ 302 for (i = 0; i < CAS_NRXDESC; i++) { 303 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 304 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 305 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 306 device_printf(sc->sc_dev, 307 "unable to allocate RX buffer %d, error = %d\n", 308 i, error); 309 goto fail_rxmem; 310 } 311 312 sc->sc_rxdptr = i; 313 sc->sc_rxdsoft[i].rxds_paddr = 0; 314 if ((error = bus_dmamap_load(sc->sc_rdmatag, 315 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 316 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 317 sc->sc_rxdsoft[i].rxds_paddr == 0) { 318 device_printf(sc->sc_dev, 319 "unable to load RX DMA map %d, error = %d\n", 320 i, error); 321 goto fail_rxmap; 322 } 323 } 324 325 if ((sc->sc_flags & CAS_SERDES) == 0) { 326 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 327 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 328 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 329 cas_mifinit(sc); 330 /* 331 * Look for an external PHY. 332 */ 333 error = ENXIO; 334 v = CAS_READ_4(sc, CAS_MIF_CONF); 335 if ((v & CAS_MIF_CONF_MDI1) != 0) { 336 v |= CAS_MIF_CONF_PHY_SELECT; 337 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 338 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 339 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 340 /* Enable/unfreeze the GMII pins of Saturn. */ 341 if (sc->sc_variant == CAS_SATURN) { 342 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 343 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 344 BUS_SPACE_BARRIER_READ | 345 BUS_SPACE_BARRIER_WRITE); 346 } 347 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 348 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 349 MII_PHY_ANY, MII_OFFSET_ANY, 0); 350 } 351 /* 352 * Fall back on an internal PHY if no external PHY was found. 353 */ 354 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 355 v &= ~CAS_MIF_CONF_PHY_SELECT; 356 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 357 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 358 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 359 /* Freeze the GMII pins of Saturn for saving power. */ 360 if (sc->sc_variant == CAS_SATURN) { 361 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 362 CAS_SATURN_PCFG_FSI); 363 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 364 BUS_SPACE_BARRIER_READ | 365 BUS_SPACE_BARRIER_WRITE); 366 } 367 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 368 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 369 MII_PHY_ANY, MII_OFFSET_ANY, 0); 370 } 371 } else { 372 /* 373 * Use the external PCS SERDES. 374 */ 375 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 376 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 377 /* Enable/unfreeze the SERDES pins of Saturn. */ 378 if (sc->sc_variant == CAS_SATURN) { 379 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 380 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 381 BUS_SPACE_BARRIER_WRITE); 382 } 383 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 384 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 385 BUS_SPACE_BARRIER_WRITE); 386 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 387 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 388 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 389 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 390 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 391 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, 0); 392 } 393 if (error != 0) { 394 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 395 goto fail_rxmap; 396 } 397 sc->sc_mii = device_get_softc(sc->sc_miibus); 398 399 /* 400 * From this point forward, the attachment cannot fail. A failure 401 * before this point releases all resources that may have been 402 * allocated. 403 */ 404 405 /* Announce FIFO sizes. */ 406 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 407 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 408 CAS_RX_FIFO_SIZE / 1024, v / 16); 409 410 /* Attach the interface. */ 411 ether_ifattach(ifp, sc->sc_enaddr); 412 413 /* 414 * Tell the upper layer(s) we support long frames/checksum offloads. 415 */ 416 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 417 ifp->if_capabilities = IFCAP_VLAN_MTU; 418 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 419 ifp->if_capabilities |= IFCAP_HWCSUM; 420 ifp->if_hwassist = CAS_CSUM_FEATURES; 421 } 422 ifp->if_capenable = ifp->if_capabilities; 423 424 return (0); 425 426 /* 427 * Free any resources we've allocated during the failed attach 428 * attempt. Do this in reverse order and fall through. 429 */ 430 fail_rxmap: 431 for (i = 0; i < CAS_NRXDESC; i++) 432 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 433 bus_dmamap_unload(sc->sc_rdmatag, 434 sc->sc_rxdsoft[i].rxds_dmamap); 435 fail_rxmem: 436 for (i = 0; i < CAS_NRXDESC; i++) 437 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 438 bus_dmamem_free(sc->sc_rdmatag, 439 sc->sc_rxdsoft[i].rxds_buf, 440 sc->sc_rxdsoft[i].rxds_dmamap); 441 fail_txd: 442 for (i = 0; i < CAS_TXQUEUELEN; i++) 443 if (sc->sc_txsoft[i].txs_dmamap != NULL) 444 bus_dmamap_destroy(sc->sc_tdmatag, 445 sc->sc_txsoft[i].txs_dmamap); 446 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 447 fail_cmem: 448 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 449 sc->sc_cddmamap); 450 fail_ctag: 451 bus_dma_tag_destroy(sc->sc_cdmatag); 452 fail_ttag: 453 bus_dma_tag_destroy(sc->sc_tdmatag); 454 fail_rtag: 455 bus_dma_tag_destroy(sc->sc_rdmatag); 456 fail_ptag: 457 bus_dma_tag_destroy(sc->sc_pdmatag); 458 fail_taskq: 459 taskqueue_free(sc->sc_tq); 460 fail_ifnet: 461 if_free(ifp); 462 return (error); 463} 464 465static void 466cas_detach(struct cas_softc *sc) 467{ 468 struct ifnet *ifp = sc->sc_ifp; 469 int i; 470 471 ether_ifdetach(ifp); 472 CAS_LOCK(sc); 473 cas_stop(ifp); 474 CAS_UNLOCK(sc); 475 callout_drain(&sc->sc_tick_ch); 476 callout_drain(&sc->sc_rx_ch); 477 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 478 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 479 if_free(ifp); 480 taskqueue_free(sc->sc_tq); 481 device_delete_child(sc->sc_dev, sc->sc_miibus); 482 483 for (i = 0; i < CAS_NRXDESC; i++) 484 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 485 bus_dmamap_sync(sc->sc_rdmatag, 486 sc->sc_rxdsoft[i].rxds_dmamap, 487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 488 for (i = 0; i < CAS_NRXDESC; i++) 489 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 490 bus_dmamap_unload(sc->sc_rdmatag, 491 sc->sc_rxdsoft[i].rxds_dmamap); 492 for (i = 0; i < CAS_NRXDESC; i++) 493 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 494 bus_dmamem_free(sc->sc_rdmatag, 495 sc->sc_rxdsoft[i].rxds_buf, 496 sc->sc_rxdsoft[i].rxds_dmamap); 497 for (i = 0; i < CAS_TXQUEUELEN; i++) 498 if (sc->sc_txsoft[i].txs_dmamap != NULL) 499 bus_dmamap_destroy(sc->sc_tdmatag, 500 sc->sc_txsoft[i].txs_dmamap); 501 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 502 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 503 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 504 sc->sc_cddmamap); 505 bus_dma_tag_destroy(sc->sc_cdmatag); 506 bus_dma_tag_destroy(sc->sc_tdmatag); 507 bus_dma_tag_destroy(sc->sc_rdmatag); 508 bus_dma_tag_destroy(sc->sc_pdmatag); 509} 510 511static void 512cas_suspend(struct cas_softc *sc) 513{ 514 struct ifnet *ifp = sc->sc_ifp; 515 516 CAS_LOCK(sc); 517 cas_stop(ifp); 518 CAS_UNLOCK(sc); 519} 520 521static void 522cas_resume(struct cas_softc *sc) 523{ 524 struct ifnet *ifp = sc->sc_ifp; 525 526 CAS_LOCK(sc); 527 /* 528 * On resume all registers have to be initialized again like 529 * after power-on. 530 */ 531 sc->sc_flags &= ~CAS_INITED; 532 if (ifp->if_flags & IFF_UP) 533 cas_init_locked(sc); 534 CAS_UNLOCK(sc); 535} 536 537static inline void 538cas_rxcksum(struct mbuf *m, uint16_t cksum) 539{ 540 struct ether_header *eh; 541 struct ip *ip; 542 struct udphdr *uh; 543 uint16_t *opts; 544 int32_t hlen, len, pktlen; 545 uint32_t temp32; 546 547 pktlen = m->m_pkthdr.len; 548 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 549 return; 550 eh = mtod(m, struct ether_header *); 551 if (eh->ether_type != htons(ETHERTYPE_IP)) 552 return; 553 ip = (struct ip *)(eh + 1); 554 if (ip->ip_v != IPVERSION) 555 return; 556 557 hlen = ip->ip_hl << 2; 558 pktlen -= sizeof(struct ether_header); 559 if (hlen < sizeof(struct ip)) 560 return; 561 if (ntohs(ip->ip_len) < hlen) 562 return; 563 if (ntohs(ip->ip_len) != pktlen) 564 return; 565 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 566 return; /* Cannot handle fragmented packet. */ 567 568 switch (ip->ip_p) { 569 case IPPROTO_TCP: 570 if (pktlen < (hlen + sizeof(struct tcphdr))) 571 return; 572 break; 573 case IPPROTO_UDP: 574 if (pktlen < (hlen + sizeof(struct udphdr))) 575 return; 576 uh = (struct udphdr *)((uint8_t *)ip + hlen); 577 if (uh->uh_sum == 0) 578 return; /* no checksum */ 579 break; 580 default: 581 return; 582 } 583 584 cksum = ~cksum; 585 /* checksum fixup for IP options */ 586 len = hlen - sizeof(struct ip); 587 if (len > 0) { 588 opts = (uint16_t *)(ip + 1); 589 for (; len > 0; len -= sizeof(uint16_t), opts++) { 590 temp32 = cksum - *opts; 591 temp32 = (temp32 >> 16) + (temp32 & 65535); 592 cksum = temp32 & 65535; 593 } 594 } 595 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 596 m->m_pkthdr.csum_data = cksum; 597} 598 599static void 600cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 601{ 602 struct cas_softc *sc = xsc; 603 604 if (error != 0) 605 return; 606 if (nsegs != 1) 607 panic("%s: bad control buffer segment count", __func__); 608 sc->sc_cddma = segs[0].ds_addr; 609} 610 611static void 612cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 613{ 614 struct cas_softc *sc = xsc; 615 616 if (error != 0) 617 return; 618 if (nsegs != 1) 619 panic("%s: bad RX buffer segment count", __func__); 620 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 621} 622 623static void 624cas_tick(void *arg) 625{ 626 struct cas_softc *sc = arg; 627 struct ifnet *ifp = sc->sc_ifp; 628 uint32_t v; 629 630 CAS_LOCK_ASSERT(sc, MA_OWNED); 631 632 /* 633 * Unload collision and error counters. 634 */ 635 ifp->if_collisions += 636 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 637 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT); 638 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 639 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 640 ifp->if_collisions += v; 641 ifp->if_oerrors += v; 642 ifp->if_ierrors += 643 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 644 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 645 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 646 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL); 647 648 /* 649 * Then clear the hardware counters. 650 */ 651 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 652 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 653 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 654 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 655 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 656 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 657 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 658 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 659 660 mii_tick(sc->sc_mii); 661 662 if (sc->sc_txfree != CAS_MAXTXFREE) 663 cas_tint(sc); 664 665 cas_watchdog(sc); 666 667 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 668} 669 670static int 671cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 672{ 673 int i; 674 uint32_t reg; 675 676 for (i = CAS_TRIES; i--; DELAY(100)) { 677 reg = CAS_READ_4(sc, r); 678 if ((reg & clr) == 0 && (reg & set) == set) 679 return (1); 680 } 681 return (0); 682} 683 684static void 685cas_reset(struct cas_softc *sc) 686{ 687 688#ifdef CAS_DEBUG 689 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 690#endif 691 /* Disable all interrupts in order to avoid spurious ones. */ 692 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 693 694 cas_reset_rx(sc); 695 cas_reset_tx(sc); 696 697 /* 698 * Do a full reset modulo the result of the last auto-negotiation 699 * when using the SERDES. 700 */ 701 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 702 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 703 CAS_BARRIER(sc, CAS_RESET, 4, 704 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 705 DELAY(3000); 706 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 707 device_printf(sc->sc_dev, "cannot reset device\n"); 708} 709 710static void 711cas_stop(struct ifnet *ifp) 712{ 713 struct cas_softc *sc = ifp->if_softc; 714 struct cas_txsoft *txs; 715 716#ifdef CAS_DEBUG 717 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 718#endif 719 720 callout_stop(&sc->sc_tick_ch); 721 callout_stop(&sc->sc_rx_ch); 722 723 /* Disable all interrupts in order to avoid spurious ones. */ 724 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 725 726 cas_reset_tx(sc); 727 cas_reset_rx(sc); 728 729 /* 730 * Release any queued transmit buffers. 731 */ 732 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 733 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 734 if (txs->txs_ndescs != 0) { 735 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 736 BUS_DMASYNC_POSTWRITE); 737 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 738 if (txs->txs_mbuf != NULL) { 739 m_freem(txs->txs_mbuf); 740 txs->txs_mbuf = NULL; 741 } 742 } 743 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 744 } 745 746 /* 747 * Mark the interface down and cancel the watchdog timer. 748 */ 749 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 750 sc->sc_flags &= ~CAS_LINK; 751 sc->sc_wdog_timer = 0; 752} 753 754static int 755cas_reset_rx(struct cas_softc *sc) 756{ 757 758 /* 759 * Resetting while DMA is in progress can cause a bus hang, so we 760 * disable DMA first. 761 */ 762 cas_disable_rx(sc); 763 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 764 CAS_BARRIER(sc, CAS_RX_CONF, 4, 765 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 766 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 767 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 768 769 /* Finally, reset the ERX. */ 770 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 771 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 772 CAS_BARRIER(sc, CAS_RESET, 4, 773 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 774 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) { 775 device_printf(sc->sc_dev, "cannot reset receiver\n"); 776 return (1); 777 } 778 return (0); 779} 780 781static int 782cas_reset_tx(struct cas_softc *sc) 783{ 784 785 /* 786 * Resetting while DMA is in progress can cause a bus hang, so we 787 * disable DMA first. 788 */ 789 cas_disable_tx(sc); 790 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 791 CAS_BARRIER(sc, CAS_TX_CONF, 4, 792 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 793 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 794 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 795 796 /* Finally, reset the ETX. */ 797 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 798 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 799 CAS_BARRIER(sc, CAS_RESET, 4, 800 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 801 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) { 802 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 803 return (1); 804 } 805 return (0); 806} 807 808static int 809cas_disable_rx(struct cas_softc *sc) 810{ 811 812 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 813 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 814 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 815 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 816 return (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)); 817} 818 819static int 820cas_disable_tx(struct cas_softc *sc) 821{ 822 823 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 824 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 825 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 826 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 827 return (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)); 828} 829 830static inline void 831cas_rxcompinit(struct cas_rx_comp *rxcomp) 832{ 833 834 rxcomp->crc_word1 = 0; 835 rxcomp->crc_word2 = 0; 836 rxcomp->crc_word3 = 837 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 838 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 839} 840 841static void 842cas_meminit(struct cas_softc *sc) 843{ 844 int i; 845 846 CAS_LOCK_ASSERT(sc, MA_OWNED); 847 848 /* 849 * Initialize the transmit descriptor ring. 850 */ 851 for (i = 0; i < CAS_NTXDESC; i++) { 852 sc->sc_txdescs[i].cd_flags = 0; 853 sc->sc_txdescs[i].cd_buf_ptr = 0; 854 } 855 sc->sc_txfree = CAS_MAXTXFREE; 856 sc->sc_txnext = 0; 857 sc->sc_txwin = 0; 858 859 /* 860 * Initialize the receive completion ring. 861 */ 862 for (i = 0; i < CAS_NRXCOMP; i++) 863 cas_rxcompinit(&sc->sc_rxcomps[i]); 864 sc->sc_rxcptr = 0; 865 866 /* 867 * Initialize the first receive descriptor ring. We leave 868 * the second one zeroed as we don't actually use it. 869 */ 870 for (i = 0; i < CAS_NRXDESC; i++) 871 CAS_INIT_RXDESC(sc, i, i); 872 sc->sc_rxdptr = 0; 873 874 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 875} 876 877static u_int 878cas_descsize(u_int sz) 879{ 880 881 switch (sz) { 882 case 32: 883 return (CAS_DESC_32); 884 case 64: 885 return (CAS_DESC_64); 886 case 128: 887 return (CAS_DESC_128); 888 case 256: 889 return (CAS_DESC_256); 890 case 512: 891 return (CAS_DESC_512); 892 case 1024: 893 return (CAS_DESC_1K); 894 case 2048: 895 return (CAS_DESC_2K); 896 case 4096: 897 return (CAS_DESC_4K); 898 case 8192: 899 return (CAS_DESC_8K); 900 default: 901 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 902 return (CAS_DESC_32); 903 } 904} 905 906static u_int 907cas_rxcompsize(u_int sz) 908{ 909 910 switch (sz) { 911 case 128: 912 return (CAS_RX_CONF_COMP_128); 913 case 256: 914 return (CAS_RX_CONF_COMP_256); 915 case 512: 916 return (CAS_RX_CONF_COMP_512); 917 case 1024: 918 return (CAS_RX_CONF_COMP_1K); 919 case 2048: 920 return (CAS_RX_CONF_COMP_2K); 921 case 4096: 922 return (CAS_RX_CONF_COMP_4K); 923 case 8192: 924 return (CAS_RX_CONF_COMP_8K); 925 case 16384: 926 return (CAS_RX_CONF_COMP_16K); 927 case 32768: 928 return (CAS_RX_CONF_COMP_32K); 929 default: 930 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 931 return (CAS_RX_CONF_COMP_128); 932 } 933} 934 935static void 936cas_init(void *xsc) 937{ 938 struct cas_softc *sc = xsc; 939 940 CAS_LOCK(sc); 941 cas_init_locked(sc); 942 CAS_UNLOCK(sc); 943} 944 945/* 946 * Initialization of interface; set up initialization block 947 * and transmit/receive descriptor rings. 948 */ 949static void 950cas_init_locked(struct cas_softc *sc) 951{ 952 struct ifnet *ifp = sc->sc_ifp; 953 uint32_t v; 954 955 CAS_LOCK_ASSERT(sc, MA_OWNED); 956 957 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 958 return; 959 960#ifdef CAS_DEBUG 961 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 962 __func__); 963#endif 964 /* 965 * Initialization sequence. The numbered steps below correspond 966 * to the sequence outlined in section 6.3.5.1 in the Ethernet 967 * Channel Engine manual (part of the PCIO manual). 968 * See also the STP2002-STQ document from Sun Microsystems. 969 */ 970 971 /* step 1 & 2. Reset the Ethernet Channel. */ 972 cas_stop(ifp); 973 cas_reset(sc); 974#ifdef CAS_DEBUG 975 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 976 __func__); 977#endif 978 979 if ((sc->sc_flags & CAS_SERDES) == 0) 980 /* Re-initialize the MIF. */ 981 cas_mifinit(sc); 982 983 /* step 3. Setup data structures in host memory. */ 984 cas_meminit(sc); 985 986 /* step 4. TX MAC registers & counters */ 987 cas_init_regs(sc); 988 989 /* step 5. RX MAC registers & counters */ 990 cas_setladrf(sc); 991 992 /* step 6 & 7. Program Ring Base Addresses. */ 993 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 994 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 995 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 996 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 997 998 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 999 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1000 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1001 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1002 1003 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1004 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1005 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1006 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1007 1008 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1009 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1010 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1011 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1012 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1013 } 1014 1015#ifdef CAS_DEBUG 1016 CTR5(KTR_CAS, 1017 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1018 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1019 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1020#endif 1021 1022 /* step 8. Global Configuration & Interrupt Masks */ 1023 1024 /* Disable weighted round robin. */ 1025 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1026 1027 /* 1028 * Enable infinite bursts for revisions without PCI issues if 1029 * applicable. Doing so greatly improves the TX performance on 1030 * !__sparc64__. 1031 */ 1032 CAS_WRITE_4(sc, CAS_INF_BURST, 1033#if !defined(__sparc64__) 1034 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1035#endif 1036 0); 1037 1038 /* Set up interrupts. */ 1039 CAS_WRITE_4(sc, CAS_INTMASK, 1040 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1041 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1042 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1043 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1044 CAS_INTR_PCI_ERROR_INT 1045#ifdef CAS_DEBUG 1046 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1047#endif 1048 )); 1049 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1050 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1051 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1052 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1053 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1054#ifdef CAS_DEBUG 1055 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1056 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1057 CAS_MAC_CTRL_NON_PAUSE)); 1058#else 1059 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1060 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1061 CAS_MAC_CTRL_NON_PAUSE); 1062#endif 1063 1064 /* Enable PCI error interrupts. */ 1065 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1066 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1067 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1068 1069 /* Enable PCI error interrupts in BIM configuration. */ 1070 CAS_WRITE_4(sc, CAS_BIM_CONF, 1071 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1072 1073 /* 1074 * step 9. ETX Configuration: encode receive descriptor ring size, 1075 * enable DMA and disable pre-interrupt writeback completion. 1076 */ 1077 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1078 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1079 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1080 1081 /* step 10. ERX Configuration */ 1082 1083 /* 1084 * Encode receive completion and descriptor ring sizes, set the 1085 * swivel offset. 1086 */ 1087 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1088 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1089 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1090 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1091 CAS_WRITE_4(sc, CAS_RX_CONF, 1092 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1093 1094 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1095 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1096 ((111 * 64) << CAS_RX_PTHRS_XOFF_SHFT) | 1097 ((15 * 64) << CAS_RX_PTHRS_XON_SHFT)); 1098 1099 /* RX blanking */ 1100 CAS_WRITE_4(sc, CAS_RX_BLANK, 1101 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1102 1103 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1104 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1105 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1106 1107 /* Initialize the RX page size register as appropriate for 8k. */ 1108 CAS_WRITE_4(sc, CAS_RX_PSZ, 1109 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1110 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1111 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1112 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1113 1114 /* Disable RX random early detection. */ 1115 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1116 1117 /* Zero the RX reassembly DMA table. */ 1118 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1119 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1120 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1121 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1122 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1123 } 1124 1125 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1126 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1127 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1128 1129 /* Finally, enable RX DMA. */ 1130 CAS_WRITE_4(sc, CAS_RX_CONF, 1131 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1132 1133 /* step 11. Configure Media. */ 1134 1135 /* step 12. RX_MAC Configuration Register */ 1136 v = CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_STRPPAD; 1137 v |= CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_STRPFCS; 1138 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0); 1139 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 1140 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1141 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 1142 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1143 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 1144 1145 /* step 13. TX_MAC Configuration Register */ 1146 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1147 v |= CAS_MAC_TX_CONF_EN; 1148 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0); 1149 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 1150 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1151 if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 1152 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1153 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1154 1155 /* step 14. Issue Transmit Pending command. */ 1156 1157 /* step 15. Give the reciever a swift kick. */ 1158 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1159 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1160 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1161 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1162 1163 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1164 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1165 1166 mii_mediachg(sc->sc_mii); 1167 1168 /* Start the one second timer. */ 1169 sc->sc_wdog_timer = 0; 1170 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1171} 1172 1173static int 1174cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1175{ 1176 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1177 struct cas_txsoft *txs; 1178 struct ip *ip; 1179 struct mbuf *m; 1180 uint64_t cflags; 1181 int error, nexttx, nsegs, offset, seg; 1182 1183 CAS_LOCK_ASSERT(sc, MA_OWNED); 1184 1185 /* Get a work queue entry. */ 1186 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1187 /* Ran out of descriptors. */ 1188 return (ENOBUFS); 1189 } 1190 1191 cflags = 0; 1192 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1193 if (M_WRITABLE(*m_head) == 0) { 1194 m = m_dup(*m_head, M_DONTWAIT); 1195 m_freem(*m_head); 1196 *m_head = m; 1197 if (m == NULL) 1198 return (ENOBUFS); 1199 } 1200 offset = sizeof(struct ether_header); 1201 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1202 if (m == NULL) { 1203 *m_head = NULL; 1204 return (ENOBUFS); 1205 } 1206 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1207 offset += (ip->ip_hl << 2); 1208 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1209 ((offset + m->m_pkthdr.csum_data) << 1210 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1211 *m_head = m; 1212 } 1213 1214 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1215 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1216 if (error == EFBIG) { 1217 m = m_collapse(*m_head, M_DONTWAIT, CAS_NTXSEGS); 1218 if (m == NULL) { 1219 m_freem(*m_head); 1220 *m_head = NULL; 1221 return (ENOBUFS); 1222 } 1223 *m_head = m; 1224 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1225 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1226 BUS_DMA_NOWAIT); 1227 if (error != 0) { 1228 m_freem(*m_head); 1229 *m_head = NULL; 1230 return (error); 1231 } 1232 } else if (error != 0) 1233 return (error); 1234 /* If nsegs is wrong then the stack is corrupt. */ 1235 KASSERT(nsegs <= CAS_NTXSEGS, 1236 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1237 if (nsegs == 0) { 1238 m_freem(*m_head); 1239 *m_head = NULL; 1240 return (EIO); 1241 } 1242 1243 /* 1244 * Ensure we have enough descriptors free to describe 1245 * the packet. Note, we always reserve one descriptor 1246 * at the end of the ring as a termination point, in 1247 * order to prevent wrap-around. 1248 */ 1249 if (nsegs > sc->sc_txfree - 1) { 1250 txs->txs_ndescs = 0; 1251 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1252 return (ENOBUFS); 1253 } 1254 1255 txs->txs_ndescs = nsegs; 1256 txs->txs_firstdesc = sc->sc_txnext; 1257 nexttx = txs->txs_firstdesc; 1258 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1259#ifdef CAS_DEBUG 1260 CTR6(KTR_CAS, 1261 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1262 __func__, seg, nexttx, txsegs[seg].ds_len, 1263 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1264#endif 1265 sc->sc_txdescs[nexttx].cd_buf_ptr = 1266 htole64(txsegs[seg].ds_addr); 1267 KASSERT(txsegs[seg].ds_len < 1268 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1269 ("%s: segment size too large!", __func__)); 1270 sc->sc_txdescs[nexttx].cd_flags = 1271 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1272 txs->txs_lastdesc = nexttx; 1273 } 1274 1275 /* Set EOF on the last descriptor. */ 1276#ifdef CAS_DEBUG 1277 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1278 __func__, seg, nexttx); 1279#endif 1280 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1281 htole64(CAS_TD_END_OF_FRAME); 1282 1283 /* Lastly set SOF on the first descriptor. */ 1284#ifdef CAS_DEBUG 1285 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1286 __func__, seg, nexttx); 1287#endif 1288 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1289 sc->sc_txwin = 0; 1290 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1291 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1292 } else 1293 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1294 htole64(cflags | CAS_TD_START_OF_FRAME); 1295 1296 /* Sync the DMA map. */ 1297 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1298 BUS_DMASYNC_PREWRITE); 1299 1300#ifdef CAS_DEBUG 1301 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1302 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1303 txs->txs_ndescs); 1304#endif 1305 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1306 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1307 txs->txs_mbuf = *m_head; 1308 1309 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1310 sc->sc_txfree -= txs->txs_ndescs; 1311 1312 return (0); 1313} 1314 1315static void 1316cas_init_regs(struct cas_softc *sc) 1317{ 1318 int i; 1319 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1320 1321 CAS_LOCK_ASSERT(sc, MA_OWNED); 1322 1323 /* These registers are not cleared on reset. */ 1324 if ((sc->sc_flags & CAS_INITED) == 0) { 1325 /* magic values */ 1326 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1327 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1328 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1329 1330 /* min frame length */ 1331 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1332 /* max frame length and max burst size */ 1333 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1334 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1335 CAS_MAC_MAX_BF_FRM_SHFT) | 1336 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1337 1338 /* more magic values */ 1339 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1340 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1341 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1342 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8088); 1343 1344 /* random number seed */ 1345 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1346 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1347 1348 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1349 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1350 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1351 CAS_WRITE_4(sc, i, 0); 1352 1353 /* MAC control address: 01:80:c2:00:00:01 */ 1354 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1355 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1356 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1357 1358 /* MAC filter address: 0:0:0:0:0:0 */ 1359 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1360 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1361 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1362 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1363 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1364 1365 /* Zero the hash table. */ 1366 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1367 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1368 CAS_WRITE_4(sc, i, 0); 1369 1370 sc->sc_flags |= CAS_INITED; 1371 } 1372 1373 /* Counters need to be zeroed. */ 1374 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1375 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1376 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1377 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1378 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1379 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1380 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1381 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1382 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1383 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1384 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1385 1386 /* Set XOFF PAUSE time. */ 1387 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1388 1389 /* Set the station address. */ 1390 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1391 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1392 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1393 1394 /* Enable MII outputs. */ 1395 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1396} 1397 1398static void 1399cas_tx_task(void *arg, int pending __unused) 1400{ 1401 struct ifnet *ifp; 1402 1403 ifp = (struct ifnet *)arg; 1404 cas_start(ifp); 1405} 1406 1407static inline void 1408cas_txkick(struct cas_softc *sc) 1409{ 1410 1411 /* 1412 * Update the TX kick register. This register has to point to the 1413 * descriptor after the last valid one and for optimum performance 1414 * should be incremented in multiples of 4 (the DMA engine fetches/ 1415 * updates descriptors in batches of 4). 1416 */ 1417#ifdef CAS_DEBUG 1418 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1419 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1420#endif 1421 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1422 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1423} 1424 1425static void 1426cas_start(struct ifnet *ifp) 1427{ 1428 struct cas_softc *sc = ifp->if_softc; 1429 struct mbuf *m; 1430 int kicked, ntx; 1431 1432 CAS_LOCK(sc); 1433 1434 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1435 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1436 CAS_UNLOCK(sc); 1437 return; 1438 } 1439 1440 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1441 cas_tint(sc); 1442 1443#ifdef CAS_DEBUG 1444 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1445 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1446 sc->sc_txnext); 1447#endif 1448 ntx = 0; 1449 kicked = 0; 1450 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1451 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1452 if (m == NULL) 1453 break; 1454 if (cas_load_txmbuf(sc, &m) != 0) { 1455 if (m == NULL) 1456 break; 1457 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1458 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1459 break; 1460 } 1461 if ((sc->sc_txnext % 4) == 0) { 1462 cas_txkick(sc); 1463 kicked = 1; 1464 } else 1465 kicked = 0; 1466 ntx++; 1467 BPF_MTAP(ifp, m); 1468 } 1469 1470 if (ntx > 0) { 1471 if (kicked == 0) 1472 cas_txkick(sc); 1473#ifdef CAS_DEBUG 1474 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1475 device_get_name(sc->sc_dev), sc->sc_txnext); 1476#endif 1477 1478 /* Set a watchdog timer in case the chip flakes out. */ 1479 sc->sc_wdog_timer = 5; 1480#ifdef CAS_DEBUG 1481 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1482 device_get_name(sc->sc_dev), __func__, 1483 sc->sc_wdog_timer); 1484#endif 1485 } 1486 1487 CAS_UNLOCK(sc); 1488} 1489 1490static void 1491cas_tint(struct cas_softc *sc) 1492{ 1493 struct ifnet *ifp = sc->sc_ifp; 1494 struct cas_txsoft *txs; 1495 int progress; 1496 uint32_t txlast; 1497#ifdef CAS_DEBUG 1498 int i; 1499 1500 CAS_LOCK_ASSERT(sc, MA_OWNED); 1501 1502 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1503#endif 1504 1505 /* 1506 * Go through our TX list and free mbufs for those 1507 * frames that have been transmitted. 1508 */ 1509 progress = 0; 1510 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1511 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1512#ifdef CAS_DEBUG 1513 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1514 printf(" txsoft %p transmit chain:\n", txs); 1515 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1516 printf("descriptor %d: ", i); 1517 printf("cd_flags: 0x%016llx\t", 1518 (long long)le64toh( 1519 sc->sc_txdescs[i].cd_flags)); 1520 printf("cd_buf_ptr: 0x%016llx\n", 1521 (long long)le64toh( 1522 sc->sc_txdescs[i].cd_buf_ptr)); 1523 if (i == txs->txs_lastdesc) 1524 break; 1525 } 1526 } 1527#endif 1528 1529 /* 1530 * In theory, we could harvest some descriptors before 1531 * the ring is empty, but that's a bit complicated. 1532 * 1533 * CAS_TX_COMPn points to the last descriptor 1534 * processed + 1. 1535 */ 1536 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1537#ifdef CAS_DEBUG 1538 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1539 "txs->txs_lastdesc = %d, txlast = %d", 1540 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1541#endif 1542 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1543 if ((txlast >= txs->txs_firstdesc) && 1544 (txlast <= txs->txs_lastdesc)) 1545 break; 1546 } else { 1547 /* Ick -- this command wraps. */ 1548 if ((txlast >= txs->txs_firstdesc) || 1549 (txlast <= txs->txs_lastdesc)) 1550 break; 1551 } 1552 1553#ifdef CAS_DEBUG 1554 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1555#endif 1556 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1557 1558 sc->sc_txfree += txs->txs_ndescs; 1559 1560 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1561 BUS_DMASYNC_POSTWRITE); 1562 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1563 if (txs->txs_mbuf != NULL) { 1564 m_freem(txs->txs_mbuf); 1565 txs->txs_mbuf = NULL; 1566 } 1567 1568 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1569 1570 ifp->if_opackets++; 1571 progress = 1; 1572 } 1573 1574#ifdef CAS_DEBUG 1575 CTR4(KTR_CAS, "%s: CAS_TX_STATE_MACHINE %x CAS_TX_DESC_BASE %llx " 1576 "CAS_TX_COMP3 %x", 1577 __func__, CAS_READ_4(sc, CAS_TX_STATE_MACHINE), 1578 ((long long)CAS_READ_4(sc, CAS_TX_DESC_BASE_HI3) << 32) | 1579 CAS_READ_4(sc, CAS_TX_DESC_BASE_LO3), 1580 CAS_READ_4(sc, CAS_TX_COMP3)); 1581#endif 1582 1583 if (progress) { 1584 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1585 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1586 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1587 sc->sc_wdog_timer = 0; 1588 } 1589 1590#ifdef CAS_DEBUG 1591 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1592 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1593#endif 1594} 1595 1596static void 1597cas_rint_timeout(void *arg) 1598{ 1599 struct cas_softc *sc = arg; 1600 1601 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1602 1603 cas_rint(sc); 1604} 1605 1606static void 1607cas_rint(struct cas_softc *sc) 1608{ 1609 struct cas_rxdsoft *rxds, *rxds2; 1610 struct ifnet *ifp = sc->sc_ifp; 1611 struct mbuf *m, *m2; 1612 uint64_t word1, word2, word3, word4; 1613 uint32_t rxhead; 1614 u_int idx, idx2, len, off, skip; 1615 1616 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1617 1618 callout_stop(&sc->sc_rx_ch); 1619 1620#ifdef CAS_DEBUG 1621 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1622#endif 1623 1624#define PRINTWORD(n, delimiter) \ 1625 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1626 1627#define SKIPASSERT(n) \ 1628 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1629 ("%s: word ## n not 0", __func__)) 1630 1631#define WORDTOH(n) \ 1632 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1633 1634 /* 1635 * Read the completion head register once. This limits 1636 * how long the following loop can execute. 1637 */ 1638 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1639#ifdef CAS_DEBUG 1640 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1641 __func__, sc->rxcptr, sc->sc_rxdptr, rxhead); 1642#endif 1643 skip = 0; 1644 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1645 for (; sc->sc_rxcptr != rxhead; 1646 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1647 if (skip != 0) { 1648 SKIPASSERT(1); 1649 SKIPASSERT(2); 1650 SKIPASSERT(3); 1651 1652 --skip; 1653 goto skip; 1654 } 1655 1656 WORDTOH(1); 1657 WORDTOH(2); 1658 WORDTOH(3); 1659 WORDTOH(4); 1660 1661#ifdef CAS_DEBUG 1662 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1663 printf(" completion %d: ", sc->sc_rxcptr); 1664 PRINTWORD(1, '\t'); 1665 PRINTWORD(2, '\t'); 1666 PRINTWORD(3, '\t'); 1667 PRINTWORD(4, '\n'); 1668 } 1669#endif 1670 1671 if (__predict_false( 1672 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1673 (word4 & CAS_RC4_ZERO) != 0)) { 1674 /* 1675 * The descriptor is still marked as owned, although 1676 * it is supposed to have completed. This has been 1677 * observed on some machines. Just exiting here 1678 * might leave the packet sitting around until another 1679 * one arrives to trigger a new interrupt, which is 1680 * generally undesirable, so set up a timeout. 1681 */ 1682 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1683 cas_rint_timeout, sc); 1684 break; 1685 } 1686 1687 if (__predict_false( 1688 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1689 ifp->if_ierrors++; 1690 device_printf(sc->sc_dev, 1691 "receive error: CRC error\n"); 1692 continue; 1693 } 1694 1695 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1696 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1697 ("%s: data and header present", __func__)); 1698 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1699 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1700 ("%s: split and header present", __func__)); 1701 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1702 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1703 ("%s: data present but header release", __func__)); 1704 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1705 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1706 ("%s: header present but data release", __func__)); 1707 1708 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1709 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1710 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1711#ifdef CAS_DEBUG 1712 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1713 __func__, idx, off, len); 1714#endif 1715 rxds = &sc->sc_rxdsoft[idx]; 1716 MGETHDR(m, M_DONTWAIT, MT_DATA); 1717 if (m != NULL) { 1718 refcount_acquire(&rxds->rxds_refcount); 1719 bus_dmamap_sync(sc->sc_rdmatag, 1720 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1721#if __FreeBSD_version < 800016 1722 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1723 off * 256 + ETHER_ALIGN, len, cas_free, 1724 rxds, M_RDONLY, EXT_NET_DRV); 1725#else 1726 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1727 off * 256 + ETHER_ALIGN, len, cas_free, 1728 sc, (void *)(uintptr_t)idx, 1729 M_RDONLY, EXT_NET_DRV); 1730#endif 1731 if ((m->m_flags & M_EXT) == 0) { 1732 m_freem(m); 1733 m = NULL; 1734 } 1735 } 1736 if (m != NULL) { 1737 m->m_pkthdr.rcvif = ifp; 1738 m->m_pkthdr.len = m->m_len = len; 1739 ifp->if_ipackets++; 1740 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1741 cas_rxcksum(m, CAS_GET(word4, 1742 CAS_RC4_TCP_CSUM)); 1743 /* Pass it on. */ 1744 (*ifp->if_input)(ifp, m); 1745 } else 1746 ifp->if_ierrors++; 1747 1748 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1749 refcount_release(&rxds->rxds_refcount) != 0) 1750 cas_add_rxdesc(sc, idx); 1751 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1752 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1753 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1754#ifdef CAS_DEBUG 1755 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1756 __func__, idx, off, len); 1757#endif 1758 rxds = &sc->sc_rxdsoft[idx]; 1759 MGETHDR(m, M_DONTWAIT, MT_DATA); 1760 if (m != NULL) { 1761 refcount_acquire(&rxds->rxds_refcount); 1762 off += ETHER_ALIGN; 1763 m->m_len = min(CAS_PAGE_SIZE - off, len); 1764 bus_dmamap_sync(sc->sc_rdmatag, 1765 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1766#if __FreeBSD_version < 800016 1767 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1768 m->m_len, cas_free, rxds, M_RDONLY, 1769 EXT_NET_DRV); 1770#else 1771 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1772 m->m_len, cas_free, sc, 1773 (void *)(uintptr_t)idx, M_RDONLY, 1774 EXT_NET_DRV); 1775#endif 1776 if ((m->m_flags & M_EXT) == 0) { 1777 m_freem(m); 1778 m = NULL; 1779 } 1780 } 1781 idx2 = 0; 1782 m2 = NULL; 1783 rxds2 = NULL; 1784 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1785 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1786 ("%s: split but no release next", 1787 __func__)); 1788 1789 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1790#ifdef CAS_DEBUG 1791 CTR2(KTR_CAS, "%s: split at idx %d", 1792 __func__, idx2); 1793#endif 1794 rxds2 = &sc->sc_rxdsoft[idx2]; 1795 if (m != NULL) { 1796 MGET(m2, M_DONTWAIT, MT_DATA); 1797 if (m2 != NULL) { 1798 refcount_acquire( 1799 &rxds2->rxds_refcount); 1800 m2->m_len = len - m->m_len; 1801 bus_dmamap_sync( 1802 sc->sc_rdmatag, 1803 rxds2->rxds_dmamap, 1804 BUS_DMASYNC_POSTREAD); 1805#if __FreeBSD_version < 800016 1806 MEXTADD(m2, 1807 (caddr_t)rxds2->rxds_buf, 1808 m2->m_len, cas_free, 1809 rxds2, M_RDONLY, 1810 EXT_NET_DRV); 1811#else 1812 MEXTADD(m2, 1813 (caddr_t)rxds2->rxds_buf, 1814 m2->m_len, cas_free, sc, 1815 (void *)(uintptr_t)idx2, 1816 M_RDONLY, EXT_NET_DRV); 1817#endif 1818 if ((m2->m_flags & M_EXT) == 1819 0) { 1820 m_freem(m2); 1821 m2 = NULL; 1822 } 1823 } 1824 } 1825 if (m2 != NULL) 1826 m->m_next = m2; 1827 else if (m != NULL) { 1828 m_freem(m); 1829 m = NULL; 1830 } 1831 } 1832 if (m != NULL) { 1833 m->m_pkthdr.rcvif = ifp; 1834 m->m_pkthdr.len = len; 1835 ifp->if_ipackets++; 1836 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1837 cas_rxcksum(m, CAS_GET(word4, 1838 CAS_RC4_TCP_CSUM)); 1839 /* Pass it on. */ 1840 (*ifp->if_input)(ifp, m); 1841 } else 1842 ifp->if_ierrors++; 1843 1844 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1845 refcount_release(&rxds->rxds_refcount) != 0) 1846 cas_add_rxdesc(sc, idx); 1847 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1848 refcount_release(&rxds2->rxds_refcount) != 0) 1849 cas_add_rxdesc(sc, idx2); 1850 } 1851 1852 skip = CAS_GET(word1, CAS_RC1_SKIP); 1853 1854 skip: 1855 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1856 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1857 break; 1858 } 1859 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1860 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1861 1862#undef PRINTWORD 1863#undef SKIPASSERT 1864#undef WORDTOH 1865 1866#ifdef CAS_DEBUG 1867 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1868 __func__, sc->rxcptr, sc->sc_rxdptr, 1869 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1870#endif 1871} 1872 1873static void 1874cas_free(void *arg1, void *arg2) 1875{ 1876 struct cas_rxdsoft *rxds; 1877 struct cas_softc *sc; 1878 u_int idx; 1879 1880#if __FreeBSD_version < 800016 1881 rxds = arg2; 1882 sc = rxds->rxds_sc; 1883 idx = rxds->rxds_idx; 1884#else 1885 sc = arg1; 1886 idx = (uintptr_t)arg2; 1887 rxds = &sc->sc_rxdsoft[idx]; 1888#endif 1889 if (refcount_release(&rxds->rxds_refcount) == 0) 1890 return; 1891 1892 /* 1893 * NB: this function can be called via m_freem(9) within 1894 * this driver! 1895 */ 1896 1897 cas_add_rxdesc(sc, idx); 1898} 1899 1900static inline void 1901cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1902{ 1903 u_int locked; 1904 1905 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1906 CAS_LOCK(sc); 1907 1908 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1909 BUS_DMASYNC_PREREAD); 1910 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1911 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1912 1913 /* 1914 * Update the RX kick register. This register has to point to the 1915 * descriptor after the last valid one (before the current batch) 1916 * and for optimum performance should be incremented in multiples 1917 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1918 */ 1919 if ((sc->sc_rxdptr % 4) == 0) { 1920 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1921 CAS_WRITE_4(sc, CAS_RX_KICK, 1922 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1923 } 1924 1925 if (locked == 0) 1926 CAS_UNLOCK(sc); 1927} 1928 1929static void 1930cas_eint(struct cas_softc *sc, u_int status) 1931{ 1932 struct ifnet *ifp = sc->sc_ifp; 1933 1934 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1935 1936 ifp->if_ierrors++; 1937 1938 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1939 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1940 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1941 printf(", PCI bus error 0x%x", status); 1942 if ((status & CAS_ERROR_OTHER) != 0) { 1943 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1944 printf(", PCI status 0x%x", status); 1945 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1946 } 1947 } 1948 printf("\n"); 1949 1950 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1951 cas_init(sc); 1952 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1953 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1954} 1955 1956static int 1957cas_intr(void *v) 1958{ 1959 struct cas_softc *sc = v; 1960 1961 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1962 CAS_INTR_SUMMARY) == 0)) 1963 return (FILTER_STRAY); 1964 1965 /* Disable interrupts. */ 1966 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1967 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1968 1969 return (FILTER_HANDLED); 1970} 1971 1972static void 1973cas_intr_task(void *arg, int pending __unused) 1974{ 1975 struct cas_softc *sc = arg; 1976 struct ifnet *ifp = sc->sc_ifp; 1977 uint32_t status, status2; 1978 1979 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1980 1981 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1982 return; 1983 1984 status = CAS_READ_4(sc, CAS_STATUS); 1985 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1986 goto done; 1987 1988#ifdef CAS_DEBUG 1989 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1990 device_get_name(sc->sc_dev), __func__, 1991 (status >> CAS_STATUS_TX_COMP3_SHIFT), (u_int)status); 1992 1993 /* 1994 * PCS interrupts must be cleared, otherwise no traffic is passed! 1995 */ 1996 if ((status & CAS_INTR_PCS_INT) != 0) { 1997 status2 = 1998 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 1999 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 2000 if ((status2 & CAS_PCS_INTR_LINK) != 0) 2001 device_printf(sc->sc_dev, 2002 "%s: PCS link status changed\n", __func__); 2003 } 2004 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 2005 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 2006 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2007 device_printf(sc->sc_dev, 2008 "%s: PAUSE received (PAUSE time %d slots)\n", 2009 __func__, 2010 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2011 CAS_MAC_CTRL_STATUS_PT_SHFT); 2012 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2013 device_printf(sc->sc_dev, 2014 "%s: transited to PAUSE state\n", __func__); 2015 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2016 device_printf(sc->sc_dev, 2017 "%s: transited to non-PAUSE state\n", __func__); 2018 } 2019 if ((status & CAS_INTR_MIF) != 0) 2020 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2021#endif 2022 2023 if (__predict_false((status & 2024 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2025 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2026 cas_eint(sc, status); 2027 return; 2028 } 2029 2030 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2031 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2032 if ((status2 & 2033 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2034 sc->sc_ifp->if_oerrors++; 2035 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2036 device_printf(sc->sc_dev, 2037 "MAC TX fault, status %x\n", status2); 2038 } 2039 2040 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2041 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2042 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2043 sc->sc_ifp->if_ierrors++; 2044 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2045 device_printf(sc->sc_dev, 2046 "MAC RX fault, status %x\n", status2); 2047 } 2048 2049 if ((status & 2050 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2051 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2052 cas_rint(sc); 2053#ifdef CAS_DEBUG 2054 if (__predict_false((status & 2055 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2056 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2057 device_printf(sc->sc_dev, 2058 "RX fault, status %x\n", status); 2059#endif 2060 } 2061 2062 if ((status & 2063 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) { 2064 CAS_LOCK(sc); 2065 cas_tint(sc); 2066 CAS_UNLOCK(sc); 2067 } 2068 2069 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2070 return; 2071 else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2072 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2073 2074 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2075 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2076 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2077 return; 2078 } 2079 2080 done: 2081 /* Re-enable interrupts. */ 2082 CAS_WRITE_4(sc, CAS_INTMASK, 2083 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2084 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2085 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2086 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2087 CAS_INTR_PCI_ERROR_INT 2088#ifdef CAS_DEBUG 2089 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2090#endif 2091 )); 2092} 2093 2094static void 2095cas_watchdog(struct cas_softc *sc) 2096{ 2097 struct ifnet *ifp = sc->sc_ifp; 2098 2099 CAS_LOCK_ASSERT(sc, MA_OWNED); 2100 2101#ifdef CAS_DEBUG 2102 CTR4(KTR_CAS, 2103 "%s: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONFIG %x", 2104 __func__, CAS_READ_4(sc, CAS_RX_CONFIG), 2105 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2106 CAS_READ_4(sc, CAS_MAC_RX_CONFIG)); 2107 CTR4(KTR_CAS, 2108 "%s: CAS_TX_CONFIG %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONFIG %x", 2109 __func__, CAS_READ_4(sc, CAS_TX_CONFIG), 2110 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2111 CAS_READ_4(sc, CAS_MAC_TX_CONFIG)); 2112#endif 2113 2114 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2115 return; 2116 2117 if ((sc->sc_flags & CAS_LINK) != 0) 2118 device_printf(sc->sc_dev, "device timeout\n"); 2119 else if (bootverbose) 2120 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2121 ++ifp->if_oerrors; 2122 2123 /* Try to get more packets going. */ 2124 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2125 cas_init_locked(sc); 2126 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2127 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2128} 2129 2130static void 2131cas_mifinit(struct cas_softc *sc) 2132{ 2133 2134 /* Configure the MIF in frame mode. */ 2135 CAS_WRITE_4(sc, CAS_MIF_CONF, 2136 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2137 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2138 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2139} 2140 2141/* 2142 * MII interface 2143 * 2144 * The MII interface supports at least three different operating modes: 2145 * 2146 * Bitbang mode is implemented using data, clock and output enable registers. 2147 * 2148 * Frame mode is implemented by loading a complete frame into the frame 2149 * register and polling the valid bit for completion. 2150 * 2151 * Polling mode uses the frame register but completion is indicated by 2152 * an interrupt. 2153 * 2154 */ 2155static int 2156cas_mii_readreg(device_t dev, int phy, int reg) 2157{ 2158 struct cas_softc *sc; 2159 int n; 2160 uint32_t v; 2161 2162#ifdef CAS_DEBUG_PHY 2163 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2164#endif 2165 2166 sc = device_get_softc(dev); 2167 if ((sc->sc_flags & CAS_SERDES) != 0) { 2168 switch (reg) { 2169 case MII_BMCR: 2170 reg = CAS_PCS_CTRL; 2171 break; 2172 case MII_BMSR: 2173 reg = CAS_PCS_STATUS; 2174 break; 2175 case MII_PHYIDR1: 2176 case MII_PHYIDR2: 2177 return (0); 2178 case MII_ANAR: 2179 reg = CAS_PCS_ANAR; 2180 break; 2181 case MII_ANLPAR: 2182 reg = CAS_PCS_ANLPAR; 2183 break; 2184 case MII_EXTSR: 2185 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2186 default: 2187 device_printf(sc->sc_dev, 2188 "%s: unhandled register %d\n", __func__, reg); 2189 return (0); 2190 } 2191 return (CAS_READ_4(sc, reg)); 2192 } 2193 2194 /* Construct the frame command. */ 2195 v = CAS_MIF_FRAME_READ | 2196 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2197 (reg << CAS_MIF_FRAME_REG_SHFT); 2198 2199 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2200 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2201 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2202 for (n = 0; n < 100; n++) { 2203 DELAY(1); 2204 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2205 if (v & CAS_MIF_FRAME_TA_LSB) 2206 return (v & CAS_MIF_FRAME_DATA); 2207 } 2208 2209 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2210 return (0); 2211} 2212 2213static int 2214cas_mii_writereg(device_t dev, int phy, int reg, int val) 2215{ 2216 struct cas_softc *sc; 2217 int n; 2218 uint32_t v; 2219 2220#ifdef CAS_DEBUG_PHY 2221 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2222#endif 2223 2224 sc = device_get_softc(dev); 2225 if ((sc->sc_flags & CAS_SERDES) != 0) { 2226 switch (reg) { 2227 case MII_BMSR: 2228 reg = CAS_PCS_STATUS; 2229 break; 2230 case MII_BMCR: 2231 reg = CAS_PCS_CTRL; 2232 if ((val & CAS_PCS_CTRL_RESET) == 0) 2233 break; 2234 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2235 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2236 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2237 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2238 CAS_PCS_CTRL_RESET, 0)) 2239 device_printf(sc->sc_dev, 2240 "cannot reset PCS\n"); 2241 /* FALLTHROUGH */ 2242 case MII_ANAR: 2243 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2244 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2245 BUS_SPACE_BARRIER_WRITE); 2246 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2247 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2248 BUS_SPACE_BARRIER_WRITE); 2249 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2250 CAS_PCS_SERDES_CTRL_ESD); 2251 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2252 BUS_SPACE_BARRIER_WRITE); 2253 CAS_WRITE_4(sc, CAS_PCS_CONF, 2254 CAS_PCS_CONF_EN); 2255 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2256 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2257 return (0); 2258 case MII_ANLPAR: 2259 reg = CAS_PCS_ANLPAR; 2260 break; 2261 default: 2262 device_printf(sc->sc_dev, 2263 "%s: unhandled register %d\n", __func__, reg); 2264 return (0); 2265 } 2266 CAS_WRITE_4(sc, reg, val); 2267 CAS_BARRIER(sc, reg, 4, 2268 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2269 return (0); 2270 } 2271 2272 /* Construct the frame command. */ 2273 v = CAS_MIF_FRAME_WRITE | 2274 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2275 (reg << CAS_MIF_FRAME_REG_SHFT) | 2276 (val & CAS_MIF_FRAME_DATA); 2277 2278 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2279 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2280 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2281 for (n = 0; n < 100; n++) { 2282 DELAY(1); 2283 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2284 if (v & CAS_MIF_FRAME_TA_LSB) 2285 return (1); 2286 } 2287 2288 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2289 return (0); 2290} 2291 2292static void 2293cas_mii_statchg(device_t dev) 2294{ 2295 struct cas_softc *sc; 2296 struct ifnet *ifp; 2297 int gigabit; 2298 uint32_t rxcfg, txcfg, v; 2299 2300 sc = device_get_softc(dev); 2301 ifp = sc->sc_ifp; 2302 2303 CAS_LOCK_ASSERT(sc, MA_OWNED); 2304 2305#ifdef CAS_DEBUG 2306 if ((ifp->if_flags & IFF_DEBUG) != 0) 2307 device_printf(sc->sc_dev, "%s: status changen", __func__); 2308#endif 2309 2310 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2311 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2312 sc->sc_flags |= CAS_LINK; 2313 else 2314 sc->sc_flags &= ~CAS_LINK; 2315 2316 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2317 case IFM_1000_SX: 2318 case IFM_1000_LX: 2319 case IFM_1000_CX: 2320 case IFM_1000_T: 2321 gigabit = 1; 2322 break; 2323 default: 2324 gigabit = 0; 2325 } 2326 2327 /* 2328 * The configuration done here corresponds to the steps F) and 2329 * G) and as far as enabling of RX and TX MAC goes also step H) 2330 * of the initialization sequence outlined in section 11.2.1 of 2331 * the Cassini+ ASIC Specification. 2332 */ 2333 2334 rxcfg = CAS_READ_4(sc, CAS_MAC_RX_CONF); 2335 rxcfg &= ~(CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_CARR); 2336 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2337 CAS_MAC_TX_CONF_NGUL; 2338 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2339 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2340 else if (gigabit != 0) { 2341 rxcfg |= CAS_MAC_RX_CONF_CARR; 2342 txcfg |= CAS_MAC_TX_CONF_CARR; 2343 } 2344 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0); 2345 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 2346 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2347 if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 2348 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2349 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2350 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0); 2351 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2352 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2353 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 2354 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2355 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2356 2357 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2358 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2359#ifdef notyet 2360 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2361 IFM_ETH_RXPAUSE) != 0) 2362 v |= CAS_MAC_CTRL_CONF_RXP; 2363 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2364 IFM_ETH_TXPAUSE) != 0) 2365 v |= CAS_MAC_CTRL_CONF_TXP; 2366#endif 2367 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2368 2369 /* 2370 * All supported chips have a bug causing incorrect checksum 2371 * to be calculated when letting them strip the FCS in half- 2372 * duplex mode. In theory we could disable FCS stripping and 2373 * manually adjust the checksum accordingly. It seems to make 2374 * more sense to optimze for the common case and just disable 2375 * hardware checksumming in half-duplex mode though. 2376 */ 2377 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2378 ifp->if_capenable &= ~IFCAP_HWCSUM; 2379 ifp->if_hwassist = 0; 2380 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2381 ifp->if_capenable = ifp->if_capabilities; 2382 ifp->if_hwassist = CAS_CSUM_FEATURES; 2383 } 2384 2385 if (sc->sc_variant == CAS_SATURN) { 2386 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2387 /* silicon bug workaround */ 2388 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2389 else 2390 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2391 } 2392 2393 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2394 gigabit != 0) 2395 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2396 CAS_MAC_SLOT_TIME_CARR); 2397 else 2398 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2399 CAS_MAC_SLOT_TIME_NORM); 2400 2401 /* XIF Configuration */ 2402 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2403 if ((sc->sc_flags & CAS_SERDES) == 0) { 2404 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2405 v |= CAS_MAC_XIF_CONF_NOECHO; 2406 v |= CAS_MAC_XIF_CONF_BUF_OE; 2407 } 2408 if (gigabit != 0) 2409 v |= CAS_MAC_XIF_CONF_GMII; 2410 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2411 v |= CAS_MAC_XIF_CONF_FDXLED; 2412 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2413 2414 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2415 (sc->sc_flags & CAS_LINK) != 0) { 2416 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2417 txcfg | CAS_MAC_TX_CONF_EN); 2418 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2419 rxcfg | CAS_MAC_RX_CONF_EN); 2420 } 2421} 2422 2423static int 2424cas_mediachange(struct ifnet *ifp) 2425{ 2426 struct cas_softc *sc = ifp->if_softc; 2427 int error; 2428 2429 /* XXX add support for serial media. */ 2430 2431 CAS_LOCK(sc); 2432 error = mii_mediachg(sc->sc_mii); 2433 CAS_UNLOCK(sc); 2434 return (error); 2435} 2436 2437static void 2438cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2439{ 2440 struct cas_softc *sc = ifp->if_softc; 2441 2442 CAS_LOCK(sc); 2443 if ((ifp->if_flags & IFF_UP) == 0) { 2444 CAS_UNLOCK(sc); 2445 return; 2446 } 2447 2448 mii_pollstat(sc->sc_mii); 2449 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2450 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2451 CAS_UNLOCK(sc); 2452} 2453 2454static int 2455cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2456{ 2457 struct cas_softc *sc = ifp->if_softc; 2458 struct ifreq *ifr = (struct ifreq *)data; 2459 int error; 2460 2461 error = 0; 2462 switch (cmd) { 2463 case SIOCSIFFLAGS: 2464 CAS_LOCK(sc); 2465 if ((ifp->if_flags & IFF_UP) != 0) { 2466 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2467 ((ifp->if_flags ^ sc->sc_ifflags) & 2468 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2469 cas_setladrf(sc); 2470 else 2471 cas_init_locked(sc); 2472 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2473 cas_stop(ifp); 2474 sc->sc_ifflags = ifp->if_flags; 2475 CAS_UNLOCK(sc); 2476 break; 2477 case SIOCSIFCAP: 2478 CAS_LOCK(sc); 2479 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2480 error = EINVAL; 2481 CAS_UNLOCK(sc); 2482 break; 2483 } 2484 ifp->if_capenable = ifr->ifr_reqcap; 2485 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2486 ifp->if_hwassist = CAS_CSUM_FEATURES; 2487 else 2488 ifp->if_hwassist = 0; 2489 CAS_UNLOCK(sc); 2490 break; 2491 case SIOCADDMULTI: 2492 case SIOCDELMULTI: 2493 CAS_LOCK(sc); 2494 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2495 cas_setladrf(sc); 2496 CAS_UNLOCK(sc); 2497 break; 2498 case SIOCSIFMTU: 2499 if ((ifr->ifr_mtu < ETHERMIN) || 2500 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2501 error = EINVAL; 2502 else 2503 ifp->if_mtu = ifr->ifr_mtu; 2504 break; 2505 case SIOCGIFMEDIA: 2506 case SIOCSIFMEDIA: 2507 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2508 break; 2509 default: 2510 error = ether_ioctl(ifp, cmd, data); 2511 break; 2512 } 2513 2514 return (error); 2515} 2516 2517static void 2518cas_setladrf(struct cas_softc *sc) 2519{ 2520 struct ifnet *ifp = sc->sc_ifp; 2521 struct ifmultiaddr *inm; 2522 int i; 2523 uint32_t hash[16]; 2524 uint32_t crc, v; 2525 2526 CAS_LOCK_ASSERT(sc, MA_OWNED); 2527 2528 /* Get the current RX configuration. */ 2529 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 2530 2531 /* 2532 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2533 * and hash filter. Depending on the case, the right bit will be 2534 * enabled. 2535 */ 2536 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_HFILTER | 2537 CAS_MAC_RX_CONF_PGRP); 2538 2539 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2540 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2541 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2542 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER, 0)) 2543 device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2544 2545 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2546 v |= CAS_MAC_RX_CONF_PROMISC; 2547 goto chipit; 2548 } 2549 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2550 v |= CAS_MAC_RX_CONF_PGRP; 2551 goto chipit; 2552 } 2553 2554 /* 2555 * Set up multicast address filter by passing all multicast 2556 * addresses through a crc generator, and then using the high 2557 * order 8 bits as an index into the 256 bit logical address 2558 * filter. The high order 4 bits selects the word, while the 2559 * other 4 bits select the bit within the word (where bit 0 2560 * is the MSB). 2561 */ 2562 2563 /* Clear the hash table. */ 2564 memset(hash, 0, sizeof(hash)); 2565 2566 if_maddr_rlock(ifp); 2567 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2568 if (inm->ifma_addr->sa_family != AF_LINK) 2569 continue; 2570 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2571 inm->ifma_addr), ETHER_ADDR_LEN); 2572 2573 /* We just want the 8 most significant bits. */ 2574 crc >>= 24; 2575 2576 /* Set the corresponding bit in the filter. */ 2577 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2578 } 2579 if_maddr_runlock(ifp); 2580 2581 v |= CAS_MAC_RX_CONF_HFILTER; 2582 2583 /* Now load the hash table into the chip (if we are using it). */ 2584 for (i = 0; i < 16; i++) 2585 CAS_WRITE_4(sc, 2586 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2587 hash[i]); 2588 2589 chipit: 2590 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2591} 2592 2593static int cas_pci_attach(device_t dev); 2594static int cas_pci_detach(device_t dev); 2595static int cas_pci_probe(device_t dev); 2596static int cas_pci_resume(device_t dev); 2597static int cas_pci_suspend(device_t dev); 2598 2599static device_method_t cas_pci_methods[] = { 2600 /* Device interface */ 2601 DEVMETHOD(device_probe, cas_pci_probe), 2602 DEVMETHOD(device_attach, cas_pci_attach), 2603 DEVMETHOD(device_detach, cas_pci_detach), 2604 DEVMETHOD(device_suspend, cas_pci_suspend), 2605 DEVMETHOD(device_resume, cas_pci_resume), 2606 /* Use the suspend handler here, it is all that is required. */ 2607 DEVMETHOD(device_shutdown, cas_pci_suspend), 2608 2609 /* bus interface */ 2610 DEVMETHOD(bus_print_child, bus_generic_print_child), 2611 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2612 2613 /* MII interface */ 2614 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2615 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2616 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2617 2618 KOBJMETHOD_END 2619}; 2620 2621static driver_t cas_pci_driver = { 2622 "cas", 2623 cas_pci_methods, 2624 sizeof(struct cas_softc) 2625}; 2626 2627DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2628DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2629MODULE_DEPEND(cas, pci, 1, 1, 1); 2630 2631static const struct cas_pci_dev { 2632 uint32_t cpd_devid; 2633 uint8_t cpd_revid; 2634 int cpd_variant; 2635 const char *cpd_desc; 2636} const cas_pci_devlist[] = { 2637 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2638 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2639 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2640 { 0, 0, 0, NULL } 2641}; 2642 2643static int 2644cas_pci_probe(device_t dev) 2645{ 2646 int i; 2647 2648 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2649 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2650 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2651 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2652 return (BUS_PROBE_DEFAULT); 2653 } 2654 } 2655 2656 return (ENXIO); 2657} 2658 2659static struct resource_spec cas_pci_res_spec[] = { 2660 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2661 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2662 { -1, 0 } 2663}; 2664 2665#define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2666#define CAS_PHY_INTERFACE "phy-interface" 2667#define CAS_PHY_TYPE "phy-type" 2668#define CAS_PHY_TYPE_PCS "pcs" 2669 2670static int 2671cas_pci_attach(device_t dev) 2672{ 2673 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2674 struct cas_softc *sc; 2675 int i; 2676#if !(defined(__powerpc__) || defined(__sparc64__)) 2677 u_char enaddr[4][ETHER_ADDR_LEN]; 2678 u_int j, k, lma, pcs[4], phy; 2679#endif 2680 2681 sc = device_get_softc(dev); 2682 sc->sc_variant = CAS_UNKNOWN; 2683 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2684 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2685 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2686 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2687 break; 2688 } 2689 } 2690 if (sc->sc_variant == CAS_UNKNOWN) { 2691 device_printf(dev, "unknown adaptor\n"); 2692 return (ENXIO); 2693 } 2694 2695 pci_enable_busmaster(dev); 2696 2697 sc->sc_dev = dev; 2698 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2699 /* Hardware checksumming may hang TX. */ 2700 sc->sc_flags |= CAS_NO_CSUM; 2701 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2702 sc->sc_flags |= CAS_REG_PLUS; 2703 if (sc->sc_variant == CAS_CAS || 2704 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2705 sc->sc_flags |= CAS_TABORT; 2706 if (bootverbose) 2707 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2708 2709 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2710 device_printf(dev, "failed to allocate resources\n"); 2711 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2712 return (ENXIO); 2713 } 2714 2715 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2716 2717#if defined(__powerpc__) || defined(__sparc64__) 2718 OF_getetheraddr(dev, sc->sc_enaddr); 2719 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2720 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2721 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2722 buf[sizeof(buf) - 1] = '\0'; 2723 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2724 sc->sc_flags |= CAS_SERDES; 2725 } 2726#else 2727 /* 2728 * Dig out VPD (vital product data) and read the MAC address as well 2729 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2730 * FCode) and can't be accessed via the PCI capability pointer. 2731 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2732 * in the free US Patent 7149820. 2733 */ 2734 2735#define PCI_ROMHDR_SIZE 0x1c 2736#define PCI_ROMHDR_SIG 0x00 2737#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2738#define PCI_ROMHDR_PTR_DATA 0x18 2739#define PCI_ROM_SIZE 0x18 2740#define PCI_ROM_SIG 0x00 2741#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2742 /* reversed */ 2743#define PCI_ROM_VENDOR 0x04 2744#define PCI_ROM_DEVICE 0x06 2745#define PCI_ROM_PTR_VPD 0x08 2746#define PCI_VPDRES_BYTE0 0x00 2747#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2748#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2749#define PCI_VPDRES_LARGE_LEN_LSB 0x01 2750#define PCI_VPDRES_LARGE_LEN_MSB 0x02 2751#define PCI_VPDRES_LARGE_SIZE 0x03 2752#define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2753#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2754#define PCI_VPD_KEY0 0x00 2755#define PCI_VPD_KEY1 0x01 2756#define PCI_VPD_LEN 0x02 2757#define PCI_VPD_SIZE 0x03 2758 2759#define CAS_ROM_READ_1(sc, offs) \ 2760 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2761#define CAS_ROM_READ_2(sc, offs) \ 2762 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2763#define CAS_ROM_READ_4(sc, offs) \ 2764 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2765 2766 lma = phy = 0; 2767 memset(enaddr, 0, sizeof(enaddr)); 2768 memset(pcs, 0, sizeof(pcs)); 2769 2770 /* Enable PCI Expansion ROM access. */ 2771 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2772 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2773 2774 /* Read PCI Expansion ROM header. */ 2775 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2776 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2777 PCI_ROMHDR_SIZE) { 2778 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2779 goto fail_prom; 2780 } 2781 2782 /* Read PCI Expansion ROM data. */ 2783 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2784 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2785 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2786 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2787 i + PCI_ROM_SIZE) { 2788 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2789 goto fail_prom; 2790 } 2791 2792 /* Read PCI VPD. */ 2793 next: 2794 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2795 j + PCI_VPDRES_BYTE0)) == 0) { 2796 device_printf(dev, "no large PCI VPD\n"); 2797 goto fail_prom; 2798 } 2799 2800 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2801 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2802 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2803 j + PCI_VPDRES_BYTE0))) { 2804 case PCI_VPDRES_TYPE_ID_STRING: 2805 /* Skip identifier string. */ 2806 j += PCI_VPDRES_LARGE_SIZE + i; 2807 goto next; 2808 case PCI_VPDRES_TYPE_VPD: 2809 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2810 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2811 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2812 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2813 /* no Enhanced VPD */ 2814 continue; 2815 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2816 /* no instance property */ 2817 continue; 2818 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2819 /* byte array */ 2820 if (CAS_ROM_READ_1(sc, 2821 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2822 continue; 2823 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2824 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2825 buf, sizeof(buf)); 2826 buf[sizeof(buf) - 1] = '\0'; 2827 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2828 continue; 2829 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2830 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2831 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2832 enaddr[lma], sizeof(enaddr[lma])); 2833 lma++; 2834 if (lma == 4 && phy == 4) 2835 break; 2836 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2837 'S') { 2838 /* string */ 2839 if (CAS_ROM_READ_1(sc, 2840 j + PCI_VPD_SIZE + 4) != 2841 sizeof(CAS_PHY_TYPE_PCS)) 2842 continue; 2843 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2844 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2845 buf, sizeof(buf)); 2846 buf[sizeof(buf) - 1] = '\0'; 2847 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2848 k = sizeof(CAS_PHY_INTERFACE); 2849 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2850 k = sizeof(CAS_PHY_TYPE); 2851 else 2852 continue; 2853 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2854 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2855 5 + k, buf, sizeof(buf)); 2856 buf[sizeof(buf) - 1] = '\0'; 2857 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2858 pcs[phy] = 1; 2859 phy++; 2860 if (lma == 4 && phy == 4) 2861 break; 2862 } 2863 } 2864 break; 2865 default: 2866 device_printf(dev, "unexpected PCI VPD\n"); 2867 goto fail_prom; 2868 } 2869 2870 fail_prom: 2871 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2872 2873 if (lma == 0) { 2874 device_printf(dev, "could not determine Ethernet address\n"); 2875 goto fail; 2876 } 2877 i = 0; 2878 if (lma > 1 && pci_get_slot(dev) < sizeof(enaddr) / sizeof(*enaddr)) 2879 i = pci_get_slot(dev); 2880 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2881 2882 if (phy == 0) { 2883 device_printf(dev, "could not determine PHY type\n"); 2884 goto fail; 2885 } 2886 i = 0; 2887 if (phy > 1 && pci_get_slot(dev) < sizeof(pcs) / sizeof(*pcs)) 2888 i = pci_get_slot(dev); 2889 if (pcs[i] != 0) 2890 sc->sc_flags |= CAS_SERDES; 2891#endif 2892 2893 if (cas_attach(sc) != 0) { 2894 device_printf(dev, "could not be attached\n"); 2895 goto fail; 2896 } 2897 2898 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2899 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2900 device_printf(dev, "failed to set up interrupt\n"); 2901 cas_detach(sc); 2902 goto fail; 2903 } 2904 return (0); 2905 2906 fail: 2907 CAS_LOCK_DESTROY(sc); 2908 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2909 return (ENXIO); 2910} 2911 2912static int 2913cas_pci_detach(device_t dev) 2914{ 2915 struct cas_softc *sc; 2916 2917 sc = device_get_softc(dev); 2918 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2919 cas_detach(sc); 2920 CAS_LOCK_DESTROY(sc); 2921 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2922 return (0); 2923} 2924 2925static int 2926cas_pci_suspend(device_t dev) 2927{ 2928 2929 cas_suspend(device_get_softc(dev)); 2930 return (0); 2931} 2932 2933static int 2934cas_pci_resume(device_t dev) 2935{ 2936 2937 cas_resume(device_get_softc(dev)); 2938 return (0); 2939} 2940