1194246Smarius/*- 2194246Smarius * Copyright (C) 2001 Eduardo Horvath. 3194246Smarius * Copyright (c) 2001-2003 Thomas Moestl 4194246Smarius * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5194246Smarius * All rights reserved. 6194246Smarius * 7194246Smarius * Redistribution and use in source and binary forms, with or without 8194246Smarius * modification, are permitted provided that the following conditions 9194246Smarius * are met: 10194246Smarius * 1. Redistributions of source code must retain the above copyright 11194246Smarius * notice, this list of conditions and the following disclaimer. 12194246Smarius * 2. Redistributions in binary form must reproduce the above copyright 13194246Smarius * notice, this list of conditions and the following disclaimer in the 14194246Smarius * documentation and/or other materials provided with the distribution. 15194246Smarius * 16194246Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17194246Smarius * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18194246Smarius * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19194246Smarius * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20194246Smarius * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21194246Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22194246Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23194246Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24194246Smarius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25194246Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26194246Smarius * SUCH DAMAGE. 27194246Smarius * 28194246Smarius * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29194246Smarius * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30194246Smarius */ 31194246Smarius 32194246Smarius#include <sys/cdefs.h> 33194246Smarius__FBSDID("$FreeBSD$"); 34194246Smarius 35194246Smarius/* 36194246Smarius * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37194246Smarius * Saturn Gigabit Ethernet controllers 38194246Smarius */ 39194246Smarius 40194246Smarius#if 0 41194246Smarius#define CAS_DEBUG 42194246Smarius#endif 43194246Smarius 44194246Smarius#include <sys/param.h> 45194246Smarius#include <sys/systm.h> 46194246Smarius#include <sys/bus.h> 47194246Smarius#include <sys/callout.h> 48194246Smarius#include <sys/endian.h> 49194246Smarius#include <sys/mbuf.h> 50194246Smarius#include <sys/malloc.h> 51194246Smarius#include <sys/kernel.h> 52194246Smarius#include <sys/lock.h> 53194246Smarius#include <sys/module.h> 54194246Smarius#include <sys/mutex.h> 55194246Smarius#include <sys/refcount.h> 56194246Smarius#include <sys/resource.h> 57194246Smarius#include <sys/rman.h> 58194246Smarius#include <sys/socket.h> 59194246Smarius#include <sys/sockio.h> 60194904Smarius#include <sys/taskqueue.h> 61194246Smarius 62194246Smarius#include <net/bpf.h> 63194246Smarius#include <net/ethernet.h> 64194246Smarius#include <net/if.h> 65257176Sglebius#include <net/if_var.h> 66194246Smarius#include <net/if_arp.h> 67194246Smarius#include <net/if_dl.h> 68194246Smarius#include <net/if_media.h> 69194246Smarius#include <net/if_types.h> 70194246Smarius#include <net/if_vlan_var.h> 71194246Smarius 72194246Smarius#include <netinet/in.h> 73194246Smarius#include <netinet/in_systm.h> 74194246Smarius#include <netinet/ip.h> 75194246Smarius#include <netinet/tcp.h> 76194246Smarius#include <netinet/udp.h> 77194246Smarius 78194246Smarius#include <machine/bus.h> 79194246Smarius#if defined(__powerpc__) || defined(__sparc64__) 80207585Smarius#include <dev/ofw/ofw_bus.h> 81194246Smarius#include <dev/ofw/openfirm.h> 82194246Smarius#include <machine/ofw_machdep.h> 83194246Smarius#endif 84194246Smarius#include <machine/resource.h> 85194246Smarius 86194246Smarius#include <dev/mii/mii.h> 87194246Smarius#include <dev/mii/miivar.h> 88194246Smarius 89194246Smarius#include <dev/cas/if_casreg.h> 90194246Smarius#include <dev/cas/if_casvar.h> 91194246Smarius 92194246Smarius#include <dev/pci/pcireg.h> 93194246Smarius#include <dev/pci/pcivar.h> 94194246Smarius 95194246Smarius#include "miibus_if.h" 96194246Smarius 97194246Smarius#define RINGASSERT(n , min, max) \ 98194246Smarius CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 99194246Smarius 100194246SmariusRINGASSERT(CAS_NRXCOMP, 128, 32768); 101194246SmariusRINGASSERT(CAS_NRXDESC, 32, 8192); 102194246SmariusRINGASSERT(CAS_NRXDESC2, 32, 8192); 103194246SmariusRINGASSERT(CAS_NTXDESC, 32, 8192); 104194246Smarius 105194246Smarius#undef RINGASSERT 106194246Smarius 107194246Smarius#define CCDASSERT(m, a) \ 108194246Smarius CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 109194246Smarius 110194246SmariusCCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 111194246SmariusCCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 112194246SmariusCCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 113194246Smarius 114194246Smarius#undef CCDASSERT 115194246Smarius 116194246Smarius#define CAS_TRIES 10000 117194246Smarius 118194246Smarius/* 119194246Smarius * According to documentation, the hardware has support for basic TCP 120194246Smarius * checksum offloading only, in practice this can be also used for UDP 121194246Smarius * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 122194246Smarius * is not converted to 0xffff no longer exists). 123194246Smarius */ 124194246Smarius#define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 125194246Smarius 126194246Smariusstatic inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 127194246Smariusstatic int cas_attach(struct cas_softc *sc); 128194246Smariusstatic int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 129194246Smarius uint32_t set); 130194246Smariusstatic void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 131194246Smarius int nsegs, int error); 132194246Smariusstatic void cas_detach(struct cas_softc *sc); 133194246Smariusstatic int cas_disable_rx(struct cas_softc *sc); 134194246Smariusstatic int cas_disable_tx(struct cas_softc *sc); 135194246Smariusstatic void cas_eint(struct cas_softc *sc, u_int status); 136268529Sglebiusstatic void cas_free(struct mbuf *m, void *arg1, void* arg2); 137194246Smariusstatic void cas_init(void *xsc); 138194246Smariusstatic void cas_init_locked(struct cas_softc *sc); 139194246Smariusstatic void cas_init_regs(struct cas_softc *sc); 140194904Smariusstatic int cas_intr(void *v); 141194904Smariusstatic void cas_intr_task(void *arg, int pending __unused); 142194246Smariusstatic int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 143194246Smariusstatic int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 144194246Smariusstatic int cas_mediachange(struct ifnet *ifp); 145194246Smariusstatic void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 146194246Smariusstatic void cas_meminit(struct cas_softc *sc); 147194246Smariusstatic void cas_mifinit(struct cas_softc *sc); 148194246Smariusstatic int cas_mii_readreg(device_t dev, int phy, int reg); 149194246Smariusstatic void cas_mii_statchg(device_t dev); 150194246Smariusstatic int cas_mii_writereg(device_t dev, int phy, int reg, int val); 151194246Smariusstatic void cas_reset(struct cas_softc *sc); 152194246Smariusstatic int cas_reset_rx(struct cas_softc *sc); 153194246Smariusstatic int cas_reset_tx(struct cas_softc *sc); 154194246Smariusstatic void cas_resume(struct cas_softc *sc); 155194246Smariusstatic u_int cas_descsize(u_int sz); 156194246Smariusstatic void cas_rint(struct cas_softc *sc); 157194246Smariusstatic void cas_rint_timeout(void *arg); 158194246Smariusstatic inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 159194246Smariusstatic inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 160194246Smariusstatic u_int cas_rxcompsize(u_int sz); 161194246Smariusstatic void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 162194246Smarius int nsegs, int error); 163194246Smariusstatic void cas_setladrf(struct cas_softc *sc); 164194246Smariusstatic void cas_start(struct ifnet *ifp); 165194246Smariusstatic void cas_stop(struct ifnet *ifp); 166194246Smariusstatic void cas_suspend(struct cas_softc *sc); 167194246Smariusstatic void cas_tick(void *arg); 168194246Smariusstatic void cas_tint(struct cas_softc *sc); 169194904Smariusstatic void cas_tx_task(void *arg, int pending __unused); 170194246Smariusstatic inline void cas_txkick(struct cas_softc *sc); 171194904Smariusstatic void cas_watchdog(struct cas_softc *sc); 172194246Smarius 173194246Smariusstatic devclass_t cas_devclass; 174194246Smarius 175194246SmariusMODULE_DEPEND(cas, ether, 1, 1, 1); 176194246SmariusMODULE_DEPEND(cas, miibus, 1, 1, 1); 177194246Smarius 178194246Smarius#ifdef CAS_DEBUG 179194246Smarius#include <sys/ktr.h> 180210334Sattilio#define KTR_CAS KTR_SPARE2 181194246Smarius#endif 182194246Smarius 183194246Smariusstatic int 184194246Smariuscas_attach(struct cas_softc *sc) 185194246Smarius{ 186194246Smarius struct cas_txsoft *txs; 187194246Smarius struct ifnet *ifp; 188194246Smarius int error, i; 189194246Smarius uint32_t v; 190194246Smarius 191194246Smarius /* Set up ifnet structure. */ 192194246Smarius ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 193194246Smarius if (ifp == NULL) 194194246Smarius return (ENOSPC); 195194246Smarius ifp->if_softc = sc; 196194246Smarius if_initname(ifp, device_get_name(sc->sc_dev), 197194246Smarius device_get_unit(sc->sc_dev)); 198194246Smarius ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 199194246Smarius ifp->if_start = cas_start; 200194246Smarius ifp->if_ioctl = cas_ioctl; 201194246Smarius ifp->if_init = cas_init; 202194246Smarius IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 203194246Smarius ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 204194246Smarius IFQ_SET_READY(&ifp->if_snd); 205194246Smarius 206194246Smarius callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 207223986Smarius callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 208194904Smarius /* Create local taskq. */ 209194904Smarius TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 210194904Smarius TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 211194904Smarius sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 212194904Smarius taskqueue_thread_enqueue, &sc->sc_tq); 213194904Smarius if (sc->sc_tq == NULL) { 214194904Smarius device_printf(sc->sc_dev, "could not create taskqueue\n"); 215194904Smarius error = ENXIO; 216194904Smarius goto fail_ifnet; 217194904Smarius } 218245923Smarius error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 219194904Smarius device_get_nameunit(sc->sc_dev)); 220245923Smarius if (error != 0) { 221245923Smarius device_printf(sc->sc_dev, "could not start threads\n"); 222245923Smarius goto fail_taskq; 223245923Smarius } 224194246Smarius 225194246Smarius /* Make sure the chip is stopped. */ 226194246Smarius cas_reset(sc); 227194246Smarius 228194246Smarius error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 229194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 230194246Smarius BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 231194246Smarius &sc->sc_pdmatag); 232194246Smarius if (error != 0) 233194904Smarius goto fail_taskq; 234194246Smarius 235194246Smarius error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 236194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 237194246Smarius CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 238194246Smarius if (error != 0) 239194246Smarius goto fail_ptag; 240194246Smarius 241194246Smarius error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 242194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 243194246Smarius MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 244194246Smarius BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 245194246Smarius if (error != 0) 246194246Smarius goto fail_rtag; 247194246Smarius 248194246Smarius error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 249194246Smarius BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 250194246Smarius sizeof(struct cas_control_data), 1, 251194246Smarius sizeof(struct cas_control_data), 0, 252194246Smarius NULL, NULL, &sc->sc_cdmatag); 253194246Smarius if (error != 0) 254194246Smarius goto fail_ttag; 255194246Smarius 256194246Smarius /* 257194246Smarius * Allocate the control data structures, create and load the 258194246Smarius * DMA map for it. 259194246Smarius */ 260194246Smarius if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 261194246Smarius (void **)&sc->sc_control_data, 262194246Smarius BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 263194246Smarius &sc->sc_cddmamap)) != 0) { 264194246Smarius device_printf(sc->sc_dev, 265194246Smarius "unable to allocate control data, error = %d\n", error); 266194246Smarius goto fail_ctag; 267194246Smarius } 268194246Smarius 269194246Smarius sc->sc_cddma = 0; 270194246Smarius if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 271194246Smarius sc->sc_control_data, sizeof(struct cas_control_data), 272194246Smarius cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 273194246Smarius device_printf(sc->sc_dev, 274194246Smarius "unable to load control data DMA map, error = %d\n", 275194246Smarius error); 276194246Smarius goto fail_cmem; 277194246Smarius } 278194246Smarius 279194246Smarius /* 280194246Smarius * Initialize the transmit job descriptors. 281194246Smarius */ 282194246Smarius STAILQ_INIT(&sc->sc_txfreeq); 283194246Smarius STAILQ_INIT(&sc->sc_txdirtyq); 284194246Smarius 285194246Smarius /* 286194246Smarius * Create the transmit buffer DMA maps. 287194246Smarius */ 288194246Smarius error = ENOMEM; 289194246Smarius for (i = 0; i < CAS_TXQUEUELEN; i++) { 290194246Smarius txs = &sc->sc_txsoft[i]; 291194246Smarius txs->txs_mbuf = NULL; 292194246Smarius txs->txs_ndescs = 0; 293194246Smarius if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 294194246Smarius &txs->txs_dmamap)) != 0) { 295194246Smarius device_printf(sc->sc_dev, 296194246Smarius "unable to create TX DMA map %d, error = %d\n", 297194246Smarius i, error); 298194246Smarius goto fail_txd; 299194246Smarius } 300194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 301194246Smarius } 302194246Smarius 303194246Smarius /* 304194246Smarius * Allocate the receive buffers, create and load the DMA maps 305194246Smarius * for them. 306194246Smarius */ 307194246Smarius for (i = 0; i < CAS_NRXDESC; i++) { 308194246Smarius if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 309194246Smarius &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 310194246Smarius &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 311194246Smarius device_printf(sc->sc_dev, 312194246Smarius "unable to allocate RX buffer %d, error = %d\n", 313194246Smarius i, error); 314194246Smarius goto fail_rxmem; 315194246Smarius } 316194246Smarius 317194246Smarius sc->sc_rxdptr = i; 318194246Smarius sc->sc_rxdsoft[i].rxds_paddr = 0; 319194246Smarius if ((error = bus_dmamap_load(sc->sc_rdmatag, 320194246Smarius sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 321194246Smarius CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 322194246Smarius sc->sc_rxdsoft[i].rxds_paddr == 0) { 323194246Smarius device_printf(sc->sc_dev, 324194246Smarius "unable to load RX DMA map %d, error = %d\n", 325194246Smarius i, error); 326194246Smarius goto fail_rxmap; 327194246Smarius } 328194246Smarius } 329194246Smarius 330207585Smarius if ((sc->sc_flags & CAS_SERDES) == 0) { 331207585Smarius CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 332207585Smarius CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 333207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 334207585Smarius cas_mifinit(sc); 335207585Smarius /* 336207585Smarius * Look for an external PHY. 337207585Smarius */ 338207585Smarius error = ENXIO; 339207585Smarius v = CAS_READ_4(sc, CAS_MIF_CONF); 340207585Smarius if ((v & CAS_MIF_CONF_MDI1) != 0) { 341207585Smarius v |= CAS_MIF_CONF_PHY_SELECT; 342207585Smarius CAS_WRITE_4(sc, CAS_MIF_CONF, v); 343207585Smarius CAS_BARRIER(sc, CAS_MIF_CONF, 4, 344207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 345207585Smarius /* Enable/unfreeze the GMII pins of Saturn. */ 346207585Smarius if (sc->sc_variant == CAS_SATURN) { 347245923Smarius CAS_WRITE_4(sc, CAS_SATURN_PCFG, 348245923Smarius CAS_READ_4(sc, CAS_SATURN_PCFG) & 349245923Smarius ~CAS_SATURN_PCFG_FSI); 350207585Smarius CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 351207585Smarius BUS_SPACE_BARRIER_READ | 352207585Smarius BUS_SPACE_BARRIER_WRITE); 353245923Smarius DELAY(10000); 354207585Smarius } 355213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 356213893Smarius cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 357215721Smarius MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 358194246Smarius } 359207585Smarius /* 360207585Smarius * Fall back on an internal PHY if no external PHY was found. 361207585Smarius */ 362207585Smarius if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 363207585Smarius v &= ~CAS_MIF_CONF_PHY_SELECT; 364207585Smarius CAS_WRITE_4(sc, CAS_MIF_CONF, v); 365207585Smarius CAS_BARRIER(sc, CAS_MIF_CONF, 4, 366207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 367207585Smarius /* Freeze the GMII pins of Saturn for saving power. */ 368207585Smarius if (sc->sc_variant == CAS_SATURN) { 369207585Smarius CAS_WRITE_4(sc, CAS_SATURN_PCFG, 370245923Smarius CAS_READ_4(sc, CAS_SATURN_PCFG) | 371207585Smarius CAS_SATURN_PCFG_FSI); 372207585Smarius CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 373207585Smarius BUS_SPACE_BARRIER_READ | 374207585Smarius BUS_SPACE_BARRIER_WRITE); 375245923Smarius DELAY(10000); 376207585Smarius } 377213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 378213893Smarius cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 379215721Smarius MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 380194246Smarius } 381207585Smarius } else { 382207585Smarius /* 383207585Smarius * Use the external PCS SERDES. 384207585Smarius */ 385194246Smarius CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 386207585Smarius CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 387207585Smarius /* Enable/unfreeze the SERDES pins of Saturn. */ 388207585Smarius if (sc->sc_variant == CAS_SATURN) { 389207585Smarius CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 390207585Smarius CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 391207585Smarius BUS_SPACE_BARRIER_WRITE); 392207585Smarius } 393194246Smarius CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 394207585Smarius CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 395207585Smarius BUS_SPACE_BARRIER_WRITE); 396207585Smarius CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 397207585Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 398207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 399213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 400213893Smarius cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 401215721Smarius CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 402194246Smarius } 403194246Smarius if (error != 0) { 404213893Smarius device_printf(sc->sc_dev, "attaching PHYs failed\n"); 405194246Smarius goto fail_rxmap; 406194246Smarius } 407194246Smarius sc->sc_mii = device_get_softc(sc->sc_miibus); 408194246Smarius 409194246Smarius /* 410194246Smarius * From this point forward, the attachment cannot fail. A failure 411194246Smarius * before this point releases all resources that may have been 412194246Smarius * allocated. 413194246Smarius */ 414194246Smarius 415194246Smarius /* Announce FIFO sizes. */ 416194246Smarius v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 417194246Smarius device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 418194246Smarius CAS_RX_FIFO_SIZE / 1024, v / 16); 419194246Smarius 420194246Smarius /* Attach the interface. */ 421194246Smarius ether_ifattach(ifp, sc->sc_enaddr); 422194246Smarius 423194246Smarius /* 424194246Smarius * Tell the upper layer(s) we support long frames/checksum offloads. 425194246Smarius */ 426270856Sglebius ifp->if_hdrlen = sizeof(struct ether_vlan_header); 427194246Smarius ifp->if_capabilities = IFCAP_VLAN_MTU; 428194246Smarius if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 429194246Smarius ifp->if_capabilities |= IFCAP_HWCSUM; 430194246Smarius ifp->if_hwassist = CAS_CSUM_FEATURES; 431194246Smarius } 432194246Smarius ifp->if_capenable = ifp->if_capabilities; 433194246Smarius 434194246Smarius return (0); 435194246Smarius 436194246Smarius /* 437194246Smarius * Free any resources we've allocated during the failed attach 438194246Smarius * attempt. Do this in reverse order and fall through. 439194246Smarius */ 440194246Smarius fail_rxmap: 441194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 442194246Smarius if (sc->sc_rxdsoft[i].rxds_paddr != 0) 443194246Smarius bus_dmamap_unload(sc->sc_rdmatag, 444194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 445194246Smarius fail_rxmem: 446194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 447194246Smarius if (sc->sc_rxdsoft[i].rxds_buf != NULL) 448194246Smarius bus_dmamem_free(sc->sc_rdmatag, 449194246Smarius sc->sc_rxdsoft[i].rxds_buf, 450194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 451194246Smarius fail_txd: 452194246Smarius for (i = 0; i < CAS_TXQUEUELEN; i++) 453194246Smarius if (sc->sc_txsoft[i].txs_dmamap != NULL) 454194246Smarius bus_dmamap_destroy(sc->sc_tdmatag, 455194246Smarius sc->sc_txsoft[i].txs_dmamap); 456194246Smarius bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 457194246Smarius fail_cmem: 458194246Smarius bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 459194246Smarius sc->sc_cddmamap); 460194246Smarius fail_ctag: 461194246Smarius bus_dma_tag_destroy(sc->sc_cdmatag); 462194246Smarius fail_ttag: 463194246Smarius bus_dma_tag_destroy(sc->sc_tdmatag); 464194246Smarius fail_rtag: 465194246Smarius bus_dma_tag_destroy(sc->sc_rdmatag); 466194246Smarius fail_ptag: 467194246Smarius bus_dma_tag_destroy(sc->sc_pdmatag); 468194904Smarius fail_taskq: 469194904Smarius taskqueue_free(sc->sc_tq); 470194246Smarius fail_ifnet: 471194246Smarius if_free(ifp); 472194246Smarius return (error); 473194246Smarius} 474194246Smarius 475194246Smariusstatic void 476194246Smariuscas_detach(struct cas_softc *sc) 477194246Smarius{ 478194246Smarius struct ifnet *ifp = sc->sc_ifp; 479194246Smarius int i; 480194246Smarius 481194904Smarius ether_ifdetach(ifp); 482194246Smarius CAS_LOCK(sc); 483194246Smarius cas_stop(ifp); 484194246Smarius CAS_UNLOCK(sc); 485194246Smarius callout_drain(&sc->sc_tick_ch); 486194246Smarius callout_drain(&sc->sc_rx_ch); 487194904Smarius taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 488194904Smarius taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 489194246Smarius if_free(ifp); 490194904Smarius taskqueue_free(sc->sc_tq); 491194246Smarius device_delete_child(sc->sc_dev, sc->sc_miibus); 492194246Smarius 493194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 494194246Smarius if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 495194246Smarius bus_dmamap_sync(sc->sc_rdmatag, 496194246Smarius sc->sc_rxdsoft[i].rxds_dmamap, 497194246Smarius BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 498194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 499194246Smarius if (sc->sc_rxdsoft[i].rxds_paddr != 0) 500194246Smarius bus_dmamap_unload(sc->sc_rdmatag, 501194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 502194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 503194246Smarius if (sc->sc_rxdsoft[i].rxds_buf != NULL) 504194246Smarius bus_dmamem_free(sc->sc_rdmatag, 505194246Smarius sc->sc_rxdsoft[i].rxds_buf, 506194246Smarius sc->sc_rxdsoft[i].rxds_dmamap); 507194246Smarius for (i = 0; i < CAS_TXQUEUELEN; i++) 508194246Smarius if (sc->sc_txsoft[i].txs_dmamap != NULL) 509194246Smarius bus_dmamap_destroy(sc->sc_tdmatag, 510194246Smarius sc->sc_txsoft[i].txs_dmamap); 511194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 512194246Smarius bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 513194246Smarius bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 514194246Smarius sc->sc_cddmamap); 515194246Smarius bus_dma_tag_destroy(sc->sc_cdmatag); 516194246Smarius bus_dma_tag_destroy(sc->sc_tdmatag); 517194246Smarius bus_dma_tag_destroy(sc->sc_rdmatag); 518194246Smarius bus_dma_tag_destroy(sc->sc_pdmatag); 519194246Smarius} 520194246Smarius 521194246Smariusstatic void 522194246Smariuscas_suspend(struct cas_softc *sc) 523194246Smarius{ 524194246Smarius struct ifnet *ifp = sc->sc_ifp; 525194246Smarius 526194246Smarius CAS_LOCK(sc); 527194246Smarius cas_stop(ifp); 528194246Smarius CAS_UNLOCK(sc); 529194246Smarius} 530194246Smarius 531194246Smariusstatic void 532194246Smariuscas_resume(struct cas_softc *sc) 533194246Smarius{ 534194246Smarius struct ifnet *ifp = sc->sc_ifp; 535194246Smarius 536194246Smarius CAS_LOCK(sc); 537194246Smarius /* 538194246Smarius * On resume all registers have to be initialized again like 539194246Smarius * after power-on. 540194246Smarius */ 541194246Smarius sc->sc_flags &= ~CAS_INITED; 542194246Smarius if (ifp->if_flags & IFF_UP) 543194246Smarius cas_init_locked(sc); 544194246Smarius CAS_UNLOCK(sc); 545194246Smarius} 546194246Smarius 547194246Smariusstatic inline void 548194246Smariuscas_rxcksum(struct mbuf *m, uint16_t cksum) 549194246Smarius{ 550194246Smarius struct ether_header *eh; 551194246Smarius struct ip *ip; 552194246Smarius struct udphdr *uh; 553194246Smarius uint16_t *opts; 554194246Smarius int32_t hlen, len, pktlen; 555194246Smarius uint32_t temp32; 556194246Smarius 557194246Smarius pktlen = m->m_pkthdr.len; 558194246Smarius if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 559194246Smarius return; 560194246Smarius eh = mtod(m, struct ether_header *); 561194246Smarius if (eh->ether_type != htons(ETHERTYPE_IP)) 562194246Smarius return; 563194246Smarius ip = (struct ip *)(eh + 1); 564194246Smarius if (ip->ip_v != IPVERSION) 565194246Smarius return; 566194246Smarius 567194246Smarius hlen = ip->ip_hl << 2; 568194246Smarius pktlen -= sizeof(struct ether_header); 569194246Smarius if (hlen < sizeof(struct ip)) 570194246Smarius return; 571194246Smarius if (ntohs(ip->ip_len) < hlen) 572194246Smarius return; 573194246Smarius if (ntohs(ip->ip_len) != pktlen) 574194246Smarius return; 575194246Smarius if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 576194246Smarius return; /* Cannot handle fragmented packet. */ 577194246Smarius 578194246Smarius switch (ip->ip_p) { 579194246Smarius case IPPROTO_TCP: 580194246Smarius if (pktlen < (hlen + sizeof(struct tcphdr))) 581194246Smarius return; 582194246Smarius break; 583194246Smarius case IPPROTO_UDP: 584194246Smarius if (pktlen < (hlen + sizeof(struct udphdr))) 585194246Smarius return; 586194246Smarius uh = (struct udphdr *)((uint8_t *)ip + hlen); 587194246Smarius if (uh->uh_sum == 0) 588194246Smarius return; /* no checksum */ 589194246Smarius break; 590194246Smarius default: 591194246Smarius return; 592194246Smarius } 593194246Smarius 594194246Smarius cksum = ~cksum; 595194246Smarius /* checksum fixup for IP options */ 596194246Smarius len = hlen - sizeof(struct ip); 597194246Smarius if (len > 0) { 598194246Smarius opts = (uint16_t *)(ip + 1); 599194246Smarius for (; len > 0; len -= sizeof(uint16_t), opts++) { 600194246Smarius temp32 = cksum - *opts; 601194246Smarius temp32 = (temp32 >> 16) + (temp32 & 65535); 602194246Smarius cksum = temp32 & 65535; 603194246Smarius } 604194246Smarius } 605194246Smarius m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 606194246Smarius m->m_pkthdr.csum_data = cksum; 607194246Smarius} 608194246Smarius 609194246Smariusstatic void 610194246Smariuscas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 611194246Smarius{ 612194246Smarius struct cas_softc *sc = xsc; 613194246Smarius 614194246Smarius if (error != 0) 615194246Smarius return; 616194246Smarius if (nsegs != 1) 617194246Smarius panic("%s: bad control buffer segment count", __func__); 618194246Smarius sc->sc_cddma = segs[0].ds_addr; 619194246Smarius} 620194246Smarius 621194246Smariusstatic void 622194246Smariuscas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 623194246Smarius{ 624194246Smarius struct cas_softc *sc = xsc; 625194246Smarius 626194246Smarius if (error != 0) 627194246Smarius return; 628194246Smarius if (nsegs != 1) 629194246Smarius panic("%s: bad RX buffer segment count", __func__); 630194246Smarius sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 631194246Smarius} 632194246Smarius 633194246Smariusstatic void 634194246Smariuscas_tick(void *arg) 635194246Smarius{ 636194246Smarius struct cas_softc *sc = arg; 637194904Smarius struct ifnet *ifp = sc->sc_ifp; 638194246Smarius uint32_t v; 639194246Smarius 640194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 641194246Smarius 642194246Smarius /* 643194246Smarius * Unload collision and error counters. 644194246Smarius */ 645271824Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 646194246Smarius CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 647271824Sglebius CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT)); 648194246Smarius v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 649194246Smarius CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 650271824Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v); 651271824Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, v); 652271824Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 653194246Smarius CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 654194246Smarius CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 655194246Smarius CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 656271824Sglebius CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL)); 657194246Smarius 658194246Smarius /* 659194246Smarius * Then clear the hardware counters. 660194246Smarius */ 661194246Smarius CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 662194246Smarius CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 663194246Smarius CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 664194246Smarius CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 665194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 666194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 667194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 668194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 669194246Smarius 670194246Smarius mii_tick(sc->sc_mii); 671194246Smarius 672194904Smarius if (sc->sc_txfree != CAS_MAXTXFREE) 673194904Smarius cas_tint(sc); 674194246Smarius 675194904Smarius cas_watchdog(sc); 676194904Smarius 677194246Smarius callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 678194246Smarius} 679194246Smarius 680194246Smariusstatic int 681194246Smariuscas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 682194246Smarius{ 683194246Smarius int i; 684194246Smarius uint32_t reg; 685194246Smarius 686194246Smarius for (i = CAS_TRIES; i--; DELAY(100)) { 687194246Smarius reg = CAS_READ_4(sc, r); 688194246Smarius if ((reg & clr) == 0 && (reg & set) == set) 689194246Smarius return (1); 690194246Smarius } 691194246Smarius return (0); 692194246Smarius} 693194246Smarius 694194246Smariusstatic void 695194246Smariuscas_reset(struct cas_softc *sc) 696194246Smarius{ 697194246Smarius 698194246Smarius#ifdef CAS_DEBUG 699194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 700194246Smarius#endif 701194246Smarius /* Disable all interrupts in order to avoid spurious ones. */ 702194246Smarius CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 703194246Smarius 704194246Smarius cas_reset_rx(sc); 705194246Smarius cas_reset_tx(sc); 706194246Smarius 707194246Smarius /* 708194246Smarius * Do a full reset modulo the result of the last auto-negotiation 709194246Smarius * when using the SERDES. 710194246Smarius */ 711194246Smarius CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 712194246Smarius ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 713194246Smarius CAS_BARRIER(sc, CAS_RESET, 4, 714194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 715194246Smarius DELAY(3000); 716194246Smarius if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 717194246Smarius device_printf(sc->sc_dev, "cannot reset device\n"); 718194246Smarius} 719194246Smarius 720194246Smariusstatic void 721194246Smariuscas_stop(struct ifnet *ifp) 722194246Smarius{ 723194246Smarius struct cas_softc *sc = ifp->if_softc; 724194246Smarius struct cas_txsoft *txs; 725194246Smarius 726194246Smarius#ifdef CAS_DEBUG 727194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 728194246Smarius#endif 729194246Smarius 730194246Smarius callout_stop(&sc->sc_tick_ch); 731194246Smarius callout_stop(&sc->sc_rx_ch); 732194246Smarius 733194246Smarius /* Disable all interrupts in order to avoid spurious ones. */ 734194246Smarius CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 735194246Smarius 736194246Smarius cas_reset_tx(sc); 737194246Smarius cas_reset_rx(sc); 738194246Smarius 739194246Smarius /* 740194246Smarius * Release any queued transmit buffers. 741194246Smarius */ 742194246Smarius while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 743194246Smarius STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 744194246Smarius if (txs->txs_ndescs != 0) { 745194246Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 746194246Smarius BUS_DMASYNC_POSTWRITE); 747194246Smarius bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 748194246Smarius if (txs->txs_mbuf != NULL) { 749194246Smarius m_freem(txs->txs_mbuf); 750194246Smarius txs->txs_mbuf = NULL; 751194246Smarius } 752194246Smarius } 753194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 754194246Smarius } 755194246Smarius 756194246Smarius /* 757194246Smarius * Mark the interface down and cancel the watchdog timer. 758194246Smarius */ 759194246Smarius ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 760194246Smarius sc->sc_flags &= ~CAS_LINK; 761194246Smarius sc->sc_wdog_timer = 0; 762194246Smarius} 763194246Smarius 764194246Smariusstatic int 765194246Smariuscas_reset_rx(struct cas_softc *sc) 766194246Smarius{ 767194246Smarius 768194246Smarius /* 769194246Smarius * Resetting while DMA is in progress can cause a bus hang, so we 770194246Smarius * disable DMA first. 771194246Smarius */ 772223951Smarius (void)cas_disable_rx(sc); 773194246Smarius CAS_WRITE_4(sc, CAS_RX_CONF, 0); 774194246Smarius CAS_BARRIER(sc, CAS_RX_CONF, 4, 775194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 776194246Smarius if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 777194246Smarius device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 778194246Smarius 779194246Smarius /* Finally, reset the ERX. */ 780194246Smarius CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 781194246Smarius ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 782194246Smarius CAS_BARRIER(sc, CAS_RESET, 4, 783194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 784223951Smarius if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 785194246Smarius device_printf(sc->sc_dev, "cannot reset receiver\n"); 786194246Smarius return (1); 787194246Smarius } 788194246Smarius return (0); 789194246Smarius} 790194246Smarius 791194246Smariusstatic int 792194246Smariuscas_reset_tx(struct cas_softc *sc) 793194246Smarius{ 794194246Smarius 795194246Smarius /* 796194246Smarius * Resetting while DMA is in progress can cause a bus hang, so we 797194246Smarius * disable DMA first. 798194246Smarius */ 799223951Smarius (void)cas_disable_tx(sc); 800194246Smarius CAS_WRITE_4(sc, CAS_TX_CONF, 0); 801194246Smarius CAS_BARRIER(sc, CAS_TX_CONF, 4, 802194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 803194246Smarius if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 804194246Smarius device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 805194246Smarius 806194246Smarius /* Finally, reset the ETX. */ 807194246Smarius CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 808194246Smarius ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 809194246Smarius CAS_BARRIER(sc, CAS_RESET, 4, 810194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 811223951Smarius if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 812194246Smarius device_printf(sc->sc_dev, "cannot reset transmitter\n"); 813194246Smarius return (1); 814194246Smarius } 815194246Smarius return (0); 816194246Smarius} 817194246Smarius 818194246Smariusstatic int 819194246Smariuscas_disable_rx(struct cas_softc *sc) 820194246Smarius{ 821194246Smarius 822194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 823194246Smarius CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 824194246Smarius CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 825194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 826223951Smarius if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 827223951Smarius return (1); 828247579Smarius if (bootverbose) 829247579Smarius device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 830223951Smarius return (0); 831194246Smarius} 832194246Smarius 833194246Smariusstatic int 834194246Smariuscas_disable_tx(struct cas_softc *sc) 835194246Smarius{ 836194246Smarius 837194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 838194246Smarius CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 839194246Smarius CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 840194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 841223951Smarius if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 842223951Smarius return (1); 843247579Smarius if (bootverbose) 844247579Smarius device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 845223951Smarius return (0); 846194246Smarius} 847194246Smarius 848194246Smariusstatic inline void 849194246Smariuscas_rxcompinit(struct cas_rx_comp *rxcomp) 850194246Smarius{ 851194246Smarius 852194246Smarius rxcomp->crc_word1 = 0; 853194246Smarius rxcomp->crc_word2 = 0; 854194246Smarius rxcomp->crc_word3 = 855194246Smarius htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 856194246Smarius rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 857194246Smarius} 858194246Smarius 859194246Smariusstatic void 860194246Smariuscas_meminit(struct cas_softc *sc) 861194246Smarius{ 862194246Smarius int i; 863194246Smarius 864194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 865194246Smarius 866194246Smarius /* 867194246Smarius * Initialize the transmit descriptor ring. 868194246Smarius */ 869194246Smarius for (i = 0; i < CAS_NTXDESC; i++) { 870194246Smarius sc->sc_txdescs[i].cd_flags = 0; 871194246Smarius sc->sc_txdescs[i].cd_buf_ptr = 0; 872194246Smarius } 873194246Smarius sc->sc_txfree = CAS_MAXTXFREE; 874194246Smarius sc->sc_txnext = 0; 875194246Smarius sc->sc_txwin = 0; 876194246Smarius 877194246Smarius /* 878194246Smarius * Initialize the receive completion ring. 879194246Smarius */ 880194246Smarius for (i = 0; i < CAS_NRXCOMP; i++) 881194246Smarius cas_rxcompinit(&sc->sc_rxcomps[i]); 882194246Smarius sc->sc_rxcptr = 0; 883194246Smarius 884194246Smarius /* 885194246Smarius * Initialize the first receive descriptor ring. We leave 886194246Smarius * the second one zeroed as we don't actually use it. 887194246Smarius */ 888194246Smarius for (i = 0; i < CAS_NRXDESC; i++) 889194246Smarius CAS_INIT_RXDESC(sc, i, i); 890194246Smarius sc->sc_rxdptr = 0; 891194246Smarius 892194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 893194246Smarius} 894194246Smarius 895194246Smariusstatic u_int 896194246Smariuscas_descsize(u_int sz) 897194246Smarius{ 898194246Smarius 899194246Smarius switch (sz) { 900194246Smarius case 32: 901194246Smarius return (CAS_DESC_32); 902194246Smarius case 64: 903194246Smarius return (CAS_DESC_64); 904194246Smarius case 128: 905194246Smarius return (CAS_DESC_128); 906194246Smarius case 256: 907194246Smarius return (CAS_DESC_256); 908194246Smarius case 512: 909194246Smarius return (CAS_DESC_512); 910194246Smarius case 1024: 911194246Smarius return (CAS_DESC_1K); 912194246Smarius case 2048: 913194246Smarius return (CAS_DESC_2K); 914194246Smarius case 4096: 915194246Smarius return (CAS_DESC_4K); 916194246Smarius case 8192: 917194246Smarius return (CAS_DESC_8K); 918194246Smarius default: 919194246Smarius printf("%s: invalid descriptor ring size %d\n", __func__, sz); 920194246Smarius return (CAS_DESC_32); 921194246Smarius } 922194246Smarius} 923194246Smarius 924194246Smariusstatic u_int 925194246Smariuscas_rxcompsize(u_int sz) 926194246Smarius{ 927194246Smarius 928194246Smarius switch (sz) { 929194246Smarius case 128: 930194246Smarius return (CAS_RX_CONF_COMP_128); 931194246Smarius case 256: 932194246Smarius return (CAS_RX_CONF_COMP_256); 933194246Smarius case 512: 934194246Smarius return (CAS_RX_CONF_COMP_512); 935194246Smarius case 1024: 936194246Smarius return (CAS_RX_CONF_COMP_1K); 937194246Smarius case 2048: 938194246Smarius return (CAS_RX_CONF_COMP_2K); 939194246Smarius case 4096: 940194246Smarius return (CAS_RX_CONF_COMP_4K); 941194246Smarius case 8192: 942194246Smarius return (CAS_RX_CONF_COMP_8K); 943194246Smarius case 16384: 944194246Smarius return (CAS_RX_CONF_COMP_16K); 945194246Smarius case 32768: 946194246Smarius return (CAS_RX_CONF_COMP_32K); 947194246Smarius default: 948194246Smarius printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 949194246Smarius return (CAS_RX_CONF_COMP_128); 950194246Smarius } 951194246Smarius} 952194246Smarius 953194246Smariusstatic void 954194246Smariuscas_init(void *xsc) 955194246Smarius{ 956194246Smarius struct cas_softc *sc = xsc; 957194246Smarius 958194246Smarius CAS_LOCK(sc); 959194246Smarius cas_init_locked(sc); 960194246Smarius CAS_UNLOCK(sc); 961194246Smarius} 962194246Smarius 963194246Smarius/* 964194246Smarius * Initialization of interface; set up initialization block 965194246Smarius * and transmit/receive descriptor rings. 966194246Smarius */ 967194246Smariusstatic void 968194246Smariuscas_init_locked(struct cas_softc *sc) 969194246Smarius{ 970194246Smarius struct ifnet *ifp = sc->sc_ifp; 971194246Smarius uint32_t v; 972194246Smarius 973194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 974194246Smarius 975194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 976194904Smarius return; 977194904Smarius 978194246Smarius#ifdef CAS_DEBUG 979194246Smarius CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 980194246Smarius __func__); 981194246Smarius#endif 982194246Smarius /* 983194246Smarius * Initialization sequence. The numbered steps below correspond 984194246Smarius * to the sequence outlined in section 6.3.5.1 in the Ethernet 985194246Smarius * Channel Engine manual (part of the PCIO manual). 986194246Smarius * See also the STP2002-STQ document from Sun Microsystems. 987194246Smarius */ 988194246Smarius 989194246Smarius /* step 1 & 2. Reset the Ethernet Channel. */ 990194246Smarius cas_stop(ifp); 991194246Smarius cas_reset(sc); 992194246Smarius#ifdef CAS_DEBUG 993194246Smarius CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 994194246Smarius __func__); 995194246Smarius#endif 996194246Smarius 997207585Smarius if ((sc->sc_flags & CAS_SERDES) == 0) 998207585Smarius /* Re-initialize the MIF. */ 999207585Smarius cas_mifinit(sc); 1000194246Smarius 1001194246Smarius /* step 3. Setup data structures in host memory. */ 1002194246Smarius cas_meminit(sc); 1003194246Smarius 1004194246Smarius /* step 4. TX MAC registers & counters */ 1005194246Smarius cas_init_regs(sc); 1006194246Smarius 1007194246Smarius /* step 5. RX MAC registers & counters */ 1008194246Smarius 1009194246Smarius /* step 6 & 7. Program Ring Base Addresses. */ 1010194246Smarius CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1011194246Smarius (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1012194246Smarius CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1013194246Smarius CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1014194246Smarius 1015194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1016194246Smarius (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1017194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1018194246Smarius CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1019194246Smarius 1020194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1021194246Smarius (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1022194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1023194246Smarius CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1024194246Smarius 1025194246Smarius if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1026194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1027194246Smarius (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1028194246Smarius CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1029194246Smarius CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1030194246Smarius } 1031194246Smarius 1032194246Smarius#ifdef CAS_DEBUG 1033194246Smarius CTR5(KTR_CAS, 1034194246Smarius "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1035194246Smarius CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1036194246Smarius CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1037194246Smarius#endif 1038194246Smarius 1039194246Smarius /* step 8. Global Configuration & Interrupt Masks */ 1040194246Smarius 1041194246Smarius /* Disable weighted round robin. */ 1042194246Smarius CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1043194246Smarius 1044194246Smarius /* 1045194246Smarius * Enable infinite bursts for revisions without PCI issues if 1046194246Smarius * applicable. Doing so greatly improves the TX performance on 1047247579Smarius * !__sparc64__ (on sparc64, setting CAS_INF_BURST improves TX 1048247579Smarius * performance only marginally but hurts RX throughput quite a bit). 1049194246Smarius */ 1050194246Smarius CAS_WRITE_4(sc, CAS_INF_BURST, 1051194246Smarius#if !defined(__sparc64__) 1052194246Smarius (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1053194246Smarius#endif 1054194246Smarius 0); 1055194246Smarius 1056194246Smarius /* Set up interrupts. */ 1057194246Smarius CAS_WRITE_4(sc, CAS_INTMASK, 1058194904Smarius ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1059194246Smarius CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1060194246Smarius CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1061194246Smarius CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1062194246Smarius CAS_INTR_PCI_ERROR_INT 1063194246Smarius#ifdef CAS_DEBUG 1064194246Smarius | CAS_INTR_PCS_INT | CAS_INTR_MIF 1065194246Smarius#endif 1066194246Smarius )); 1067194904Smarius /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1068194904Smarius CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1069194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1070194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1071194246Smarius ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1072194246Smarius#ifdef CAS_DEBUG 1073194246Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1074194246Smarius ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1075194246Smarius CAS_MAC_CTRL_NON_PAUSE)); 1076194246Smarius#else 1077194246Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1078194246Smarius CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1079194246Smarius CAS_MAC_CTRL_NON_PAUSE); 1080194246Smarius#endif 1081194246Smarius 1082194246Smarius /* Enable PCI error interrupts. */ 1083194246Smarius CAS_WRITE_4(sc, CAS_ERROR_MASK, 1084194246Smarius ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1085194246Smarius CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1086194246Smarius 1087194246Smarius /* Enable PCI error interrupts in BIM configuration. */ 1088194246Smarius CAS_WRITE_4(sc, CAS_BIM_CONF, 1089194246Smarius CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1090194246Smarius 1091194246Smarius /* 1092194246Smarius * step 9. ETX Configuration: encode receive descriptor ring size, 1093194246Smarius * enable DMA and disable pre-interrupt writeback completion. 1094194246Smarius */ 1095194246Smarius v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1096194246Smarius CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1097194246Smarius CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1098194246Smarius 1099194246Smarius /* step 10. ERX Configuration */ 1100194246Smarius 1101194246Smarius /* 1102194246Smarius * Encode receive completion and descriptor ring sizes, set the 1103194246Smarius * swivel offset. 1104194246Smarius */ 1105194246Smarius v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1106194246Smarius v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1107194246Smarius if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1108194246Smarius v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1109194246Smarius CAS_WRITE_4(sc, CAS_RX_CONF, 1110194246Smarius v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1111194246Smarius 1112194246Smarius /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1113194246Smarius CAS_WRITE_4(sc, CAS_RX_PTHRS, 1114215721Smarius (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1115194246Smarius 1116194246Smarius /* RX blanking */ 1117194246Smarius CAS_WRITE_4(sc, CAS_RX_BLANK, 1118194246Smarius (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1119194246Smarius 1120194246Smarius /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1121194246Smarius CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1122194246Smarius (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1123194246Smarius 1124194246Smarius /* Initialize the RX page size register as appropriate for 8k. */ 1125194246Smarius CAS_WRITE_4(sc, CAS_RX_PSZ, 1126194246Smarius (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1127194246Smarius (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1128194246Smarius (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1129194246Smarius (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1130194246Smarius 1131194246Smarius /* Disable RX random early detection. */ 1132194246Smarius CAS_WRITE_4(sc, CAS_RX_RED, 0); 1133194246Smarius 1134194246Smarius /* Zero the RX reassembly DMA table. */ 1135194246Smarius for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1136194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1137194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1138194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1139194246Smarius CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1140194246Smarius } 1141194246Smarius 1142194246Smarius /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1143194246Smarius CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1144194246Smarius CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1145194246Smarius 1146194246Smarius /* Finally, enable RX DMA. */ 1147194246Smarius CAS_WRITE_4(sc, CAS_RX_CONF, 1148194246Smarius CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1149194246Smarius 1150194246Smarius /* step 11. Configure Media. */ 1151194246Smarius 1152194246Smarius /* step 12. RX_MAC Configuration Register */ 1153223951Smarius v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1154223951Smarius v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1155223951Smarius v |= CAS_MAC_RX_CONF_STRPFCS; 1156223951Smarius sc->sc_mac_rxcfg = v; 1157223951Smarius /* 1158223951Smarius * Clear the RX filter and reprogram it. This will also set the 1159223951Smarius * current RX MAC configuration and enable it. 1160223951Smarius */ 1161223951Smarius cas_setladrf(sc); 1162194246Smarius 1163194246Smarius /* step 13. TX_MAC Configuration Register */ 1164194246Smarius v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1165194246Smarius v |= CAS_MAC_TX_CONF_EN; 1166223951Smarius (void)cas_disable_tx(sc); 1167194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1168194246Smarius 1169194246Smarius /* step 14. Issue Transmit Pending command. */ 1170194246Smarius 1171220943Smarius /* step 15. Give the receiver a swift kick. */ 1172194246Smarius CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1173194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1174194246Smarius if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1175194246Smarius CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1176194246Smarius 1177194246Smarius ifp->if_drv_flags |= IFF_DRV_RUNNING; 1178194246Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1179194246Smarius 1180194246Smarius mii_mediachg(sc->sc_mii); 1181194246Smarius 1182194246Smarius /* Start the one second timer. */ 1183194246Smarius sc->sc_wdog_timer = 0; 1184194246Smarius callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1185194246Smarius} 1186194246Smarius 1187194246Smariusstatic int 1188194246Smariuscas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1189194246Smarius{ 1190194246Smarius bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1191194246Smarius struct cas_txsoft *txs; 1192194246Smarius struct ip *ip; 1193194246Smarius struct mbuf *m; 1194194246Smarius uint64_t cflags; 1195194246Smarius int error, nexttx, nsegs, offset, seg; 1196194246Smarius 1197194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1198194246Smarius 1199194246Smarius /* Get a work queue entry. */ 1200194246Smarius if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1201194246Smarius /* Ran out of descriptors. */ 1202194246Smarius return (ENOBUFS); 1203194246Smarius } 1204194246Smarius 1205194246Smarius cflags = 0; 1206194246Smarius if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1207194246Smarius if (M_WRITABLE(*m_head) == 0) { 1208243857Sglebius m = m_dup(*m_head, M_NOWAIT); 1209194246Smarius m_freem(*m_head); 1210194246Smarius *m_head = m; 1211194246Smarius if (m == NULL) 1212194246Smarius return (ENOBUFS); 1213194246Smarius } 1214194246Smarius offset = sizeof(struct ether_header); 1215194246Smarius m = m_pullup(*m_head, offset + sizeof(struct ip)); 1216194246Smarius if (m == NULL) { 1217194246Smarius *m_head = NULL; 1218194246Smarius return (ENOBUFS); 1219194246Smarius } 1220194246Smarius ip = (struct ip *)(mtod(m, caddr_t) + offset); 1221194246Smarius offset += (ip->ip_hl << 2); 1222194246Smarius cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1223194246Smarius ((offset + m->m_pkthdr.csum_data) << 1224194246Smarius CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1225194246Smarius *m_head = m; 1226194246Smarius } 1227194246Smarius 1228194246Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1229194246Smarius *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1230194246Smarius if (error == EFBIG) { 1231243857Sglebius m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS); 1232194246Smarius if (m == NULL) { 1233194246Smarius m_freem(*m_head); 1234194246Smarius *m_head = NULL; 1235194246Smarius return (ENOBUFS); 1236194246Smarius } 1237194246Smarius *m_head = m; 1238194246Smarius error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1239194246Smarius txs->txs_dmamap, *m_head, txsegs, &nsegs, 1240194246Smarius BUS_DMA_NOWAIT); 1241194246Smarius if (error != 0) { 1242194246Smarius m_freem(*m_head); 1243194246Smarius *m_head = NULL; 1244194246Smarius return (error); 1245194246Smarius } 1246194246Smarius } else if (error != 0) 1247194246Smarius return (error); 1248194246Smarius /* If nsegs is wrong then the stack is corrupt. */ 1249194246Smarius KASSERT(nsegs <= CAS_NTXSEGS, 1250194246Smarius ("%s: too many DMA segments (%d)", __func__, nsegs)); 1251194246Smarius if (nsegs == 0) { 1252194246Smarius m_freem(*m_head); 1253194246Smarius *m_head = NULL; 1254194246Smarius return (EIO); 1255194246Smarius } 1256194246Smarius 1257194246Smarius /* 1258194246Smarius * Ensure we have enough descriptors free to describe 1259194246Smarius * the packet. Note, we always reserve one descriptor 1260194246Smarius * at the end of the ring as a termination point, in 1261194246Smarius * order to prevent wrap-around. 1262194246Smarius */ 1263194246Smarius if (nsegs > sc->sc_txfree - 1) { 1264194246Smarius txs->txs_ndescs = 0; 1265194246Smarius bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1266194246Smarius return (ENOBUFS); 1267194246Smarius } 1268194246Smarius 1269194246Smarius txs->txs_ndescs = nsegs; 1270194246Smarius txs->txs_firstdesc = sc->sc_txnext; 1271194246Smarius nexttx = txs->txs_firstdesc; 1272194246Smarius for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1273194246Smarius#ifdef CAS_DEBUG 1274194246Smarius CTR6(KTR_CAS, 1275194246Smarius "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1276194246Smarius __func__, seg, nexttx, txsegs[seg].ds_len, 1277194246Smarius txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1278194246Smarius#endif 1279194246Smarius sc->sc_txdescs[nexttx].cd_buf_ptr = 1280194246Smarius htole64(txsegs[seg].ds_addr); 1281194246Smarius KASSERT(txsegs[seg].ds_len < 1282194246Smarius CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1283194246Smarius ("%s: segment size too large!", __func__)); 1284194246Smarius sc->sc_txdescs[nexttx].cd_flags = 1285194246Smarius htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1286194246Smarius txs->txs_lastdesc = nexttx; 1287194246Smarius } 1288194246Smarius 1289194246Smarius /* Set EOF on the last descriptor. */ 1290194246Smarius#ifdef CAS_DEBUG 1291194246Smarius CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1292194246Smarius __func__, seg, nexttx); 1293194246Smarius#endif 1294194246Smarius sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1295194246Smarius htole64(CAS_TD_END_OF_FRAME); 1296194246Smarius 1297194246Smarius /* Lastly set SOF on the first descriptor. */ 1298194246Smarius#ifdef CAS_DEBUG 1299194246Smarius CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1300194246Smarius __func__, seg, nexttx); 1301194246Smarius#endif 1302194904Smarius if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1303194246Smarius sc->sc_txwin = 0; 1304194246Smarius sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1305194246Smarius htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1306194246Smarius } else 1307194246Smarius sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1308194246Smarius htole64(cflags | CAS_TD_START_OF_FRAME); 1309194246Smarius 1310194246Smarius /* Sync the DMA map. */ 1311194246Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1312194246Smarius BUS_DMASYNC_PREWRITE); 1313194246Smarius 1314194246Smarius#ifdef CAS_DEBUG 1315194246Smarius CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1316194246Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1317194246Smarius txs->txs_ndescs); 1318194246Smarius#endif 1319194246Smarius STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1320194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1321194246Smarius txs->txs_mbuf = *m_head; 1322194246Smarius 1323194246Smarius sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1324194246Smarius sc->sc_txfree -= txs->txs_ndescs; 1325194246Smarius 1326194246Smarius return (0); 1327194246Smarius} 1328194246Smarius 1329194246Smariusstatic void 1330194246Smariuscas_init_regs(struct cas_softc *sc) 1331194246Smarius{ 1332194246Smarius int i; 1333194246Smarius const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1334194246Smarius 1335194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1336194246Smarius 1337194246Smarius /* These registers are not cleared on reset. */ 1338194246Smarius if ((sc->sc_flags & CAS_INITED) == 0) { 1339194246Smarius /* magic values */ 1340194246Smarius CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1341194246Smarius CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1342194246Smarius CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1343194246Smarius 1344194246Smarius /* min frame length */ 1345194246Smarius CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1346194246Smarius /* max frame length and max burst size */ 1347194246Smarius CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1348194246Smarius ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1349194246Smarius CAS_MAC_MAX_BF_FRM_SHFT) | 1350194246Smarius (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1351194246Smarius 1352194246Smarius /* more magic values */ 1353194246Smarius CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1354194246Smarius CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1355194246Smarius CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1356215721Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1357194246Smarius 1358194246Smarius /* random number seed */ 1359194246Smarius CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1360194246Smarius ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1361194246Smarius 1362194246Smarius /* secondary MAC addresses: 0:0:0:0:0:0 */ 1363194246Smarius for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1364194246Smarius i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1365194246Smarius CAS_WRITE_4(sc, i, 0); 1366194246Smarius 1367194246Smarius /* MAC control address: 01:80:c2:00:00:01 */ 1368194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1369194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1370194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1371194246Smarius 1372194246Smarius /* MAC filter address: 0:0:0:0:0:0 */ 1373194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1374194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1375194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1376194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1377194246Smarius CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1378194246Smarius 1379194246Smarius /* Zero the hash table. */ 1380194246Smarius for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1381194246Smarius i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1382194246Smarius CAS_WRITE_4(sc, i, 0); 1383194246Smarius 1384194246Smarius sc->sc_flags |= CAS_INITED; 1385194246Smarius } 1386194246Smarius 1387194246Smarius /* Counters need to be zeroed. */ 1388194246Smarius CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1389194246Smarius CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1390194246Smarius CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1391194246Smarius CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1392194246Smarius CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1393194246Smarius CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1394194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1395194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1396194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1397194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1398194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1399194246Smarius 1400194246Smarius /* Set XOFF PAUSE time. */ 1401194246Smarius CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1402194246Smarius 1403194246Smarius /* Set the station address. */ 1404194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1405194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1406194246Smarius CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1407194246Smarius 1408194246Smarius /* Enable MII outputs. */ 1409194246Smarius CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1410194246Smarius} 1411194246Smarius 1412194246Smariusstatic void 1413194904Smariuscas_tx_task(void *arg, int pending __unused) 1414194246Smarius{ 1415194904Smarius struct ifnet *ifp; 1416194246Smarius 1417194904Smarius ifp = (struct ifnet *)arg; 1418194904Smarius cas_start(ifp); 1419194246Smarius} 1420194246Smarius 1421194246Smariusstatic inline void 1422194246Smariuscas_txkick(struct cas_softc *sc) 1423194246Smarius{ 1424194246Smarius 1425194246Smarius /* 1426194246Smarius * Update the TX kick register. This register has to point to the 1427194246Smarius * descriptor after the last valid one and for optimum performance 1428194246Smarius * should be incremented in multiples of 4 (the DMA engine fetches/ 1429194246Smarius * updates descriptors in batches of 4). 1430194246Smarius */ 1431194246Smarius#ifdef CAS_DEBUG 1432194246Smarius CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1433194246Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1434194246Smarius#endif 1435194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1436194246Smarius CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1437194246Smarius} 1438194246Smarius 1439194246Smariusstatic void 1440194904Smariuscas_start(struct ifnet *ifp) 1441194246Smarius{ 1442194246Smarius struct cas_softc *sc = ifp->if_softc; 1443194246Smarius struct mbuf *m; 1444194246Smarius int kicked, ntx; 1445194246Smarius 1446194904Smarius CAS_LOCK(sc); 1447194246Smarius 1448194246Smarius if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1449194904Smarius IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1450194904Smarius CAS_UNLOCK(sc); 1451194246Smarius return; 1452194904Smarius } 1453194246Smarius 1454194904Smarius if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1455194904Smarius cas_tint(sc); 1456194904Smarius 1457194246Smarius#ifdef CAS_DEBUG 1458194246Smarius CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1459194246Smarius device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1460194246Smarius sc->sc_txnext); 1461194246Smarius#endif 1462194246Smarius ntx = 0; 1463194246Smarius kicked = 0; 1464194246Smarius for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1465194246Smarius IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1466194246Smarius if (m == NULL) 1467194246Smarius break; 1468194246Smarius if (cas_load_txmbuf(sc, &m) != 0) { 1469194246Smarius if (m == NULL) 1470194246Smarius break; 1471194246Smarius ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1472194246Smarius IFQ_DRV_PREPEND(&ifp->if_snd, m); 1473194246Smarius break; 1474194246Smarius } 1475194246Smarius if ((sc->sc_txnext % 4) == 0) { 1476194246Smarius cas_txkick(sc); 1477194246Smarius kicked = 1; 1478194246Smarius } else 1479194246Smarius kicked = 0; 1480194246Smarius ntx++; 1481194246Smarius BPF_MTAP(ifp, m); 1482194246Smarius } 1483194246Smarius 1484194246Smarius if (ntx > 0) { 1485194246Smarius if (kicked == 0) 1486194246Smarius cas_txkick(sc); 1487194246Smarius#ifdef CAS_DEBUG 1488194246Smarius CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1489194246Smarius device_get_name(sc->sc_dev), sc->sc_txnext); 1490194246Smarius#endif 1491194246Smarius 1492194246Smarius /* Set a watchdog timer in case the chip flakes out. */ 1493194246Smarius sc->sc_wdog_timer = 5; 1494194246Smarius#ifdef CAS_DEBUG 1495194246Smarius CTR3(KTR_CAS, "%s: %s: watchdog %d", 1496194246Smarius device_get_name(sc->sc_dev), __func__, 1497194246Smarius sc->sc_wdog_timer); 1498194246Smarius#endif 1499194246Smarius } 1500194904Smarius 1501194904Smarius CAS_UNLOCK(sc); 1502194246Smarius} 1503194246Smarius 1504194246Smariusstatic void 1505194246Smariuscas_tint(struct cas_softc *sc) 1506194246Smarius{ 1507194246Smarius struct ifnet *ifp = sc->sc_ifp; 1508194246Smarius struct cas_txsoft *txs; 1509194246Smarius int progress; 1510194246Smarius uint32_t txlast; 1511194246Smarius#ifdef CAS_DEBUG 1512194246Smarius int i; 1513194246Smarius 1514194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1515194246Smarius 1516194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1517194246Smarius#endif 1518194246Smarius 1519194246Smarius /* 1520194246Smarius * Go through our TX list and free mbufs for those 1521194246Smarius * frames that have been transmitted. 1522194246Smarius */ 1523194246Smarius progress = 0; 1524194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1525194246Smarius while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1526194246Smarius#ifdef CAS_DEBUG 1527194246Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1528194246Smarius printf(" txsoft %p transmit chain:\n", txs); 1529194246Smarius for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1530194246Smarius printf("descriptor %d: ", i); 1531194246Smarius printf("cd_flags: 0x%016llx\t", 1532194246Smarius (long long)le64toh( 1533194246Smarius sc->sc_txdescs[i].cd_flags)); 1534194246Smarius printf("cd_buf_ptr: 0x%016llx\n", 1535194246Smarius (long long)le64toh( 1536194246Smarius sc->sc_txdescs[i].cd_buf_ptr)); 1537194246Smarius if (i == txs->txs_lastdesc) 1538194246Smarius break; 1539194246Smarius } 1540194246Smarius } 1541194246Smarius#endif 1542194246Smarius 1543194246Smarius /* 1544194246Smarius * In theory, we could harvest some descriptors before 1545194246Smarius * the ring is empty, but that's a bit complicated. 1546194246Smarius * 1547194246Smarius * CAS_TX_COMPn points to the last descriptor 1548194246Smarius * processed + 1. 1549194246Smarius */ 1550194246Smarius txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1551194246Smarius#ifdef CAS_DEBUG 1552194246Smarius CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1553194246Smarius "txs->txs_lastdesc = %d, txlast = %d", 1554194246Smarius __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1555194246Smarius#endif 1556194246Smarius if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1557194246Smarius if ((txlast >= txs->txs_firstdesc) && 1558194246Smarius (txlast <= txs->txs_lastdesc)) 1559194246Smarius break; 1560194246Smarius } else { 1561194246Smarius /* Ick -- this command wraps. */ 1562194246Smarius if ((txlast >= txs->txs_firstdesc) || 1563194246Smarius (txlast <= txs->txs_lastdesc)) 1564194246Smarius break; 1565194246Smarius } 1566194246Smarius 1567194246Smarius#ifdef CAS_DEBUG 1568194246Smarius CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1569194246Smarius#endif 1570194246Smarius STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1571194246Smarius 1572194246Smarius sc->sc_txfree += txs->txs_ndescs; 1573194246Smarius 1574194246Smarius bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1575194246Smarius BUS_DMASYNC_POSTWRITE); 1576194246Smarius bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1577194246Smarius if (txs->txs_mbuf != NULL) { 1578194246Smarius m_freem(txs->txs_mbuf); 1579194246Smarius txs->txs_mbuf = NULL; 1580194246Smarius } 1581194246Smarius 1582194246Smarius STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1583194246Smarius 1584271824Sglebius if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1585194246Smarius progress = 1; 1586194246Smarius } 1587194246Smarius 1588194246Smarius#ifdef CAS_DEBUG 1589215721Smarius CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1590194246Smarius "CAS_TX_COMP3 %x", 1591215721Smarius __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1592215721Smarius ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1593215721Smarius CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1594194246Smarius CAS_READ_4(sc, CAS_TX_COMP3)); 1595194246Smarius#endif 1596194246Smarius 1597194246Smarius if (progress) { 1598194904Smarius /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1599194246Smarius ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1600194246Smarius if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1601194246Smarius sc->sc_wdog_timer = 0; 1602194246Smarius } 1603194246Smarius 1604194246Smarius#ifdef CAS_DEBUG 1605194246Smarius CTR3(KTR_CAS, "%s: %s: watchdog %d", 1606194246Smarius device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1607194246Smarius#endif 1608194246Smarius} 1609194246Smarius 1610194246Smariusstatic void 1611194246Smariuscas_rint_timeout(void *arg) 1612194246Smarius{ 1613194246Smarius struct cas_softc *sc = arg; 1614194246Smarius 1615223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1616194246Smarius 1617194246Smarius cas_rint(sc); 1618194246Smarius} 1619194246Smarius 1620194246Smariusstatic void 1621194246Smariuscas_rint(struct cas_softc *sc) 1622194246Smarius{ 1623194246Smarius struct cas_rxdsoft *rxds, *rxds2; 1624194246Smarius struct ifnet *ifp = sc->sc_ifp; 1625194246Smarius struct mbuf *m, *m2; 1626194246Smarius uint64_t word1, word2, word3, word4; 1627194246Smarius uint32_t rxhead; 1628194246Smarius u_int idx, idx2, len, off, skip; 1629194246Smarius 1630223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1631194246Smarius 1632194246Smarius callout_stop(&sc->sc_rx_ch); 1633194246Smarius 1634194246Smarius#ifdef CAS_DEBUG 1635194246Smarius CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1636194246Smarius#endif 1637194246Smarius 1638194246Smarius#define PRINTWORD(n, delimiter) \ 1639194246Smarius printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1640194246Smarius 1641194246Smarius#define SKIPASSERT(n) \ 1642194246Smarius KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1643194246Smarius ("%s: word ## n not 0", __func__)) 1644194246Smarius 1645194246Smarius#define WORDTOH(n) \ 1646194246Smarius word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1647194246Smarius 1648194246Smarius /* 1649194246Smarius * Read the completion head register once. This limits 1650194246Smarius * how long the following loop can execute. 1651194246Smarius */ 1652194246Smarius rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1653194246Smarius#ifdef CAS_DEBUG 1654194246Smarius CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1655215721Smarius __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1656194246Smarius#endif 1657194246Smarius skip = 0; 1658194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1659194246Smarius for (; sc->sc_rxcptr != rxhead; 1660194246Smarius sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1661194246Smarius if (skip != 0) { 1662194246Smarius SKIPASSERT(1); 1663194246Smarius SKIPASSERT(2); 1664194246Smarius SKIPASSERT(3); 1665194246Smarius 1666194246Smarius --skip; 1667194246Smarius goto skip; 1668194246Smarius } 1669194246Smarius 1670194246Smarius WORDTOH(1); 1671194246Smarius WORDTOH(2); 1672194246Smarius WORDTOH(3); 1673194246Smarius WORDTOH(4); 1674194246Smarius 1675194246Smarius#ifdef CAS_DEBUG 1676194246Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) { 1677194246Smarius printf(" completion %d: ", sc->sc_rxcptr); 1678194246Smarius PRINTWORD(1, '\t'); 1679194246Smarius PRINTWORD(2, '\t'); 1680194246Smarius PRINTWORD(3, '\t'); 1681194246Smarius PRINTWORD(4, '\n'); 1682194246Smarius } 1683194246Smarius#endif 1684194246Smarius 1685194246Smarius if (__predict_false( 1686194246Smarius (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1687194246Smarius (word4 & CAS_RC4_ZERO) != 0)) { 1688194246Smarius /* 1689194246Smarius * The descriptor is still marked as owned, although 1690194246Smarius * it is supposed to have completed. This has been 1691194246Smarius * observed on some machines. Just exiting here 1692194246Smarius * might leave the packet sitting around until another 1693194246Smarius * one arrives to trigger a new interrupt, which is 1694194246Smarius * generally undesirable, so set up a timeout. 1695194246Smarius */ 1696194246Smarius callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1697194246Smarius cas_rint_timeout, sc); 1698194246Smarius break; 1699194246Smarius } 1700194246Smarius 1701194246Smarius if (__predict_false( 1702194246Smarius (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1703271824Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1704194246Smarius device_printf(sc->sc_dev, 1705194246Smarius "receive error: CRC error\n"); 1706194246Smarius continue; 1707194246Smarius } 1708194246Smarius 1709194246Smarius KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1710194246Smarius CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1711194246Smarius ("%s: data and header present", __func__)); 1712194246Smarius KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1713194246Smarius CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1714194246Smarius ("%s: split and header present", __func__)); 1715194246Smarius KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1716194246Smarius (word1 & CAS_RC1_RELEASE_HDR) == 0, 1717194246Smarius ("%s: data present but header release", __func__)); 1718194246Smarius KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1719194246Smarius (word1 & CAS_RC1_RELEASE_DATA) == 0, 1720194246Smarius ("%s: header present but data release", __func__)); 1721194246Smarius 1722194246Smarius if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1723194246Smarius idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1724194246Smarius off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1725194246Smarius#ifdef CAS_DEBUG 1726194246Smarius CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1727194246Smarius __func__, idx, off, len); 1728194246Smarius#endif 1729194246Smarius rxds = &sc->sc_rxdsoft[idx]; 1730243857Sglebius MGETHDR(m, M_NOWAIT, MT_DATA); 1731194246Smarius if (m != NULL) { 1732194246Smarius refcount_acquire(&rxds->rxds_refcount); 1733194246Smarius bus_dmamap_sync(sc->sc_rdmatag, 1734194246Smarius rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1735194973Smarius#if __FreeBSD_version < 800016 1736194246Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + 1737194246Smarius off * 256 + ETHER_ALIGN, len, cas_free, 1738194973Smarius rxds, M_RDONLY, EXT_NET_DRV); 1739194246Smarius#else 1740194973Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + 1741194973Smarius off * 256 + ETHER_ALIGN, len, cas_free, 1742194246Smarius sc, (void *)(uintptr_t)idx, 1743194973Smarius M_RDONLY, EXT_NET_DRV); 1744194246Smarius#endif 1745194246Smarius if ((m->m_flags & M_EXT) == 0) { 1746194246Smarius m_freem(m); 1747194246Smarius m = NULL; 1748194246Smarius } 1749194246Smarius } 1750194246Smarius if (m != NULL) { 1751194246Smarius m->m_pkthdr.rcvif = ifp; 1752194246Smarius m->m_pkthdr.len = m->m_len = len; 1753271824Sglebius if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1754194246Smarius if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1755194246Smarius cas_rxcksum(m, CAS_GET(word4, 1756194246Smarius CAS_RC4_TCP_CSUM)); 1757194246Smarius /* Pass it on. */ 1758223986Smarius CAS_UNLOCK(sc); 1759194246Smarius (*ifp->if_input)(ifp, m); 1760223986Smarius CAS_LOCK(sc); 1761194246Smarius } else 1762271824Sglebius if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1763194246Smarius 1764194246Smarius if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1765194246Smarius refcount_release(&rxds->rxds_refcount) != 0) 1766194246Smarius cas_add_rxdesc(sc, idx); 1767194246Smarius } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1768194246Smarius idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1769194246Smarius off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1770194246Smarius#ifdef CAS_DEBUG 1771194246Smarius CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1772194246Smarius __func__, idx, off, len); 1773194246Smarius#endif 1774194246Smarius rxds = &sc->sc_rxdsoft[idx]; 1775243857Sglebius MGETHDR(m, M_NOWAIT, MT_DATA); 1776194246Smarius if (m != NULL) { 1777194246Smarius refcount_acquire(&rxds->rxds_refcount); 1778194246Smarius off += ETHER_ALIGN; 1779194246Smarius m->m_len = min(CAS_PAGE_SIZE - off, len); 1780194246Smarius bus_dmamap_sync(sc->sc_rdmatag, 1781194246Smarius rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1782194973Smarius#if __FreeBSD_version < 800016 1783194246Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1784194973Smarius m->m_len, cas_free, rxds, M_RDONLY, 1785194973Smarius EXT_NET_DRV); 1786194246Smarius#else 1787194973Smarius MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1788194973Smarius m->m_len, cas_free, sc, 1789194973Smarius (void *)(uintptr_t)idx, M_RDONLY, 1790194973Smarius EXT_NET_DRV); 1791194246Smarius#endif 1792194246Smarius if ((m->m_flags & M_EXT) == 0) { 1793194246Smarius m_freem(m); 1794194246Smarius m = NULL; 1795194246Smarius } 1796194246Smarius } 1797194246Smarius idx2 = 0; 1798208776Smarius m2 = NULL; 1799194246Smarius rxds2 = NULL; 1800194246Smarius if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1801194246Smarius KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1802194246Smarius ("%s: split but no release next", 1803194246Smarius __func__)); 1804194246Smarius 1805194246Smarius idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1806194246Smarius#ifdef CAS_DEBUG 1807194246Smarius CTR2(KTR_CAS, "%s: split at idx %d", 1808194246Smarius __func__, idx2); 1809194246Smarius#endif 1810194246Smarius rxds2 = &sc->sc_rxdsoft[idx2]; 1811208776Smarius if (m != NULL) { 1812243857Sglebius MGET(m2, M_NOWAIT, MT_DATA); 1813208776Smarius if (m2 != NULL) { 1814208776Smarius refcount_acquire( 1815208776Smarius &rxds2->rxds_refcount); 1816208776Smarius m2->m_len = len - m->m_len; 1817208776Smarius bus_dmamap_sync( 1818208776Smarius sc->sc_rdmatag, 1819208776Smarius rxds2->rxds_dmamap, 1820208776Smarius BUS_DMASYNC_POSTREAD); 1821194973Smarius#if __FreeBSD_version < 800016 1822208776Smarius MEXTADD(m2, 1823208776Smarius (caddr_t)rxds2->rxds_buf, 1824208776Smarius m2->m_len, cas_free, 1825208776Smarius rxds2, M_RDONLY, 1826208776Smarius EXT_NET_DRV); 1827194973Smarius#else 1828208776Smarius MEXTADD(m2, 1829208776Smarius (caddr_t)rxds2->rxds_buf, 1830208776Smarius m2->m_len, cas_free, sc, 1831208776Smarius (void *)(uintptr_t)idx2, 1832208776Smarius M_RDONLY, EXT_NET_DRV); 1833194246Smarius#endif 1834208776Smarius if ((m2->m_flags & M_EXT) == 1835208776Smarius 0) { 1836208776Smarius m_freem(m2); 1837208776Smarius m2 = NULL; 1838208776Smarius } 1839194246Smarius } 1840194246Smarius } 1841194246Smarius if (m2 != NULL) 1842194246Smarius m->m_next = m2; 1843208776Smarius else if (m != NULL) { 1844194246Smarius m_freem(m); 1845194246Smarius m = NULL; 1846194246Smarius } 1847194246Smarius } 1848194246Smarius if (m != NULL) { 1849194246Smarius m->m_pkthdr.rcvif = ifp; 1850194246Smarius m->m_pkthdr.len = len; 1851271824Sglebius if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1852194246Smarius if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1853194246Smarius cas_rxcksum(m, CAS_GET(word4, 1854194246Smarius CAS_RC4_TCP_CSUM)); 1855194246Smarius /* Pass it on. */ 1856223986Smarius CAS_UNLOCK(sc); 1857194246Smarius (*ifp->if_input)(ifp, m); 1858223986Smarius CAS_LOCK(sc); 1859194246Smarius } else 1860271824Sglebius if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1861194246Smarius 1862194246Smarius if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1863194246Smarius refcount_release(&rxds->rxds_refcount) != 0) 1864194246Smarius cas_add_rxdesc(sc, idx); 1865194246Smarius if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1866194246Smarius refcount_release(&rxds2->rxds_refcount) != 0) 1867194246Smarius cas_add_rxdesc(sc, idx2); 1868194246Smarius } 1869194246Smarius 1870194246Smarius skip = CAS_GET(word1, CAS_RC1_SKIP); 1871194246Smarius 1872194246Smarius skip: 1873194246Smarius cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1874194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1875194904Smarius break; 1876194246Smarius } 1877194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878194246Smarius CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1879194246Smarius 1880194246Smarius#undef PRINTWORD 1881194246Smarius#undef SKIPASSERT 1882194246Smarius#undef WORDTOH 1883194246Smarius 1884194246Smarius#ifdef CAS_DEBUG 1885194246Smarius CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1886215721Smarius __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1887194246Smarius CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1888194246Smarius#endif 1889194246Smarius} 1890194246Smarius 1891268529Sglebiusstatic void 1892254799Sandrecas_free(struct mbuf *m, void *arg1, void *arg2) 1893194246Smarius{ 1894194246Smarius struct cas_rxdsoft *rxds; 1895194246Smarius struct cas_softc *sc; 1896223986Smarius u_int idx, locked; 1897194246Smarius 1898194246Smarius#if __FreeBSD_version < 800016 1899194246Smarius rxds = arg2; 1900194246Smarius sc = rxds->rxds_sc; 1901194246Smarius idx = rxds->rxds_idx; 1902194246Smarius#else 1903194246Smarius sc = arg1; 1904194246Smarius idx = (uintptr_t)arg2; 1905194246Smarius rxds = &sc->sc_rxdsoft[idx]; 1906194246Smarius#endif 1907194246Smarius if (refcount_release(&rxds->rxds_refcount) == 0) 1908268529Sglebius return; 1909194246Smarius 1910194246Smarius /* 1911194246Smarius * NB: this function can be called via m_freem(9) within 1912194246Smarius * this driver! 1913194246Smarius */ 1914223986Smarius if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1915223986Smarius CAS_LOCK(sc); 1916194246Smarius cas_add_rxdesc(sc, idx); 1917223986Smarius if (locked == 0) 1918223986Smarius CAS_UNLOCK(sc); 1919194246Smarius} 1920194246Smarius 1921194246Smariusstatic inline void 1922194246Smariuscas_add_rxdesc(struct cas_softc *sc, u_int idx) 1923194246Smarius{ 1924194246Smarius 1925223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1926194246Smarius 1927194246Smarius bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1928194246Smarius BUS_DMASYNC_PREREAD); 1929194246Smarius CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1930194246Smarius sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1931194246Smarius 1932194246Smarius /* 1933194246Smarius * Update the RX kick register. This register has to point to the 1934194246Smarius * descriptor after the last valid one (before the current batch) 1935194246Smarius * and for optimum performance should be incremented in multiples 1936194246Smarius * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1937194246Smarius */ 1938194246Smarius if ((sc->sc_rxdptr % 4) == 0) { 1939194246Smarius CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1940194246Smarius CAS_WRITE_4(sc, CAS_RX_KICK, 1941194246Smarius (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1942194246Smarius } 1943194246Smarius} 1944194246Smarius 1945194246Smariusstatic void 1946194246Smariuscas_eint(struct cas_softc *sc, u_int status) 1947194246Smarius{ 1948194904Smarius struct ifnet *ifp = sc->sc_ifp; 1949194246Smarius 1950223986Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 1951194246Smarius 1952271824Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1953194904Smarius 1954194246Smarius device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1955194246Smarius if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1956194246Smarius status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1957194246Smarius printf(", PCI bus error 0x%x", status); 1958194246Smarius if ((status & CAS_ERROR_OTHER) != 0) { 1959194246Smarius status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1960194246Smarius printf(", PCI status 0x%x", status); 1961194246Smarius pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1962194246Smarius } 1963194246Smarius } 1964194246Smarius printf("\n"); 1965194246Smarius 1966194904Smarius ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1967223986Smarius cas_init_locked(sc); 1968194904Smarius if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1969194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1970194246Smarius} 1971194246Smarius 1972194904Smariusstatic int 1973194246Smariuscas_intr(void *v) 1974194246Smarius{ 1975194246Smarius struct cas_softc *sc = v; 1976194904Smarius 1977194904Smarius if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1978194904Smarius CAS_INTR_SUMMARY) == 0)) 1979194904Smarius return (FILTER_STRAY); 1980194904Smarius 1981194904Smarius /* Disable interrupts. */ 1982194904Smarius CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1983194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1984194904Smarius 1985194904Smarius return (FILTER_HANDLED); 1986194904Smarius} 1987194904Smarius 1988194904Smariusstatic void 1989194904Smariuscas_intr_task(void *arg, int pending __unused) 1990194904Smarius{ 1991194904Smarius struct cas_softc *sc = arg; 1992194904Smarius struct ifnet *ifp = sc->sc_ifp; 1993194246Smarius uint32_t status, status2; 1994194246Smarius 1995194904Smarius CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1996194904Smarius 1997194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1998194904Smarius return; 1999194904Smarius 2000194246Smarius status = CAS_READ_4(sc, CAS_STATUS); 2001194246Smarius if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 2002194904Smarius goto done; 2003194246Smarius 2004223986Smarius CAS_LOCK(sc); 2005194246Smarius#ifdef CAS_DEBUG 2006194246Smarius CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 2007194246Smarius device_get_name(sc->sc_dev), __func__, 2008215721Smarius (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 2009194246Smarius 2010194246Smarius /* 2011194246Smarius * PCS interrupts must be cleared, otherwise no traffic is passed! 2012194246Smarius */ 2013194246Smarius if ((status & CAS_INTR_PCS_INT) != 0) { 2014194246Smarius status2 = 2015194246Smarius CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 2016194246Smarius CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 2017194246Smarius if ((status2 & CAS_PCS_INTR_LINK) != 0) 2018194246Smarius device_printf(sc->sc_dev, 2019194246Smarius "%s: PCS link status changed\n", __func__); 2020194246Smarius } 2021194246Smarius if ((status & CAS_MAC_CTRL_STATUS) != 0) { 2022194246Smarius status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 2023194246Smarius if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2024194246Smarius device_printf(sc->sc_dev, 2025194246Smarius "%s: PAUSE received (PAUSE time %d slots)\n", 2026194246Smarius __func__, 2027194246Smarius (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2028194246Smarius CAS_MAC_CTRL_STATUS_PT_SHFT); 2029194246Smarius if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2030194246Smarius device_printf(sc->sc_dev, 2031194246Smarius "%s: transited to PAUSE state\n", __func__); 2032194246Smarius if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2033194246Smarius device_printf(sc->sc_dev, 2034194246Smarius "%s: transited to non-PAUSE state\n", __func__); 2035194246Smarius } 2036194246Smarius if ((status & CAS_INTR_MIF) != 0) 2037194246Smarius device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2038194246Smarius#endif 2039194246Smarius 2040194246Smarius if (__predict_false((status & 2041194246Smarius (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2042194246Smarius CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2043194246Smarius cas_eint(sc, status); 2044223986Smarius CAS_UNLOCK(sc); 2045194246Smarius return; 2046194246Smarius } 2047194246Smarius 2048194246Smarius if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2049194246Smarius status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2050194246Smarius if ((status2 & 2051194246Smarius (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2052271824Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2053194246Smarius else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2054194246Smarius device_printf(sc->sc_dev, 2055194246Smarius "MAC TX fault, status %x\n", status2); 2056194246Smarius } 2057194246Smarius 2058194246Smarius if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2059194246Smarius status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2060194246Smarius if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2061271824Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2062194246Smarius else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2063194246Smarius device_printf(sc->sc_dev, 2064194246Smarius "MAC RX fault, status %x\n", status2); 2065194246Smarius } 2066194246Smarius 2067194246Smarius if ((status & 2068194246Smarius (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2069194246Smarius CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2070194246Smarius cas_rint(sc); 2071194904Smarius#ifdef CAS_DEBUG 2072194246Smarius if (__predict_false((status & 2073194246Smarius (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2074194246Smarius CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2075194246Smarius device_printf(sc->sc_dev, 2076194246Smarius "RX fault, status %x\n", status); 2077194904Smarius#endif 2078194246Smarius } 2079194246Smarius 2080194246Smarius if ((status & 2081223986Smarius (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2082194246Smarius cas_tint(sc); 2083223986Smarius 2084223986Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2085194904Smarius CAS_UNLOCK(sc); 2086194904Smarius return; 2087223986Smarius } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2088194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2089223986Smarius CAS_UNLOCK(sc); 2090194904Smarius 2091194904Smarius status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2092194904Smarius if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2093194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2094194904Smarius return; 2095194904Smarius } 2096194904Smarius 2097194904Smarius done: 2098194904Smarius /* Re-enable interrupts. */ 2099194904Smarius CAS_WRITE_4(sc, CAS_INTMASK, 2100194904Smarius ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2101194904Smarius CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2102194904Smarius CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2103194904Smarius CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2104194904Smarius CAS_INTR_PCI_ERROR_INT 2105194904Smarius#ifdef CAS_DEBUG 2106194904Smarius | CAS_INTR_PCS_INT | CAS_INTR_MIF 2107194904Smarius#endif 2108194904Smarius )); 2109194246Smarius} 2110194246Smarius 2111194904Smariusstatic void 2112194246Smariuscas_watchdog(struct cas_softc *sc) 2113194246Smarius{ 2114194246Smarius struct ifnet *ifp = sc->sc_ifp; 2115194246Smarius 2116194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 2117194246Smarius 2118194246Smarius#ifdef CAS_DEBUG 2119194246Smarius CTR4(KTR_CAS, 2120215721Smarius "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2121215721Smarius __func__, CAS_READ_4(sc, CAS_RX_CONF), 2122194246Smarius CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2123215721Smarius CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2124194246Smarius CTR4(KTR_CAS, 2125215721Smarius "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2126215721Smarius __func__, CAS_READ_4(sc, CAS_TX_CONF), 2127194246Smarius CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2128215721Smarius CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2129194246Smarius#endif 2130194246Smarius 2131194246Smarius if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2132194904Smarius return; 2133194246Smarius 2134194246Smarius if ((sc->sc_flags & CAS_LINK) != 0) 2135194246Smarius device_printf(sc->sc_dev, "device timeout\n"); 2136194246Smarius else if (bootverbose) 2137194246Smarius device_printf(sc->sc_dev, "device timeout (no link)\n"); 2138271824Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2139194246Smarius 2140194246Smarius /* Try to get more packets going. */ 2141194904Smarius ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2142194246Smarius cas_init_locked(sc); 2143194904Smarius if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2144194904Smarius taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2145194246Smarius} 2146194246Smarius 2147194246Smariusstatic void 2148194246Smariuscas_mifinit(struct cas_softc *sc) 2149194246Smarius{ 2150194246Smarius 2151194246Smarius /* Configure the MIF in frame mode. */ 2152194246Smarius CAS_WRITE_4(sc, CAS_MIF_CONF, 2153194246Smarius CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2154207585Smarius CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2155207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2156194246Smarius} 2157194246Smarius 2158194246Smarius/* 2159194246Smarius * MII interface 2160194246Smarius * 2161194246Smarius * The MII interface supports at least three different operating modes: 2162194246Smarius * 2163194246Smarius * Bitbang mode is implemented using data, clock and output enable registers. 2164194246Smarius * 2165194246Smarius * Frame mode is implemented by loading a complete frame into the frame 2166194246Smarius * register and polling the valid bit for completion. 2167194246Smarius * 2168194246Smarius * Polling mode uses the frame register but completion is indicated by 2169194246Smarius * an interrupt. 2170194246Smarius * 2171194246Smarius */ 2172194246Smariusstatic int 2173194246Smariuscas_mii_readreg(device_t dev, int phy, int reg) 2174194246Smarius{ 2175194246Smarius struct cas_softc *sc; 2176194246Smarius int n; 2177194246Smarius uint32_t v; 2178194246Smarius 2179194246Smarius#ifdef CAS_DEBUG_PHY 2180194246Smarius printf("%s: phy %d reg %d\n", __func__, phy, reg); 2181194246Smarius#endif 2182194246Smarius 2183194246Smarius sc = device_get_softc(dev); 2184194246Smarius if ((sc->sc_flags & CAS_SERDES) != 0) { 2185194246Smarius switch (reg) { 2186194246Smarius case MII_BMCR: 2187194246Smarius reg = CAS_PCS_CTRL; 2188194246Smarius break; 2189194246Smarius case MII_BMSR: 2190194246Smarius reg = CAS_PCS_STATUS; 2191194246Smarius break; 2192194246Smarius case MII_PHYIDR1: 2193194246Smarius case MII_PHYIDR2: 2194194246Smarius return (0); 2195194246Smarius case MII_ANAR: 2196194246Smarius reg = CAS_PCS_ANAR; 2197194246Smarius break; 2198194246Smarius case MII_ANLPAR: 2199194246Smarius reg = CAS_PCS_ANLPAR; 2200194246Smarius break; 2201194246Smarius case MII_EXTSR: 2202194246Smarius return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2203194246Smarius default: 2204194246Smarius device_printf(sc->sc_dev, 2205194246Smarius "%s: unhandled register %d\n", __func__, reg); 2206194246Smarius return (0); 2207194246Smarius } 2208194246Smarius return (CAS_READ_4(sc, reg)); 2209194246Smarius } 2210194246Smarius 2211194246Smarius /* Construct the frame command. */ 2212194246Smarius v = CAS_MIF_FRAME_READ | 2213194246Smarius (phy << CAS_MIF_FRAME_PHY_SHFT) | 2214194246Smarius (reg << CAS_MIF_FRAME_REG_SHFT); 2215194246Smarius 2216194246Smarius CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2217194246Smarius CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2218194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2219194246Smarius for (n = 0; n < 100; n++) { 2220194246Smarius DELAY(1); 2221194246Smarius v = CAS_READ_4(sc, CAS_MIF_FRAME); 2222194246Smarius if (v & CAS_MIF_FRAME_TA_LSB) 2223194246Smarius return (v & CAS_MIF_FRAME_DATA); 2224194246Smarius } 2225194246Smarius 2226194246Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2227194246Smarius return (0); 2228194246Smarius} 2229194246Smarius 2230194246Smariusstatic int 2231194246Smariuscas_mii_writereg(device_t dev, int phy, int reg, int val) 2232194246Smarius{ 2233194246Smarius struct cas_softc *sc; 2234194246Smarius int n; 2235194246Smarius uint32_t v; 2236194246Smarius 2237194246Smarius#ifdef CAS_DEBUG_PHY 2238194246Smarius printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2239194246Smarius#endif 2240194246Smarius 2241194246Smarius sc = device_get_softc(dev); 2242194246Smarius if ((sc->sc_flags & CAS_SERDES) != 0) { 2243194246Smarius switch (reg) { 2244194246Smarius case MII_BMSR: 2245194246Smarius reg = CAS_PCS_STATUS; 2246194246Smarius break; 2247194246Smarius case MII_BMCR: 2248194246Smarius reg = CAS_PCS_CTRL; 2249194246Smarius if ((val & CAS_PCS_CTRL_RESET) == 0) 2250194246Smarius break; 2251194246Smarius CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2252194246Smarius CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2253194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2254194246Smarius if (!cas_bitwait(sc, CAS_PCS_CTRL, 2255194246Smarius CAS_PCS_CTRL_RESET, 0)) 2256194246Smarius device_printf(sc->sc_dev, 2257194246Smarius "cannot reset PCS\n"); 2258194246Smarius /* FALLTHROUGH */ 2259194246Smarius case MII_ANAR: 2260194246Smarius CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2261194246Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2262194246Smarius BUS_SPACE_BARRIER_WRITE); 2263194246Smarius CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2264207585Smarius CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2265207585Smarius BUS_SPACE_BARRIER_WRITE); 2266194246Smarius CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2267194246Smarius CAS_PCS_SERDES_CTRL_ESD); 2268207585Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2269207585Smarius BUS_SPACE_BARRIER_WRITE); 2270194246Smarius CAS_WRITE_4(sc, CAS_PCS_CONF, 2271194246Smarius CAS_PCS_CONF_EN); 2272207585Smarius CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2273207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2274194246Smarius return (0); 2275194246Smarius case MII_ANLPAR: 2276194246Smarius reg = CAS_PCS_ANLPAR; 2277194246Smarius break; 2278194246Smarius default: 2279194246Smarius device_printf(sc->sc_dev, 2280194246Smarius "%s: unhandled register %d\n", __func__, reg); 2281194246Smarius return (0); 2282194246Smarius } 2283194246Smarius CAS_WRITE_4(sc, reg, val); 2284207585Smarius CAS_BARRIER(sc, reg, 4, 2285207585Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2286194246Smarius return (0); 2287194246Smarius } 2288194246Smarius 2289194246Smarius /* Construct the frame command. */ 2290194246Smarius v = CAS_MIF_FRAME_WRITE | 2291194246Smarius (phy << CAS_MIF_FRAME_PHY_SHFT) | 2292194246Smarius (reg << CAS_MIF_FRAME_REG_SHFT) | 2293194246Smarius (val & CAS_MIF_FRAME_DATA); 2294194246Smarius 2295194246Smarius CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2296194246Smarius CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2297194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2298194246Smarius for (n = 0; n < 100; n++) { 2299194246Smarius DELAY(1); 2300194246Smarius v = CAS_READ_4(sc, CAS_MIF_FRAME); 2301194246Smarius if (v & CAS_MIF_FRAME_TA_LSB) 2302194246Smarius return (1); 2303194246Smarius } 2304194246Smarius 2305194246Smarius device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2306194246Smarius return (0); 2307194246Smarius} 2308194246Smarius 2309194246Smariusstatic void 2310194246Smariuscas_mii_statchg(device_t dev) 2311194246Smarius{ 2312194246Smarius struct cas_softc *sc; 2313194246Smarius struct ifnet *ifp; 2314194246Smarius int gigabit; 2315194246Smarius uint32_t rxcfg, txcfg, v; 2316194246Smarius 2317194246Smarius sc = device_get_softc(dev); 2318194246Smarius ifp = sc->sc_ifp; 2319194246Smarius 2320194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 2321194246Smarius 2322194246Smarius#ifdef CAS_DEBUG 2323194246Smarius if ((ifp->if_flags & IFF_DEBUG) != 0) 2324213893Smarius device_printf(sc->sc_dev, "%s: status changen", __func__); 2325194246Smarius#endif 2326194246Smarius 2327194246Smarius if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2328194246Smarius IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2329194246Smarius sc->sc_flags |= CAS_LINK; 2330194246Smarius else 2331194246Smarius sc->sc_flags &= ~CAS_LINK; 2332194246Smarius 2333194246Smarius switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2334194246Smarius case IFM_1000_SX: 2335194246Smarius case IFM_1000_LX: 2336194246Smarius case IFM_1000_CX: 2337194246Smarius case IFM_1000_T: 2338194246Smarius gigabit = 1; 2339194246Smarius break; 2340194246Smarius default: 2341194246Smarius gigabit = 0; 2342194246Smarius } 2343194246Smarius 2344194246Smarius /* 2345194246Smarius * The configuration done here corresponds to the steps F) and 2346194246Smarius * G) and as far as enabling of RX and TX MAC goes also step H) 2347194246Smarius * of the initialization sequence outlined in section 11.2.1 of 2348194246Smarius * the Cassini+ ASIC Specification. 2349194246Smarius */ 2350194246Smarius 2351223951Smarius rxcfg = sc->sc_mac_rxcfg; 2352223951Smarius rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2353194246Smarius txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2354194246Smarius CAS_MAC_TX_CONF_NGUL; 2355194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2356194246Smarius txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2357194246Smarius else if (gigabit != 0) { 2358194246Smarius rxcfg |= CAS_MAC_RX_CONF_CARR; 2359194246Smarius txcfg |= CAS_MAC_TX_CONF_CARR; 2360194246Smarius } 2361223951Smarius (void)cas_disable_tx(sc); 2362194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2363223951Smarius (void)cas_disable_rx(sc); 2364194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2365194246Smarius 2366194246Smarius v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2367194246Smarius ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2368194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2369194246Smarius IFM_ETH_RXPAUSE) != 0) 2370194246Smarius v |= CAS_MAC_CTRL_CONF_RXP; 2371194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2372194246Smarius IFM_ETH_TXPAUSE) != 0) 2373194246Smarius v |= CAS_MAC_CTRL_CONF_TXP; 2374194246Smarius CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2375194246Smarius 2376194246Smarius /* 2377194246Smarius * All supported chips have a bug causing incorrect checksum 2378194246Smarius * to be calculated when letting them strip the FCS in half- 2379194246Smarius * duplex mode. In theory we could disable FCS stripping and 2380194246Smarius * manually adjust the checksum accordingly. It seems to make 2381194246Smarius * more sense to optimze for the common case and just disable 2382194246Smarius * hardware checksumming in half-duplex mode though. 2383194246Smarius */ 2384194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2385194246Smarius ifp->if_capenable &= ~IFCAP_HWCSUM; 2386194246Smarius ifp->if_hwassist = 0; 2387194246Smarius } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2388194246Smarius ifp->if_capenable = ifp->if_capabilities; 2389194246Smarius ifp->if_hwassist = CAS_CSUM_FEATURES; 2390194246Smarius } 2391194246Smarius 2392194246Smarius if (sc->sc_variant == CAS_SATURN) { 2393194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2394194246Smarius /* silicon bug workaround */ 2395194246Smarius CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2396194246Smarius else 2397194246Smarius CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2398194246Smarius } 2399194246Smarius 2400194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2401194246Smarius gigabit != 0) 2402194246Smarius CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2403194246Smarius CAS_MAC_SLOT_TIME_CARR); 2404194246Smarius else 2405194246Smarius CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2406194246Smarius CAS_MAC_SLOT_TIME_NORM); 2407194246Smarius 2408194246Smarius /* XIF Configuration */ 2409194246Smarius v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2410194246Smarius if ((sc->sc_flags & CAS_SERDES) == 0) { 2411194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2412194246Smarius v |= CAS_MAC_XIF_CONF_NOECHO; 2413194246Smarius v |= CAS_MAC_XIF_CONF_BUF_OE; 2414194246Smarius } 2415194246Smarius if (gigabit != 0) 2416194246Smarius v |= CAS_MAC_XIF_CONF_GMII; 2417194246Smarius if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2418194246Smarius v |= CAS_MAC_XIF_CONF_FDXLED; 2419194246Smarius CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2420194246Smarius 2421223951Smarius sc->sc_mac_rxcfg = rxcfg; 2422223986Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2423194246Smarius (sc->sc_flags & CAS_LINK) != 0) { 2424194246Smarius CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2425194246Smarius txcfg | CAS_MAC_TX_CONF_EN); 2426194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2427194246Smarius rxcfg | CAS_MAC_RX_CONF_EN); 2428194246Smarius } 2429194246Smarius} 2430194246Smarius 2431194246Smariusstatic int 2432194246Smariuscas_mediachange(struct ifnet *ifp) 2433194246Smarius{ 2434194246Smarius struct cas_softc *sc = ifp->if_softc; 2435194246Smarius int error; 2436194246Smarius 2437194246Smarius /* XXX add support for serial media. */ 2438194246Smarius 2439194246Smarius CAS_LOCK(sc); 2440194246Smarius error = mii_mediachg(sc->sc_mii); 2441194246Smarius CAS_UNLOCK(sc); 2442194246Smarius return (error); 2443194246Smarius} 2444194246Smarius 2445194246Smariusstatic void 2446194246Smariuscas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2447194246Smarius{ 2448194246Smarius struct cas_softc *sc = ifp->if_softc; 2449194246Smarius 2450194246Smarius CAS_LOCK(sc); 2451194246Smarius if ((ifp->if_flags & IFF_UP) == 0) { 2452194246Smarius CAS_UNLOCK(sc); 2453194246Smarius return; 2454194246Smarius } 2455194246Smarius 2456194246Smarius mii_pollstat(sc->sc_mii); 2457194246Smarius ifmr->ifm_active = sc->sc_mii->mii_media_active; 2458194246Smarius ifmr->ifm_status = sc->sc_mii->mii_media_status; 2459194246Smarius CAS_UNLOCK(sc); 2460194246Smarius} 2461194246Smarius 2462194246Smariusstatic int 2463194246Smariuscas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2464194246Smarius{ 2465194246Smarius struct cas_softc *sc = ifp->if_softc; 2466194246Smarius struct ifreq *ifr = (struct ifreq *)data; 2467194246Smarius int error; 2468194246Smarius 2469194246Smarius error = 0; 2470194246Smarius switch (cmd) { 2471194246Smarius case SIOCSIFFLAGS: 2472194246Smarius CAS_LOCK(sc); 2473194246Smarius if ((ifp->if_flags & IFF_UP) != 0) { 2474194246Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2475194246Smarius ((ifp->if_flags ^ sc->sc_ifflags) & 2476194246Smarius (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2477194246Smarius cas_setladrf(sc); 2478194246Smarius else 2479194246Smarius cas_init_locked(sc); 2480194246Smarius } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2481194246Smarius cas_stop(ifp); 2482194246Smarius sc->sc_ifflags = ifp->if_flags; 2483194246Smarius CAS_UNLOCK(sc); 2484194246Smarius break; 2485194246Smarius case SIOCSIFCAP: 2486194246Smarius CAS_LOCK(sc); 2487194246Smarius if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2488194246Smarius error = EINVAL; 2489194246Smarius CAS_UNLOCK(sc); 2490194246Smarius break; 2491194246Smarius } 2492194246Smarius ifp->if_capenable = ifr->ifr_reqcap; 2493194246Smarius if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2494194246Smarius ifp->if_hwassist = CAS_CSUM_FEATURES; 2495194246Smarius else 2496194246Smarius ifp->if_hwassist = 0; 2497194246Smarius CAS_UNLOCK(sc); 2498194246Smarius break; 2499194246Smarius case SIOCADDMULTI: 2500194246Smarius case SIOCDELMULTI: 2501194246Smarius CAS_LOCK(sc); 2502194904Smarius if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2503194904Smarius cas_setladrf(sc); 2504194246Smarius CAS_UNLOCK(sc); 2505194246Smarius break; 2506194246Smarius case SIOCSIFMTU: 2507194246Smarius if ((ifr->ifr_mtu < ETHERMIN) || 2508194246Smarius (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2509194246Smarius error = EINVAL; 2510194246Smarius else 2511194246Smarius ifp->if_mtu = ifr->ifr_mtu; 2512194246Smarius break; 2513194246Smarius case SIOCGIFMEDIA: 2514194246Smarius case SIOCSIFMEDIA: 2515194246Smarius error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2516194246Smarius break; 2517194246Smarius default: 2518194246Smarius error = ether_ioctl(ifp, cmd, data); 2519194246Smarius break; 2520194246Smarius } 2521194246Smarius 2522194246Smarius return (error); 2523194246Smarius} 2524194246Smarius 2525194246Smariusstatic void 2526194246Smariuscas_setladrf(struct cas_softc *sc) 2527194246Smarius{ 2528194246Smarius struct ifnet *ifp = sc->sc_ifp; 2529194246Smarius struct ifmultiaddr *inm; 2530194246Smarius int i; 2531194246Smarius uint32_t hash[16]; 2532194246Smarius uint32_t crc, v; 2533194246Smarius 2534194246Smarius CAS_LOCK_ASSERT(sc, MA_OWNED); 2535194246Smarius 2536194246Smarius /* 2537223951Smarius * Turn off the RX MAC and the hash filter as required by the Sun 2538223951Smarius * Cassini programming restrictions. 2539194246Smarius */ 2540223951Smarius v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2541223951Smarius CAS_MAC_RX_CONF_EN); 2542194246Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2543194246Smarius CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2544194246Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2545223951Smarius if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2546223951Smarius CAS_MAC_RX_CONF_EN, 0)) 2547223951Smarius device_printf(sc->sc_dev, 2548223951Smarius "cannot disable RX MAC or hash filter\n"); 2549194246Smarius 2550223951Smarius v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2551194246Smarius if ((ifp->if_flags & IFF_PROMISC) != 0) { 2552194246Smarius v |= CAS_MAC_RX_CONF_PROMISC; 2553194246Smarius goto chipit; 2554194246Smarius } 2555194246Smarius if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2556194246Smarius v |= CAS_MAC_RX_CONF_PGRP; 2557194246Smarius goto chipit; 2558194246Smarius } 2559194246Smarius 2560194246Smarius /* 2561194246Smarius * Set up multicast address filter by passing all multicast 2562194246Smarius * addresses through a crc generator, and then using the high 2563194246Smarius * order 8 bits as an index into the 256 bit logical address 2564194246Smarius * filter. The high order 4 bits selects the word, while the 2565194246Smarius * other 4 bits select the bit within the word (where bit 0 2566194246Smarius * is the MSB). 2567194246Smarius */ 2568194246Smarius 2569194246Smarius /* Clear the hash table. */ 2570194246Smarius memset(hash, 0, sizeof(hash)); 2571194246Smarius 2572195049Srwatson if_maddr_rlock(ifp); 2573194246Smarius TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2574194246Smarius if (inm->ifma_addr->sa_family != AF_LINK) 2575194246Smarius continue; 2576194246Smarius crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2577194246Smarius inm->ifma_addr), ETHER_ADDR_LEN); 2578194246Smarius 2579194246Smarius /* We just want the 8 most significant bits. */ 2580194246Smarius crc >>= 24; 2581194246Smarius 2582194246Smarius /* Set the corresponding bit in the filter. */ 2583194246Smarius hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2584194246Smarius } 2585195049Srwatson if_maddr_runlock(ifp); 2586194246Smarius 2587194246Smarius v |= CAS_MAC_RX_CONF_HFILTER; 2588194246Smarius 2589194246Smarius /* Now load the hash table into the chip (if we are using it). */ 2590194246Smarius for (i = 0; i < 16; i++) 2591194246Smarius CAS_WRITE_4(sc, 2592194246Smarius CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2593194246Smarius hash[i]); 2594194246Smarius 2595194246Smarius chipit: 2596223951Smarius sc->sc_mac_rxcfg = v; 2597223951Smarius CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2598194246Smarius} 2599194246Smarius 2600194246Smariusstatic int cas_pci_attach(device_t dev); 2601194246Smariusstatic int cas_pci_detach(device_t dev); 2602194246Smariusstatic int cas_pci_probe(device_t dev); 2603194246Smariusstatic int cas_pci_resume(device_t dev); 2604194246Smariusstatic int cas_pci_suspend(device_t dev); 2605194246Smarius 2606194246Smariusstatic device_method_t cas_pci_methods[] = { 2607194246Smarius /* Device interface */ 2608194246Smarius DEVMETHOD(device_probe, cas_pci_probe), 2609194246Smarius DEVMETHOD(device_attach, cas_pci_attach), 2610194246Smarius DEVMETHOD(device_detach, cas_pci_detach), 2611194246Smarius DEVMETHOD(device_suspend, cas_pci_suspend), 2612194246Smarius DEVMETHOD(device_resume, cas_pci_resume), 2613194246Smarius /* Use the suspend handler here, it is all that is required. */ 2614194246Smarius DEVMETHOD(device_shutdown, cas_pci_suspend), 2615194246Smarius 2616194246Smarius /* MII interface */ 2617194246Smarius DEVMETHOD(miibus_readreg, cas_mii_readreg), 2618194246Smarius DEVMETHOD(miibus_writereg, cas_mii_writereg), 2619194246Smarius DEVMETHOD(miibus_statchg, cas_mii_statchg), 2620194246Smarius 2621227843Smarius DEVMETHOD_END 2622194246Smarius}; 2623194246Smarius 2624194246Smariusstatic driver_t cas_pci_driver = { 2625194246Smarius "cas", 2626194246Smarius cas_pci_methods, 2627194246Smarius sizeof(struct cas_softc) 2628194246Smarius}; 2629194246Smarius 2630194246SmariusDRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2631194246SmariusDRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2632194246SmariusMODULE_DEPEND(cas, pci, 1, 1, 1); 2633194246Smarius 2634194246Smariusstatic const struct cas_pci_dev { 2635194246Smarius uint32_t cpd_devid; 2636194246Smarius uint8_t cpd_revid; 2637194246Smarius int cpd_variant; 2638194246Smarius const char *cpd_desc; 2639242625Sdim} cas_pci_devlist[] = { 2640194246Smarius { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2641194246Smarius { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2642194246Smarius { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2643194246Smarius { 0, 0, 0, NULL } 2644194246Smarius}; 2645194246Smarius 2646194246Smariusstatic int 2647194246Smariuscas_pci_probe(device_t dev) 2648194246Smarius{ 2649194246Smarius int i; 2650194246Smarius 2651194246Smarius for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2652194246Smarius if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2653194246Smarius pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2654194246Smarius device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2655194246Smarius return (BUS_PROBE_DEFAULT); 2656194246Smarius } 2657194246Smarius } 2658194246Smarius 2659194246Smarius return (ENXIO); 2660194246Smarius} 2661194246Smarius 2662194246Smariusstatic struct resource_spec cas_pci_res_spec[] = { 2663194246Smarius { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2664194246Smarius { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2665194246Smarius { -1, 0 } 2666194246Smarius}; 2667194246Smarius 2668207585Smarius#define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2669207585Smarius#define CAS_PHY_INTERFACE "phy-interface" 2670207585Smarius#define CAS_PHY_TYPE "phy-type" 2671207585Smarius#define CAS_PHY_TYPE_PCS "pcs" 2672207585Smarius 2673194246Smariusstatic int 2674194246Smariuscas_pci_attach(device_t dev) 2675194246Smarius{ 2676207585Smarius char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2677194246Smarius struct cas_softc *sc; 2678194246Smarius int i; 2679194246Smarius#if !(defined(__powerpc__) || defined(__sparc64__)) 2680194246Smarius u_char enaddr[4][ETHER_ADDR_LEN]; 2681207585Smarius u_int j, k, lma, pcs[4], phy; 2682194246Smarius#endif 2683194246Smarius 2684194246Smarius sc = device_get_softc(dev); 2685194246Smarius sc->sc_variant = CAS_UNKNOWN; 2686194246Smarius for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2687194246Smarius if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2688194246Smarius pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2689194246Smarius sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2690194246Smarius break; 2691194246Smarius } 2692194246Smarius } 2693194246Smarius if (sc->sc_variant == CAS_UNKNOWN) { 2694194246Smarius device_printf(dev, "unknown adaptor\n"); 2695194246Smarius return (ENXIO); 2696194246Smarius } 2697194246Smarius 2698247579Smarius /* PCI configuration */ 2699247579Smarius pci_write_config(dev, PCIR_COMMAND, 2700247579Smarius pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN | 2701247579Smarius PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2); 2702194246Smarius 2703194246Smarius sc->sc_dev = dev; 2704194246Smarius if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2705194246Smarius /* Hardware checksumming may hang TX. */ 2706194246Smarius sc->sc_flags |= CAS_NO_CSUM; 2707194246Smarius if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2708194246Smarius sc->sc_flags |= CAS_REG_PLUS; 2709194246Smarius if (sc->sc_variant == CAS_CAS || 2710194246Smarius (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2711194246Smarius sc->sc_flags |= CAS_TABORT; 2712194246Smarius if (bootverbose) 2713194246Smarius device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2714194246Smarius 2715194246Smarius if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2716194246Smarius device_printf(dev, "failed to allocate resources\n"); 2717194246Smarius bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2718194246Smarius return (ENXIO); 2719194246Smarius } 2720194246Smarius 2721194246Smarius CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2722194246Smarius 2723194246Smarius#if defined(__powerpc__) || defined(__sparc64__) 2724194246Smarius OF_getetheraddr(dev, sc->sc_enaddr); 2725207585Smarius if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2726207585Smarius sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2727207585Smarius CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2728207585Smarius buf[sizeof(buf) - 1] = '\0'; 2729207585Smarius if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2730207585Smarius sc->sc_flags |= CAS_SERDES; 2731207585Smarius } 2732194246Smarius#else 2733194246Smarius /* 2734207585Smarius * Dig out VPD (vital product data) and read the MAC address as well 2735207585Smarius * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2736207585Smarius * FCode) and can't be accessed via the PCI capability pointer. 2737207585Smarius * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2738207585Smarius * in the free US Patent 7149820. 2739194246Smarius */ 2740194246Smarius 2741194246Smarius#define PCI_ROMHDR_SIZE 0x1c 2742194246Smarius#define PCI_ROMHDR_SIG 0x00 2743194246Smarius#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2744194246Smarius#define PCI_ROMHDR_PTR_DATA 0x18 2745194246Smarius#define PCI_ROM_SIZE 0x18 2746194246Smarius#define PCI_ROM_SIG 0x00 2747194246Smarius#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2748194246Smarius /* reversed */ 2749194246Smarius#define PCI_ROM_VENDOR 0x04 2750194246Smarius#define PCI_ROM_DEVICE 0x06 2751194246Smarius#define PCI_ROM_PTR_VPD 0x08 2752194246Smarius#define PCI_VPDRES_BYTE0 0x00 2753194246Smarius#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2754194246Smarius#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2755194246Smarius#define PCI_VPDRES_LARGE_LEN_LSB 0x01 2756194246Smarius#define PCI_VPDRES_LARGE_LEN_MSB 0x02 2757194246Smarius#define PCI_VPDRES_LARGE_SIZE 0x03 2758194246Smarius#define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2759194246Smarius#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2760194246Smarius#define PCI_VPD_KEY0 0x00 2761194246Smarius#define PCI_VPD_KEY1 0x01 2762194246Smarius#define PCI_VPD_LEN 0x02 2763194246Smarius#define PCI_VPD_SIZE 0x03 2764194246Smarius 2765194246Smarius#define CAS_ROM_READ_1(sc, offs) \ 2766194246Smarius CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2767194246Smarius#define CAS_ROM_READ_2(sc, offs) \ 2768194246Smarius CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2769194246Smarius#define CAS_ROM_READ_4(sc, offs) \ 2770194246Smarius CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2771194246Smarius 2772207585Smarius lma = phy = 0; 2773207585Smarius memset(enaddr, 0, sizeof(enaddr)); 2774207585Smarius memset(pcs, 0, sizeof(pcs)); 2775207585Smarius 2776194246Smarius /* Enable PCI Expansion ROM access. */ 2777194246Smarius CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2778194246Smarius CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2779194246Smarius 2780194246Smarius /* Read PCI Expansion ROM header. */ 2781194246Smarius if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2782194246Smarius (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2783194246Smarius PCI_ROMHDR_SIZE) { 2784194246Smarius device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2785194246Smarius goto fail_prom; 2786194246Smarius } 2787194246Smarius 2788194246Smarius /* Read PCI Expansion ROM data. */ 2789194246Smarius if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2790194246Smarius CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2791194246Smarius CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2792194246Smarius (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2793194246Smarius i + PCI_ROM_SIZE) { 2794194246Smarius device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2795194246Smarius goto fail_prom; 2796194246Smarius } 2797194246Smarius 2798194246Smarius /* Read PCI VPD. */ 2799194246Smarius next: 2800194246Smarius if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2801194246Smarius j + PCI_VPDRES_BYTE0)) == 0) { 2802194246Smarius device_printf(dev, "no large PCI VPD\n"); 2803194246Smarius goto fail_prom; 2804194246Smarius } 2805194246Smarius 2806194246Smarius i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2807194246Smarius CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2808194246Smarius switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2809194246Smarius j + PCI_VPDRES_BYTE0))) { 2810194246Smarius case PCI_VPDRES_TYPE_ID_STRING: 2811194246Smarius /* Skip identifier string. */ 2812194246Smarius j += PCI_VPDRES_LARGE_SIZE + i; 2813194246Smarius goto next; 2814194246Smarius case PCI_VPDRES_TYPE_VPD: 2815194246Smarius for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2816194246Smarius i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2817194246Smarius j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2818194246Smarius if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2819194246Smarius /* no Enhanced VPD */ 2820194246Smarius continue; 2821194246Smarius if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2822194246Smarius /* no instance property */ 2823194246Smarius continue; 2824207585Smarius if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2825207585Smarius /* byte array */ 2826207585Smarius if (CAS_ROM_READ_1(sc, 2827207585Smarius j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2828207585Smarius continue; 2829207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2830207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2831207585Smarius buf, sizeof(buf)); 2832207585Smarius buf[sizeof(buf) - 1] = '\0'; 2833207585Smarius if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2834207585Smarius continue; 2835207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2836207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2837207585Smarius 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2838207585Smarius enaddr[lma], sizeof(enaddr[lma])); 2839207585Smarius lma++; 2840207585Smarius if (lma == 4 && phy == 4) 2841207585Smarius break; 2842207585Smarius } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2843207585Smarius 'S') { 2844207585Smarius /* string */ 2845207585Smarius if (CAS_ROM_READ_1(sc, 2846207585Smarius j + PCI_VPD_SIZE + 4) != 2847207585Smarius sizeof(CAS_PHY_TYPE_PCS)) 2848207585Smarius continue; 2849207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2850207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2851207585Smarius buf, sizeof(buf)); 2852207585Smarius buf[sizeof(buf) - 1] = '\0'; 2853207585Smarius if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2854207585Smarius k = sizeof(CAS_PHY_INTERFACE); 2855207585Smarius else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2856207585Smarius k = sizeof(CAS_PHY_TYPE); 2857207585Smarius else 2858207585Smarius continue; 2859207585Smarius bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2860207585Smarius CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2861207585Smarius 5 + k, buf, sizeof(buf)); 2862207585Smarius buf[sizeof(buf) - 1] = '\0'; 2863207585Smarius if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2864207585Smarius pcs[phy] = 1; 2865207585Smarius phy++; 2866207585Smarius if (lma == 4 && phy == 4) 2867207585Smarius break; 2868207585Smarius } 2869194246Smarius } 2870194246Smarius break; 2871194246Smarius default: 2872194246Smarius device_printf(dev, "unexpected PCI VPD\n"); 2873194246Smarius goto fail_prom; 2874194246Smarius } 2875194246Smarius 2876194246Smarius fail_prom: 2877194246Smarius CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2878194246Smarius 2879207585Smarius if (lma == 0) { 2880194246Smarius device_printf(dev, "could not determine Ethernet address\n"); 2881194246Smarius goto fail; 2882194246Smarius } 2883194246Smarius i = 0; 2884245923Smarius if (lma > 1 && pci_get_slot(dev) < nitems(enaddr)) 2885194246Smarius i = pci_get_slot(dev); 2886194246Smarius memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2887207585Smarius 2888207585Smarius if (phy == 0) { 2889207585Smarius device_printf(dev, "could not determine PHY type\n"); 2890207585Smarius goto fail; 2891207585Smarius } 2892207585Smarius i = 0; 2893245923Smarius if (phy > 1 && pci_get_slot(dev) < nitems(pcs)) 2894207585Smarius i = pci_get_slot(dev); 2895207585Smarius if (pcs[i] != 0) 2896207585Smarius sc->sc_flags |= CAS_SERDES; 2897194246Smarius#endif 2898194246Smarius 2899194246Smarius if (cas_attach(sc) != 0) { 2900194246Smarius device_printf(dev, "could not be attached\n"); 2901194246Smarius goto fail; 2902194246Smarius } 2903194246Smarius 2904194246Smarius if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2905194904Smarius INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2906194246Smarius device_printf(dev, "failed to set up interrupt\n"); 2907194246Smarius cas_detach(sc); 2908194246Smarius goto fail; 2909194246Smarius } 2910194246Smarius return (0); 2911194246Smarius 2912194246Smarius fail: 2913194246Smarius CAS_LOCK_DESTROY(sc); 2914194246Smarius bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2915194246Smarius return (ENXIO); 2916194246Smarius} 2917194246Smarius 2918194246Smariusstatic int 2919194246Smariuscas_pci_detach(device_t dev) 2920194246Smarius{ 2921194246Smarius struct cas_softc *sc; 2922194246Smarius 2923194246Smarius sc = device_get_softc(dev); 2924194246Smarius bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2925194246Smarius cas_detach(sc); 2926194246Smarius CAS_LOCK_DESTROY(sc); 2927194246Smarius bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2928194246Smarius return (0); 2929194246Smarius} 2930194246Smarius 2931194246Smariusstatic int 2932194246Smariuscas_pci_suspend(device_t dev) 2933194246Smarius{ 2934194246Smarius 2935194246Smarius cas_suspend(device_get_softc(dev)); 2936194246Smarius return (0); 2937194246Smarius} 2938194246Smarius 2939194246Smariusstatic int 2940194246Smariuscas_pci_resume(device_t dev) 2941194246Smarius{ 2942194246Smarius 2943194246Smarius cas_resume(device_get_softc(dev)); 2944194246Smarius return (0); 2945194246Smarius} 2946