bxe.h revision 297898
1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#ifndef __BXE_H__ 28#define __BXE_H__ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bxe/bxe.h 297898 2016-04-13 00:53:04Z davidcs $"); 32 33#include <sys/param.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/sx.h> 39#include <sys/module.h> 40#include <sys/endian.h> 41#include <sys/types.h> 42#include <sys/malloc.h> 43#include <sys/kobj.h> 44#include <sys/bus.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/sysctl.h> 49#include <sys/smp.h> 50#include <sys/bitstring.h> 51#include <sys/limits.h> 52#include <sys/queue.h> 53#include <sys/taskqueue.h> 54#include <sys/zlib.h> 55 56#include <net/if.h> 57#include <net/if_types.h> 58#include <net/if_arp.h> 59#include <net/ethernet.h> 60#include <net/if_dl.h> 61#include <net/if_var.h> 62#include <net/if_media.h> 63#include <net/if_vlan_var.h> 64#include <net/bpf.h> 65 66#include <netinet/in.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/udp.h> 71 72#include <dev/pci/pcireg.h> 73#include <dev/pci/pcivar.h> 74 75#include <machine/atomic.h> 76#include <machine/resource.h> 77#include <machine/endian.h> 78#include <machine/bus.h> 79#include <machine/in_cksum.h> 80 81#include "device_if.h" 82#include "bus_if.h" 83#include "pci_if.h" 84 85#if _BYTE_ORDER == _LITTLE_ENDIAN 86#ifndef LITTLE_ENDIAN 87#define LITTLE_ENDIAN 88#endif 89#ifndef __LITTLE_ENDIAN 90#define __LITTLE_ENDIAN 91#endif 92#undef BIG_ENDIAN 93#undef __BIG_ENDIAN 94#else /* _BIG_ENDIAN */ 95#ifndef BIG_ENDIAN 96#define BIG_ENDIAN 97#endif 98#ifndef __BIG_ENDIAN 99#define __BIG_ENDIAN 100#endif 101#undef LITTLE_ENDIAN 102#undef __LITTLE_ENDIAN 103#endif 104 105#include "ecore_mfw_req.h" 106#include "ecore_fw_defs.h" 107#include "ecore_hsi.h" 108#include "ecore_reg.h" 109#include "bxe_dcb.h" 110#include "bxe_stats.h" 111 112#include "bxe_elink.h" 113 114#define VF_MAC_CREDIT_CNT 0 115#define VF_VLAN_CREDIT_CNT (0) 116 117#if __FreeBSD_version < 800054 118#if defined(__i386__) || defined(__amd64__) 119#define mb() __asm volatile("mfence;" : : : "memory") 120#define wmb() __asm volatile("sfence;" : : : "memory") 121#define rmb() __asm volatile("lfence;" : : : "memory") 122static __inline void prefetch(void *x) 123{ 124 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 125} 126#else 127#define mb() 128#define rmb() 129#define wmb() 130#define prefetch(x) 131#endif 132#endif 133 134#if __FreeBSD_version >= 1000000 135#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 136#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 137#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 138#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 139#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 140#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 141#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 142#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 143#endif 144 145#ifndef ARRAY_SIZE 146#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 147#endif 148#ifndef ARRSIZE 149#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 150#endif 151#ifndef DIV_ROUND_UP 152#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 153#endif 154#ifndef roundup 155#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 156#endif 157#ifndef ilog2 158static inline 159int bxe_ilog2(int x) 160{ 161 int log = 0; 162 while (x >>= 1) log++; 163 return (log); 164} 165#define ilog2(x) bxe_ilog2(x) 166#endif 167 168#include "ecore_sp.h" 169 170#define BRCM_VENDORID 0x14e4 171#define PCI_ANY_ID (uint16_t)(~0U) 172 173struct bxe_device_type 174{ 175 uint16_t bxe_vid; 176 uint16_t bxe_did; 177 uint16_t bxe_svid; 178 uint16_t bxe_sdid; 179 char *bxe_name; 180}; 181 182#define BCM_PAGE_SHIFT 12 183#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 184#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 185#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 186 187#if BCM_PAGE_SIZE != 4096 188#error Page sizes other than 4KB are unsupported! 189#endif 190 191#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 192#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 193#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 194#else 195#define U64_LO(addr) ((uint32_t)(addr)) 196#define U64_HI(addr) (0) 197#endif 198#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 199 200#define SET_FLAG(value, mask, flag) \ 201 do { \ 202 (value) &= ~(mask); \ 203 (value) |= ((flag) << (mask##_SHIFT)); \ 204 } while (0) 205 206#define GET_FLAG(value, mask) \ 207 (((value) & (mask)) >> (mask##_SHIFT)) 208 209#define GET_FIELD(value, fname) \ 210 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 211 212#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 213#define BXE_TSO_MAX_SEGMENTS 32 214#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 215#define BXE_TSO_MAX_SEG_SIZE 4096 216 217/* dropless fc FW/HW related params */ 218#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 219#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 220 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 221 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 222#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 223#define FW_PREFETCH_CNT 16 224#define DROPLESS_FC_HEADROOM 100 225 226/******************/ 227/* RX SGE defines */ 228/******************/ 229 230#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 231#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 232#define RX_SGE_NEXT_PAGE_DESC_CNT 2 233#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 234#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 235#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 236#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 237#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 238#define RX_SGE(x) ((x) & RX_SGE_MAX) 239 240#define RX_SGE_NEXT(x) \ 241 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 242 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 243 244#define RX_SGE_MASK_ELEM_SZ 64 245#define RX_SGE_MASK_ELEM_SHIFT 6 246#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 247 248/* 249 * Creates a bitmask of all ones in less significant bits. 250 * idx - index of the most significant bit in the created mask. 251 */ 252#define RX_SGE_ONES_MASK(idx) \ 253 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 254#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 255 256/* Number of uint64_t elements in SGE mask array. */ 257#define RX_SGE_MASK_LEN \ 258 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 259#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 260#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 261 262/* 263 * dropless fc calculations for SGEs 264 * Number of required SGEs is the sum of two: 265 * 1. Number of possible opened aggregations (next packet for 266 * these aggregations will probably consume SGE immidiatelly) 267 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 268 * after placement on BD for new TPA aggregation) 269 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 270 */ 271#define NUM_SGE_REQ(sc) \ 272 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 273#define NUM_SGE_PG_REQ(sc) \ 274 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 275#define SGE_TH_LO(sc) \ 276 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 277#define SGE_TH_HI(sc) \ 278 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 279 280#define PAGES_PER_SGE_SHIFT 0 281#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 282#define SGE_PAGE_SIZE BCM_PAGE_SIZE 283#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 284#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 285#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 286#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 287 288/*****************/ 289/* TX BD defines */ 290/*****************/ 291 292#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 293#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 294#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 295#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 296#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 297#define TX_BD_MAX (TX_BD_TOTAL - 1) 298 299#define TX_BD_NEXT(x) \ 300 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 301 ((x) + 2) : ((x) + 1)) 302#define TX_BD(x) ((x) & TX_BD_MAX) 303#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 304#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 305 306/* 307 * Trigger pending transmits when the number of available BDs is greater 308 * than 1/8 of the total number of usable BDs. 309 */ 310#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 311#define BXE_TX_TIMEOUT 5 312 313/*****************/ 314/* RX BD defines */ 315/*****************/ 316 317#define RX_BD_NUM_PAGES 8 /* power of 2 */ 318#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 319#define RX_BD_NEXT_PAGE_DESC_CNT 2 320#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 321#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 322#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 323#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 324#define RX_BD_MAX (RX_BD_TOTAL - 1) 325 326#define RX_BD_NEXT(x) \ 327 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 328 ((x) + 3) : ((x) + 1)) 329#define RX_BD(x) ((x) & RX_BD_MAX) 330#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 331#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 332 333/* 334 * dropless fc calculations for BDs 335 * Number of BDs should be as number of buffers in BRB: 336 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 337 * "next" elements on each page 338 */ 339#define NUM_BD_REQ(sc) \ 340 BRB_SIZE(sc) 341#define NUM_BD_PG_REQ(sc) \ 342 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 343#define BD_TH_LO(sc) \ 344 (NUM_BD_REQ(sc) + \ 345 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 346 FW_DROP_LEVEL(sc)) 347#define BD_TH_HI(sc) \ 348 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 349#define MIN_RX_AVAIL(sc) \ 350 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 351#define MIN_RX_SIZE_TPA_HW(sc) \ 352 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 353 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 354#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 355#define MIN_RX_SIZE_TPA(sc) \ 356 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 357#define MIN_RX_SIZE_NONTPA(sc) \ 358 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 359 360/***************/ 361/* RCQ defines */ 362/***************/ 363 364/* 365 * As long as CQE is X times bigger than BD entry we have to allocate X times 366 * more pages for CQ ring in order to keep it balanced with BD ring 367 */ 368#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 369 sizeof(struct eth_rx_bd)) 370#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 371#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 372#define RCQ_NEXT_PAGE_DESC_CNT 1 373#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 374#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 375#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 376#define RCQ_MAX (RCQ_TOTAL - 1) 377 378#define RCQ_NEXT(x) \ 379 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 380 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 381#define RCQ(x) ((x) & RCQ_MAX) 382#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 383#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 384 385/* 386 * dropless fc calculations for RCQs 387 * Number of RCQs should be as number of buffers in BRB: 388 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 389 * "next" elements on each page 390 */ 391#define NUM_RCQ_REQ(sc) \ 392 BRB_SIZE(sc) 393#define NUM_RCQ_PG_REQ(sc) \ 394 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 395#define RCQ_TH_LO(sc) \ 396 (NUM_RCQ_REQ(sc) + \ 397 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 398 FW_DROP_LEVEL(sc)) 399#define RCQ_TH_HI(sc) \ 400 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 401 402/* This is needed for determening of last_max */ 403#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 404 405#define __SGE_MASK_SET_BIT(el, bit) \ 406 do { \ 407 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 408 } while (0) 409 410#define __SGE_MASK_CLEAR_BIT(el, bit) \ 411 do { \ 412 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 413 } while (0) 414 415#define SGE_MASK_SET_BIT(fp, idx) \ 416 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 417 ((idx) & RX_SGE_MASK_ELEM_MASK)) 418 419#define SGE_MASK_CLEAR_BIT(fp, idx) \ 420 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 421 ((idx) & RX_SGE_MASK_ELEM_MASK)) 422 423/* Load / Unload modes */ 424#define LOAD_NORMAL 0 425#define LOAD_OPEN 1 426#define LOAD_DIAG 2 427#define LOAD_LOOPBACK_EXT 3 428#define UNLOAD_NORMAL 0 429#define UNLOAD_CLOSE 1 430#define UNLOAD_RECOVERY 2 431 432/* Some constants... */ 433//#define MAX_PATH_NUM 2 434//#define E2_MAX_NUM_OF_VFS 64 435//#define E1H_FUNC_MAX 8 436//#define E2_FUNC_MAX 4 /* per path */ 437#define MAX_VNIC_NUM 4 438#define MAX_FUNC_NUM 8 /* common to all chips */ 439//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 440#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 441#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 442 443#define ILT_NUM_PAGE_ENTRIES 3072 444/* 445 * 57710/11 we use whole table since we have 8 functions. 446 * 57712 we have only 4 functions, but use same size per func, so only half 447 * of the table is used. 448 */ 449#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 450#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 451/* 452 * the phys address is shifted right 12 bits and has an added 453 * 1=valid bit added to the 53rd bit 454 * then since this is a wide register(TM) 455 * we split it into two 32 bit writes 456 */ 457#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 458#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 459 460/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 461#define ETH_HLEN 14 462#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 463#define ETH_MIN_PACKET_SIZE 60 464#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 465#define ETH_MAX_JUMBO_PACKET_SIZE 9600 466/* TCP with Timestamp Option (32) + IPv6 (40) */ 467#define ETH_MAX_TPA_HEADER_SIZE 72 468 469/* max supported alignment is 256 (8 shift) */ 470//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 471#define BXE_RX_ALIGN_SHIFT 8 472/* FW uses 2 cache lines alignment for start packet and size */ 473#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 474#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 475 476#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 477 478struct bxe_bar { 479 struct resource *resource; 480 int rid; 481 bus_space_tag_t tag; 482 bus_space_handle_t handle; 483 vm_offset_t kva; 484}; 485 486struct bxe_intr { 487 struct resource *resource; 488 int rid; 489 void *tag; 490}; 491 492/* Used to manage DMA allocations. */ 493struct bxe_dma { 494 struct bxe_softc *sc; 495 bus_addr_t paddr; 496 void *vaddr; 497 bus_dma_tag_t tag; 498 bus_dmamap_t map; 499 bus_dma_segment_t seg; 500 bus_size_t size; 501 int nseg; 502 char msg[32]; 503}; 504 505/* attn group wiring */ 506#define MAX_DYNAMIC_ATTN_GRPS 8 507 508struct attn_route { 509 uint32_t sig[5]; 510}; 511 512struct iro { 513 uint32_t base; 514 uint16_t m1; 515 uint16_t m2; 516 uint16_t m3; 517 uint16_t size; 518}; 519 520union bxe_host_hc_status_block { 521 /* pointer to fp status block e2 */ 522 struct host_hc_status_block_e2 *e2_sb; 523 /* pointer to fp status block e1x */ 524 struct host_hc_status_block_e1x *e1x_sb; 525}; 526 527union bxe_db_prod { 528 struct doorbell_set_prod data; 529 uint32_t raw; 530}; 531 532struct bxe_sw_tx_bd { 533 struct mbuf *m; 534 bus_dmamap_t m_map; 535 uint16_t first_bd; 536 uint8_t flags; 537/* set on the first BD descriptor when there is a split BD */ 538#define BXE_TSO_SPLIT_BD (1 << 0) 539}; 540 541struct bxe_sw_rx_bd { 542 struct mbuf *m; 543 bus_dmamap_t m_map; 544}; 545 546struct bxe_sw_tpa_info { 547 struct bxe_sw_rx_bd bd; 548 bus_dma_segment_t seg; 549 uint8_t state; 550#define BXE_TPA_STATE_START 1 551#define BXE_TPA_STATE_STOP 2 552 uint8_t placement_offset; 553 uint16_t parsing_flags; 554 uint16_t vlan_tag; 555 uint16_t len_on_bd; 556}; 557 558/* 559 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 560 * instances of the fastpath structure when using multiple queues. 561 */ 562struct bxe_fastpath { 563 /* pointer back to parent structure */ 564 struct bxe_softc *sc; 565 566 struct mtx tx_mtx; 567 char tx_mtx_name[32]; 568 struct mtx rx_mtx; 569 char rx_mtx_name[32]; 570 571#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 572#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 573#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 574#define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 575 576#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 577#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 578#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 579 580 /* status block */ 581 struct bxe_dma sb_dma; 582 union bxe_host_hc_status_block status_block; 583 584 /* transmit chain (tx bds) */ 585 struct bxe_dma tx_dma; 586 union eth_tx_bd_types *tx_chain; 587 588 /* receive chain (rx bds) */ 589 struct bxe_dma rx_dma; 590 struct eth_rx_bd *rx_chain; 591 592 /* receive completion queue chain (rcq bds) */ 593 struct bxe_dma rcq_dma; 594 union eth_rx_cqe *rcq_chain; 595 596 /* receive scatter/gather entry chain (for TPA) */ 597 struct bxe_dma rx_sge_dma; 598 struct eth_rx_sge *rx_sge_chain; 599 600 /* tx mbufs */ 601 bus_dma_tag_t tx_mbuf_tag; 602 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 603 604 /* rx mbufs */ 605 bus_dma_tag_t rx_mbuf_tag; 606 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 607 bus_dmamap_t rx_mbuf_spare_map; 608 609 /* rx sge mbufs */ 610 bus_dma_tag_t rx_sge_mbuf_tag; 611 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 612 bus_dmamap_t rx_sge_mbuf_spare_map; 613 614 /* rx tpa mbufs (use the larger size for TPA queue length) */ 615 int tpa_enable; /* disabled per fastpath upon error */ 616 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 617 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 618 uint64_t rx_tpa_queue_used; 619 620 uint16_t *sb_index_values; 621 uint16_t *sb_running_index; 622 uint32_t ustorm_rx_prods_offset; 623 624 uint8_t igu_sb_id; /* status block number in HW */ 625 uint8_t fw_sb_id; /* status block number in FW */ 626 627 uint32_t rx_buf_size; 628 int mbuf_alloc_size; 629 630 int state; 631#define BXE_FP_STATE_CLOSED 0x01 632#define BXE_FP_STATE_IRQ 0x02 633#define BXE_FP_STATE_OPENING 0x04 634#define BXE_FP_STATE_OPEN 0x08 635#define BXE_FP_STATE_HALTING 0x10 636#define BXE_FP_STATE_HALTED 0x20 637 638 /* reference back to this fastpath queue number */ 639 uint8_t index; /* this is also the 'cid' */ 640#define FP_IDX(fp) (fp->index) 641 642 /* interrupt taskqueue (fast) */ 643 struct task tq_task; 644 struct taskqueue *tq; 645 char tq_name[32]; 646 647 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 648 uint8_t cl_id; 649#define FP_CL_ID(fp) (fp->cl_id) 650 uint8_t cl_qzone_id; 651 652 uint16_t fp_hc_idx; 653 654 /* driver copy of the receive buffer descriptor prod/cons indices */ 655 uint16_t rx_bd_prod; 656 uint16_t rx_bd_cons; 657 658 /* driver copy of the receive completion queue prod/cons indices */ 659 uint16_t rx_cq_prod; 660 uint16_t rx_cq_cons; 661 662 union bxe_db_prod tx_db; 663 664 /* Transmit packet producer index (used in eth_tx_bd). */ 665 uint16_t tx_pkt_prod; 666 uint16_t tx_pkt_cons; 667 668 /* Transmit buffer descriptor producer index. */ 669 uint16_t tx_bd_prod; 670 uint16_t tx_bd_cons; 671 672 uint64_t sge_mask[RX_SGE_MASK_LEN]; 673 uint16_t rx_sge_prod; 674 675 struct tstorm_per_queue_stats old_tclient; 676 struct ustorm_per_queue_stats old_uclient; 677 struct xstorm_per_queue_stats old_xclient; 678 struct bxe_eth_q_stats eth_q_stats; 679 struct bxe_eth_q_stats_old eth_q_stats_old; 680 681 /* Pointer to the receive consumer in the status block */ 682 uint16_t *rx_cq_cons_sb; 683 684 /* Pointer to the transmit consumer in the status block */ 685 uint16_t *tx_cons_sb; 686 687 /* transmit timeout until chip reset */ 688 int watchdog_timer; 689 690 /* Free/used buffer descriptor counters. */ 691 //uint16_t used_tx_bd; 692 693 /* Last maximal completed SGE */ 694 uint16_t last_max_sge; 695 696 //uint16_t rx_sge_free_idx; 697 698 //uint8_t segs; 699 700#if __FreeBSD_version >= 800000 701#define BXE_BR_SIZE 4096 702 struct buf_ring *tx_br; 703#endif 704}; /* struct bxe_fastpath */ 705 706/* sriov XXX */ 707#define BXE_MAX_NUM_OF_VFS 64 708#define BXE_VF_CID_WND 0 709#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 710#define BXE_CLIENTS_PER_VF 1 711#define BXE_FIRST_VF_CID 256 712#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 713#define BXE_VF_ID_INVALID 0xFF 714#define IS_SRIOV(sc) 0 715 716#define GET_NUM_VFS_PER_PATH(sc) 0 717#define GET_NUM_VFS_PER_PF(sc) 0 718 719/* maximum number of fast-path interrupt contexts */ 720#define FP_SB_MAX_E1x 16 721#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 722 723union cdu_context { 724 struct eth_context eth; 725 char pad[1024]; 726}; 727 728/* CDU host DB constants */ 729#define CDU_ILT_PAGE_SZ_HW 2 730#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 731#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 732 733#define CNIC_ISCSI_CID_MAX 256 734#define CNIC_FCOE_CID_MAX 2048 735#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 736#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 737 738#define QM_ILT_PAGE_SZ_HW 0 739#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 740#define QM_CID_ROUND 1024 741 742/* TM (timers) host DB constants */ 743#define TM_ILT_PAGE_SZ_HW 0 744#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 745/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 746#define TM_CONN_NUM 1024 747#define TM_ILT_SZ (8 * TM_CONN_NUM) 748#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 749 750/* SRC (Searcher) host DB constants */ 751#define SRC_ILT_PAGE_SZ_HW 0 752#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 753#define SRC_HASH_BITS 10 754#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 755#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 756#define SRC_T2_SZ SRC_ILT_SZ 757#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 758 759struct hw_context { 760 struct bxe_dma vcxt_dma; 761 union cdu_context *vcxt; 762 //bus_addr_t cxt_mapping; 763 size_t size; 764}; 765 766#define SM_RX_ID 0 767#define SM_TX_ID 1 768 769/* defines for multiple tx priority indices */ 770#define FIRST_TX_ONLY_COS_INDEX 1 771#define FIRST_TX_COS_INDEX 0 772 773#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 774 775#define HC_INDEX_ETH_RX_CQ_CONS 1 776#define HC_INDEX_OOO_TX_CQ_CONS 4 777#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 778#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 779#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 780#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 781 782/* congestion management fairness mode */ 783#define CMNG_FNS_NONE 0 784#define CMNG_FNS_MINMAX 1 785 786/* CMNG constants, as derived from system spec calculations */ 787/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 788#define DEF_MIN_RATE 100 789/* resolution of the rate shaping timer - 400 usec */ 790#define RS_PERIODIC_TIMEOUT_USEC 400 791/* number of bytes in single QM arbitration cycle - 792 * coefficient for calculating the fairness timer */ 793#define QM_ARB_BYTES 160000 794/* resolution of Min algorithm 1:100 */ 795#define MIN_RES 100 796/* how many bytes above threshold for the minimal credit of Min algorithm*/ 797#define MIN_ABOVE_THRESH 32768 798/* fairness algorithm integration time coefficient - 799 * for calculating the actual Tfair */ 800#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 801/* memory of fairness algorithm - 2 cycles */ 802#define FAIR_MEM 2 803 804#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 805#define HC_SEG_ACCESS_ATTN 4 806#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 807 808/* 809 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 810 * control by the number of fast-path status blocks supported by the 811 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 812 * status block represents an independent interrupts context that can 813 * serve a regular L2 networking queue. However special L2 queues such 814 * as the FCoE queue do not require a FP-SB and other components like 815 * the CNIC may consume FP-SB reducing the number of possible L2 queues 816 * 817 * If the maximum number of FP-SB available is X then: 818 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 819 * regular L2 queues is Y=X-1 820 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 821 * c. If the FCoE L2 queue is supported the actual number of L2 queues 822 * is Y+1 823 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 824 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 825 * FP interrupt context for the CNIC). 826 * e. The number of HW context (CID count) is always X or X+1 if FCoE 827 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 828 * 829 * So this is quite simple for now as no ULPs are supported yet. :-) 830 */ 831#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 832#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 833#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 834#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 835 836#define FOR_EACH_QUEUE(sc, var) \ 837 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 838 839#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 840 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 841 842#define FOR_EACH_ETH_QUEUE(sc, var) \ 843 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 844 845#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 846 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 847 848#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 849 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 850 851#define FOR_EACH_CNIC_QUEUE(sc, var) \ 852 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 853 (var) < BXE_NUM_QUEUES(sc); \ 854 (var)++) 855 856enum { 857 OOO_IDX_OFFSET, 858 FCOE_IDX_OFFSET, 859 FWD_IDX_OFFSET, 860}; 861 862#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 863#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 864#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 865#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 866#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 867#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 868 869#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 870#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 871#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 872#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 873#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 874 875#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 876#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 877#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 878#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 879#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 880#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 881 882#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 883#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 884#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 885#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 886#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 887#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 888#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 889 890enum { 891 BXE_PORT_QUERY_IDX, 892 BXE_PF_QUERY_IDX, 893 BXE_FCOE_QUERY_IDX, 894 BXE_FIRST_QUEUE_QUERY_IDX, 895}; 896 897struct bxe_fw_stats_req { 898 struct stats_query_header hdr; 899 struct stats_query_entry query[FP_SB_MAX_E1x + 900 BXE_FIRST_QUEUE_QUERY_IDX]; 901}; 902 903struct bxe_fw_stats_data { 904 struct stats_counter storm_counters; 905 struct per_port_stats port; 906 struct per_pf_stats pf; 907 //struct fcoe_statistics_params fcoe; 908 struct per_queue_stats queue_stats[1]; 909}; 910 911/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 912#define BXE_IGU_STAS_MSG_VF_CNT 64 913#define BXE_IGU_STAS_MSG_PF_CNT 4 914 915#define MAX_DMAE_C 8 916 917/* 918 * For the main interface up/down code paths, a not-so-fine-grained CORE 919 * mutex lock is used. Inside this code are various calls to kernel routines 920 * that can cause a sleep to occur. Namely memory allocations and taskqueue 921 * handling. If using an MTX lock we are *not* allowed to sleep but we can 922 * with an SX lock. This define forces the CORE lock to use and SX lock. 923 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 924 * path can cause problems since it's called by a non-sleepable thread. To 925 * alleviate a potential sleep, any IOCTL processing that results in the 926 * chip/interface being started/stopped/reinitialized, the actual work is 927 * offloaded to a taskqueue. 928 */ 929#define BXE_CORE_LOCK_SX 930 931/* 932 * This is the slowpath data structure. It is mapped into non-paged memory 933 * so that the hardware can access it's contents directly and must be page 934 * aligned. 935 */ 936struct bxe_slowpath { 937 938 /* used by the DMAE command executer */ 939 struct dmae_cmd dmae[MAX_DMAE_C]; 940 941 /* statistics completion */ 942 uint32_t stats_comp; 943 944 /* firmware defined statistics blocks */ 945 union mac_stats mac_stats; 946 struct nig_stats nig_stats; 947 struct host_port_stats port_stats; 948 struct host_func_stats func_stats; 949 //struct host_func_stats func_stats_base; 950 951 /* DMAE completion value and data source/sink */ 952 uint32_t wb_comp; 953 uint32_t wb_data[4]; 954 955 union { 956 struct mac_configuration_cmd e1x; 957 struct eth_classify_rules_ramrod_data e2; 958 } mac_rdata; 959 960 union { 961 struct tstorm_eth_mac_filter_config e1x; 962 struct eth_filter_rules_ramrod_data e2; 963 } rx_mode_rdata; 964 965 struct eth_rss_update_ramrod_data rss_rdata; 966 967 union { 968 struct mac_configuration_cmd e1; 969 struct eth_multicast_rules_ramrod_data e2; 970 } mcast_rdata; 971 972 union { 973 struct function_start_data func_start; 974 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 975 } func_rdata; 976 977 /* Queue State related ramrods */ 978 union { 979 struct client_init_ramrod_data init_data; 980 struct client_update_ramrod_data update_data; 981 } q_rdata; 982 983 /* 984 * AFEX ramrod can not be a part of func_rdata union because these 985 * events might arrive in parallel to other events from func_rdata. 986 * If they were defined in the same union the data can get corrupted. 987 */ 988 struct afex_vif_list_ramrod_data func_afex_rdata; 989 990 union drv_info_to_mcp drv_info_to_mcp; 991}; /* struct bxe_slowpath */ 992 993/* 994 * Port specifc data structure. 995 */ 996struct bxe_port { 997 /* 998 * Port Management Function (for 57711E only). 999 * When this field is set the driver instance is 1000 * responsible for managing port specifc 1001 * configurations such as handling link attentions. 1002 */ 1003 uint32_t pmf; 1004 1005 /* Ethernet maximum transmission unit. */ 1006 uint16_t ether_mtu; 1007 1008 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1009 1010 uint32_t ext_phy_config; 1011 1012 /* Port feature config.*/ 1013 uint32_t config; 1014 1015 /* Defines the features supported by the PHY. */ 1016 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1017 1018 /* Defines the features advertised by the PHY. */ 1019 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1020#define ADVERTISED_10baseT_Half (1 << 1) 1021#define ADVERTISED_10baseT_Full (1 << 2) 1022#define ADVERTISED_100baseT_Half (1 << 3) 1023#define ADVERTISED_100baseT_Full (1 << 4) 1024#define ADVERTISED_1000baseT_Half (1 << 5) 1025#define ADVERTISED_1000baseT_Full (1 << 6) 1026#define ADVERTISED_TP (1 << 7) 1027#define ADVERTISED_FIBRE (1 << 8) 1028#define ADVERTISED_Autoneg (1 << 9) 1029#define ADVERTISED_Asym_Pause (1 << 10) 1030#define ADVERTISED_Pause (1 << 11) 1031#define ADVERTISED_2500baseX_Full (1 << 15) 1032#define ADVERTISED_10000baseT_Full (1 << 16) 1033 1034 uint32_t phy_addr; 1035 1036 /* Used to synchronize phy accesses. */ 1037 struct mtx phy_mtx; 1038 char phy_mtx_name[32]; 1039 1040#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1041#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1042#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1043 1044 /* 1045 * MCP scratchpad address for port specific statistics. 1046 * The device is responsible for writing statistcss 1047 * back to the MCP for use with management firmware such 1048 * as UMP/NC-SI. 1049 */ 1050 uint32_t port_stx; 1051 1052 struct nig_stats old_nig_stats; 1053}; /* struct bxe_port */ 1054 1055struct bxe_mf_info { 1056 uint32_t mf_config[E1HVN_MAX]; 1057 1058 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1059 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1060 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1061 1062#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1063#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1064#define VNICS_PER_PATH(sc) \ 1065 ((sc)->devinfo.mf_info.vnics_per_port * \ 1066 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1067 1068 uint8_t min_bw[MAX_VNIC_NUM]; 1069 uint8_t max_bw[MAX_VNIC_NUM]; 1070 1071 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1072#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1073#define INVALID_VIF_ID 0xFFFF 1074#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1075#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1076 1077 uint16_t default_vlan; 1078#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1079 1080 uint8_t niv_allowed_priorities; 1081#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1082 1083 uint8_t niv_default_cos; 1084#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1085 1086 uint8_t niv_mba_enabled; 1087 1088 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1089#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1090 int afex_def_vlan_tag; 1091 uint32_t pending_max; 1092 1093 uint16_t flags; 1094#define MF_INFO_VALID_MAC 0x0001 1095 1096 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1097#define IS_MF(sc) \ 1098 (IS_MULTI_VNIC(sc) && \ 1099 ((sc)->devinfo.mf_info.mf_mode != 0)) 1100#define IS_MF_SD(sc) \ 1101 (IS_MULTI_VNIC(sc) && \ 1102 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1103#define IS_MF_SI(sc) \ 1104 (IS_MULTI_VNIC(sc) && \ 1105 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1106#define IS_MF_AFEX(sc) \ 1107 (IS_MULTI_VNIC(sc) && \ 1108 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1109#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1110#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1111#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1112 1113 uint32_t mf_protos_supported; 1114 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1115 #define MF_PROTO_SUPPORT_ISCSI 0x2 1116 #define MF_PROTO_SUPPORT_FCOE 0x4 1117}; /* struct bxe_mf_info */ 1118 1119/* Device information data structure. */ 1120struct bxe_devinfo { 1121 /* PCIe info */ 1122 uint16_t vendor_id; 1123 uint16_t device_id; 1124 uint16_t subvendor_id; 1125 uint16_t subdevice_id; 1126 1127 /* 1128 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1129 * C = Chip Number (bits 16-31) 1130 * R = Chip Revision (bits 12-15) 1131 * M = Chip Metal (bits 4-11) 1132 * B = Chip Bond ID (bits 0-3) 1133 */ 1134 uint32_t chip_id; 1135#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1136#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1137/* device ids */ 1138#define CHIP_NUM_57710 0x164e 1139#define CHIP_NUM_57711 0x164f 1140#define CHIP_NUM_57711E 0x1650 1141#define CHIP_NUM_57712 0x1662 1142#define CHIP_NUM_57712_MF 0x1663 1143#define CHIP_NUM_57712_VF 0x166f 1144#define CHIP_NUM_57800 0x168a 1145#define CHIP_NUM_57800_MF 0x16a5 1146#define CHIP_NUM_57800_VF 0x16a9 1147#define CHIP_NUM_57810 0x168e 1148#define CHIP_NUM_57810_MF 0x16ae 1149#define CHIP_NUM_57810_VF 0x16af 1150#define CHIP_NUM_57811 0x163d 1151#define CHIP_NUM_57811_MF 0x163e 1152#define CHIP_NUM_57811_VF 0x163f 1153#define CHIP_NUM_57840_OBS 0x168d 1154#define CHIP_NUM_57840_OBS_MF 0x16ab 1155#define CHIP_NUM_57840_4_10 0x16a1 1156#define CHIP_NUM_57840_2_20 0x16a2 1157#define CHIP_NUM_57840_MF 0x16a4 1158#define CHIP_NUM_57840_VF 0x16ad 1159 1160#define CHIP_REV_SHIFT 12 1161#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1162#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1163 1164#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1165#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1166#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1167 1168#define CHIP_REV_IS_SLOW(sc) \ 1169 (CHIP_REV(sc) > 0x00005000) 1170#define CHIP_REV_IS_FPGA(sc) \ 1171 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1172#define CHIP_REV_IS_EMUL(sc) \ 1173 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1174#define CHIP_REV_IS_ASIC(sc) \ 1175 (!CHIP_REV_IS_SLOW(sc)) 1176 1177#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1178#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1179 1180#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1181#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1182#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1183#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1184#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1185 (CHIP_IS_57711E(sc))) 1186#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1187 CHIP_IS_E1H((sc))) 1188 1189#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1190#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1191#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1192#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1193 CHIP_IS_57712_MF(sc)) 1194 1195#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1196#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1197#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1198#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1199#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1200#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1201#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1202#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1203#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1204#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1205 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1206 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1207#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1208 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1209#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1210 1211#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1212 CHIP_IS_57800_MF(sc) || \ 1213 CHIP_IS_57800_VF(sc) || \ 1214 CHIP_IS_57810(sc) || \ 1215 CHIP_IS_57810_MF(sc) || \ 1216 CHIP_IS_57810_VF(sc) || \ 1217 CHIP_IS_57811(sc) || \ 1218 CHIP_IS_57811_MF(sc) || \ 1219 CHIP_IS_57811_VF(sc) || \ 1220 CHIP_IS_57840(sc) || \ 1221 CHIP_IS_57840_MF(sc) || \ 1222 CHIP_IS_57840_VF(sc)) 1223#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1224 (CHIP_REV(sc) == CHIP_REV_Ax)) 1225#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1226 (CHIP_REV(sc) == CHIP_REV_Bx)) 1227 1228#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1229#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1230 CHIP_IS_E3(sc)) 1231 1232#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1233 CHIP_IS_57712_MF(sc) || \ 1234 CHIP_IS_E3(sc)) 1235 1236#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1237 CHIP_IS_57800_VF(sc) || \ 1238 CHIP_IS_57810_VF(sc) || \ 1239 CHIP_IS_57840_VF(sc)) 1240#define IS_PF(sc) (!IS_VF(sc)) 1241 1242/* 1243 * This define is used in two main places: 1244 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1245 * to nic-only mode or to offload mode. Offload mode is configured if either 1246 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1247 * already registered for this port (which means that the user wants storage 1248 * services). 1249 * 2. During cnic-related load, to know if offload mode is already configured 1250 * in the HW or needs to be configrued. Since the transition from nic-mode to 1251 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1252 * in ports on which storage services where never requested. 1253 */ 1254#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1255 1256 uint8_t chip_port_mode; 1257#define CHIP_4_PORT_MODE 0x0 1258#define CHIP_2_PORT_MODE 0x1 1259#define CHIP_PORT_MODE_NONE 0x2 1260#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1261#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1262 1263 uint8_t int_block; 1264#define INT_BLOCK_HC 0 1265#define INT_BLOCK_IGU 1 1266#define INT_BLOCK_MODE_NORMAL 0 1267#define INT_BLOCK_MODE_BW_COMP 2 1268#define CHIP_INT_MODE_IS_NBC(sc) \ 1269 (!CHIP_IS_E1x(sc) && \ 1270 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1271#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1272 1273 uint32_t shmem_base; 1274 uint32_t shmem2_base; 1275 uint32_t bc_ver; 1276 char bc_ver_str[32]; 1277 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1278 struct bxe_mf_info mf_info; 1279 1280 int flash_size; 1281#define NVRAM_1MB_SIZE 0x20000 1282#define NVRAM_TIMEOUT_COUNT 30000 1283#define NVRAM_PAGE_SIZE 256 1284 1285 /* PCIe capability information */ 1286 uint32_t pcie_cap_flags; 1287#define BXE_PM_CAPABLE_FLAG 0x00000001 1288#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1289#define BXE_MSI_CAPABLE_FLAG 0x00000004 1290#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1291 uint16_t pcie_pm_cap_reg; 1292 uint16_t pcie_pcie_cap_reg; 1293 //uint16_t pcie_devctl; 1294 uint16_t pcie_link_width; 1295 uint16_t pcie_link_speed; 1296 uint16_t pcie_msi_cap_reg; 1297 uint16_t pcie_msix_cap_reg; 1298 1299 /* device configuration read from bootcode shared memory */ 1300 uint32_t hw_config; 1301 uint32_t hw_config2; 1302}; /* struct bxe_devinfo */ 1303 1304struct bxe_sp_objs { 1305 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1306 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1307}; /* struct bxe_sp_objs */ 1308 1309/* 1310 * Data that will be used to create a link report message. We will keep the 1311 * data used for the last link report in order to prevent reporting the same 1312 * link parameters twice. 1313 */ 1314struct bxe_link_report_data { 1315 uint16_t line_speed; /* Effective line speed */ 1316 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1317}; 1318enum { 1319 BXE_LINK_REPORT_FULL_DUPLEX, 1320 BXE_LINK_REPORT_LINK_DOWN, 1321 BXE_LINK_REPORT_RX_FC_ON, 1322 BXE_LINK_REPORT_TX_FC_ON 1323}; 1324 1325/* Top level device private data structure. */ 1326struct bxe_softc { 1327 /* 1328 * First entry must be a pointer to the BSD ifnet struct which 1329 * has a first element of 'void *if_softc' (which is us). XXX 1330 */ 1331 if_t ifp; 1332 struct ifmedia ifmedia; /* network interface media structure */ 1333 int media; 1334 1335 int state; /* device state */ 1336#define BXE_STATE_CLOSED 0x0000 1337#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1338#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1339#define BXE_STATE_OPEN 0x3000 1340#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1341#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1342#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1343#define BXE_STATE_DISABLED 0xD000 1344#define BXE_STATE_DIAG 0xE000 1345#define BXE_STATE_ERROR 0xF000 1346 1347 int flags; 1348#define BXE_ONE_PORT_FLAG 0x00000001 1349#define BXE_NO_ISCSI 0x00000002 1350#define BXE_NO_FCOE 0x00000004 1351#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1352//#define BXE_NO_WOL_FLAG 0x00000008 1353//#define BXE_USING_DAC_FLAG 0x00000010 1354//#define BXE_USING_MSIX_FLAG 0x00000020 1355//#define BXE_USING_MSI_FLAG 0x00000040 1356//#define BXE_DISABLE_MSI_FLAG 0x00000080 1357#define BXE_NO_MCP_FLAG 0x00000200 1358#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1359//#define BXE_SAFC_TX_FLAG 0x00000400 1360#define BXE_MF_FUNC_DIS 0x00000800 1361#define BXE_TX_SWITCHING 0x00001000 1362#define BXE_NO_PULSE 0x00002000 1363 1364 unsigned long debug; /* per-instance debug logging config */ 1365 1366#define MAX_BARS 5 1367 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1368 1369 uint16_t doorbell_size; 1370 1371 /* periodic timer callout */ 1372#define PERIODIC_STOP 0 1373#define PERIODIC_GO 1 1374 volatile unsigned long periodic_flags; 1375 struct callout periodic_callout; 1376 1377 /* chip start/stop/reset taskqueue */ 1378#define CHIP_TQ_NONE 0 1379#define CHIP_TQ_START 1 1380#define CHIP_TQ_STOP 2 1381#define CHIP_TQ_REINIT 3 1382 volatile unsigned long chip_tq_flags; 1383 struct task chip_tq_task; 1384 struct taskqueue *chip_tq; 1385 char chip_tq_name[32]; 1386 1387 /* slowpath interrupt taskqueue */ 1388 struct task sp_tq_task; 1389 struct taskqueue *sp_tq; 1390 char sp_tq_name[32]; 1391 1392 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1393 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1394 1395 device_t dev; /* parent device handle */ 1396 uint8_t unit; /* driver instance number */ 1397 1398 int pcie_bus; /* PCIe bus number */ 1399 int pcie_device; /* PCIe device/slot number */ 1400 int pcie_func; /* PCIe function number */ 1401 1402 uint8_t pfunc_rel; /* function relative */ 1403 uint8_t pfunc_abs; /* function absolute */ 1404 uint8_t path_id; /* function absolute */ 1405#define SC_PATH(sc) (sc->path_id) 1406#define SC_PORT(sc) (sc->pfunc_rel & 1) 1407#define SC_FUNC(sc) (sc->pfunc_rel) 1408#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1409#define SC_VN(sc) (sc->pfunc_rel >> 1) 1410#define SC_L_ID(sc) (SC_VN(sc) << 2) 1411#define PORT_ID(sc) SC_PORT(sc) 1412#define PATH_ID(sc) SC_PATH(sc) 1413#define VNIC_ID(sc) SC_VN(sc) 1414#define FUNC_ID(sc) SC_FUNC(sc) 1415#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1416#define SC_FW_MB_IDX_VN(sc, vn) \ 1417 (SC_PORT(sc) + (vn) * \ 1418 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1419#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1420 1421 int if_capen; /* enabled interface capabilities */ 1422 1423 struct bxe_devinfo devinfo; 1424 char fw_ver_str[32]; 1425 char mf_mode_str[32]; 1426 char pci_link_str[32]; 1427 1428 const struct iro *iro_array; 1429 1430#ifdef BXE_CORE_LOCK_SX 1431 struct sx core_sx; 1432 char core_sx_name[32]; 1433#else 1434 struct mtx core_mtx; 1435 char core_mtx_name[32]; 1436#endif 1437 struct mtx sp_mtx; 1438 char sp_mtx_name[32]; 1439 struct mtx dmae_mtx; 1440 char dmae_mtx_name[32]; 1441 struct mtx fwmb_mtx; 1442 char fwmb_mtx_name[32]; 1443 struct mtx print_mtx; 1444 char print_mtx_name[32]; 1445 struct mtx stats_mtx; 1446 char stats_mtx_name[32]; 1447 struct mtx mcast_mtx; 1448 char mcast_mtx_name[32]; 1449 1450#ifdef BXE_CORE_LOCK_SX 1451#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1452#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1453#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1454#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1455#else 1456#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1457#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1458#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1459#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1460#endif 1461 1462#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1463#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1464#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1465 1466#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1467#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1468#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1469 1470#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1471#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1472#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1473 1474#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1475#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1476#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1477 1478#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1479#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1480#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1481 1482#if __FreeBSD_version < 800000 1483#define BXE_MCAST_LOCK(sc) \ 1484 do { \ 1485 mtx_lock(&sc->mcast_mtx); \ 1486 IF_ADDR_LOCK(sc->ifp); \ 1487 } while (0) 1488#define BXE_MCAST_UNLOCK(sc) \ 1489 do { \ 1490 IF_ADDR_UNLOCK(sc->ifp); \ 1491 mtx_unlock(&sc->mcast_mtx); \ 1492 } while (0) 1493#else 1494#define BXE_MCAST_LOCK(sc) \ 1495 do { \ 1496 mtx_lock(&sc->mcast_mtx); \ 1497 if_maddr_rlock(sc->ifp); \ 1498 } while (0) 1499#define BXE_MCAST_UNLOCK(sc) \ 1500 do { \ 1501 if_maddr_runlock(sc->ifp); \ 1502 mtx_unlock(&sc->mcast_mtx); \ 1503 } while (0) 1504#endif 1505#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1506 1507 int dmae_ready; 1508#define DMAE_READY(sc) (sc->dmae_ready) 1509 1510 struct ecore_credit_pool_obj vlans_pool; 1511 struct ecore_credit_pool_obj macs_pool; 1512 struct ecore_rx_mode_obj rx_mode_obj; 1513 struct ecore_mcast_obj mcast_obj; 1514 struct ecore_rss_config_obj rss_conf_obj; 1515 struct ecore_func_sp_obj func_obj; 1516 1517 uint16_t fw_seq; 1518 uint16_t fw_drv_pulse_wr_seq; 1519 uint32_t func_stx; 1520 1521 struct elink_params link_params; 1522 struct elink_vars link_vars; 1523 uint32_t link_cnt; 1524 struct bxe_link_report_data last_reported_link; 1525 char mac_addr_str[32]; 1526 1527 int last_reported_link_state; 1528 1529 int tx_ring_size; 1530 int rx_ring_size; 1531 int wol; 1532 1533 int is_leader; 1534 int recovery_state; 1535#define BXE_RECOVERY_DONE 1 1536#define BXE_RECOVERY_INIT 2 1537#define BXE_RECOVERY_WAIT 3 1538#define BXE_RECOVERY_FAILED 4 1539#define BXE_RECOVERY_NIC_LOADING 5 1540 1541 uint32_t rx_mode; 1542#define BXE_RX_MODE_NONE 0 1543#define BXE_RX_MODE_NORMAL 1 1544#define BXE_RX_MODE_ALLMULTI 2 1545#define BXE_RX_MODE_PROMISC 3 1546#define BXE_MAX_MULTICAST 64 1547 1548 struct bxe_port port; 1549 1550 struct cmng_init cmng; 1551 1552 /* user configs */ 1553 int num_queues; 1554 int max_rx_bufs; 1555 int hc_rx_ticks; 1556 int hc_tx_ticks; 1557 int rx_budget; 1558 int max_aggregation_size; 1559 int mrrs; 1560 int autogreeen; 1561#define AUTO_GREEN_HW_DEFAULT 0 1562#define AUTO_GREEN_FORCE_ON 1 1563#define AUTO_GREEN_FORCE_OFF 2 1564 int interrupt_mode; 1565#define INTR_MODE_INTX 0 1566#define INTR_MODE_MSI 1 1567#define INTR_MODE_MSIX 2 1568 int udp_rss; 1569 1570 /* interrupt allocations */ 1571 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1572 int intr_count; 1573 uint8_t igu_dsb_id; 1574 uint8_t igu_base_sb; 1575 uint8_t igu_sb_cnt; 1576 //uint8_t min_msix_vec_cnt; 1577 uint32_t igu_base_addr; 1578 //bus_addr_t def_status_blk_mapping; 1579 uint8_t base_fw_ndsb; 1580#define DEF_SB_IGU_ID 16 1581#define DEF_SB_ID HC_SP_SB_ID 1582 1583 /* parent bus DMA tag */ 1584 bus_dma_tag_t parent_dma_tag; 1585 1586 /* default status block */ 1587 struct bxe_dma def_sb_dma; 1588 struct host_sp_status_block *def_sb; 1589 uint16_t def_idx; 1590 uint16_t def_att_idx; 1591 uint32_t attn_state; 1592 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1593 1594/* general SP events - stats query, cfc delete, etc */ 1595#define HC_SP_INDEX_ETH_DEF_CONS 3 1596/* EQ completions */ 1597#define HC_SP_INDEX_EQ_CONS 7 1598/* FCoE L2 connection completions */ 1599#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1600#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1601/* iSCSI L2 */ 1602#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1603#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1604 1605 /* event queue */ 1606 struct bxe_dma eq_dma; 1607 union event_ring_elem *eq; 1608 uint16_t eq_prod; 1609 uint16_t eq_cons; 1610 uint16_t *eq_cons_sb; 1611#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1612#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1613#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1614#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1615#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1616#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1617/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1618#define NEXT_EQ_IDX(x) \ 1619 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1620 ((x) + 2) : ((x) + 1)) 1621/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1622#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1623 1624 /* slow path */ 1625 struct bxe_dma sp_dma; 1626 struct bxe_slowpath *sp; 1627 unsigned long sp_state; 1628 1629 /* slow path queue */ 1630 struct bxe_dma spq_dma; 1631 struct eth_spe *spq; 1632#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1633#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1634#define MAX_SPQ_PENDING 8 1635 1636 uint16_t spq_prod_idx; 1637 struct eth_spe *spq_prod_bd; 1638 struct eth_spe *spq_last_bd; 1639 uint16_t *dsb_sp_prod; 1640 //uint16_t *spq_hw_con; 1641 //uint16_t spq_left; 1642 1643 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1644 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1645 1646 /* fw decompression buffer */ 1647 struct bxe_dma gz_buf_dma; 1648 void *gz_buf; 1649 z_streamp gz_strm; 1650 uint32_t gz_outlen; 1651#define GUNZIP_BUF(sc) (sc->gz_buf) 1652#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1653#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1654#define FW_BUF_SIZE 0x40000 1655 1656 const struct raw_op *init_ops; 1657 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1658 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1659 uint32_t init_mode_flags; 1660#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1661 /* PRAM blobs - raw data */ 1662 const uint8_t *tsem_int_table_data; 1663 const uint8_t *tsem_pram_data; 1664 const uint8_t *usem_int_table_data; 1665 const uint8_t *usem_pram_data; 1666 const uint8_t *xsem_int_table_data; 1667 const uint8_t *xsem_pram_data; 1668 const uint8_t *csem_int_table_data; 1669 const uint8_t *csem_pram_data; 1670#define INIT_OPS(sc) (sc->init_ops) 1671#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1672#define INIT_DATA(sc) (sc->init_data) 1673#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1674#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1675#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1676#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1677#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1678#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1679#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1680#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1681 1682 /* ILT 1683 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1684 * context size we need 8 ILT entries. 1685 */ 1686#define ILT_MAX_L2_LINES 8 1687 struct hw_context context[ILT_MAX_L2_LINES]; 1688 struct ecore_ilt *ilt; 1689#define ILT_MAX_LINES 256 1690 1691/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1692#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1693/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1694#if 1 1695#define BXE_L2_MAX_CID(sc) \ 1696 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1697#else 1698#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1699 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1700#endif 1701#if 1 1702#define BXE_L2_CID_COUNT(sc) \ 1703 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1704#else 1705#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1706 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1707#endif 1708#define L2_ILT_LINES(sc) \ 1709 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1710 1711 int qm_cid_count; 1712 1713 uint8_t dropless_fc; 1714 1715 /* total number of FW statistics requests */ 1716 uint8_t fw_stats_num; 1717 /* 1718 * This is a memory buffer that will contain both statistics ramrod 1719 * request and data. 1720 */ 1721 struct bxe_dma fw_stats_dma; 1722 /* 1723 * FW statistics request shortcut (points at the beginning of fw_stats 1724 * buffer). 1725 */ 1726 int fw_stats_req_size; 1727 struct bxe_fw_stats_req *fw_stats_req; 1728 bus_addr_t fw_stats_req_mapping; 1729 /* 1730 * FW statistics data shortcut (points at the beginning of fw_stats 1731 * buffer + fw_stats_req_size). 1732 */ 1733 int fw_stats_data_size; 1734 struct bxe_fw_stats_data *fw_stats_data; 1735 bus_addr_t fw_stats_data_mapping; 1736 1737 /* tracking a pending STAT_QUERY ramrod */ 1738 uint16_t stats_pending; 1739 /* number of completed statistics ramrods */ 1740 uint16_t stats_comp; 1741 uint16_t stats_counter; 1742 uint8_t stats_init; 1743 int stats_state; 1744 1745 struct bxe_eth_stats eth_stats; 1746 struct host_func_stats func_stats; 1747 struct bxe_eth_stats_old eth_stats_old; 1748 struct bxe_net_stats_old net_stats_old; 1749 struct bxe_fw_port_stats_old fw_stats_old; 1750 1751 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1752 int executer_idx; 1753 1754 int mtu; 1755 1756 /* LLDP params */ 1757 struct bxe_config_lldp_params lldp_config_params; 1758 /* DCB support on/off */ 1759 int dcb_state; 1760#define BXE_DCB_STATE_OFF 0 1761#define BXE_DCB_STATE_ON 1 1762 /* DCBX engine mode */ 1763 int dcbx_enabled; 1764#define BXE_DCBX_ENABLED_OFF 0 1765#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1766#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1767#define BXE_DCBX_ENABLED_INVALID -1 1768 uint8_t dcbx_mode_uset; 1769 struct bxe_config_dcbx_params dcbx_config_params; 1770 struct bxe_dcbx_port_params dcbx_port_params; 1771 int dcb_version; 1772 1773 uint8_t cnic_support; 1774 uint8_t cnic_enabled; 1775 uint8_t cnic_loaded; 1776#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1777#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1778#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1779 1780 /* multiple tx classes of service */ 1781 uint8_t max_cos; 1782#define BXE_MAX_PRIORITY 8 1783 /* priority to cos mapping */ 1784 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1785 1786 int panic; 1787 1788 struct cdev *ioctl_dev; 1789 1790 void *grc_dump; 1791 unsigned int trigger_grcdump; 1792 unsigned int grcdump_done; 1793 unsigned int grcdump_started; 1794 1795 void *eeprom; 1796}; /* struct bxe_softc */ 1797 1798/* IOCTL sub-commands for edebug and firmware upgrade */ 1799#define BXE_IOC_RD_NVRAM 1 1800#define BXE_IOC_WR_NVRAM 2 1801#define BXE_IOC_STATS_SHOW_NUM 3 1802#define BXE_IOC_STATS_SHOW_STR 4 1803#define BXE_IOC_STATS_SHOW_CNT 5 1804 1805struct bxe_nvram_data { 1806 uint32_t op; /* ioctl sub-command */ 1807 uint32_t offset; 1808 uint32_t len; 1809 uint32_t value[1]; /* variable */ 1810}; 1811 1812union bxe_stats_show_data { 1813 uint32_t op; /* ioctl sub-command */ 1814 1815 struct { 1816 uint32_t num; /* return number of stats */ 1817 uint32_t len; /* length of each string item */ 1818 } desc; 1819 1820 /* variable length... */ 1821 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1822 1823 /* variable length... */ 1824 uint64_t stats[1]; /* holds all stats */ 1825}; 1826 1827/* function init flags */ 1828#define FUNC_FLG_RSS 0x0001 1829#define FUNC_FLG_STATS 0x0002 1830/* FUNC_FLG_UNMATCHED 0x0004 */ 1831#define FUNC_FLG_TPA 0x0008 1832#define FUNC_FLG_SPQ 0x0010 1833#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1834 1835struct bxe_func_init_params { 1836 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1837 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1838 uint16_t func_flgs; 1839 uint16_t func_id; /* abs function id */ 1840 uint16_t pf_id; 1841 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1842}; 1843 1844/* memory resources reside at BARs 0, 2, 4 */ 1845/* Run `pciconf -lb` to see mappings */ 1846#define BAR0 0 1847#define BAR1 2 1848#define BAR2 4 1849 1850#ifdef BXE_REG_NO_INLINE 1851 1852uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1853uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1854uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1855 1856void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1857void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1858void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1859 1860#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1861#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1862#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1863 1864#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1865#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1866#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1867 1868#else /* not BXE_REG_NO_INLINE */ 1869 1870#define REG_WR8(sc, offset, val) \ 1871 bus_space_write_1(sc->bar[BAR0].tag, \ 1872 sc->bar[BAR0].handle, \ 1873 offset, val) 1874 1875#define REG_WR16(sc, offset, val) \ 1876 bus_space_write_2(sc->bar[BAR0].tag, \ 1877 sc->bar[BAR0].handle, \ 1878 offset, val) 1879 1880#define REG_WR32(sc, offset, val) \ 1881 bus_space_write_4(sc->bar[BAR0].tag, \ 1882 sc->bar[BAR0].handle, \ 1883 offset, val) 1884 1885#define REG_RD8(sc, offset) \ 1886 bus_space_read_1(sc->bar[BAR0].tag, \ 1887 sc->bar[BAR0].handle, \ 1888 offset) 1889 1890#define REG_RD16(sc, offset) \ 1891 bus_space_read_2(sc->bar[BAR0].tag, \ 1892 sc->bar[BAR0].handle, \ 1893 offset) 1894 1895#define REG_RD32(sc, offset) \ 1896 bus_space_read_4(sc->bar[BAR0].tag, \ 1897 sc->bar[BAR0].handle, \ 1898 offset) 1899 1900#endif /* BXE_REG_NO_INLINE */ 1901 1902#define REG_RD(sc, offset) REG_RD32(sc, offset) 1903#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1904 1905#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1906#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1907 1908#define BXE_SP(sc, var) (&(sc)->sp->var) 1909#define BXE_SP_MAPPING(sc, var) \ 1910 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1911 1912#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1913#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1914 1915#define REG_RD_DMAE(sc, offset, valp, len32) \ 1916 do { \ 1917 bxe_read_dmae(sc, offset, len32); \ 1918 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1919 } while (0) 1920 1921#define REG_WR_DMAE(sc, offset, valp, len32) \ 1922 do { \ 1923 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1924 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1925 } while (0) 1926 1927#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1928 REG_WR_DMAE(sc, offset, valp, len32) 1929 1930#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1931 REG_RD_DMAE(sc, offset, valp, len32) 1932 1933#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1934 do { \ 1935 /* if (le32_swap) { */ \ 1936 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1937 /* } */ \ 1938 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1939 ecore_write_big_buf_wb(sc, addr, len32); \ 1940 } while (0) 1941 1942#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1943#define BXE_DB_SHIFT 7 /* 128 bytes */ 1944#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1945#error "Minimum DB doorbell stride is 8" 1946#endif 1947#define DPM_TRIGGER_TYPE 0x40 1948#define DOORBELL(sc, cid, val) \ 1949 do { \ 1950 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1951 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1952 (uint32_t)val); \ 1953 } while(0) 1954 1955#define SHMEM_ADDR(sc, field) \ 1956 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1957#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1958#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1959#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1960 1961#define SHMEM2_ADDR(sc, field) \ 1962 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1963#define SHMEM2_HAS(sc, field) \ 1964 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1965 offsetof(struct shmem2_region, field))) 1966#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1967#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1968 1969#define MFCFG_ADDR(sc, field) \ 1970 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1971#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1972#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1973#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1974 1975/* DMAE command defines */ 1976 1977#define DMAE_TIMEOUT -1 1978#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1979#define DMAE_NOT_RDY -3 1980#define DMAE_PCI_ERR_FLAG 0x80000000 1981 1982#define DMAE_SRC_PCI 0 1983#define DMAE_SRC_GRC 1 1984 1985#define DMAE_DST_NONE 0 1986#define DMAE_DST_PCI 1 1987#define DMAE_DST_GRC 2 1988 1989#define DMAE_COMP_PCI 0 1990#define DMAE_COMP_GRC 1 1991 1992#define DMAE_COMP_REGULAR 0 1993#define DMAE_COM_SET_ERR 1 1994 1995#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 1996#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 1997#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 1998#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 1999 2000#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 2001#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 2002 2003#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 2004#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 2005#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 2006#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 2007 2008#define DMAE_CMD_PORT_0 0 2009#define DMAE_CMD_PORT_1 DMAE_CMD_PORT 2010 2011#define DMAE_SRC_PF 0 2012#define DMAE_SRC_VF 1 2013 2014#define DMAE_DST_PF 0 2015#define DMAE_DST_VF 1 2016 2017#define DMAE_C_SRC 0 2018#define DMAE_C_DST 1 2019 2020#define DMAE_LEN32_RD_MAX 0x80 2021#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2022 2023#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2024 2025#define MAX_DMAE_C_PER_PORT 8 2026#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2027#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2028 2029static const uint32_t dmae_reg_go_c[] = { 2030 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2031 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2032 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2033 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2034}; 2035 2036#define ATTN_NIG_FOR_FUNC (1L << 8) 2037#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2038#define GPIO_2_FUNC (1L << 10) 2039#define GPIO_3_FUNC (1L << 11) 2040#define GPIO_4_FUNC (1L << 12) 2041#define ATTN_GENERAL_ATTN_1 (1L << 13) 2042#define ATTN_GENERAL_ATTN_2 (1L << 14) 2043#define ATTN_GENERAL_ATTN_3 (1L << 15) 2044#define ATTN_GENERAL_ATTN_4 (1L << 13) 2045#define ATTN_GENERAL_ATTN_5 (1L << 14) 2046#define ATTN_GENERAL_ATTN_6 (1L << 15) 2047#define ATTN_HARD_WIRED_MASK 0xff00 2048#define ATTENTION_ID 4 2049 2050#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2051 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2052 2053#define MAX_IGU_ATTN_ACK_TO 100 2054 2055#define STORM_ASSERT_ARRAY_SIZE 50 2056 2057#define BXE_PMF_LINK_ASSERT(sc) \ 2058 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2059 2060#define BXE_MC_ASSERT_BITS \ 2061 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2062 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2063 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2064 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2065 2066#define BXE_MCP_ASSERT \ 2067 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2068 2069#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2070#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2071 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2072 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2073 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2074 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2075 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2076 2077#define MULTI_MASK 0x7f 2078 2079#define PFS_PER_PORT(sc) \ 2080 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2081#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2082 2083#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2084 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2085 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2086 2087#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2088 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2089 (i) < MAX_FUNC_NUM; \ 2090 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2091 2092#define BXE_SWCID_SHIFT 17 2093#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2094 2095#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2096#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2097 2098#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2099#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2100#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2101#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2102#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2103 2104/* must be used on a CID before placing it on a HW ring */ 2105#define HW_CID(sc, x) \ 2106 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2107 2108#define SPEED_10 10 2109#define SPEED_100 100 2110#define SPEED_1000 1000 2111#define SPEED_2500 2500 2112#define SPEED_10000 10000 2113 2114#define PCI_PM_D0 1 2115#define PCI_PM_D3hot 2 2116 2117#ifndef DUPLEX_UNKNOWN 2118#define DUPLEX_UNKNOWN (0xff) 2119#endif 2120 2121#ifndef SPEED_UNKNOWN 2122#define SPEED_UNKNOWN (-1) 2123#endif 2124 2125/* Enable or disable autonegotiation. */ 2126#define AUTONEG_DISABLE 0x00 2127#define AUTONEG_ENABLE 0x01 2128 2129/* Which connector port. */ 2130#define PORT_TP 0x00 2131#define PORT_AUI 0x01 2132#define PORT_MII 0x02 2133#define PORT_FIBRE 0x03 2134#define PORT_BNC 0x04 2135#define PORT_DA 0x05 2136#define PORT_NONE 0xef 2137#define PORT_OTHER 0xff 2138 2139int bxe_test_bit(int nr, volatile unsigned long * addr); 2140void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2141void bxe_clear_bit(int nr, volatile unsigned long * addr); 2142int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2143int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2144int bxe_cmpxchg(volatile int *addr, int old, int new); 2145 2146void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2147 uint32_t val); 2148uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2149 2150 2151int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2152 struct bxe_dma *dma, const char *msg); 2153void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2154 2155uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2156uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2157uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2158 uint8_t dst_type, uint8_t with_comp, 2159 uint8_t comp_type); 2160void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2161void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2162void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2163 uint32_t dst_addr, uint32_t len32); 2164void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2165 uint32_t addr, uint32_t len); 2166 2167void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2168 uint32_t cid); 2169void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2170 uint8_t sb_index, uint8_t disable, 2171 uint16_t usec); 2172 2173int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2174 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2175 2176void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2177 uint8_t segment, uint16_t index, uint8_t op, 2178 uint8_t update); 2179 2180void ecore_init_e1_firmware(struct bxe_softc *sc); 2181void ecore_init_e1h_firmware(struct bxe_softc *sc); 2182void ecore_init_e2_firmware(struct bxe_softc *sc); 2183 2184void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2185 size_t size, uint32_t *data); 2186 2187/*********************/ 2188/* LOGGING AND DEBUG */ 2189/*********************/ 2190 2191/* debug logging codepaths */ 2192#define DBG_LOAD 0x00000001 /* load and unload */ 2193#define DBG_INTR 0x00000002 /* interrupt handling */ 2194#define DBG_SP 0x00000004 /* slowpath handling */ 2195#define DBG_STATS 0x00000008 /* stats updates */ 2196#define DBG_TX 0x00000010 /* packet transmit */ 2197#define DBG_RX 0x00000020 /* packet receive */ 2198#define DBG_PHY 0x00000040 /* phy/link handling */ 2199#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2200#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2201#define DBG_REGS 0x00000200 /* register access */ 2202#define DBG_LRO 0x00000400 /* lro processing */ 2203#define DBG_ASSERT 0x80000000 /* debug assert */ 2204#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2205 2206#define DBASSERT(sc, exp, msg) \ 2207 do { \ 2208 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2209 if (__predict_false(!(exp))) { \ 2210 panic msg; \ 2211 } \ 2212 } \ 2213 } while (0) 2214 2215/* log a debug message */ 2216#define BLOGD(sc, codepath, format, args...) \ 2217 do { \ 2218 if (__predict_false(sc->debug & (codepath))) { \ 2219 device_printf((sc)->dev, \ 2220 "%s(%s:%d) " format, \ 2221 __FUNCTION__, \ 2222 __FILE__, \ 2223 __LINE__, \ 2224 ## args); \ 2225 } \ 2226 } while(0) 2227 2228/* log a info message */ 2229#define BLOGI(sc, format, args...) \ 2230 do { \ 2231 if (__predict_false(sc->debug)) { \ 2232 device_printf((sc)->dev, \ 2233 "%s(%s:%d) " format, \ 2234 __FUNCTION__, \ 2235 __FILE__, \ 2236 __LINE__, \ 2237 ## args); \ 2238 } else { \ 2239 device_printf((sc)->dev, \ 2240 format, \ 2241 ## args); \ 2242 } \ 2243 } while(0) 2244 2245/* log a warning message */ 2246#define BLOGW(sc, format, args...) \ 2247 do { \ 2248 if (__predict_false(sc->debug)) { \ 2249 device_printf((sc)->dev, \ 2250 "%s(%s:%d) WARNING: " format, \ 2251 __FUNCTION__, \ 2252 __FILE__, \ 2253 __LINE__, \ 2254 ## args); \ 2255 } else { \ 2256 device_printf((sc)->dev, \ 2257 "WARNING: " format, \ 2258 ## args); \ 2259 } \ 2260 } while(0) 2261 2262/* log a error message */ 2263#define BLOGE(sc, format, args...) \ 2264 do { \ 2265 if (__predict_false(sc->debug)) { \ 2266 device_printf((sc)->dev, \ 2267 "%s(%s:%d) ERROR: " format, \ 2268 __FUNCTION__, \ 2269 __FILE__, \ 2270 __LINE__, \ 2271 ## args); \ 2272 } else { \ 2273 device_printf((sc)->dev, \ 2274 "ERROR: " format, \ 2275 ## args); \ 2276 } \ 2277 } while(0) 2278 2279#ifdef ECORE_STOP_ON_ERROR 2280 2281#define bxe_panic(sc, msg) \ 2282 do { \ 2283 panic msg; \ 2284 } while (0) 2285 2286#else 2287 2288#define bxe_panic(sc, msg) \ 2289 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2290 2291#endif 2292 2293#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2294#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2295 2296void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2297 uint8_t *mem, uint32_t len); 2298void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2299 struct mbuf *m, uint8_t contents); 2300extern int bxe_grc_dump(struct bxe_softc *sc); 2301 2302#if __FreeBSD_version >= 800000 2303#if __FreeBSD_version >= 1000000 2304#define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2305#define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2306#else 2307#define BXE_VALID_FLOWID(m) ((m->m_flags & M_FLOWID) != 0) 2308#define BXE_SET_FLOWID(m) m->m_flags |= M_FLOWID 2309#endif 2310#endif /* #if __FreeBSD_version >= 800000 */ 2311 2312/***********/ 2313/* INLINES */ 2314/***********/ 2315 2316static inline uint32_t 2317reg_poll(struct bxe_softc *sc, 2318 uint32_t reg, 2319 uint32_t expected, 2320 int ms, 2321 int wait) 2322{ 2323 uint32_t val; 2324 2325 do { 2326 val = REG_RD(sc, reg); 2327 if (val == expected) { 2328 break; 2329 } 2330 ms -= wait; 2331 DELAY(wait * 1000); 2332 } while (ms > 0); 2333 2334 return (val); 2335} 2336 2337static inline void 2338bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2339{ 2340 mb(); /* status block is written to by the chip */ 2341 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2342} 2343 2344static inline void 2345bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2346 uint8_t igu_sb_id, 2347 uint8_t segment, 2348 uint16_t index, 2349 uint8_t op, 2350 uint8_t update, 2351 uint32_t igu_addr) 2352{ 2353 struct igu_regular cmd_data = {0}; 2354 2355 cmd_data.sb_id_and_flags = 2356 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2357 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2358 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2359 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2360 2361 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2362 cmd_data.sb_id_and_flags, igu_addr); 2363 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2364 2365 /* Make sure that ACK is written */ 2366 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2367 BUS_SPACE_BARRIER_WRITE); 2368 mb(); 2369} 2370 2371static inline void 2372bxe_hc_ack_sb(struct bxe_softc *sc, 2373 uint8_t sb_id, 2374 uint8_t storm, 2375 uint16_t index, 2376 uint8_t op, 2377 uint8_t update) 2378{ 2379 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2380 COMMAND_REG_INT_ACK); 2381 struct igu_ack_register igu_ack; 2382 2383 igu_ack.status_block_index = index; 2384 igu_ack.sb_id_and_flags = 2385 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2386 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2387 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2388 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2389 2390 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2391 2392 /* Make sure that ACK is written */ 2393 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2394 BUS_SPACE_BARRIER_WRITE); 2395 mb(); 2396} 2397 2398static inline void 2399bxe_ack_sb(struct bxe_softc *sc, 2400 uint8_t igu_sb_id, 2401 uint8_t storm, 2402 uint16_t index, 2403 uint8_t op, 2404 uint8_t update) 2405{ 2406 if (sc->devinfo.int_block == INT_BLOCK_HC) 2407 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2408 else { 2409 uint8_t segment; 2410 if (CHIP_INT_MODE_IS_BC(sc)) { 2411 segment = storm; 2412 } else if (igu_sb_id != sc->igu_dsb_id) { 2413 segment = IGU_SEG_ACCESS_DEF; 2414 } else if (storm == ATTENTION_ID) { 2415 segment = IGU_SEG_ACCESS_ATTN; 2416 } else { 2417 segment = IGU_SEG_ACCESS_DEF; 2418 } 2419 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2420 } 2421} 2422 2423static inline uint16_t 2424bxe_hc_ack_int(struct bxe_softc *sc) 2425{ 2426 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2427 COMMAND_REG_SIMD_MASK); 2428 uint32_t result = REG_RD(sc, hc_addr); 2429 2430 mb(); 2431 return (result); 2432} 2433 2434static inline uint16_t 2435bxe_igu_ack_int(struct bxe_softc *sc) 2436{ 2437 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2438 uint32_t result = REG_RD(sc, igu_addr); 2439 2440 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2441 result, igu_addr); 2442 2443 mb(); 2444 return (result); 2445} 2446 2447static inline uint16_t 2448bxe_ack_int(struct bxe_softc *sc) 2449{ 2450 mb(); 2451 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2452 return (bxe_hc_ack_int(sc)); 2453 } else { 2454 return (bxe_igu_ack_int(sc)); 2455 } 2456} 2457 2458static inline int 2459func_by_vn(struct bxe_softc *sc, 2460 int vn) 2461{ 2462 return (2 * vn + SC_PORT(sc)); 2463} 2464 2465/* 2466 * Statistics ID are global per chip/path, while Client IDs for E1x 2467 * are per port. 2468 */ 2469static inline uint8_t 2470bxe_stats_id(struct bxe_fastpath *fp) 2471{ 2472 struct bxe_softc *sc = fp->sc; 2473 2474 if (!CHIP_IS_E1x(sc)) { 2475 return (fp->cl_id); 2476 } 2477 2478 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2479} 2480 2481#endif /* __BXE_H__ */ 2482 2483