bxe.h revision 258187
1255736Sdavidch/*- 2255736Sdavidch * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3255736Sdavidch * 4255736Sdavidch * Eric Davis <edavis@broadcom.com> 5255736Sdavidch * David Christensen <davidch@broadcom.com> 6255736Sdavidch * Gary Zambrano <zambrano@broadcom.com> 7255736Sdavidch * 8255736Sdavidch * Redistribution and use in source and binary forms, with or without 9255736Sdavidch * modification, are permitted provided that the following conditions 10255736Sdavidch * are met: 11255736Sdavidch * 12255736Sdavidch * 1. Redistributions of source code must retain the above copyright 13255736Sdavidch * notice, this list of conditions and the following disclaimer. 14255736Sdavidch * 2. Redistributions in binary form must reproduce the above copyright 15255736Sdavidch * notice, this list of conditions and the following disclaimer in the 16255736Sdavidch * documentation and/or other materials provided with the distribution. 17255736Sdavidch * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18255736Sdavidch * may be used to endorse or promote products derived from this software 19255736Sdavidch * without specific prior written consent. 20255736Sdavidch * 21255736Sdavidch * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22255736Sdavidch * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23255736Sdavidch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24255736Sdavidch * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25255736Sdavidch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26255736Sdavidch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27255736Sdavidch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28255736Sdavidch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29255736Sdavidch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30255736Sdavidch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31255736Sdavidch * THE POSSIBILITY OF SUCH DAMAGE. 32255736Sdavidch */ 33255736Sdavidch 34255736Sdavidch#ifndef __BXE_H__ 35255736Sdavidch#define __BXE_H__ 36255736Sdavidch 37255736Sdavidch#include <sys/cdefs.h> 38255736Sdavidch__FBSDID("$FreeBSD: head/sys/dev/bxe/bxe.h 258187 2013-11-15 20:26:14Z edavis $"); 39255736Sdavidch 40255736Sdavidch#include <sys/param.h> 41255736Sdavidch#include <sys/kernel.h> 42255736Sdavidch#include <sys/systm.h> 43255736Sdavidch#include <sys/lock.h> 44255736Sdavidch#include <sys/mutex.h> 45255736Sdavidch#include <sys/sx.h> 46255736Sdavidch#include <sys/module.h> 47255736Sdavidch#include <sys/endian.h> 48255736Sdavidch#include <sys/types.h> 49255736Sdavidch#include <sys/malloc.h> 50255736Sdavidch#include <sys/kobj.h> 51255736Sdavidch#include <sys/bus.h> 52255736Sdavidch#include <sys/rman.h> 53255736Sdavidch#include <sys/socket.h> 54255736Sdavidch#include <sys/sockio.h> 55255736Sdavidch#include <sys/sysctl.h> 56255736Sdavidch#include <sys/smp.h> 57255736Sdavidch#include <sys/bitstring.h> 58255736Sdavidch#include <sys/limits.h> 59255736Sdavidch#include <sys/queue.h> 60255736Sdavidch#include <sys/taskqueue.h> 61255736Sdavidch 62255736Sdavidch#include <net/if.h> 63255736Sdavidch#include <net/if_types.h> 64255736Sdavidch#include <net/if_arp.h> 65255736Sdavidch#include <net/ethernet.h> 66255736Sdavidch#include <net/if_dl.h> 67255736Sdavidch#include <net/if_media.h> 68255736Sdavidch#include <net/if_var.h> 69255736Sdavidch#include <net/if_vlan_var.h> 70255736Sdavidch#include <net/zlib.h> 71255736Sdavidch#include <net/bpf.h> 72255736Sdavidch 73255736Sdavidch#include <netinet/in.h> 74255736Sdavidch#include <netinet/ip.h> 75255736Sdavidch#include <netinet/ip6.h> 76255736Sdavidch#include <netinet/tcp.h> 77255736Sdavidch#include <netinet/udp.h> 78255736Sdavidch 79255736Sdavidch#include <dev/pci/pcireg.h> 80255736Sdavidch#include <dev/pci/pcivar.h> 81255736Sdavidch 82255736Sdavidch#include <machine/atomic.h> 83255736Sdavidch#include <machine/resource.h> 84255736Sdavidch#include <machine/endian.h> 85255736Sdavidch#include <machine/bus.h> 86255736Sdavidch#include <machine/in_cksum.h> 87255736Sdavidch 88255736Sdavidch#include "device_if.h" 89255736Sdavidch#include "bus_if.h" 90255736Sdavidch#include "pci_if.h" 91255736Sdavidch 92255736Sdavidch#if _BYTE_ORDER == _LITTLE_ENDIAN 93255736Sdavidch#ifndef LITTLE_ENDIAN 94255736Sdavidch#define LITTLE_ENDIAN 95255736Sdavidch#endif 96255736Sdavidch#ifndef __LITTLE_ENDIAN 97255736Sdavidch#define __LITTLE_ENDIAN 98255736Sdavidch#endif 99255736Sdavidch#undef BIG_ENDIAN 100255736Sdavidch#undef __BIG_ENDIAN 101255736Sdavidch#else /* _BIG_ENDIAN */ 102255736Sdavidch#ifndef BIG_ENDIAN 103255736Sdavidch#define BIG_ENDIAN 104255736Sdavidch#endif 105255736Sdavidch#ifndef __BIG_ENDIAN 106255736Sdavidch#define __BIG_ENDIAN 107255736Sdavidch#endif 108255736Sdavidch#undef LITTLE_ENDIAN 109255736Sdavidch#undef __LITTLE_ENDIAN 110255736Sdavidch#endif 111255736Sdavidch 112255736Sdavidch#include "ecore_mfw_req.h" 113255736Sdavidch#include "ecore_fw_defs.h" 114255736Sdavidch#include "ecore_hsi.h" 115255736Sdavidch#include "ecore_reg.h" 116255736Sdavidch#include "bxe_dcb.h" 117255736Sdavidch#include "bxe_stats.h" 118255736Sdavidch 119255736Sdavidch#include "bxe_elink.h" 120255736Sdavidch 121255736Sdavidch#if __FreeBSD_version < 800054 122255736Sdavidch#if defined(__i386__) || defined(__amd64__) 123255736Sdavidch#define mb() __asm volatile("mfence;" : : : "memory") 124255736Sdavidch#define wmb() __asm volatile("sfence;" : : : "memory") 125255736Sdavidch#define rmb() __asm volatile("lfence;" : : : "memory") 126255736Sdavidchstatic __inline void prefetch(void *x) 127255736Sdavidch{ 128255736Sdavidch __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 129255736Sdavidch} 130255736Sdavidch#else 131255736Sdavidch#define mb() 132255736Sdavidch#define rmb() 133255736Sdavidch#define wmb() 134255736Sdavidch#define prefetch(x) 135255736Sdavidch#endif 136255736Sdavidch#endif 137255736Sdavidch 138255736Sdavidch#if __FreeBSD_version >= 1000000 139255736Sdavidch#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 140255736Sdavidch#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 141255736Sdavidch#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 142255736Sdavidch#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 143255736Sdavidch#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 144255736Sdavidch#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 145255736Sdavidch#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 146255736Sdavidch#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 147255736Sdavidch#endif 148255736Sdavidch 149255736Sdavidch#ifndef ARRAY_SIZE 150255736Sdavidch#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 151255736Sdavidch#endif 152255736Sdavidch#ifndef ARRSIZE 153255736Sdavidch#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 154255736Sdavidch#endif 155255736Sdavidch#ifndef DIV_ROUND_UP 156255736Sdavidch#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 157255736Sdavidch#endif 158255736Sdavidch#ifndef roundup 159255736Sdavidch#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 160255736Sdavidch#endif 161255736Sdavidch#ifndef ilog2 162255736Sdavidchstatic inline 163255736Sdavidchint bxe_ilog2(int x) 164255736Sdavidch{ 165255736Sdavidch int log = 0; 166255736Sdavidch while (x >>= 1) log++; 167255736Sdavidch return (log); 168255736Sdavidch} 169255736Sdavidch#define ilog2(x) bxe_ilog2(x) 170255736Sdavidch#endif 171255736Sdavidch 172255736Sdavidch#include "ecore_sp.h" 173255736Sdavidch 174255736Sdavidch#define BRCM_VENDORID 0x14e4 175255736Sdavidch#define PCI_ANY_ID (uint16_t)(~0U) 176255736Sdavidch 177255736Sdavidchstruct bxe_device_type 178255736Sdavidch{ 179255736Sdavidch uint16_t bxe_vid; 180255736Sdavidch uint16_t bxe_did; 181255736Sdavidch uint16_t bxe_svid; 182255736Sdavidch uint16_t bxe_sdid; 183255736Sdavidch char *bxe_name; 184255736Sdavidch}; 185255736Sdavidch 186255736Sdavidch#define BCM_PAGE_SHIFT 12 187255736Sdavidch#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 188255736Sdavidch#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 189255736Sdavidch#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 190255736Sdavidch 191255736Sdavidch#if BCM_PAGE_SIZE != 4096 192255736Sdavidch#error Page sizes other than 4KB are unsupported! 193255736Sdavidch#endif 194255736Sdavidch 195255736Sdavidch#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 196255736Sdavidch#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 197255736Sdavidch#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 198255736Sdavidch#else 199255736Sdavidch#define U64_LO(addr) ((uint32_t)(addr)) 200255736Sdavidch#define U64_HI(addr) (0) 201255736Sdavidch#endif 202255736Sdavidch#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 203255736Sdavidch 204255736Sdavidch#define SET_FLAG(value, mask, flag) \ 205255736Sdavidch do { \ 206255736Sdavidch (value) &= ~(mask); \ 207255736Sdavidch (value) |= ((flag) << (mask##_SHIFT)); \ 208255736Sdavidch } while (0) 209255736Sdavidch 210255736Sdavidch#define GET_FLAG(value, mask) \ 211255736Sdavidch (((value) & (mask)) >> (mask##_SHIFT)) 212255736Sdavidch 213255736Sdavidch#define GET_FIELD(value, fname) \ 214255736Sdavidch (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 215255736Sdavidch 216255736Sdavidch#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 217255736Sdavidch#define BXE_TSO_MAX_SEGMENTS 32 218255736Sdavidch#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 219255736Sdavidch#define BXE_TSO_MAX_SEG_SIZE 4096 220255736Sdavidch 221255736Sdavidch/* dropless fc FW/HW related params */ 222255736Sdavidch#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 223255736Sdavidch#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 224255736Sdavidch ETH_MAX_AGGREGATION_QUEUES_E1 : \ 225255736Sdavidch ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 226255736Sdavidch#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 227255736Sdavidch#define FW_PREFETCH_CNT 16 228255736Sdavidch#define DROPLESS_FC_HEADROOM 100 229255736Sdavidch 230255736Sdavidch/******************/ 231255736Sdavidch/* RX SGE defines */ 232255736Sdavidch/******************/ 233255736Sdavidch 234255736Sdavidch#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 235255736Sdavidch#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 236255736Sdavidch#define RX_SGE_NEXT_PAGE_DESC_CNT 2 237255736Sdavidch#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 238255736Sdavidch#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 239255736Sdavidch#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 240255736Sdavidch#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 241255736Sdavidch#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 242255736Sdavidch#define RX_SGE(x) ((x) & RX_SGE_MAX) 243255736Sdavidch 244255736Sdavidch#define RX_SGE_NEXT(x) \ 245255736Sdavidch ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 246255736Sdavidch ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 247255736Sdavidch 248255736Sdavidch#define RX_SGE_MASK_ELEM_SZ 64 249255736Sdavidch#define RX_SGE_MASK_ELEM_SHIFT 6 250255736Sdavidch#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 251255736Sdavidch 252255736Sdavidch/* 253255736Sdavidch * Creates a bitmask of all ones in less significant bits. 254255736Sdavidch * idx - index of the most significant bit in the created mask. 255255736Sdavidch */ 256255736Sdavidch#define RX_SGE_ONES_MASK(idx) \ 257255736Sdavidch (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 258255736Sdavidch#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 259255736Sdavidch 260255736Sdavidch/* Number of uint64_t elements in SGE mask array. */ 261255736Sdavidch#define RX_SGE_MASK_LEN \ 262255736Sdavidch ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 263255736Sdavidch#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 264255736Sdavidch#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 265255736Sdavidch 266255736Sdavidch/* 267255736Sdavidch * dropless fc calculations for SGEs 268255736Sdavidch * Number of required SGEs is the sum of two: 269255736Sdavidch * 1. Number of possible opened aggregations (next packet for 270255736Sdavidch * these aggregations will probably consume SGE immidiatelly) 271255736Sdavidch * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 272255736Sdavidch * after placement on BD for new TPA aggregation) 273255736Sdavidch * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 274255736Sdavidch */ 275255736Sdavidch#define NUM_SGE_REQ(sc) \ 276255736Sdavidch (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 277255736Sdavidch#define NUM_SGE_PG_REQ(sc) \ 278255736Sdavidch ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 279255736Sdavidch#define SGE_TH_LO(sc) \ 280255736Sdavidch (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 281255736Sdavidch#define SGE_TH_HI(sc) \ 282255736Sdavidch (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 283255736Sdavidch 284255736Sdavidch#define PAGES_PER_SGE_SHIFT 0 285255736Sdavidch#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 286255736Sdavidch#define SGE_PAGE_SIZE BCM_PAGE_SIZE 287255736Sdavidch#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 288255736Sdavidch#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 289255736Sdavidch#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 290255736Sdavidch#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 291255736Sdavidch 292255736Sdavidch/*****************/ 293255736Sdavidch/* TX BD defines */ 294255736Sdavidch/*****************/ 295255736Sdavidch 296255736Sdavidch#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 297255736Sdavidch#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 298255736Sdavidch#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 299255736Sdavidch#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 300255736Sdavidch#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 301255736Sdavidch#define TX_BD_MAX (TX_BD_TOTAL - 1) 302255736Sdavidch 303255736Sdavidch#define TX_BD_NEXT(x) \ 304255736Sdavidch ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 305255736Sdavidch ((x) + 2) : ((x) + 1)) 306255736Sdavidch#define TX_BD(x) ((x) & TX_BD_MAX) 307255736Sdavidch#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 308255736Sdavidch#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 309255736Sdavidch 310255736Sdavidch/* 311255736Sdavidch * Trigger pending transmits when the number of available BDs is greater 312255736Sdavidch * than 1/8 of the total number of usable BDs. 313255736Sdavidch */ 314255736Sdavidch#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 315255736Sdavidch#define BXE_TX_TIMEOUT 5 316255736Sdavidch 317255736Sdavidch/*****************/ 318255736Sdavidch/* RX BD defines */ 319255736Sdavidch/*****************/ 320255736Sdavidch 321255736Sdavidch#define RX_BD_NUM_PAGES 8 /* power of 2 */ 322255736Sdavidch#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 323255736Sdavidch#define RX_BD_NEXT_PAGE_DESC_CNT 2 324255736Sdavidch#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 325255736Sdavidch#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 326255736Sdavidch#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 327255736Sdavidch#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 328255736Sdavidch#define RX_BD_MAX (RX_BD_TOTAL - 1) 329255736Sdavidch 330255736Sdavidch#if 0 331255736Sdavidch#define NUM_RX_RINGS RX_BD_NUM_PAGES 332255736Sdavidch#define NUM_RX_BD RX_BD_TOTAL 333255736Sdavidch#define MAX_RX_BD RX_BD_MAX 334255736Sdavidch#define MAX_RX_AVAIL RX_BD_USABLE 335255736Sdavidch#endif 336255736Sdavidch 337255736Sdavidch#define RX_BD_NEXT(x) \ 338255736Sdavidch ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 339255736Sdavidch ((x) + 3) : ((x) + 1)) 340255736Sdavidch#define RX_BD(x) ((x) & RX_BD_MAX) 341255736Sdavidch#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 342255736Sdavidch#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 343255736Sdavidch 344255736Sdavidch/* 345255736Sdavidch * dropless fc calculations for BDs 346255736Sdavidch * Number of BDs should be as number of buffers in BRB: 347255736Sdavidch * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 348255736Sdavidch * "next" elements on each page 349255736Sdavidch */ 350255736Sdavidch#define NUM_BD_REQ(sc) \ 351255736Sdavidch BRB_SIZE(sc) 352255736Sdavidch#define NUM_BD_PG_REQ(sc) \ 353255736Sdavidch ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 354255736Sdavidch#define BD_TH_LO(sc) \ 355255736Sdavidch (NUM_BD_REQ(sc) + \ 356255736Sdavidch NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 357255736Sdavidch FW_DROP_LEVEL(sc)) 358255736Sdavidch#define BD_TH_HI(sc) \ 359255736Sdavidch (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 360255736Sdavidch#define MIN_RX_AVAIL(sc) \ 361255736Sdavidch ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 362255736Sdavidch#define MIN_RX_SIZE_TPA_HW(sc) \ 363255736Sdavidch (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 364255736Sdavidch ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 365255736Sdavidch#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 366255736Sdavidch#define MIN_RX_SIZE_TPA(sc) \ 367255736Sdavidch (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 368255736Sdavidch#define MIN_RX_SIZE_NONTPA(sc) \ 369255736Sdavidch (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 370255736Sdavidch 371255736Sdavidch/***************/ 372255736Sdavidch/* RCQ defines */ 373255736Sdavidch/***************/ 374255736Sdavidch 375255736Sdavidch/* 376255736Sdavidch * As long as CQE is X times bigger than BD entry we have to allocate X times 377255736Sdavidch * more pages for CQ ring in order to keep it balanced with BD ring 378255736Sdavidch */ 379255736Sdavidch#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 380255736Sdavidch sizeof(struct eth_rx_bd)) 381255736Sdavidch#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 382255736Sdavidch#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 383255736Sdavidch#define RCQ_NEXT_PAGE_DESC_CNT 1 384255736Sdavidch#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 385255736Sdavidch#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 386255736Sdavidch#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 387255736Sdavidch#define RCQ_MAX (RCQ_TOTAL - 1) 388255736Sdavidch 389255736Sdavidch#define RCQ_NEXT(x) \ 390255736Sdavidch ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 391255736Sdavidch ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 392255736Sdavidch#define RCQ(x) ((x) & RCQ_MAX) 393255736Sdavidch#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 394255736Sdavidch#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 395255736Sdavidch 396255736Sdavidch#if 0 397255736Sdavidch#define NUM_RCQ_RINGS RCQ_NUM_PAGES 398255736Sdavidch#define NUM_RCQ_BD RCQ_TOTAL 399255736Sdavidch#define MAX_RCQ_BD RCQ_MAX 400255736Sdavidch#define MAX_RCQ_AVAIL RCQ_USABLE 401255736Sdavidch#endif 402255736Sdavidch 403255736Sdavidch/* 404255736Sdavidch * dropless fc calculations for RCQs 405255736Sdavidch * Number of RCQs should be as number of buffers in BRB: 406255736Sdavidch * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 407255736Sdavidch * "next" elements on each page 408255736Sdavidch */ 409255736Sdavidch#define NUM_RCQ_REQ(sc) \ 410255736Sdavidch BRB_SIZE(sc) 411255736Sdavidch#define NUM_RCQ_PG_REQ(sc) \ 412255736Sdavidch ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 413255736Sdavidch#define RCQ_TH_LO(sc) \ 414255736Sdavidch (NUM_RCQ_REQ(sc) + \ 415255736Sdavidch NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 416255736Sdavidch FW_DROP_LEVEL(sc)) 417255736Sdavidch#define RCQ_TH_HI(sc) \ 418255736Sdavidch (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 419255736Sdavidch 420255736Sdavidch/* This is needed for determening of last_max */ 421255736Sdavidch#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 422255736Sdavidch 423255736Sdavidch#define __SGE_MASK_SET_BIT(el, bit) \ 424255736Sdavidch do { \ 425255736Sdavidch (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 426255736Sdavidch } while (0) 427255736Sdavidch 428255736Sdavidch#define __SGE_MASK_CLEAR_BIT(el, bit) \ 429255736Sdavidch do { \ 430255736Sdavidch (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 431255736Sdavidch } while (0) 432255736Sdavidch 433255736Sdavidch#define SGE_MASK_SET_BIT(fp, idx) \ 434255736Sdavidch __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 435255736Sdavidch ((idx) & RX_SGE_MASK_ELEM_MASK)) 436255736Sdavidch 437255736Sdavidch#define SGE_MASK_CLEAR_BIT(fp, idx) \ 438255736Sdavidch __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 439255736Sdavidch ((idx) & RX_SGE_MASK_ELEM_MASK)) 440255736Sdavidch 441255736Sdavidch/* Load / Unload modes */ 442255736Sdavidch#define LOAD_NORMAL 0 443255736Sdavidch#define LOAD_OPEN 1 444255736Sdavidch#define LOAD_DIAG 2 445255736Sdavidch#define LOAD_LOOPBACK_EXT 3 446255736Sdavidch#define UNLOAD_NORMAL 0 447255736Sdavidch#define UNLOAD_CLOSE 1 448255736Sdavidch#define UNLOAD_RECOVERY 2 449255736Sdavidch 450255736Sdavidch/* Some constants... */ 451255736Sdavidch//#define MAX_PATH_NUM 2 452255736Sdavidch//#define E2_MAX_NUM_OF_VFS 64 453255736Sdavidch//#define E1H_FUNC_MAX 8 454255736Sdavidch//#define E2_FUNC_MAX 4 /* per path */ 455255736Sdavidch#define MAX_VNIC_NUM 4 456255736Sdavidch#define MAX_FUNC_NUM 8 /* common to all chips */ 457255736Sdavidch//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 458255736Sdavidch#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 459255736Sdavidch#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 460255736Sdavidch 461255736Sdavidch#define ILT_NUM_PAGE_ENTRIES 3072 462255736Sdavidch/* 463255736Sdavidch * 57710/11 we use whole table since we have 8 functions. 464255736Sdavidch * 57712 we have only 4 functions, but use same size per func, so only half 465255736Sdavidch * of the table is used. 466255736Sdavidch */ 467255736Sdavidch#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 468255736Sdavidch#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 469255736Sdavidch/* 470255736Sdavidch * the phys address is shifted right 12 bits and has an added 471255736Sdavidch * 1=valid bit added to the 53rd bit 472255736Sdavidch * then since this is a wide register(TM) 473255736Sdavidch * we split it into two 32 bit writes 474255736Sdavidch */ 475255736Sdavidch#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 476255736Sdavidch#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 477255736Sdavidch 478255736Sdavidch/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 479255736Sdavidch#define ETH_HLEN 14 480255736Sdavidch#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 481255736Sdavidch#define ETH_MIN_PACKET_SIZE 60 482255736Sdavidch#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 483255736Sdavidch#define ETH_MAX_JUMBO_PACKET_SIZE 9600 484255736Sdavidch/* TCP with Timestamp Option (32) + IPv6 (40) */ 485255736Sdavidch#define ETH_MAX_TPA_HEADER_SIZE 72 486255736Sdavidch 487255736Sdavidch/* max supported alignment is 256 (8 shift) */ 488255736Sdavidch//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 489255736Sdavidch#define BXE_RX_ALIGN_SHIFT 8 490255736Sdavidch/* FW uses 2 cache lines alignment for start packet and size */ 491255736Sdavidch#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 492255736Sdavidch#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 493255736Sdavidch 494255736Sdavidch#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 495255736Sdavidch 496255736Sdavidchstruct bxe_bar { 497255736Sdavidch struct resource *resource; 498255736Sdavidch int rid; 499255736Sdavidch bus_space_tag_t tag; 500255736Sdavidch bus_space_handle_t handle; 501255736Sdavidch vm_offset_t kva; 502255736Sdavidch}; 503255736Sdavidch 504255736Sdavidchstruct bxe_intr { 505255736Sdavidch struct resource *resource; 506255736Sdavidch int rid; 507255736Sdavidch void *tag; 508255736Sdavidch}; 509255736Sdavidch 510255736Sdavidch/* Used to manage DMA allocations. */ 511255736Sdavidchstruct bxe_dma { 512255736Sdavidch struct bxe_softc *sc; 513255736Sdavidch bus_addr_t paddr; 514255736Sdavidch void *vaddr; 515255736Sdavidch bus_dma_tag_t tag; 516255736Sdavidch bus_dmamap_t map; 517255736Sdavidch bus_dma_segment_t seg; 518255736Sdavidch bus_size_t size; 519255736Sdavidch int nseg; 520255736Sdavidch char msg[32]; 521255736Sdavidch}; 522255736Sdavidch 523255736Sdavidch/* attn group wiring */ 524255736Sdavidch#define MAX_DYNAMIC_ATTN_GRPS 8 525255736Sdavidch 526255736Sdavidchstruct attn_route { 527255736Sdavidch uint32_t sig[5]; 528255736Sdavidch}; 529255736Sdavidch 530255736Sdavidchstruct iro { 531255736Sdavidch uint32_t base; 532255736Sdavidch uint16_t m1; 533255736Sdavidch uint16_t m2; 534255736Sdavidch uint16_t m3; 535255736Sdavidch uint16_t size; 536255736Sdavidch}; 537255736Sdavidch 538255736Sdavidchunion bxe_host_hc_status_block { 539255736Sdavidch /* pointer to fp status block e2 */ 540255736Sdavidch struct host_hc_status_block_e2 *e2_sb; 541255736Sdavidch /* pointer to fp status block e1x */ 542255736Sdavidch struct host_hc_status_block_e1x *e1x_sb; 543255736Sdavidch}; 544255736Sdavidch 545255736Sdavidchunion bxe_db_prod { 546255736Sdavidch struct doorbell_set_prod data; 547255736Sdavidch uint32_t raw; 548255736Sdavidch}; 549255736Sdavidch 550255736Sdavidchstruct bxe_sw_tx_bd { 551255736Sdavidch struct mbuf *m; 552255736Sdavidch bus_dmamap_t m_map; 553255736Sdavidch uint16_t first_bd; 554255736Sdavidch uint8_t flags; 555255736Sdavidch/* set on the first BD descriptor when there is a split BD */ 556255736Sdavidch#define BXE_TSO_SPLIT_BD (1 << 0) 557255736Sdavidch}; 558255736Sdavidch 559255736Sdavidchstruct bxe_sw_rx_bd { 560255736Sdavidch struct mbuf *m; 561255736Sdavidch bus_dmamap_t m_map; 562255736Sdavidch}; 563255736Sdavidch 564255736Sdavidchstruct bxe_sw_tpa_info { 565255736Sdavidch struct bxe_sw_rx_bd bd; 566255736Sdavidch bus_dma_segment_t seg; 567255736Sdavidch uint8_t state; 568255736Sdavidch#define BXE_TPA_STATE_START 1 569255736Sdavidch#define BXE_TPA_STATE_STOP 2 570255736Sdavidch uint8_t placement_offset; 571255736Sdavidch uint16_t parsing_flags; 572255736Sdavidch uint16_t vlan_tag; 573255736Sdavidch uint16_t len_on_bd; 574255736Sdavidch}; 575255736Sdavidch 576255736Sdavidch/* 577255736Sdavidch * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 578255736Sdavidch * instances of the fastpath structure when using multiple queues. 579255736Sdavidch */ 580255736Sdavidchstruct bxe_fastpath { 581255736Sdavidch /* pointer back to parent structure */ 582255736Sdavidch struct bxe_softc *sc; 583255736Sdavidch 584255736Sdavidch struct mtx tx_mtx; 585255736Sdavidch char tx_mtx_name[32]; 586255736Sdavidch struct mtx rx_mtx; 587255736Sdavidch char rx_mtx_name[32]; 588255736Sdavidch 589255736Sdavidch#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 590255736Sdavidch#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 591255736Sdavidch#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 592255736Sdavidch 593255736Sdavidch#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 594255736Sdavidch#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 595255736Sdavidch#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 596255736Sdavidch 597255736Sdavidch /* status block */ 598255736Sdavidch struct bxe_dma sb_dma; 599255736Sdavidch union bxe_host_hc_status_block status_block; 600255736Sdavidch 601255736Sdavidch /* transmit chain (tx bds) */ 602255736Sdavidch struct bxe_dma tx_dma; 603255736Sdavidch union eth_tx_bd_types *tx_chain; 604255736Sdavidch 605255736Sdavidch /* receive chain (rx bds) */ 606255736Sdavidch struct bxe_dma rx_dma; 607255736Sdavidch struct eth_rx_bd *rx_chain; 608255736Sdavidch 609255736Sdavidch /* receive completion queue chain (rcq bds) */ 610255736Sdavidch struct bxe_dma rcq_dma; 611255736Sdavidch union eth_rx_cqe *rcq_chain; 612255736Sdavidch 613255736Sdavidch /* receive scatter/gather entry chain (for TPA) */ 614255736Sdavidch struct bxe_dma rx_sge_dma; 615255736Sdavidch struct eth_rx_sge *rx_sge_chain; 616255736Sdavidch 617255736Sdavidch /* tx mbufs */ 618255736Sdavidch bus_dma_tag_t tx_mbuf_tag; 619255736Sdavidch struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 620255736Sdavidch 621255736Sdavidch /* rx mbufs */ 622255736Sdavidch bus_dma_tag_t rx_mbuf_tag; 623255736Sdavidch struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 624255736Sdavidch bus_dmamap_t rx_mbuf_spare_map; 625255736Sdavidch 626255736Sdavidch /* rx sge mbufs */ 627255736Sdavidch bus_dma_tag_t rx_sge_mbuf_tag; 628255736Sdavidch struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 629255736Sdavidch bus_dmamap_t rx_sge_mbuf_spare_map; 630255736Sdavidch 631255736Sdavidch /* rx tpa mbufs (use the larger size for TPA queue length) */ 632255736Sdavidch int tpa_enable; /* disabled per fastpath upon error */ 633255736Sdavidch struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 634255736Sdavidch bus_dmamap_t rx_tpa_info_mbuf_spare_map; 635255736Sdavidch uint64_t rx_tpa_queue_used; 636255736Sdavidch#if 0 637255736Sdavidch bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 638255736Sdavidch bus_dmamap_t rx_tpa_mbuf_spare_map; 639255736Sdavidch struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 640255736Sdavidch bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 641255736Sdavidch 642255736Sdavidch uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 643255736Sdavidch#endif 644255736Sdavidch 645255736Sdavidch uint16_t *sb_index_values; 646255736Sdavidch uint16_t *sb_running_index; 647255736Sdavidch uint32_t ustorm_rx_prods_offset; 648255736Sdavidch 649255736Sdavidch uint8_t igu_sb_id; /* status block number in HW */ 650255736Sdavidch uint8_t fw_sb_id; /* status block number in FW */ 651255736Sdavidch 652255736Sdavidch uint32_t rx_buf_size; 653255736Sdavidch int mbuf_alloc_size; 654255736Sdavidch 655255736Sdavidch int state; 656255736Sdavidch#define BXE_FP_STATE_CLOSED 0x01 657255736Sdavidch#define BXE_FP_STATE_IRQ 0x02 658255736Sdavidch#define BXE_FP_STATE_OPENING 0x04 659255736Sdavidch#define BXE_FP_STATE_OPEN 0x08 660255736Sdavidch#define BXE_FP_STATE_HALTING 0x10 661255736Sdavidch#define BXE_FP_STATE_HALTED 0x20 662255736Sdavidch 663255736Sdavidch /* reference back to this fastpath queue number */ 664255736Sdavidch uint8_t index; /* this is also the 'cid' */ 665255736Sdavidch#define FP_IDX(fp) (fp->index) 666255736Sdavidch 667255736Sdavidch /* interrupt taskqueue (fast) */ 668255736Sdavidch struct task tq_task; 669255736Sdavidch struct taskqueue *tq; 670255736Sdavidch char tq_name[32]; 671255736Sdavidch 672255736Sdavidch /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 673255736Sdavidch uint8_t cl_id; 674255736Sdavidch#define FP_CL_ID(fp) (fp->cl_id) 675255736Sdavidch uint8_t cl_qzone_id; 676255736Sdavidch 677255736Sdavidch uint16_t fp_hc_idx; 678255736Sdavidch 679255736Sdavidch /* driver copy of the receive buffer descriptor prod/cons indices */ 680255736Sdavidch uint16_t rx_bd_prod; 681255736Sdavidch uint16_t rx_bd_cons; 682255736Sdavidch 683255736Sdavidch /* driver copy of the receive completion queue prod/cons indices */ 684255736Sdavidch uint16_t rx_cq_prod; 685255736Sdavidch uint16_t rx_cq_cons; 686255736Sdavidch 687255736Sdavidch union bxe_db_prod tx_db; 688255736Sdavidch 689255736Sdavidch /* Transmit packet producer index (used in eth_tx_bd). */ 690255736Sdavidch uint16_t tx_pkt_prod; 691255736Sdavidch uint16_t tx_pkt_cons; 692255736Sdavidch 693255736Sdavidch /* Transmit buffer descriptor producer index. */ 694255736Sdavidch uint16_t tx_bd_prod; 695255736Sdavidch uint16_t tx_bd_cons; 696255736Sdavidch 697255736Sdavidch#if 0 698255736Sdavidch /* status block number in hardware */ 699255736Sdavidch uint8_t sb_id; 700255736Sdavidch#define FP_SB_ID(fp) (fp->sb_id) 701255736Sdavidch 702255736Sdavidch /* driver copy of the fastpath CSTORM/USTORM indices */ 703255736Sdavidch uint16_t fp_c_idx; 704255736Sdavidch uint16_t fp_u_idx; 705255736Sdavidch#endif 706255736Sdavidch 707255736Sdavidch uint64_t sge_mask[RX_SGE_MASK_LEN]; 708255736Sdavidch uint16_t rx_sge_prod; 709255736Sdavidch 710255736Sdavidch struct tstorm_per_queue_stats old_tclient; 711255736Sdavidch struct ustorm_per_queue_stats old_uclient; 712255736Sdavidch struct xstorm_per_queue_stats old_xclient; 713255736Sdavidch struct bxe_eth_q_stats eth_q_stats; 714255736Sdavidch struct bxe_eth_q_stats_old eth_q_stats_old; 715255736Sdavidch 716255736Sdavidch /* Pointer to the receive consumer in the status block */ 717255736Sdavidch uint16_t *rx_cq_cons_sb; 718255736Sdavidch 719255736Sdavidch /* Pointer to the transmit consumer in the status block */ 720255736Sdavidch uint16_t *tx_cons_sb; 721255736Sdavidch 722255736Sdavidch /* transmit timeout until chip reset */ 723255736Sdavidch int watchdog_timer; 724255736Sdavidch 725255736Sdavidch /* Free/used buffer descriptor counters. */ 726255736Sdavidch //uint16_t used_tx_bd; 727255736Sdavidch 728255736Sdavidch /* Last maximal completed SGE */ 729255736Sdavidch uint16_t last_max_sge; 730255736Sdavidch 731255736Sdavidch //uint16_t rx_sge_free_idx; 732255736Sdavidch 733255736Sdavidch //uint8_t segs; 734255736Sdavidch 735255736Sdavidch#if __FreeBSD_version >= 800000 736255736Sdavidch#define BXE_BR_SIZE 4096 737255736Sdavidch struct buf_ring *tx_br; 738255736Sdavidch#endif 739255736Sdavidch}; /* struct bxe_fastpath */ 740255736Sdavidch 741255736Sdavidch/* sriov XXX */ 742255736Sdavidch#define BXE_MAX_NUM_OF_VFS 64 743255736Sdavidch#define BXE_VF_CID_WND 0 744255736Sdavidch#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 745255736Sdavidch#define BXE_CLIENTS_PER_VF 1 746255736Sdavidch#define BXE_FIRST_VF_CID 256 747255736Sdavidch#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 748255736Sdavidch#define BXE_VF_ID_INVALID 0xFF 749255736Sdavidch#define IS_SRIOV(sc) 0 750255736Sdavidch 751258187Sedavis#define GET_NUM_VFS_PER_PATH(sc) 0 752258187Sedavis#define GET_NUM_VFS_PER_PF(sc) 0 753258187Sedavis 754255736Sdavidch/* maximum number of fast-path interrupt contexts */ 755255736Sdavidch#define FP_SB_MAX_E1x 16 756255736Sdavidch#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 757255736Sdavidch 758255736Sdavidchunion cdu_context { 759255736Sdavidch struct eth_context eth; 760255736Sdavidch char pad[1024]; 761255736Sdavidch}; 762255736Sdavidch 763255736Sdavidch/* CDU host DB constants */ 764255736Sdavidch#define CDU_ILT_PAGE_SZ_HW 2 765255736Sdavidch#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 766255736Sdavidch#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 767255736Sdavidch 768255736Sdavidch#define CNIC_ISCSI_CID_MAX 256 769255736Sdavidch#define CNIC_FCOE_CID_MAX 2048 770255736Sdavidch#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 771255736Sdavidch#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 772255736Sdavidch 773255736Sdavidch#define QM_ILT_PAGE_SZ_HW 0 774255736Sdavidch#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 775255736Sdavidch#define QM_CID_ROUND 1024 776255736Sdavidch 777255736Sdavidch/* TM (timers) host DB constants */ 778255736Sdavidch#define TM_ILT_PAGE_SZ_HW 0 779255736Sdavidch#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 780255736Sdavidch/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 781255736Sdavidch#define TM_CONN_NUM 1024 782255736Sdavidch#define TM_ILT_SZ (8 * TM_CONN_NUM) 783255736Sdavidch#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 784255736Sdavidch 785255736Sdavidch/* SRC (Searcher) host DB constants */ 786255736Sdavidch#define SRC_ILT_PAGE_SZ_HW 0 787255736Sdavidch#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 788255736Sdavidch#define SRC_HASH_BITS 10 789255736Sdavidch#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 790255736Sdavidch#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 791255736Sdavidch#define SRC_T2_SZ SRC_ILT_SZ 792255736Sdavidch#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 793255736Sdavidch 794255736Sdavidchstruct hw_context { 795255736Sdavidch struct bxe_dma vcxt_dma; 796255736Sdavidch union cdu_context *vcxt; 797255736Sdavidch //bus_addr_t cxt_mapping; 798255736Sdavidch size_t size; 799255736Sdavidch}; 800255736Sdavidch 801255736Sdavidch#define SM_RX_ID 0 802255736Sdavidch#define SM_TX_ID 1 803255736Sdavidch 804255736Sdavidch/* defines for multiple tx priority indices */ 805255736Sdavidch#define FIRST_TX_ONLY_COS_INDEX 1 806255736Sdavidch#define FIRST_TX_COS_INDEX 0 807255736Sdavidch 808255736Sdavidch#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 809255736Sdavidch 810255736Sdavidch#define HC_INDEX_ETH_RX_CQ_CONS 1 811255736Sdavidch#define HC_INDEX_OOO_TX_CQ_CONS 4 812255736Sdavidch#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 813255736Sdavidch#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 814255736Sdavidch#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 815255736Sdavidch#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 816255736Sdavidch 817255736Sdavidch/* congestion management fairness mode */ 818255736Sdavidch#define CMNG_FNS_NONE 0 819255736Sdavidch#define CMNG_FNS_MINMAX 1 820255736Sdavidch 821255736Sdavidch/* CMNG constants, as derived from system spec calculations */ 822255736Sdavidch/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 823255736Sdavidch#define DEF_MIN_RATE 100 824255736Sdavidch/* resolution of the rate shaping timer - 400 usec */ 825255736Sdavidch#define RS_PERIODIC_TIMEOUT_USEC 400 826255736Sdavidch/* number of bytes in single QM arbitration cycle - 827255736Sdavidch * coefficient for calculating the fairness timer */ 828255736Sdavidch#define QM_ARB_BYTES 160000 829255736Sdavidch/* resolution of Min algorithm 1:100 */ 830255736Sdavidch#define MIN_RES 100 831255736Sdavidch/* how many bytes above threshold for the minimal credit of Min algorithm*/ 832255736Sdavidch#define MIN_ABOVE_THRESH 32768 833255736Sdavidch/* fairness algorithm integration time coefficient - 834255736Sdavidch * for calculating the actual Tfair */ 835255736Sdavidch#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 836255736Sdavidch/* memory of fairness algorithm - 2 cycles */ 837255736Sdavidch#define FAIR_MEM 2 838255736Sdavidch 839255736Sdavidch#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 840255736Sdavidch#define HC_SEG_ACCESS_ATTN 4 841255736Sdavidch#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 842255736Sdavidch 843255736Sdavidch/* 844255736Sdavidch * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 845255736Sdavidch * control by the number of fast-path status blocks supported by the 846255736Sdavidch * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 847255736Sdavidch * status block represents an independent interrupts context that can 848255736Sdavidch * serve a regular L2 networking queue. However special L2 queues such 849255736Sdavidch * as the FCoE queue do not require a FP-SB and other components like 850255736Sdavidch * the CNIC may consume FP-SB reducing the number of possible L2 queues 851255736Sdavidch * 852255736Sdavidch * If the maximum number of FP-SB available is X then: 853255736Sdavidch * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 854255736Sdavidch * regular L2 queues is Y=X-1 855255736Sdavidch * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 856255736Sdavidch * c. If the FCoE L2 queue is supported the actual number of L2 queues 857255736Sdavidch * is Y+1 858255736Sdavidch * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 859255736Sdavidch * slow-path interrupts) or Y+2 if CNIC is supported (one additional 860255736Sdavidch * FP interrupt context for the CNIC). 861255736Sdavidch * e. The number of HW context (CID count) is always X or X+1 if FCoE 862255736Sdavidch * L2 queue is supported. the cid for the FCoE L2 queue is always X. 863255736Sdavidch * 864255736Sdavidch * So this is quite simple for now as no ULPs are supported yet. :-) 865255736Sdavidch */ 866255736Sdavidch#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 867255736Sdavidch#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 868255736Sdavidch#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 869255736Sdavidch#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 870255736Sdavidch 871255736Sdavidch#define FOR_EACH_QUEUE(sc, var) \ 872255736Sdavidch for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 873255736Sdavidch 874255736Sdavidch#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 875255736Sdavidch for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 876255736Sdavidch 877255736Sdavidch#define FOR_EACH_ETH_QUEUE(sc, var) \ 878255736Sdavidch for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 879255736Sdavidch 880255736Sdavidch#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 881255736Sdavidch for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 882255736Sdavidch 883255736Sdavidch#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 884255736Sdavidch for ((var) = 0; (var) < (sc)->max_cos; (var)++) 885255736Sdavidch 886255736Sdavidch#define FOR_EACH_CNIC_QUEUE(sc, var) \ 887255736Sdavidch for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 888255736Sdavidch (var) < BXE_NUM_QUEUES(sc); \ 889255736Sdavidch (var)++) 890255736Sdavidch 891255736Sdavidchenum { 892255736Sdavidch OOO_IDX_OFFSET, 893255736Sdavidch FCOE_IDX_OFFSET, 894255736Sdavidch FWD_IDX_OFFSET, 895255736Sdavidch}; 896255736Sdavidch 897255736Sdavidch#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 898255736Sdavidch#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 899255736Sdavidch#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 900255736Sdavidch#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 901255736Sdavidch#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 902255736Sdavidch#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 903255736Sdavidch 904255736Sdavidch#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 905255736Sdavidch#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 906255736Sdavidch#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 907255736Sdavidch#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 908255736Sdavidch#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 909255736Sdavidch 910255736Sdavidch#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 911255736Sdavidch#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 912255736Sdavidch#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 913255736Sdavidch#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 914255736Sdavidch#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 915255736Sdavidch#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 916255736Sdavidch 917255736Sdavidch#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 918255736Sdavidch#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 919255736Sdavidch#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 920255736Sdavidch#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 921255736Sdavidch#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 922255736Sdavidch#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 923255736Sdavidch#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 924255736Sdavidch 925255736Sdavidchenum { 926255736Sdavidch BXE_PORT_QUERY_IDX, 927255736Sdavidch BXE_PF_QUERY_IDX, 928255736Sdavidch BXE_FCOE_QUERY_IDX, 929255736Sdavidch BXE_FIRST_QUEUE_QUERY_IDX, 930255736Sdavidch}; 931255736Sdavidch 932255736Sdavidchstruct bxe_fw_stats_req { 933255736Sdavidch struct stats_query_header hdr; 934255736Sdavidch struct stats_query_entry query[FP_SB_MAX_E1x + 935255736Sdavidch BXE_FIRST_QUEUE_QUERY_IDX]; 936255736Sdavidch}; 937255736Sdavidch 938255736Sdavidchstruct bxe_fw_stats_data { 939255736Sdavidch struct stats_counter storm_counters; 940255736Sdavidch struct per_port_stats port; 941255736Sdavidch struct per_pf_stats pf; 942255736Sdavidch //struct fcoe_statistics_params fcoe; 943255736Sdavidch struct per_queue_stats queue_stats[1]; 944255736Sdavidch}; 945255736Sdavidch 946255736Sdavidch/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 947255736Sdavidch#define BXE_IGU_STAS_MSG_VF_CNT 64 948255736Sdavidch#define BXE_IGU_STAS_MSG_PF_CNT 4 949255736Sdavidch 950255736Sdavidch#define MAX_DMAE_C 8 951255736Sdavidch 952255736Sdavidch/* 953255736Sdavidch * For the main interface up/down code paths, a not-so-fine-grained CORE 954255736Sdavidch * mutex lock is used. Inside this code are various calls to kernel routines 955255736Sdavidch * that can cause a sleep to occur. Namely memory allocations and taskqueue 956255736Sdavidch * handling. If using an MTX lock we are *not* allowed to sleep but we can 957255736Sdavidch * with an SX lock. This define forces the CORE lock to use and SX lock. 958255736Sdavidch * Undefine this and an MTX lock will be used instead. Note that the IOCTL 959255736Sdavidch * path can cause problems since it's called by a non-sleepable thread. To 960255736Sdavidch * alleviate a potential sleep, any IOCTL processing that results in the 961255736Sdavidch * chip/interface being started/stopped/reinitialized, the actual work is 962255736Sdavidch * offloaded to a taskqueue. 963255736Sdavidch */ 964255736Sdavidch#define BXE_CORE_LOCK_SX 965255736Sdavidch 966255736Sdavidch/* 967255736Sdavidch * This is the slowpath data structure. It is mapped into non-paged memory 968255736Sdavidch * so that the hardware can access it's contents directly and must be page 969255736Sdavidch * aligned. 970255736Sdavidch */ 971255736Sdavidchstruct bxe_slowpath { 972255736Sdavidch 973255736Sdavidch#if 0 974255736Sdavidch /* 975255736Sdavidch * The cdu_context array MUST be the first element in this 976255736Sdavidch * structure. It is used during the leading edge ramrod 977255736Sdavidch * operation. 978255736Sdavidch */ 979255736Sdavidch union cdu_context context[MAX_CONTEXT]; 980255736Sdavidch 981255736Sdavidch /* Used as a DMA source for MAC configuration. */ 982255736Sdavidch struct mac_configuration_cmd mac_config; 983255736Sdavidch struct mac_configuration_cmd mcast_config; 984255736Sdavidch#endif 985255736Sdavidch 986255736Sdavidch /* used by the DMAE command executer */ 987255736Sdavidch struct dmae_command dmae[MAX_DMAE_C]; 988255736Sdavidch 989255736Sdavidch /* statistics completion */ 990255736Sdavidch uint32_t stats_comp; 991255736Sdavidch 992255736Sdavidch /* firmware defined statistics blocks */ 993255736Sdavidch union mac_stats mac_stats; 994255736Sdavidch struct nig_stats nig_stats; 995255736Sdavidch struct host_port_stats port_stats; 996255736Sdavidch struct host_func_stats func_stats; 997255736Sdavidch //struct host_func_stats func_stats_base; 998255736Sdavidch 999255736Sdavidch /* DMAE completion value and data source/sink */ 1000255736Sdavidch uint32_t wb_comp; 1001255736Sdavidch uint32_t wb_data[4]; 1002255736Sdavidch 1003255736Sdavidch union { 1004255736Sdavidch struct mac_configuration_cmd e1x; 1005255736Sdavidch struct eth_classify_rules_ramrod_data e2; 1006255736Sdavidch } mac_rdata; 1007255736Sdavidch 1008255736Sdavidch union { 1009255736Sdavidch struct tstorm_eth_mac_filter_config e1x; 1010255736Sdavidch struct eth_filter_rules_ramrod_data e2; 1011255736Sdavidch } rx_mode_rdata; 1012255736Sdavidch 1013255736Sdavidch struct eth_rss_update_ramrod_data rss_rdata; 1014255736Sdavidch 1015255736Sdavidch union { 1016255736Sdavidch struct mac_configuration_cmd e1; 1017255736Sdavidch struct eth_multicast_rules_ramrod_data e2; 1018255736Sdavidch } mcast_rdata; 1019255736Sdavidch 1020255736Sdavidch union { 1021255736Sdavidch struct function_start_data func_start; 1022255736Sdavidch struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 1023255736Sdavidch } func_rdata; 1024255736Sdavidch 1025255736Sdavidch /* Queue State related ramrods */ 1026255736Sdavidch union { 1027255736Sdavidch struct client_init_ramrod_data init_data; 1028255736Sdavidch struct client_update_ramrod_data update_data; 1029255736Sdavidch } q_rdata; 1030255736Sdavidch 1031255736Sdavidch /* 1032255736Sdavidch * AFEX ramrod can not be a part of func_rdata union because these 1033255736Sdavidch * events might arrive in parallel to other events from func_rdata. 1034255736Sdavidch * If they were defined in the same union the data can get corrupted. 1035255736Sdavidch */ 1036255736Sdavidch struct afex_vif_list_ramrod_data func_afex_rdata; 1037255736Sdavidch 1038255736Sdavidch union drv_info_to_mcp drv_info_to_mcp; 1039255736Sdavidch}; /* struct bxe_slowpath */ 1040255736Sdavidch 1041255736Sdavidch/* 1042255736Sdavidch * Port specifc data structure. 1043255736Sdavidch */ 1044255736Sdavidchstruct bxe_port { 1045255736Sdavidch /* 1046255736Sdavidch * Port Management Function (for 57711E only). 1047255736Sdavidch * When this field is set the driver instance is 1048255736Sdavidch * responsible for managing port specifc 1049255736Sdavidch * configurations such as handling link attentions. 1050255736Sdavidch */ 1051255736Sdavidch uint32_t pmf; 1052255736Sdavidch 1053255736Sdavidch /* Ethernet maximum transmission unit. */ 1054255736Sdavidch uint16_t ether_mtu; 1055255736Sdavidch 1056255736Sdavidch uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1057255736Sdavidch 1058255736Sdavidch uint32_t ext_phy_config; 1059255736Sdavidch 1060255736Sdavidch /* Port feature config.*/ 1061255736Sdavidch uint32_t config; 1062255736Sdavidch 1063255736Sdavidch /* Defines the features supported by the PHY. */ 1064255736Sdavidch uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1065255736Sdavidch 1066255736Sdavidch /* Defines the features advertised by the PHY. */ 1067255736Sdavidch uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1068255736Sdavidch#define ADVERTISED_10baseT_Half (1 << 1) 1069255736Sdavidch#define ADVERTISED_10baseT_Full (1 << 2) 1070255736Sdavidch#define ADVERTISED_100baseT_Half (1 << 3) 1071255736Sdavidch#define ADVERTISED_100baseT_Full (1 << 4) 1072255736Sdavidch#define ADVERTISED_1000baseT_Half (1 << 5) 1073255736Sdavidch#define ADVERTISED_1000baseT_Full (1 << 6) 1074255736Sdavidch#define ADVERTISED_TP (1 << 7) 1075255736Sdavidch#define ADVERTISED_FIBRE (1 << 8) 1076255736Sdavidch#define ADVERTISED_Autoneg (1 << 9) 1077255736Sdavidch#define ADVERTISED_Asym_Pause (1 << 10) 1078255736Sdavidch#define ADVERTISED_Pause (1 << 11) 1079255736Sdavidch#define ADVERTISED_2500baseX_Full (1 << 15) 1080255736Sdavidch#define ADVERTISED_10000baseT_Full (1 << 16) 1081255736Sdavidch 1082255736Sdavidch uint32_t phy_addr; 1083255736Sdavidch 1084255736Sdavidch /* Used to synchronize phy accesses. */ 1085255736Sdavidch struct mtx phy_mtx; 1086255736Sdavidch char phy_mtx_name[32]; 1087255736Sdavidch 1088255736Sdavidch#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1089255736Sdavidch#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1090255736Sdavidch#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1091255736Sdavidch 1092255736Sdavidch /* 1093255736Sdavidch * MCP scratchpad address for port specific statistics. 1094255736Sdavidch * The device is responsible for writing statistcss 1095255736Sdavidch * back to the MCP for use with management firmware such 1096255736Sdavidch * as UMP/NC-SI. 1097255736Sdavidch */ 1098255736Sdavidch uint32_t port_stx; 1099255736Sdavidch 1100255736Sdavidch struct nig_stats old_nig_stats; 1101255736Sdavidch}; /* struct bxe_port */ 1102255736Sdavidch 1103255736Sdavidchstruct bxe_mf_info { 1104255736Sdavidch uint32_t mf_config[E1HVN_MAX]; 1105255736Sdavidch 1106255736Sdavidch uint32_t vnics_per_port; /* 1, 2 or 4 */ 1107255736Sdavidch uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1108255736Sdavidch uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1109255736Sdavidch 1110255736Sdavidch#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1111255736Sdavidch#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1112255736Sdavidch#define VNICS_PER_PATH(sc) \ 1113255736Sdavidch ((sc)->devinfo.mf_info.vnics_per_port * \ 1114255736Sdavidch ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1115255736Sdavidch 1116255736Sdavidch uint8_t min_bw[MAX_VNIC_NUM]; 1117255736Sdavidch uint8_t max_bw[MAX_VNIC_NUM]; 1118255736Sdavidch 1119255736Sdavidch uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1120255736Sdavidch#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1121255736Sdavidch#define INVALID_VIF_ID 0xFFFF 1122255736Sdavidch#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1123255736Sdavidch#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1124255736Sdavidch 1125255736Sdavidch uint16_t default_vlan; 1126255736Sdavidch#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1127255736Sdavidch 1128255736Sdavidch uint8_t niv_allowed_priorities; 1129255736Sdavidch#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1130255736Sdavidch 1131255736Sdavidch uint8_t niv_default_cos; 1132255736Sdavidch#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1133255736Sdavidch 1134255736Sdavidch uint8_t niv_mba_enabled; 1135255736Sdavidch 1136255736Sdavidch enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1137255736Sdavidch#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1138255736Sdavidch int afex_def_vlan_tag; 1139255736Sdavidch uint32_t pending_max; 1140255736Sdavidch 1141255736Sdavidch uint16_t flags; 1142255736Sdavidch#define MF_INFO_VALID_MAC 0x0001 1143255736Sdavidch 1144255736Sdavidch uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1145255736Sdavidch#define IS_MF(sc) \ 1146255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1147255736Sdavidch ((sc)->devinfo.mf_info.mf_mode != 0)) 1148255736Sdavidch#define IS_MF_SD(sc) \ 1149255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1150255736Sdavidch ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1151255736Sdavidch#define IS_MF_SI(sc) \ 1152255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1153255736Sdavidch ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1154255736Sdavidch#define IS_MF_AFEX(sc) \ 1155255736Sdavidch (IS_MULTI_VNIC(sc) && \ 1156255736Sdavidch ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1157255736Sdavidch#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1158255736Sdavidch#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1159255736Sdavidch#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1160255736Sdavidch 1161255736Sdavidch uint32_t mf_protos_supported; 1162255736Sdavidch #define MF_PROTO_SUPPORT_ETHERNET 0x1 1163255736Sdavidch #define MF_PROTO_SUPPORT_ISCSI 0x2 1164255736Sdavidch #define MF_PROTO_SUPPORT_FCOE 0x4 1165255736Sdavidch}; /* struct bxe_mf_info */ 1166255736Sdavidch 1167255736Sdavidch/* Device information data structure. */ 1168255736Sdavidchstruct bxe_devinfo { 1169255736Sdavidch /* PCIe info */ 1170255736Sdavidch uint16_t vendor_id; 1171255736Sdavidch uint16_t device_id; 1172255736Sdavidch uint16_t subvendor_id; 1173255736Sdavidch uint16_t subdevice_id; 1174255736Sdavidch 1175255736Sdavidch /* 1176255736Sdavidch * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1177255736Sdavidch * C = Chip Number (bits 16-31) 1178255736Sdavidch * R = Chip Revision (bits 12-15) 1179255736Sdavidch * M = Chip Metal (bits 4-11) 1180255736Sdavidch * B = Chip Bond ID (bits 0-3) 1181255736Sdavidch */ 1182255736Sdavidch uint32_t chip_id; 1183255736Sdavidch#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1184255736Sdavidch#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1185255736Sdavidch/* device ids */ 1186255736Sdavidch#define CHIP_NUM_57710 0x164e 1187255736Sdavidch#define CHIP_NUM_57711 0x164f 1188255736Sdavidch#define CHIP_NUM_57711E 0x1650 1189255736Sdavidch#define CHIP_NUM_57712 0x1662 1190255736Sdavidch#define CHIP_NUM_57712_MF 0x1663 1191255736Sdavidch#define CHIP_NUM_57712_VF 0x166f 1192255736Sdavidch#define CHIP_NUM_57800 0x168a 1193255736Sdavidch#define CHIP_NUM_57800_MF 0x16a5 1194255736Sdavidch#define CHIP_NUM_57800_VF 0x16a9 1195255736Sdavidch#define CHIP_NUM_57810 0x168e 1196255736Sdavidch#define CHIP_NUM_57810_MF 0x16ae 1197255736Sdavidch#define CHIP_NUM_57810_VF 0x16af 1198255736Sdavidch#define CHIP_NUM_57811 0x163d 1199255736Sdavidch#define CHIP_NUM_57811_MF 0x163e 1200255736Sdavidch#define CHIP_NUM_57811_VF 0x163f 1201255736Sdavidch#define CHIP_NUM_57840_OBS 0x168d 1202255736Sdavidch#define CHIP_NUM_57840_OBS_MF 0x16ab 1203255736Sdavidch#define CHIP_NUM_57840_4_10 0x16a1 1204255736Sdavidch#define CHIP_NUM_57840_2_20 0x16a2 1205255736Sdavidch#define CHIP_NUM_57840_MF 0x16a4 1206255736Sdavidch#define CHIP_NUM_57840_VF 0x16ad 1207255736Sdavidch 1208255736Sdavidch#define CHIP_REV_SHIFT 12 1209255736Sdavidch#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1210255736Sdavidch#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1211255736Sdavidch 1212255736Sdavidch#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1213255736Sdavidch#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1214255736Sdavidch#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1215255736Sdavidch 1216255736Sdavidch#define CHIP_REV_IS_SLOW(sc) \ 1217255736Sdavidch (CHIP_REV(sc) > 0x00005000) 1218255736Sdavidch#define CHIP_REV_IS_FPGA(sc) \ 1219255736Sdavidch (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1220255736Sdavidch#define CHIP_REV_IS_EMUL(sc) \ 1221255736Sdavidch (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1222255736Sdavidch#define CHIP_REV_IS_ASIC(sc) \ 1223255736Sdavidch (!CHIP_REV_IS_SLOW(sc)) 1224255736Sdavidch 1225255736Sdavidch#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1226255736Sdavidch#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1227255736Sdavidch 1228255736Sdavidch#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1229255736Sdavidch#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1230255736Sdavidch#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1231255736Sdavidch#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1232255736Sdavidch#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1233255736Sdavidch (CHIP_IS_57711E(sc))) 1234255736Sdavidch#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1235255736Sdavidch CHIP_IS_E1H((sc))) 1236255736Sdavidch 1237255736Sdavidch#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1238255736Sdavidch#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1239255736Sdavidch#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1240255736Sdavidch#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1241255736Sdavidch CHIP_IS_57712_MF(sc)) 1242255736Sdavidch 1243255736Sdavidch#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1244255736Sdavidch#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1245255736Sdavidch#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1246255736Sdavidch#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1247255736Sdavidch#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1248255736Sdavidch#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1249255736Sdavidch#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1250255736Sdavidch#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1251255736Sdavidch#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1252255736Sdavidch#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1253255736Sdavidch (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1254255736Sdavidch (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1255255736Sdavidch#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1256255736Sdavidch (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1257255736Sdavidch#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1258255736Sdavidch 1259255736Sdavidch#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1260255736Sdavidch CHIP_IS_57800_MF(sc) || \ 1261255736Sdavidch CHIP_IS_57800_VF(sc) || \ 1262255736Sdavidch CHIP_IS_57810(sc) || \ 1263255736Sdavidch CHIP_IS_57810_MF(sc) || \ 1264255736Sdavidch CHIP_IS_57810_VF(sc) || \ 1265255736Sdavidch CHIP_IS_57811(sc) || \ 1266255736Sdavidch CHIP_IS_57811_MF(sc) || \ 1267255736Sdavidch CHIP_IS_57811_VF(sc) || \ 1268255736Sdavidch CHIP_IS_57840(sc) || \ 1269255736Sdavidch CHIP_IS_57840_MF(sc) || \ 1270255736Sdavidch CHIP_IS_57840_VF(sc)) 1271255736Sdavidch#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1272255736Sdavidch (CHIP_REV(sc) == CHIP_REV_Ax)) 1273255736Sdavidch#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1274255736Sdavidch (CHIP_REV(sc) == CHIP_REV_Bx)) 1275255736Sdavidch 1276255736Sdavidch#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1277255736Sdavidch#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1278255736Sdavidch CHIP_IS_E3(sc)) 1279255736Sdavidch 1280255736Sdavidch#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1281255736Sdavidch CHIP_IS_57712_MF(sc) || \ 1282255736Sdavidch CHIP_IS_E3(sc)) 1283255736Sdavidch 1284255736Sdavidch#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1285255736Sdavidch CHIP_IS_57800_VF(sc) || \ 1286255736Sdavidch CHIP_IS_57810_VF(sc) || \ 1287255736Sdavidch CHIP_IS_57840_VF(sc)) 1288255736Sdavidch#define IS_PF(sc) (!IS_VF(sc)) 1289255736Sdavidch 1290255736Sdavidch/* 1291255736Sdavidch * This define is used in two main places: 1292255736Sdavidch * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1293255736Sdavidch * to nic-only mode or to offload mode. Offload mode is configured if either 1294255736Sdavidch * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1295255736Sdavidch * already registered for this port (which means that the user wants storage 1296255736Sdavidch * services). 1297255736Sdavidch * 2. During cnic-related load, to know if offload mode is already configured 1298255736Sdavidch * in the HW or needs to be configrued. Since the transition from nic-mode to 1299255736Sdavidch * offload-mode in HW causes traffic coruption, nic-mode is configured only 1300255736Sdavidch * in ports on which storage services where never requested. 1301255736Sdavidch */ 1302255736Sdavidch#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1303255736Sdavidch 1304255736Sdavidch uint8_t chip_port_mode; 1305255736Sdavidch#define CHIP_4_PORT_MODE 0x0 1306255736Sdavidch#define CHIP_2_PORT_MODE 0x1 1307255736Sdavidch#define CHIP_PORT_MODE_NONE 0x2 1308255736Sdavidch#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1309255736Sdavidch#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1310255736Sdavidch 1311255736Sdavidch uint8_t int_block; 1312255736Sdavidch#define INT_BLOCK_HC 0 1313255736Sdavidch#define INT_BLOCK_IGU 1 1314255736Sdavidch#define INT_BLOCK_MODE_NORMAL 0 1315255736Sdavidch#define INT_BLOCK_MODE_BW_COMP 2 1316255736Sdavidch#define CHIP_INT_MODE_IS_NBC(sc) \ 1317255736Sdavidch (!CHIP_IS_E1x(sc) && \ 1318255736Sdavidch !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1319255736Sdavidch#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1320255736Sdavidch 1321255736Sdavidch uint32_t shmem_base; 1322255736Sdavidch uint32_t shmem2_base; 1323255736Sdavidch uint32_t bc_ver; 1324255736Sdavidch char bc_ver_str[32]; 1325255736Sdavidch uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1326255736Sdavidch struct bxe_mf_info mf_info; 1327255736Sdavidch 1328255736Sdavidch int flash_size; 1329255736Sdavidch#define NVRAM_1MB_SIZE 0x20000 1330255736Sdavidch#define NVRAM_TIMEOUT_COUNT 30000 1331255736Sdavidch#define NVRAM_PAGE_SIZE 256 1332255736Sdavidch 1333255736Sdavidch /* PCIe capability information */ 1334255736Sdavidch uint32_t pcie_cap_flags; 1335255736Sdavidch#define BXE_PM_CAPABLE_FLAG 0x00000001 1336255736Sdavidch#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1337255736Sdavidch#define BXE_MSI_CAPABLE_FLAG 0x00000004 1338255736Sdavidch#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1339255736Sdavidch uint16_t pcie_pm_cap_reg; 1340255736Sdavidch uint16_t pcie_pcie_cap_reg; 1341255736Sdavidch //uint16_t pcie_devctl; 1342255736Sdavidch uint16_t pcie_link_width; 1343255736Sdavidch uint16_t pcie_link_speed; 1344255736Sdavidch uint16_t pcie_msi_cap_reg; 1345255736Sdavidch uint16_t pcie_msix_cap_reg; 1346255736Sdavidch 1347255736Sdavidch /* device configuration read from bootcode shared memory */ 1348255736Sdavidch uint32_t hw_config; 1349255736Sdavidch uint32_t hw_config2; 1350255736Sdavidch}; /* struct bxe_devinfo */ 1351255736Sdavidch 1352255736Sdavidchstruct bxe_sp_objs { 1353255736Sdavidch struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1354255736Sdavidch struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1355255736Sdavidch}; /* struct bxe_sp_objs */ 1356255736Sdavidch 1357255736Sdavidch/* 1358255736Sdavidch * Data that will be used to create a link report message. We will keep the 1359255736Sdavidch * data used for the last link report in order to prevent reporting the same 1360255736Sdavidch * link parameters twice. 1361255736Sdavidch */ 1362255736Sdavidchstruct bxe_link_report_data { 1363255736Sdavidch uint16_t line_speed; /* Effective line speed */ 1364255736Sdavidch unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1365255736Sdavidch}; 1366255736Sdavidchenum { 1367255736Sdavidch BXE_LINK_REPORT_FULL_DUPLEX, 1368255736Sdavidch BXE_LINK_REPORT_LINK_DOWN, 1369255736Sdavidch BXE_LINK_REPORT_RX_FC_ON, 1370255736Sdavidch BXE_LINK_REPORT_TX_FC_ON 1371255736Sdavidch}; 1372255736Sdavidch 1373255736Sdavidch/* Top level device private data structure. */ 1374255736Sdavidchstruct bxe_softc { 1375255736Sdavidch /* 1376255736Sdavidch * First entry must be a pointer to the BSD ifnet struct which 1377255736Sdavidch * has a first element of 'void *if_softc' (which is us). 1378255736Sdavidch */ 1379255736Sdavidch struct ifnet *ifnet; 1380255736Sdavidch struct ifmedia ifmedia; /* network interface media structure */ 1381255736Sdavidch int media; 1382255736Sdavidch 1383255736Sdavidch int state; /* device state */ 1384255736Sdavidch#define BXE_STATE_CLOSED 0x0000 1385255736Sdavidch#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1386255736Sdavidch#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1387255736Sdavidch#define BXE_STATE_OPEN 0x3000 1388255736Sdavidch#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1389255736Sdavidch#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1390255736Sdavidch#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1391255736Sdavidch#define BXE_STATE_DISABLED 0xD000 1392255736Sdavidch#define BXE_STATE_DIAG 0xE000 1393255736Sdavidch#define BXE_STATE_ERROR 0xF000 1394255736Sdavidch 1395255736Sdavidch int flags; 1396255736Sdavidch#define BXE_ONE_PORT_FLAG 0x00000001 1397255736Sdavidch#define BXE_NO_ISCSI 0x00000002 1398255736Sdavidch#define BXE_NO_FCOE 0x00000004 1399255736Sdavidch#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1400255736Sdavidch//#define BXE_NO_WOL_FLAG 0x00000008 1401255736Sdavidch//#define BXE_USING_DAC_FLAG 0x00000010 1402255736Sdavidch//#define BXE_USING_MSIX_FLAG 0x00000020 1403255736Sdavidch//#define BXE_USING_MSI_FLAG 0x00000040 1404255736Sdavidch//#define BXE_DISABLE_MSI_FLAG 0x00000080 1405255736Sdavidch#define BXE_NO_MCP_FLAG 0x00000200 1406255736Sdavidch#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1407255736Sdavidch//#define BXE_SAFC_TX_FLAG 0x00000400 1408255736Sdavidch#define BXE_MF_FUNC_DIS 0x00000800 1409255736Sdavidch#define BXE_TX_SWITCHING 0x00001000 1410255736Sdavidch 1411258187Sedavis unsigned long debug; /* per-instance debug logging config */ 1412255736Sdavidch 1413255736Sdavidch#define MAX_BARS 5 1414255736Sdavidch struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1415255736Sdavidch 1416255736Sdavidch uint16_t doorbell_size; 1417255736Sdavidch 1418255736Sdavidch /* periodic timer callout */ 1419255736Sdavidch#define PERIODIC_STOP 0 1420255736Sdavidch#define PERIODIC_GO 1 1421255736Sdavidch volatile unsigned long periodic_flags; 1422255736Sdavidch struct callout periodic_callout; 1423255736Sdavidch 1424255736Sdavidch /* chip start/stop/reset taskqueue */ 1425255736Sdavidch#define CHIP_TQ_NONE 0 1426255736Sdavidch#define CHIP_TQ_START 1 1427255736Sdavidch#define CHIP_TQ_STOP 2 1428255736Sdavidch#define CHIP_TQ_REINIT 3 1429255736Sdavidch volatile unsigned long chip_tq_flags; 1430255736Sdavidch struct task chip_tq_task; 1431255736Sdavidch struct taskqueue *chip_tq; 1432255736Sdavidch char chip_tq_name[32]; 1433255736Sdavidch 1434255736Sdavidch /* slowpath interrupt taskqueue */ 1435255736Sdavidch struct task sp_tq_task; 1436255736Sdavidch struct taskqueue *sp_tq; 1437255736Sdavidch char sp_tq_name[32]; 1438255736Sdavidch 1439255736Sdavidch /* set rx_mode asynchronous taskqueue */ 1440255736Sdavidch struct task rx_mode_tq_task; 1441255736Sdavidch struct taskqueue *rx_mode_tq; 1442255736Sdavidch char rx_mode_tq_name[32]; 1443255736Sdavidch 1444255736Sdavidch struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1445255736Sdavidch struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1446255736Sdavidch 1447255736Sdavidch device_t dev; /* parent device handle */ 1448255736Sdavidch uint8_t unit; /* driver instance number */ 1449255736Sdavidch 1450255736Sdavidch int pcie_bus; /* PCIe bus number */ 1451255736Sdavidch int pcie_device; /* PCIe device/slot number */ 1452255736Sdavidch int pcie_func; /* PCIe function number */ 1453255736Sdavidch 1454255736Sdavidch uint8_t pfunc_rel; /* function relative */ 1455255736Sdavidch uint8_t pfunc_abs; /* function absolute */ 1456255736Sdavidch uint8_t path_id; /* function absolute */ 1457255736Sdavidch#define SC_PATH(sc) (sc->path_id) 1458255736Sdavidch#define SC_PORT(sc) (sc->pfunc_rel & 1) 1459255736Sdavidch#define SC_FUNC(sc) (sc->pfunc_rel) 1460255736Sdavidch#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1461255736Sdavidch#define SC_VN(sc) (sc->pfunc_rel >> 1) 1462255736Sdavidch#define SC_L_ID(sc) (SC_VN(sc) << 2) 1463255736Sdavidch#define PORT_ID(sc) SC_PORT(sc) 1464255736Sdavidch#define PATH_ID(sc) SC_PATH(sc) 1465255736Sdavidch#define VNIC_ID(sc) SC_VN(sc) 1466255736Sdavidch#define FUNC_ID(sc) SC_FUNC(sc) 1467255736Sdavidch#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1468255736Sdavidch#define SC_FW_MB_IDX_VN(sc, vn) \ 1469255736Sdavidch (SC_PORT(sc) + (vn) * \ 1470255736Sdavidch ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1471255736Sdavidch#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1472255736Sdavidch 1473255736Sdavidch int if_capen; /* enabled interface capabilities */ 1474255736Sdavidch 1475255736Sdavidch struct bxe_devinfo devinfo; 1476255736Sdavidch char fw_ver_str[32]; 1477255736Sdavidch char mf_mode_str[32]; 1478255736Sdavidch char pci_link_str[32]; 1479255736Sdavidch 1480255736Sdavidch const struct iro *iro_array; 1481255736Sdavidch 1482255736Sdavidch#ifdef BXE_CORE_LOCK_SX 1483255736Sdavidch struct sx core_sx; 1484255736Sdavidch char core_sx_name[32]; 1485255736Sdavidch#else 1486255736Sdavidch struct mtx core_mtx; 1487255736Sdavidch char core_mtx_name[32]; 1488255736Sdavidch#endif 1489255736Sdavidch struct mtx sp_mtx; 1490255736Sdavidch char sp_mtx_name[32]; 1491255736Sdavidch struct mtx dmae_mtx; 1492255736Sdavidch char dmae_mtx_name[32]; 1493255736Sdavidch struct mtx fwmb_mtx; 1494255736Sdavidch char fwmb_mtx_name[32]; 1495255736Sdavidch struct mtx print_mtx; 1496255736Sdavidch char print_mtx_name[32]; 1497255736Sdavidch struct mtx stats_mtx; 1498255736Sdavidch char stats_mtx_name[32]; 1499255736Sdavidch struct mtx mcast_mtx; 1500255736Sdavidch char mcast_mtx_name[32]; 1501255736Sdavidch 1502255736Sdavidch#ifdef BXE_CORE_LOCK_SX 1503255736Sdavidch#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1504255736Sdavidch#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1505255736Sdavidch#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1506255736Sdavidch#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1507255736Sdavidch#else 1508255736Sdavidch#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1509255736Sdavidch#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1510255736Sdavidch#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1511255736Sdavidch#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1512255736Sdavidch#endif 1513255736Sdavidch 1514255736Sdavidch#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1515255736Sdavidch#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1516255736Sdavidch#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1517255736Sdavidch 1518255736Sdavidch#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1519255736Sdavidch#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1520255736Sdavidch#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1521255736Sdavidch 1522255736Sdavidch#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1523255736Sdavidch#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1524255736Sdavidch#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1525255736Sdavidch 1526255736Sdavidch#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1527255736Sdavidch#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1528255736Sdavidch#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1529255736Sdavidch 1530255736Sdavidch#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1531255736Sdavidch#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1532255736Sdavidch#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1533255736Sdavidch 1534255736Sdavidch#if __FreeBSD_version < 800000 1535255736Sdavidch#define BXE_MCAST_LOCK(sc) \ 1536255736Sdavidch do { \ 1537255736Sdavidch mtx_lock(&sc->mcast_mtx); \ 1538255736Sdavidch IF_ADDR_LOCK(sc->ifnet); \ 1539255736Sdavidch } while (0) 1540255736Sdavidch#define BXE_MCAST_UNLOCK(sc) \ 1541255736Sdavidch do { \ 1542255736Sdavidch IF_ADDR_UNLOCK(sc->ifnet); \ 1543255736Sdavidch mtx_unlock(&sc->mcast_mtx); \ 1544255736Sdavidch } while (0) 1545255736Sdavidch#else 1546255736Sdavidch#define BXE_MCAST_LOCK(sc) \ 1547255736Sdavidch do { \ 1548255736Sdavidch mtx_lock(&sc->mcast_mtx); \ 1549255736Sdavidch if_maddr_rlock(sc->ifnet); \ 1550255736Sdavidch } while (0) 1551255736Sdavidch#define BXE_MCAST_UNLOCK(sc) \ 1552255736Sdavidch do { \ 1553255736Sdavidch if_maddr_runlock(sc->ifnet); \ 1554255736Sdavidch mtx_unlock(&sc->mcast_mtx); \ 1555255736Sdavidch } while (0) 1556255736Sdavidch#endif 1557255736Sdavidch#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1558255736Sdavidch 1559255736Sdavidch int dmae_ready; 1560255736Sdavidch#define DMAE_READY(sc) (sc->dmae_ready) 1561255736Sdavidch 1562255736Sdavidch struct ecore_credit_pool_obj vlans_pool; 1563255736Sdavidch struct ecore_credit_pool_obj macs_pool; 1564255736Sdavidch struct ecore_rx_mode_obj rx_mode_obj; 1565255736Sdavidch struct ecore_mcast_obj mcast_obj; 1566255736Sdavidch struct ecore_rss_config_obj rss_conf_obj; 1567255736Sdavidch struct ecore_func_sp_obj func_obj; 1568255736Sdavidch 1569255736Sdavidch uint16_t fw_seq; 1570255736Sdavidch uint16_t fw_drv_pulse_wr_seq; 1571255736Sdavidch uint32_t func_stx; 1572255736Sdavidch 1573255736Sdavidch struct elink_params link_params; 1574255736Sdavidch struct elink_vars link_vars; 1575255736Sdavidch uint32_t link_cnt; 1576255736Sdavidch struct bxe_link_report_data last_reported_link; 1577255736Sdavidch char mac_addr_str[32]; 1578255736Sdavidch 1579255736Sdavidch int last_reported_link_state; 1580255736Sdavidch 1581255736Sdavidch int tx_ring_size; 1582255736Sdavidch int rx_ring_size; 1583255736Sdavidch int wol; 1584255736Sdavidch 1585255736Sdavidch int is_leader; 1586255736Sdavidch int recovery_state; 1587255736Sdavidch#define BXE_RECOVERY_DONE 1 1588255736Sdavidch#define BXE_RECOVERY_INIT 2 1589255736Sdavidch#define BXE_RECOVERY_WAIT 3 1590255736Sdavidch#define BXE_RECOVERY_FAILED 4 1591255736Sdavidch#define BXE_RECOVERY_NIC_LOADING 5 1592255736Sdavidch 1593255736Sdavidch uint32_t rx_mode; 1594255736Sdavidch#define BXE_RX_MODE_NONE 0 1595255736Sdavidch#define BXE_RX_MODE_NORMAL 1 1596255736Sdavidch#define BXE_RX_MODE_ALLMULTI 2 1597255736Sdavidch#define BXE_RX_MODE_PROMISC 3 1598255736Sdavidch#define BXE_MAX_MULTICAST 64 1599255736Sdavidch 1600255736Sdavidch struct bxe_port port; 1601255736Sdavidch 1602255736Sdavidch struct cmng_init cmng; 1603255736Sdavidch 1604255736Sdavidch /* user configs */ 1605255736Sdavidch int num_queues; 1606255736Sdavidch int max_rx_bufs; 1607255736Sdavidch int hc_rx_ticks; 1608255736Sdavidch int hc_tx_ticks; 1609258187Sedavis int rx_budget; 1610255736Sdavidch int max_aggregation_size; 1611255736Sdavidch int mrrs; 1612255736Sdavidch int autogreeen; 1613255736Sdavidch#define AUTO_GREEN_HW_DEFAULT 0 1614255736Sdavidch#define AUTO_GREEN_FORCE_ON 1 1615255736Sdavidch#define AUTO_GREEN_FORCE_OFF 2 1616255736Sdavidch int interrupt_mode; 1617255736Sdavidch#define INTR_MODE_INTX 0 1618255736Sdavidch#define INTR_MODE_MSI 1 1619255736Sdavidch#define INTR_MODE_MSIX 2 1620255736Sdavidch int udp_rss; 1621255736Sdavidch 1622255736Sdavidch /* interrupt allocations */ 1623255736Sdavidch struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1624255736Sdavidch int intr_count; 1625255736Sdavidch uint8_t igu_dsb_id; 1626255736Sdavidch uint8_t igu_base_sb; 1627255736Sdavidch uint8_t igu_sb_cnt; 1628255736Sdavidch //uint8_t min_msix_vec_cnt; 1629255736Sdavidch uint32_t igu_base_addr; 1630255736Sdavidch //bus_addr_t def_status_blk_mapping; 1631255736Sdavidch uint8_t base_fw_ndsb; 1632255736Sdavidch#define DEF_SB_IGU_ID 16 1633255736Sdavidch#define DEF_SB_ID HC_SP_SB_ID 1634255736Sdavidch 1635255736Sdavidch /* parent bus DMA tag */ 1636255736Sdavidch bus_dma_tag_t parent_dma_tag; 1637255736Sdavidch 1638255736Sdavidch /* default status block */ 1639255736Sdavidch struct bxe_dma def_sb_dma; 1640255736Sdavidch struct host_sp_status_block *def_sb; 1641255736Sdavidch uint16_t def_idx; 1642255736Sdavidch uint16_t def_att_idx; 1643255736Sdavidch uint32_t attn_state; 1644255736Sdavidch struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1645255736Sdavidch 1646255736Sdavidch/* general SP events - stats query, cfc delete, etc */ 1647255736Sdavidch#define HC_SP_INDEX_ETH_DEF_CONS 3 1648255736Sdavidch/* EQ completions */ 1649255736Sdavidch#define HC_SP_INDEX_EQ_CONS 7 1650255736Sdavidch/* FCoE L2 connection completions */ 1651255736Sdavidch#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1652255736Sdavidch#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1653255736Sdavidch/* iSCSI L2 */ 1654255736Sdavidch#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1655255736Sdavidch#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1656255736Sdavidch 1657255736Sdavidch /* event queue */ 1658255736Sdavidch struct bxe_dma eq_dma; 1659255736Sdavidch union event_ring_elem *eq; 1660255736Sdavidch uint16_t eq_prod; 1661255736Sdavidch uint16_t eq_cons; 1662255736Sdavidch uint16_t *eq_cons_sb; 1663255736Sdavidch#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1664255736Sdavidch#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1665255736Sdavidch#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1666255736Sdavidch#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1667255736Sdavidch#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1668255736Sdavidch#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1669255736Sdavidch/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1670255736Sdavidch#define NEXT_EQ_IDX(x) \ 1671255736Sdavidch ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1672255736Sdavidch ((x) + 2) : ((x) + 1)) 1673255736Sdavidch/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1674255736Sdavidch#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1675255736Sdavidch 1676255736Sdavidch /* slow path */ 1677255736Sdavidch struct bxe_dma sp_dma; 1678255736Sdavidch struct bxe_slowpath *sp; 1679255736Sdavidch unsigned long sp_state; 1680255736Sdavidch 1681255736Sdavidch /* slow path queue */ 1682255736Sdavidch struct bxe_dma spq_dma; 1683255736Sdavidch struct eth_spe *spq; 1684255736Sdavidch#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1685255736Sdavidch#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1686255736Sdavidch#define MAX_SPQ_PENDING 8 1687255736Sdavidch 1688255736Sdavidch uint16_t spq_prod_idx; 1689255736Sdavidch struct eth_spe *spq_prod_bd; 1690255736Sdavidch struct eth_spe *spq_last_bd; 1691255736Sdavidch uint16_t *dsb_sp_prod; 1692255736Sdavidch //uint16_t *spq_hw_con; 1693255736Sdavidch //uint16_t spq_left; 1694255736Sdavidch 1695255736Sdavidch volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1696255736Sdavidch volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1697255736Sdavidch 1698255736Sdavidch /* fw decompression buffer */ 1699255736Sdavidch struct bxe_dma gz_buf_dma; 1700255736Sdavidch void *gz_buf; 1701255736Sdavidch z_streamp gz_strm; 1702255736Sdavidch uint32_t gz_outlen; 1703255736Sdavidch#define GUNZIP_BUF(sc) (sc->gz_buf) 1704255736Sdavidch#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1705255736Sdavidch#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1706255736Sdavidch#define FW_BUF_SIZE 0x40000 1707255736Sdavidch 1708255736Sdavidch const struct raw_op *init_ops; 1709255736Sdavidch const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1710255736Sdavidch const uint32_t *init_data; /* data blob, 32 bit granularity */ 1711255736Sdavidch uint32_t init_mode_flags; 1712255736Sdavidch#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1713255736Sdavidch /* PRAM blobs - raw data */ 1714255736Sdavidch const uint8_t *tsem_int_table_data; 1715255736Sdavidch const uint8_t *tsem_pram_data; 1716255736Sdavidch const uint8_t *usem_int_table_data; 1717255736Sdavidch const uint8_t *usem_pram_data; 1718255736Sdavidch const uint8_t *xsem_int_table_data; 1719255736Sdavidch const uint8_t *xsem_pram_data; 1720255736Sdavidch const uint8_t *csem_int_table_data; 1721255736Sdavidch const uint8_t *csem_pram_data; 1722255736Sdavidch#define INIT_OPS(sc) (sc->init_ops) 1723255736Sdavidch#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1724255736Sdavidch#define INIT_DATA(sc) (sc->init_data) 1725255736Sdavidch#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1726255736Sdavidch#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1727255736Sdavidch#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1728255736Sdavidch#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1729255736Sdavidch#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1730255736Sdavidch#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1731255736Sdavidch#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1732255736Sdavidch#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1733255736Sdavidch 1734255736Sdavidch /* ILT 1735255736Sdavidch * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1736255736Sdavidch * context size we need 8 ILT entries. 1737255736Sdavidch */ 1738255736Sdavidch#define ILT_MAX_L2_LINES 8 1739255736Sdavidch struct hw_context context[ILT_MAX_L2_LINES]; 1740255736Sdavidch struct ecore_ilt *ilt; 1741255736Sdavidch#define ILT_MAX_LINES 256 1742255736Sdavidch 1743255736Sdavidch/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1744255736Sdavidch#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1745255736Sdavidch/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1746255736Sdavidch#if 1 1747255736Sdavidch#define BXE_L2_MAX_CID(sc) \ 1748255736Sdavidch (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1749255736Sdavidch#else 1750255736Sdavidch#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1751255736Sdavidch (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1752255736Sdavidch#endif 1753255736Sdavidch#if 1 1754255736Sdavidch#define BXE_L2_CID_COUNT(sc) \ 1755255736Sdavidch (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1756255736Sdavidch#else 1757255736Sdavidch#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1758255736Sdavidch (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1759255736Sdavidch#endif 1760255736Sdavidch#define L2_ILT_LINES(sc) \ 1761255736Sdavidch (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1762255736Sdavidch 1763255736Sdavidch int qm_cid_count; 1764255736Sdavidch 1765255736Sdavidch uint8_t dropless_fc; 1766255736Sdavidch 1767255736Sdavidch#if 0 1768255736Sdavidch struct bxe_dma *t2; 1769255736Sdavidch#endif 1770255736Sdavidch 1771255736Sdavidch /* total number of FW statistics requests */ 1772255736Sdavidch uint8_t fw_stats_num; 1773255736Sdavidch /* 1774255736Sdavidch * This is a memory buffer that will contain both statistics ramrod 1775255736Sdavidch * request and data. 1776255736Sdavidch */ 1777255736Sdavidch struct bxe_dma fw_stats_dma; 1778255736Sdavidch /* 1779255736Sdavidch * FW statistics request shortcut (points at the beginning of fw_stats 1780255736Sdavidch * buffer). 1781255736Sdavidch */ 1782255736Sdavidch int fw_stats_req_size; 1783255736Sdavidch struct bxe_fw_stats_req *fw_stats_req; 1784255736Sdavidch bus_addr_t fw_stats_req_mapping; 1785255736Sdavidch /* 1786255736Sdavidch * FW statistics data shortcut (points at the beginning of fw_stats 1787255736Sdavidch * buffer + fw_stats_req_size). 1788255736Sdavidch */ 1789255736Sdavidch int fw_stats_data_size; 1790255736Sdavidch struct bxe_fw_stats_data *fw_stats_data; 1791255736Sdavidch bus_addr_t fw_stats_data_mapping; 1792255736Sdavidch 1793255736Sdavidch /* tracking a pending STAT_QUERY ramrod */ 1794255736Sdavidch uint16_t stats_pending; 1795255736Sdavidch /* number of completed statistics ramrods */ 1796255736Sdavidch uint16_t stats_comp; 1797255736Sdavidch uint16_t stats_counter; 1798255736Sdavidch uint8_t stats_init; 1799255736Sdavidch int stats_state; 1800255736Sdavidch 1801255736Sdavidch struct bxe_eth_stats eth_stats; 1802255736Sdavidch struct host_func_stats func_stats; 1803255736Sdavidch struct bxe_eth_stats_old eth_stats_old; 1804255736Sdavidch struct bxe_net_stats_old net_stats_old; 1805255736Sdavidch struct bxe_fw_port_stats_old fw_stats_old; 1806255736Sdavidch 1807255736Sdavidch struct dmae_command stats_dmae; /* used by dmae command loader */ 1808255736Sdavidch int executer_idx; 1809255736Sdavidch 1810255736Sdavidch int mtu; 1811255736Sdavidch 1812255736Sdavidch /* LLDP params */ 1813255736Sdavidch struct bxe_config_lldp_params lldp_config_params; 1814255736Sdavidch /* DCB support on/off */ 1815255736Sdavidch int dcb_state; 1816255736Sdavidch#define BXE_DCB_STATE_OFF 0 1817255736Sdavidch#define BXE_DCB_STATE_ON 1 1818255736Sdavidch /* DCBX engine mode */ 1819255736Sdavidch int dcbx_enabled; 1820255736Sdavidch#define BXE_DCBX_ENABLED_OFF 0 1821255736Sdavidch#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1822255736Sdavidch#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1823255736Sdavidch#define BXE_DCBX_ENABLED_INVALID -1 1824255736Sdavidch uint8_t dcbx_mode_uset; 1825255736Sdavidch struct bxe_config_dcbx_params dcbx_config_params; 1826255736Sdavidch struct bxe_dcbx_port_params dcbx_port_params; 1827255736Sdavidch int dcb_version; 1828255736Sdavidch 1829255736Sdavidch uint8_t cnic_support; 1830255736Sdavidch uint8_t cnic_enabled; 1831255736Sdavidch uint8_t cnic_loaded; 1832255736Sdavidch#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1833255736Sdavidch#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1834255736Sdavidch#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1835255736Sdavidch 1836255736Sdavidch /* multiple tx classes of service */ 1837255736Sdavidch uint8_t max_cos; 1838255736Sdavidch#define BXE_MAX_PRIORITY 8 1839255736Sdavidch /* priority to cos mapping */ 1840255736Sdavidch uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1841255736Sdavidch 1842255736Sdavidch int panic; 1843255736Sdavidch}; /* struct bxe_softc */ 1844255736Sdavidch 1845255736Sdavidch/* IOCTL sub-commands for edebug and firmware upgrade */ 1846255736Sdavidch#define BXE_IOC_RD_NVRAM 1 1847255736Sdavidch#define BXE_IOC_WR_NVRAM 2 1848255736Sdavidch#define BXE_IOC_STATS_SHOW_NUM 3 1849255736Sdavidch#define BXE_IOC_STATS_SHOW_STR 4 1850255736Sdavidch#define BXE_IOC_STATS_SHOW_CNT 5 1851255736Sdavidch 1852255736Sdavidchstruct bxe_nvram_data { 1853255736Sdavidch uint32_t op; /* ioctl sub-command */ 1854255736Sdavidch uint32_t offset; 1855255736Sdavidch uint32_t len; 1856255736Sdavidch uint32_t value[1]; /* variable */ 1857255736Sdavidch}; 1858255736Sdavidch 1859255736Sdavidchunion bxe_stats_show_data { 1860255736Sdavidch uint32_t op; /* ioctl sub-command */ 1861255736Sdavidch 1862255736Sdavidch struct { 1863255736Sdavidch uint32_t num; /* return number of stats */ 1864255736Sdavidch uint32_t len; /* length of each string item */ 1865255736Sdavidch } desc; 1866255736Sdavidch 1867255736Sdavidch /* variable length... */ 1868255736Sdavidch char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1869255736Sdavidch 1870255736Sdavidch /* variable length... */ 1871255736Sdavidch uint64_t stats[1]; /* holds all stats */ 1872255736Sdavidch}; 1873255736Sdavidch 1874255736Sdavidch/* function init flags */ 1875255736Sdavidch#define FUNC_FLG_RSS 0x0001 1876255736Sdavidch#define FUNC_FLG_STATS 0x0002 1877255736Sdavidch/* FUNC_FLG_UNMATCHED 0x0004 */ 1878255736Sdavidch#define FUNC_FLG_TPA 0x0008 1879255736Sdavidch#define FUNC_FLG_SPQ 0x0010 1880255736Sdavidch#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1881255736Sdavidch 1882255736Sdavidchstruct bxe_func_init_params { 1883255736Sdavidch bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1884255736Sdavidch bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1885255736Sdavidch uint16_t func_flgs; 1886255736Sdavidch uint16_t func_id; /* abs function id */ 1887255736Sdavidch uint16_t pf_id; 1888255736Sdavidch uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1889255736Sdavidch}; 1890255736Sdavidch 1891255736Sdavidch/* memory resources reside at BARs 0, 2, 4 */ 1892255736Sdavidch/* Run `pciconf -lb` to see mappings */ 1893255736Sdavidch#define BAR0 0 1894255736Sdavidch#define BAR1 2 1895255736Sdavidch#define BAR2 4 1896255736Sdavidch 1897255736Sdavidch#ifdef BXE_REG_NO_INLINE 1898255736Sdavidch 1899255736Sdavidchuint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1900255736Sdavidchuint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1901255736Sdavidchuint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1902255736Sdavidch 1903255736Sdavidchvoid bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1904255736Sdavidchvoid bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1905255736Sdavidchvoid bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1906255736Sdavidch 1907255736Sdavidch#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1908255736Sdavidch#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1909255736Sdavidch#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1910255736Sdavidch 1911255736Sdavidch#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1912255736Sdavidch#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1913255736Sdavidch#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1914255736Sdavidch 1915255736Sdavidch#else /* not BXE_REG_NO_INLINE */ 1916255736Sdavidch 1917255736Sdavidch#define REG_WR8(sc, offset, val) \ 1918255736Sdavidch bus_space_write_1(sc->bar[BAR0].tag, \ 1919255736Sdavidch sc->bar[BAR0].handle, \ 1920255736Sdavidch offset, val) 1921255736Sdavidch 1922255736Sdavidch#define REG_WR16(sc, offset, val) \ 1923255736Sdavidch bus_space_write_2(sc->bar[BAR0].tag, \ 1924255736Sdavidch sc->bar[BAR0].handle, \ 1925255736Sdavidch offset, val) 1926255736Sdavidch 1927255736Sdavidch#define REG_WR32(sc, offset, val) \ 1928255736Sdavidch bus_space_write_4(sc->bar[BAR0].tag, \ 1929255736Sdavidch sc->bar[BAR0].handle, \ 1930255736Sdavidch offset, val) 1931255736Sdavidch 1932255736Sdavidch#define REG_RD8(sc, offset) \ 1933255736Sdavidch bus_space_read_1(sc->bar[BAR0].tag, \ 1934255736Sdavidch sc->bar[BAR0].handle, \ 1935255736Sdavidch offset) 1936255736Sdavidch 1937255736Sdavidch#define REG_RD16(sc, offset) \ 1938255736Sdavidch bus_space_read_2(sc->bar[BAR0].tag, \ 1939255736Sdavidch sc->bar[BAR0].handle, \ 1940255736Sdavidch offset) 1941255736Sdavidch 1942255736Sdavidch#define REG_RD32(sc, offset) \ 1943255736Sdavidch bus_space_read_4(sc->bar[BAR0].tag, \ 1944255736Sdavidch sc->bar[BAR0].handle, \ 1945255736Sdavidch offset) 1946255736Sdavidch 1947255736Sdavidch#endif /* BXE_REG_NO_INLINE */ 1948255736Sdavidch 1949255736Sdavidch#define REG_RD(sc, offset) REG_RD32(sc, offset) 1950255736Sdavidch#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1951255736Sdavidch 1952255736Sdavidch#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1953255736Sdavidch#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1954255736Sdavidch 1955255736Sdavidch#define BXE_SP(sc, var) (&(sc)->sp->var) 1956255736Sdavidch#define BXE_SP_MAPPING(sc, var) \ 1957255736Sdavidch (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1958255736Sdavidch 1959255736Sdavidch#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1960255736Sdavidch#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1961255736Sdavidch 1962255736Sdavidch#if 0 1963255736Sdavidch#define bxe_fp(sc, nr, var) ((sc)->fp[nr].var) 1964255736Sdavidch#define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index]) 1965255736Sdavidch#define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index]) 1966255736Sdavidch#define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats) 1967255736Sdavidch#endif 1968255736Sdavidch 1969255736Sdavidch#define REG_RD_DMAE(sc, offset, valp, len32) \ 1970255736Sdavidch do { \ 1971255736Sdavidch bxe_read_dmae(sc, offset, len32); \ 1972255736Sdavidch memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1973255736Sdavidch } while (0) 1974255736Sdavidch 1975255736Sdavidch#define REG_WR_DMAE(sc, offset, valp, len32) \ 1976255736Sdavidch do { \ 1977255736Sdavidch memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1978255736Sdavidch bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1979255736Sdavidch } while (0) 1980255736Sdavidch 1981255736Sdavidch#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1982255736Sdavidch REG_WR_DMAE(sc, offset, valp, len32) 1983255736Sdavidch 1984255736Sdavidch#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1985255736Sdavidch REG_RD_DMAE(sc, offset, valp, len32) 1986255736Sdavidch 1987255736Sdavidch#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1988255736Sdavidch do { \ 1989255736Sdavidch /* if (le32_swap) { */ \ 1990255736Sdavidch /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1991255736Sdavidch /* } */ \ 1992255736Sdavidch memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1993255736Sdavidch ecore_write_big_buf_wb(sc, addr, len32); \ 1994255736Sdavidch } while (0) 1995255736Sdavidch 1996255736Sdavidch#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1997255736Sdavidch#define BXE_DB_SHIFT 7 /* 128 bytes */ 1998255736Sdavidch#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1999255736Sdavidch#error "Minimum DB doorbell stride is 8" 2000255736Sdavidch#endif 2001255736Sdavidch#define DPM_TRIGGER_TYPE 0x40 2002255736Sdavidch#define DOORBELL(sc, cid, val) \ 2003255736Sdavidch do { \ 2004255736Sdavidch bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 2005255736Sdavidch ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 2006255736Sdavidch (uint32_t)val); \ 2007255736Sdavidch } while(0) 2008255736Sdavidch 2009255736Sdavidch#define SHMEM_ADDR(sc, field) \ 2010255736Sdavidch (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 2011255736Sdavidch#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 2012255736Sdavidch#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 2013255736Sdavidch#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 2014255736Sdavidch 2015255736Sdavidch#define SHMEM2_ADDR(sc, field) \ 2016255736Sdavidch (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 2017255736Sdavidch#define SHMEM2_HAS(sc, field) \ 2018255736Sdavidch (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 2019255736Sdavidch offsetof(struct shmem2_region, field))) 2020255736Sdavidch#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 2021255736Sdavidch#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 2022255736Sdavidch 2023255736Sdavidch#define MFCFG_ADDR(sc, field) \ 2024255736Sdavidch (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 2025255736Sdavidch#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 2026255736Sdavidch#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 2027255736Sdavidch#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 2028255736Sdavidch 2029255736Sdavidch/* DMAE command defines */ 2030255736Sdavidch 2031255736Sdavidch#define DMAE_TIMEOUT -1 2032255736Sdavidch#define DMAE_PCI_ERROR -2 /* E2 and onward */ 2033255736Sdavidch#define DMAE_NOT_RDY -3 2034255736Sdavidch#define DMAE_PCI_ERR_FLAG 0x80000000 2035255736Sdavidch 2036255736Sdavidch#define DMAE_SRC_PCI 0 2037255736Sdavidch#define DMAE_SRC_GRC 1 2038255736Sdavidch 2039255736Sdavidch#define DMAE_DST_NONE 0 2040255736Sdavidch#define DMAE_DST_PCI 1 2041255736Sdavidch#define DMAE_DST_GRC 2 2042255736Sdavidch 2043255736Sdavidch#define DMAE_COMP_PCI 0 2044255736Sdavidch#define DMAE_COMP_GRC 1 2045255736Sdavidch 2046255736Sdavidch#define DMAE_COMP_REGULAR 0 2047255736Sdavidch#define DMAE_COM_SET_ERR 1 2048255736Sdavidch 2049255736Sdavidch#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT) 2050255736Sdavidch#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT) 2051255736Sdavidch#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT) 2052255736Sdavidch#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT) 2053255736Sdavidch 2054255736Sdavidch#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT) 2055255736Sdavidch#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT) 2056255736Sdavidch 2057255736Sdavidch#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2058255736Sdavidch#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2059255736Sdavidch#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2060255736Sdavidch#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2061255736Sdavidch 2062255736Sdavidch#define DMAE_CMD_PORT_0 0 2063255736Sdavidch#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2064255736Sdavidch 2065255736Sdavidch#define DMAE_SRC_PF 0 2066255736Sdavidch#define DMAE_SRC_VF 1 2067255736Sdavidch 2068255736Sdavidch#define DMAE_DST_PF 0 2069255736Sdavidch#define DMAE_DST_VF 1 2070255736Sdavidch 2071255736Sdavidch#define DMAE_C_SRC 0 2072255736Sdavidch#define DMAE_C_DST 1 2073255736Sdavidch 2074255736Sdavidch#define DMAE_LEN32_RD_MAX 0x80 2075255736Sdavidch#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2076255736Sdavidch 2077255736Sdavidch#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2078255736Sdavidch 2079255736Sdavidch#define MAX_DMAE_C_PER_PORT 8 2080255736Sdavidch#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2081255736Sdavidch#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2082255736Sdavidch 2083255736Sdavidchstatic const uint32_t dmae_reg_go_c[] = { 2084255736Sdavidch DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2085255736Sdavidch DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2086255736Sdavidch DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2087255736Sdavidch DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2088255736Sdavidch}; 2089255736Sdavidch 2090255736Sdavidch#define ATTN_NIG_FOR_FUNC (1L << 8) 2091255736Sdavidch#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2092255736Sdavidch#define GPIO_2_FUNC (1L << 10) 2093255736Sdavidch#define GPIO_3_FUNC (1L << 11) 2094255736Sdavidch#define GPIO_4_FUNC (1L << 12) 2095255736Sdavidch#define ATTN_GENERAL_ATTN_1 (1L << 13) 2096255736Sdavidch#define ATTN_GENERAL_ATTN_2 (1L << 14) 2097255736Sdavidch#define ATTN_GENERAL_ATTN_3 (1L << 15) 2098255736Sdavidch#define ATTN_GENERAL_ATTN_4 (1L << 13) 2099255736Sdavidch#define ATTN_GENERAL_ATTN_5 (1L << 14) 2100255736Sdavidch#define ATTN_GENERAL_ATTN_6 (1L << 15) 2101255736Sdavidch#define ATTN_HARD_WIRED_MASK 0xff00 2102255736Sdavidch#define ATTENTION_ID 4 2103255736Sdavidch 2104255736Sdavidch#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2105255736Sdavidch AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2106255736Sdavidch 2107255736Sdavidch#define MAX_IGU_ATTN_ACK_TO 100 2108255736Sdavidch 2109255736Sdavidch#define STORM_ASSERT_ARRAY_SIZE 50 2110255736Sdavidch 2111255736Sdavidch#define BXE_PMF_LINK_ASSERT(sc) \ 2112255736Sdavidch GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2113255736Sdavidch 2114255736Sdavidch#define BXE_MC_ASSERT_BITS \ 2115255736Sdavidch (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2116255736Sdavidch GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2117255736Sdavidch GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2118255736Sdavidch GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2119255736Sdavidch 2120255736Sdavidch#define BXE_MCP_ASSERT \ 2121255736Sdavidch GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2122255736Sdavidch 2123255736Sdavidch#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2124255736Sdavidch#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2125255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2126255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2127255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2128255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2129255736Sdavidch GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2130255736Sdavidch 2131255736Sdavidch#define MULTI_MASK 0x7f 2132255736Sdavidch 2133255736Sdavidch#define PFS_PER_PORT(sc) \ 2134255736Sdavidch ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2135255736Sdavidch#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2136255736Sdavidch 2137255736Sdavidch#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2138255736Sdavidch ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2139255736Sdavidch PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2140255736Sdavidch 2141255736Sdavidch#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2142255736Sdavidch for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2143255736Sdavidch (i) < MAX_FUNC_NUM; \ 2144255736Sdavidch (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2145255736Sdavidch 2146255736Sdavidch#define BXE_SWCID_SHIFT 17 2147255736Sdavidch#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2148255736Sdavidch 2149255736Sdavidch#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2150255736Sdavidch#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2151255736Sdavidch 2152255736Sdavidch#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2153255736Sdavidch#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2154255736Sdavidch#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2155255736Sdavidch#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2156255736Sdavidch#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2157255736Sdavidch 2158255736Sdavidch/* must be used on a CID before placing it on a HW ring */ 2159255736Sdavidch#define HW_CID(sc, x) \ 2160255736Sdavidch ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2161255736Sdavidch 2162255736Sdavidch#define SPEED_10 10 2163255736Sdavidch#define SPEED_100 100 2164255736Sdavidch#define SPEED_1000 1000 2165255736Sdavidch#define SPEED_2500 2500 2166255736Sdavidch#define SPEED_10000 10000 2167255736Sdavidch 2168255736Sdavidch#define PCI_PM_D0 1 2169255736Sdavidch#define PCI_PM_D3hot 2 2170255736Sdavidch 2171255736Sdavidchint bxe_test_bit(int nr, volatile unsigned long * addr); 2172255736Sdavidchvoid bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2173255736Sdavidchvoid bxe_clear_bit(int nr, volatile unsigned long * addr); 2174255736Sdavidchint bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2175255736Sdavidchint bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2176255736Sdavidchint bxe_cmpxchg(volatile int *addr, int old, int new); 2177255736Sdavidch 2178255736Sdavidchvoid bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2179255736Sdavidch uint32_t val); 2180255736Sdavidchuint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2181255736Sdavidch 2182255736Sdavidch 2183255736Sdavidchint bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2184255736Sdavidch struct bxe_dma *dma, const char *msg); 2185255736Sdavidchvoid bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2186255736Sdavidch 2187255736Sdavidchuint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2188255736Sdavidchuint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2189255736Sdavidchuint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2190255736Sdavidch uint8_t dst_type, uint8_t with_comp, 2191255736Sdavidch uint8_t comp_type); 2192255736Sdavidchvoid bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx); 2193255736Sdavidchvoid bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2194255736Sdavidchvoid bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2195255736Sdavidch uint32_t dst_addr, uint32_t len32); 2196255736Sdavidchvoid bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2197255736Sdavidch uint32_t addr, uint32_t len); 2198255736Sdavidch 2199255736Sdavidchvoid bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2200255736Sdavidch uint32_t cid); 2201255736Sdavidchvoid bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2202255736Sdavidch uint8_t sb_index, uint8_t disable, 2203255736Sdavidch uint16_t usec); 2204255736Sdavidch 2205255736Sdavidchint bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2206255736Sdavidch uint32_t data_hi, uint32_t data_lo, int cmd_type); 2207255736Sdavidch 2208255736Sdavidchvoid bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2209255736Sdavidch uint8_t segment, uint16_t index, uint8_t op, 2210255736Sdavidch uint8_t update); 2211255736Sdavidch 2212255736Sdavidchvoid ecore_init_e1_firmware(struct bxe_softc *sc); 2213255736Sdavidchvoid ecore_init_e1h_firmware(struct bxe_softc *sc); 2214255736Sdavidchvoid ecore_init_e2_firmware(struct bxe_softc *sc); 2215255736Sdavidch 2216255736Sdavidchvoid ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2217255736Sdavidch size_t size, uint32_t *data); 2218255736Sdavidch 2219255736Sdavidch/*********************/ 2220255736Sdavidch/* LOGGING AND DEBUG */ 2221255736Sdavidch/*********************/ 2222255736Sdavidch 2223255736Sdavidch/* debug logging codepaths */ 2224255736Sdavidch#define DBG_LOAD 0x00000001 /* load and unload */ 2225255736Sdavidch#define DBG_INTR 0x00000002 /* interrupt handling */ 2226255736Sdavidch#define DBG_SP 0x00000004 /* slowpath handling */ 2227255736Sdavidch#define DBG_STATS 0x00000008 /* stats updates */ 2228255736Sdavidch#define DBG_TX 0x00000010 /* packet transmit */ 2229255736Sdavidch#define DBG_RX 0x00000020 /* packet receive */ 2230255736Sdavidch#define DBG_PHY 0x00000040 /* phy/link handling */ 2231255736Sdavidch#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2232255736Sdavidch#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2233255736Sdavidch#define DBG_REGS 0x00000200 /* register access */ 2234255736Sdavidch#define DBG_LRO 0x00000400 /* lro processing */ 2235255736Sdavidch#define DBG_ASSERT 0x80000000 /* debug assert */ 2236255736Sdavidch#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2237255736Sdavidch 2238255736Sdavidch#define DBASSERT(sc, exp, msg) \ 2239255736Sdavidch do { \ 2240255736Sdavidch if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2241255736Sdavidch if (__predict_false(!(exp))) { \ 2242255736Sdavidch panic msg; \ 2243255736Sdavidch } \ 2244255736Sdavidch } \ 2245255736Sdavidch } while (0) 2246255736Sdavidch 2247255736Sdavidch/* log a debug message */ 2248255736Sdavidch#define BLOGD(sc, codepath, format, args...) \ 2249255736Sdavidch do { \ 2250255736Sdavidch if (__predict_false(sc->debug & (codepath))) { \ 2251255736Sdavidch device_printf((sc)->dev, \ 2252255736Sdavidch "%s(%s:%d) " format, \ 2253255736Sdavidch __FUNCTION__, \ 2254255736Sdavidch __FILE__, \ 2255255736Sdavidch __LINE__, \ 2256255736Sdavidch ## args); \ 2257255736Sdavidch } \ 2258255736Sdavidch } while(0) 2259255736Sdavidch 2260255736Sdavidch/* log a info message */ 2261255736Sdavidch#define BLOGI(sc, format, args...) \ 2262255736Sdavidch do { \ 2263255736Sdavidch if (__predict_false(sc->debug)) { \ 2264255736Sdavidch device_printf((sc)->dev, \ 2265255736Sdavidch "%s(%s:%d) " format, \ 2266255736Sdavidch __FUNCTION__, \ 2267255736Sdavidch __FILE__, \ 2268255736Sdavidch __LINE__, \ 2269255736Sdavidch ## args); \ 2270255736Sdavidch } else { \ 2271255736Sdavidch device_printf((sc)->dev, \ 2272255736Sdavidch format, \ 2273255736Sdavidch ## args); \ 2274255736Sdavidch } \ 2275255736Sdavidch } while(0) 2276255736Sdavidch 2277255736Sdavidch/* log a warning message */ 2278255736Sdavidch#define BLOGW(sc, format, args...) \ 2279255736Sdavidch do { \ 2280255736Sdavidch if (__predict_false(sc->debug)) { \ 2281255736Sdavidch device_printf((sc)->dev, \ 2282255736Sdavidch "%s(%s:%d) WARNING: " format, \ 2283255736Sdavidch __FUNCTION__, \ 2284255736Sdavidch __FILE__, \ 2285255736Sdavidch __LINE__, \ 2286255736Sdavidch ## args); \ 2287255736Sdavidch } else { \ 2288255736Sdavidch device_printf((sc)->dev, \ 2289255736Sdavidch "WARNING: " format, \ 2290255736Sdavidch ## args); \ 2291255736Sdavidch } \ 2292255736Sdavidch } while(0) 2293255736Sdavidch 2294255736Sdavidch/* log a error message */ 2295255736Sdavidch#define BLOGE(sc, format, args...) \ 2296255736Sdavidch do { \ 2297255736Sdavidch if (__predict_false(sc->debug)) { \ 2298255736Sdavidch device_printf((sc)->dev, \ 2299255736Sdavidch "%s(%s:%d) ERROR: " format, \ 2300255736Sdavidch __FUNCTION__, \ 2301255736Sdavidch __FILE__, \ 2302255736Sdavidch __LINE__, \ 2303255736Sdavidch ## args); \ 2304255736Sdavidch } else { \ 2305255736Sdavidch device_printf((sc)->dev, \ 2306255736Sdavidch "ERROR: " format, \ 2307255736Sdavidch ## args); \ 2308255736Sdavidch } \ 2309255736Sdavidch } while(0) 2310255736Sdavidch 2311255736Sdavidch#define bxe_panic(sc, msg) \ 2312255736Sdavidch do { \ 2313255736Sdavidch panic msg; \ 2314255736Sdavidch } while (0) 2315255736Sdavidch 2316255736Sdavidch#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2317255736Sdavidch#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2318255736Sdavidch 2319255736Sdavidchvoid bxe_dump_mem(struct bxe_softc *sc, char *tag, 2320255736Sdavidch uint8_t *mem, uint32_t len); 2321255736Sdavidchvoid bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2322255736Sdavidch struct mbuf *m, uint8_t contents); 2323255736Sdavidch 2324255736Sdavidch/***********/ 2325255736Sdavidch/* INLINES */ 2326255736Sdavidch/***********/ 2327255736Sdavidch 2328255736Sdavidchstatic inline uint32_t 2329255736Sdavidchreg_poll(struct bxe_softc *sc, 2330255736Sdavidch uint32_t reg, 2331255736Sdavidch uint32_t expected, 2332255736Sdavidch int ms, 2333255736Sdavidch int wait) 2334255736Sdavidch{ 2335255736Sdavidch uint32_t val; 2336255736Sdavidch 2337255736Sdavidch do { 2338255736Sdavidch val = REG_RD(sc, reg); 2339255736Sdavidch if (val == expected) { 2340255736Sdavidch break; 2341255736Sdavidch } 2342255736Sdavidch ms -= wait; 2343255736Sdavidch DELAY(wait * 1000); 2344255736Sdavidch } while (ms > 0); 2345255736Sdavidch 2346255736Sdavidch return (val); 2347255736Sdavidch} 2348255736Sdavidch 2349255736Sdavidchstatic inline void 2350255736Sdavidchbxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2351255736Sdavidch{ 2352255736Sdavidch mb(); /* status block is written to by the chip */ 2353255736Sdavidch fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2354255736Sdavidch} 2355255736Sdavidch 2356255736Sdavidchstatic inline void 2357255736Sdavidchbxe_igu_ack_sb_gen(struct bxe_softc *sc, 2358255736Sdavidch uint8_t igu_sb_id, 2359255736Sdavidch uint8_t segment, 2360255736Sdavidch uint16_t index, 2361255736Sdavidch uint8_t op, 2362255736Sdavidch uint8_t update, 2363255736Sdavidch uint32_t igu_addr) 2364255736Sdavidch{ 2365255736Sdavidch struct igu_regular cmd_data = {0}; 2366255736Sdavidch 2367255736Sdavidch cmd_data.sb_id_and_flags = 2368255736Sdavidch ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2369255736Sdavidch (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2370255736Sdavidch (update << IGU_REGULAR_BUPDATE_SHIFT) | 2371255736Sdavidch (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2372255736Sdavidch 2373255736Sdavidch BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2374255736Sdavidch cmd_data.sb_id_and_flags, igu_addr); 2375255736Sdavidch REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2376255736Sdavidch 2377255736Sdavidch /* Make sure that ACK is written */ 2378255736Sdavidch bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2379255736Sdavidch BUS_SPACE_BARRIER_WRITE); 2380255736Sdavidch mb(); 2381255736Sdavidch} 2382255736Sdavidch 2383255736Sdavidchstatic inline void 2384255736Sdavidchbxe_hc_ack_sb(struct bxe_softc *sc, 2385255736Sdavidch uint8_t sb_id, 2386255736Sdavidch uint8_t storm, 2387255736Sdavidch uint16_t index, 2388255736Sdavidch uint8_t op, 2389255736Sdavidch uint8_t update) 2390255736Sdavidch{ 2391255736Sdavidch uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2392255736Sdavidch COMMAND_REG_INT_ACK); 2393255736Sdavidch struct igu_ack_register igu_ack; 2394255736Sdavidch 2395255736Sdavidch igu_ack.status_block_index = index; 2396255736Sdavidch igu_ack.sb_id_and_flags = 2397255736Sdavidch ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2398255736Sdavidch (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2399255736Sdavidch (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2400255736Sdavidch (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2401255736Sdavidch 2402255736Sdavidch REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2403255736Sdavidch 2404255736Sdavidch /* Make sure that ACK is written */ 2405255736Sdavidch bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2406255736Sdavidch BUS_SPACE_BARRIER_WRITE); 2407255736Sdavidch mb(); 2408255736Sdavidch} 2409255736Sdavidch 2410255736Sdavidchstatic inline void 2411255736Sdavidchbxe_ack_sb(struct bxe_softc *sc, 2412255736Sdavidch uint8_t igu_sb_id, 2413255736Sdavidch uint8_t storm, 2414255736Sdavidch uint16_t index, 2415255736Sdavidch uint8_t op, 2416255736Sdavidch uint8_t update) 2417255736Sdavidch{ 2418255736Sdavidch if (sc->devinfo.int_block == INT_BLOCK_HC) 2419255736Sdavidch bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2420255736Sdavidch else { 2421255736Sdavidch uint8_t segment; 2422255736Sdavidch if (CHIP_INT_MODE_IS_BC(sc)) { 2423255736Sdavidch segment = storm; 2424255736Sdavidch } else if (igu_sb_id != sc->igu_dsb_id) { 2425255736Sdavidch segment = IGU_SEG_ACCESS_DEF; 2426255736Sdavidch } else if (storm == ATTENTION_ID) { 2427255736Sdavidch segment = IGU_SEG_ACCESS_ATTN; 2428255736Sdavidch } else { 2429255736Sdavidch segment = IGU_SEG_ACCESS_DEF; 2430255736Sdavidch } 2431255736Sdavidch bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2432255736Sdavidch } 2433255736Sdavidch} 2434255736Sdavidch 2435255736Sdavidchstatic inline uint16_t 2436255736Sdavidchbxe_hc_ack_int(struct bxe_softc *sc) 2437255736Sdavidch{ 2438255736Sdavidch uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2439255736Sdavidch COMMAND_REG_SIMD_MASK); 2440255736Sdavidch uint32_t result = REG_RD(sc, hc_addr); 2441255736Sdavidch 2442255736Sdavidch mb(); 2443255736Sdavidch return (result); 2444255736Sdavidch} 2445255736Sdavidch 2446255736Sdavidchstatic inline uint16_t 2447255736Sdavidchbxe_igu_ack_int(struct bxe_softc *sc) 2448255736Sdavidch{ 2449255736Sdavidch uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2450255736Sdavidch uint32_t result = REG_RD(sc, igu_addr); 2451255736Sdavidch 2452255736Sdavidch BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2453255736Sdavidch result, igu_addr); 2454255736Sdavidch 2455255736Sdavidch mb(); 2456255736Sdavidch return (result); 2457255736Sdavidch} 2458255736Sdavidch 2459255736Sdavidchstatic inline uint16_t 2460255736Sdavidchbxe_ack_int(struct bxe_softc *sc) 2461255736Sdavidch{ 2462255736Sdavidch mb(); 2463255736Sdavidch if (sc->devinfo.int_block == INT_BLOCK_HC) { 2464255736Sdavidch return (bxe_hc_ack_int(sc)); 2465255736Sdavidch } else { 2466255736Sdavidch return (bxe_igu_ack_int(sc)); 2467255736Sdavidch } 2468255736Sdavidch} 2469255736Sdavidch 2470255736Sdavidchstatic inline int 2471255736Sdavidchfunc_by_vn(struct bxe_softc *sc, 2472255736Sdavidch int vn) 2473255736Sdavidch{ 2474255736Sdavidch return (2 * vn + SC_PORT(sc)); 2475255736Sdavidch} 2476255736Sdavidch 2477255736Sdavidch/* 2478255736Sdavidch * Statistics ID are global per chip/path, while Client IDs for E1x 2479255736Sdavidch * are per port. 2480255736Sdavidch */ 2481255736Sdavidchstatic inline uint8_t 2482255736Sdavidchbxe_stats_id(struct bxe_fastpath *fp) 2483255736Sdavidch{ 2484255736Sdavidch struct bxe_softc *sc = fp->sc; 2485255736Sdavidch 2486255736Sdavidch if (!CHIP_IS_E1x(sc)) { 2487255736Sdavidch#if 0 2488255736Sdavidch /* there are special statistics counters for FCoE 136..140 */ 2489255736Sdavidch if (IS_FCOE_FP(fp)) { 2490255736Sdavidch return (sc->cnic_base_cl_id + (sc->pf_num >> 1)); 2491255736Sdavidch } 2492255736Sdavidch#endif 2493255736Sdavidch return (fp->cl_id); 2494255736Sdavidch } 2495255736Sdavidch 2496255736Sdavidch return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2497255736Sdavidch} 2498255736Sdavidch 2499255736Sdavidch#endif /* __BXE_H__ */ 2500255736Sdavidch 2501