bxe.h revision 255736
175295Sdes/*- 275295Sdes * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 375295Sdes * 475295Sdes * Eric Davis <edavis@broadcom.com> 575295Sdes * David Christensen <davidch@broadcom.com> 675295Sdes * Gary Zambrano <zambrano@broadcom.com> 775295Sdes * 875295Sdes * Redistribution and use in source and binary forms, with or without 975295Sdes * modification, are permitted provided that the following conditions 1075295Sdes * are met: 1175295Sdes * 1275295Sdes * 1. Redistributions of source code must retain the above copyright 1375295Sdes * notice, this list of conditions and the following disclaimer. 1475295Sdes * 2. Redistributions in binary form must reproduce the above copyright 1575295Sdes * notice, this list of conditions and the following disclaimer in the 1675295Sdes * documentation and/or other materials provided with the distribution. 1775295Sdes * 3. Neither the name of Broadcom Corporation nor the name of its contributors 1875295Sdes * may be used to endorse or promote products derived from this software 1975295Sdes * without specific prior written consent. 2075295Sdes * 2175295Sdes * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 2275295Sdes * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2375295Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2475295Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 2575295Sdes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2675295Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2775295Sdes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2875295Sdes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2975295Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3075295Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3175295Sdes * THE POSSIBILITY OF SUCH DAMAGE. 3275295Sdes */ 3375295Sdes 3475295Sdes#ifndef __BXE_H__ 3575295Sdes#define __BXE_H__ 3677965Sdes 3775295Sdes#include <sys/cdefs.h> 3875295Sdes__FBSDID("$FreeBSD: head/sys/dev/bxe/bxe.h 255736 2013-09-20 20:18:49Z davidch $"); 3975295Sdes 4075295Sdes#include <sys/param.h> 4175295Sdes#include <sys/kernel.h> 4275295Sdes#include <sys/systm.h> 4375295Sdes#include <sys/lock.h> 4477998Sdes#include <sys/mutex.h> 4575295Sdes#include <sys/sx.h> 4675295Sdes#include <sys/module.h> 4775295Sdes#include <sys/endian.h> 4875295Sdes#include <sys/types.h> 4975295Sdes#include <sys/malloc.h> 5075295Sdes#include <sys/kobj.h> 5175295Sdes#include <sys/bus.h> 5275295Sdes#include <sys/rman.h> 5375295Sdes#include <sys/socket.h> 5475295Sdes#include <sys/sockio.h> 5575295Sdes#include <sys/sysctl.h> 5675295Sdes#include <sys/smp.h> 5775295Sdes#include <sys/bitstring.h> 5875295Sdes#include <sys/limits.h> 5975295Sdes#include <sys/queue.h> 6075295Sdes#include <sys/taskqueue.h> 6175295Sdes 6275295Sdes#include <net/if.h> 6375295Sdes#include <net/if_types.h> 6475295Sdes#include <net/if_arp.h> 6575295Sdes#include <net/ethernet.h> 6675295Sdes#include <net/if_dl.h> 6775295Sdes#include <net/if_media.h> 6875295Sdes#include <net/if_var.h> 6975295Sdes#include <net/if_vlan_var.h> 7075295Sdes#include <net/zlib.h> 7175295Sdes#include <net/bpf.h> 7275295Sdes 7375295Sdes#include <netinet/in.h> 7475295Sdes#include <netinet/ip.h> 7575295Sdes#include <netinet/ip6.h> 7675295Sdes#include <netinet/tcp.h> 7775295Sdes#include <netinet/udp.h> 7875295Sdes 7975295Sdes#include <dev/pci/pcireg.h> 8075295Sdes#include <dev/pci/pcivar.h> 8175295Sdes 8275295Sdes#include <machine/atomic.h> 8375295Sdes#include <machine/resource.h> 8475295Sdes#include <machine/endian.h> 8575295Sdes#include <machine/bus.h> 8675295Sdes#include <machine/in_cksum.h> 8775295Sdes 8877998Sdes#include "device_if.h" 8977998Sdes#include "bus_if.h" 9075295Sdes#include "pci_if.h" 9175295Sdes 9277998Sdes#if _BYTE_ORDER == _LITTLE_ENDIAN 9375295Sdes#ifndef LITTLE_ENDIAN 9475295Sdes#define LITTLE_ENDIAN 9577998Sdes#endif 9675295Sdes#ifndef __LITTLE_ENDIAN 9777998Sdes#define __LITTLE_ENDIAN 9877998Sdes#endif 9977998Sdes#undef BIG_ENDIAN 10075295Sdes#undef __BIG_ENDIAN 10175295Sdes#else /* _BIG_ENDIAN */ 10275295Sdes#ifndef BIG_ENDIAN 10375295Sdes#define BIG_ENDIAN 10475295Sdes#endif 10575295Sdes#ifndef __BIG_ENDIAN 10677998Sdes#define __BIG_ENDIAN 10777998Sdes#endif 10877998Sdes#undef LITTLE_ENDIAN 10977998Sdes#undef __LITTLE_ENDIAN 11077998Sdes#endif 11175295Sdes 11275295Sdes#include "ecore_mfw_req.h" 11375295Sdes#include "ecore_fw_defs.h" 11475295Sdes#include "ecore_hsi.h" 11577998Sdes#include "ecore_reg.h" 11675295Sdes#include "bxe_dcb.h" 11777998Sdes#include "bxe_stats.h" 11875295Sdes 11977998Sdes#include "bxe_elink.h" 12077998Sdes 12177998Sdes#if __FreeBSD_version < 800054 12275295Sdes#if defined(__i386__) || defined(__amd64__) 12375295Sdes#define mb() __asm volatile("mfence;" : : : "memory") 12475295Sdes#define wmb() __asm volatile("sfence;" : : : "memory") 12575295Sdes#define rmb() __asm volatile("lfence;" : : : "memory") 12675295Sdesstatic __inline void prefetch(void *x) 12775295Sdes{ 12875295Sdes __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 12975295Sdes} 13075295Sdes#else 13177998Sdes#define mb() 13275295Sdes#define rmb() 13375295Sdes#define wmb() 13475295Sdes#define prefetch(x) 13575295Sdes#endif 13675295Sdes#endif 13775295Sdes 13875295Sdes#if __FreeBSD_version >= 1000000 13975295Sdes#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 14077998Sdes#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 14177998Sdes#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 14275295Sdes#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 14375295Sdes#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 14475295Sdes#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 14575295Sdes#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 14677998Sdes#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 14775295Sdes#endif 14875295Sdes 14975295Sdes#ifndef ARRAY_SIZE 15075295Sdes#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 15175295Sdes#endif 15275295Sdes#ifndef ARRSIZE 15375295Sdes#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 15475295Sdes#endif 15575295Sdes#ifndef DIV_ROUND_UP 15675295Sdes#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 15775295Sdes#endif 15875295Sdes#ifndef roundup 15975295Sdes#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 16077998Sdes#endif 16175295Sdes#ifndef ilog2 16275295Sdesstatic inline 16375295Sdesint bxe_ilog2(int x) 16475295Sdes{ 16575295Sdes int log = 0; 16677998Sdes while (x >>= 1) log++; 16777998Sdes return (log); 16877998Sdes} 16977998Sdes#define ilog2(x) bxe_ilog2(x) 17077998Sdes#endif 17177998Sdes 17277998Sdes#include "ecore_sp.h" 17377998Sdes 17477998Sdes#define BRCM_VENDORID 0x14e4 17575295Sdes#define PCI_ANY_ID (uint16_t)(~0U) 17677998Sdes 17775295Sdesstruct bxe_device_type 17875295Sdes{ 179 uint16_t bxe_vid; 180 uint16_t bxe_did; 181 uint16_t bxe_svid; 182 uint16_t bxe_sdid; 183 char *bxe_name; 184}; 185 186#define BCM_PAGE_SHIFT 12 187#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 188#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 189#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 190 191#if BCM_PAGE_SIZE != 4096 192#error Page sizes other than 4KB are unsupported! 193#endif 194 195#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 196#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 197#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 198#else 199#define U64_LO(addr) ((uint32_t)(addr)) 200#define U64_HI(addr) (0) 201#endif 202#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 203 204#define SET_FLAG(value, mask, flag) \ 205 do { \ 206 (value) &= ~(mask); \ 207 (value) |= ((flag) << (mask##_SHIFT)); \ 208 } while (0) 209 210#define GET_FLAG(value, mask) \ 211 (((value) & (mask)) >> (mask##_SHIFT)) 212 213#define GET_FIELD(value, fname) \ 214 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 215 216#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 217#define BXE_TSO_MAX_SEGMENTS 32 218#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 219#define BXE_TSO_MAX_SEG_SIZE 4096 220 221/* dropless fc FW/HW related params */ 222#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 223#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 224 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 225 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 226#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 227#define FW_PREFETCH_CNT 16 228#define DROPLESS_FC_HEADROOM 100 229 230/******************/ 231/* RX SGE defines */ 232/******************/ 233 234#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 235#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 236#define RX_SGE_NEXT_PAGE_DESC_CNT 2 237#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 238#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 239#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 240#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 241#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 242#define RX_SGE(x) ((x) & RX_SGE_MAX) 243 244#define RX_SGE_NEXT(x) \ 245 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 246 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 247 248#define RX_SGE_MASK_ELEM_SZ 64 249#define RX_SGE_MASK_ELEM_SHIFT 6 250#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 251 252/* 253 * Creates a bitmask of all ones in less significant bits. 254 * idx - index of the most significant bit in the created mask. 255 */ 256#define RX_SGE_ONES_MASK(idx) \ 257 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 258#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 259 260/* Number of uint64_t elements in SGE mask array. */ 261#define RX_SGE_MASK_LEN \ 262 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 263#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 264#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 265 266/* 267 * dropless fc calculations for SGEs 268 * Number of required SGEs is the sum of two: 269 * 1. Number of possible opened aggregations (next packet for 270 * these aggregations will probably consume SGE immidiatelly) 271 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 272 * after placement on BD for new TPA aggregation) 273 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 274 */ 275#define NUM_SGE_REQ(sc) \ 276 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 277#define NUM_SGE_PG_REQ(sc) \ 278 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 279#define SGE_TH_LO(sc) \ 280 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 281#define SGE_TH_HI(sc) \ 282 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 283 284#define PAGES_PER_SGE_SHIFT 0 285#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 286#define SGE_PAGE_SIZE BCM_PAGE_SIZE 287#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 288#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 289#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 290#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 291 292/*****************/ 293/* TX BD defines */ 294/*****************/ 295 296#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 297#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 298#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 299#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 300#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 301#define TX_BD_MAX (TX_BD_TOTAL - 1) 302 303#define TX_BD_NEXT(x) \ 304 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 305 ((x) + 2) : ((x) + 1)) 306#define TX_BD(x) ((x) & TX_BD_MAX) 307#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 308#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 309 310/* 311 * Trigger pending transmits when the number of available BDs is greater 312 * than 1/8 of the total number of usable BDs. 313 */ 314#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 315#define BXE_TX_TIMEOUT 5 316 317/*****************/ 318/* RX BD defines */ 319/*****************/ 320 321#define RX_BD_NUM_PAGES 8 /* power of 2 */ 322#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 323#define RX_BD_NEXT_PAGE_DESC_CNT 2 324#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 325#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 326#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 327#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 328#define RX_BD_MAX (RX_BD_TOTAL - 1) 329 330#if 0 331#define NUM_RX_RINGS RX_BD_NUM_PAGES 332#define NUM_RX_BD RX_BD_TOTAL 333#define MAX_RX_BD RX_BD_MAX 334#define MAX_RX_AVAIL RX_BD_USABLE 335#endif 336 337#define RX_BD_NEXT(x) \ 338 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 339 ((x) + 3) : ((x) + 1)) 340#define RX_BD(x) ((x) & RX_BD_MAX) 341#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 342#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 343 344/* 345 * dropless fc calculations for BDs 346 * Number of BDs should be as number of buffers in BRB: 347 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 348 * "next" elements on each page 349 */ 350#define NUM_BD_REQ(sc) \ 351 BRB_SIZE(sc) 352#define NUM_BD_PG_REQ(sc) \ 353 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 354#define BD_TH_LO(sc) \ 355 (NUM_BD_REQ(sc) + \ 356 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 357 FW_DROP_LEVEL(sc)) 358#define BD_TH_HI(sc) \ 359 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 360#define MIN_RX_AVAIL(sc) \ 361 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 362#define MIN_RX_SIZE_TPA_HW(sc) \ 363 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 364 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 365#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 366#define MIN_RX_SIZE_TPA(sc) \ 367 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 368#define MIN_RX_SIZE_NONTPA(sc) \ 369 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 370 371/***************/ 372/* RCQ defines */ 373/***************/ 374 375/* 376 * As long as CQE is X times bigger than BD entry we have to allocate X times 377 * more pages for CQ ring in order to keep it balanced with BD ring 378 */ 379#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 380 sizeof(struct eth_rx_bd)) 381#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 382#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 383#define RCQ_NEXT_PAGE_DESC_CNT 1 384#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 385#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 386#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 387#define RCQ_MAX (RCQ_TOTAL - 1) 388 389#define RCQ_NEXT(x) \ 390 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 391 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 392#define RCQ(x) ((x) & RCQ_MAX) 393#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 394#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 395 396#if 0 397#define NUM_RCQ_RINGS RCQ_NUM_PAGES 398#define NUM_RCQ_BD RCQ_TOTAL 399#define MAX_RCQ_BD RCQ_MAX 400#define MAX_RCQ_AVAIL RCQ_USABLE 401#endif 402 403/* 404 * dropless fc calculations for RCQs 405 * Number of RCQs should be as number of buffers in BRB: 406 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 407 * "next" elements on each page 408 */ 409#define NUM_RCQ_REQ(sc) \ 410 BRB_SIZE(sc) 411#define NUM_RCQ_PG_REQ(sc) \ 412 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 413#define RCQ_TH_LO(sc) \ 414 (NUM_RCQ_REQ(sc) + \ 415 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 416 FW_DROP_LEVEL(sc)) 417#define RCQ_TH_HI(sc) \ 418 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 419 420/* This is needed for determening of last_max */ 421#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 422 423#define __SGE_MASK_SET_BIT(el, bit) \ 424 do { \ 425 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 426 } while (0) 427 428#define __SGE_MASK_CLEAR_BIT(el, bit) \ 429 do { \ 430 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 431 } while (0) 432 433#define SGE_MASK_SET_BIT(fp, idx) \ 434 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 435 ((idx) & RX_SGE_MASK_ELEM_MASK)) 436 437#define SGE_MASK_CLEAR_BIT(fp, idx) \ 438 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 439 ((idx) & RX_SGE_MASK_ELEM_MASK)) 440 441/* Load / Unload modes */ 442#define LOAD_NORMAL 0 443#define LOAD_OPEN 1 444#define LOAD_DIAG 2 445#define LOAD_LOOPBACK_EXT 3 446#define UNLOAD_NORMAL 0 447#define UNLOAD_CLOSE 1 448#define UNLOAD_RECOVERY 2 449 450/* Some constants... */ 451//#define MAX_PATH_NUM 2 452//#define E2_MAX_NUM_OF_VFS 64 453//#define E1H_FUNC_MAX 8 454//#define E2_FUNC_MAX 4 /* per path */ 455#define MAX_VNIC_NUM 4 456#define MAX_FUNC_NUM 8 /* common to all chips */ 457//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 458#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 459#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 460 461#define ILT_NUM_PAGE_ENTRIES 3072 462/* 463 * 57710/11 we use whole table since we have 8 functions. 464 * 57712 we have only 4 functions, but use same size per func, so only half 465 * of the table is used. 466 */ 467#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 468#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 469/* 470 * the phys address is shifted right 12 bits and has an added 471 * 1=valid bit added to the 53rd bit 472 * then since this is a wide register(TM) 473 * we split it into two 32 bit writes 474 */ 475#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 476#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 477 478/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 479#define ETH_HLEN 14 480#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 481#define ETH_MIN_PACKET_SIZE 60 482#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 483#define ETH_MAX_JUMBO_PACKET_SIZE 9600 484/* TCP with Timestamp Option (32) + IPv6 (40) */ 485#define ETH_MAX_TPA_HEADER_SIZE 72 486 487/* max supported alignment is 256 (8 shift) */ 488//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 489#define BXE_RX_ALIGN_SHIFT 8 490/* FW uses 2 cache lines alignment for start packet and size */ 491#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 492#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 493 494#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 495 496struct bxe_bar { 497 struct resource *resource; 498 int rid; 499 bus_space_tag_t tag; 500 bus_space_handle_t handle; 501 vm_offset_t kva; 502}; 503 504struct bxe_intr { 505 struct resource *resource; 506 int rid; 507 void *tag; 508}; 509 510/* Used to manage DMA allocations. */ 511struct bxe_dma { 512 struct bxe_softc *sc; 513 bus_addr_t paddr; 514 void *vaddr; 515 bus_dma_tag_t tag; 516 bus_dmamap_t map; 517 bus_dma_segment_t seg; 518 bus_size_t size; 519 int nseg; 520 char msg[32]; 521}; 522 523/* attn group wiring */ 524#define MAX_DYNAMIC_ATTN_GRPS 8 525 526struct attn_route { 527 uint32_t sig[5]; 528}; 529 530struct iro { 531 uint32_t base; 532 uint16_t m1; 533 uint16_t m2; 534 uint16_t m3; 535 uint16_t size; 536}; 537 538union bxe_host_hc_status_block { 539 /* pointer to fp status block e2 */ 540 struct host_hc_status_block_e2 *e2_sb; 541 /* pointer to fp status block e1x */ 542 struct host_hc_status_block_e1x *e1x_sb; 543}; 544 545union bxe_db_prod { 546 struct doorbell_set_prod data; 547 uint32_t raw; 548}; 549 550struct bxe_sw_tx_bd { 551 struct mbuf *m; 552 bus_dmamap_t m_map; 553 uint16_t first_bd; 554 uint8_t flags; 555/* set on the first BD descriptor when there is a split BD */ 556#define BXE_TSO_SPLIT_BD (1 << 0) 557}; 558 559struct bxe_sw_rx_bd { 560 struct mbuf *m; 561 bus_dmamap_t m_map; 562}; 563 564struct bxe_sw_tpa_info { 565 struct bxe_sw_rx_bd bd; 566 bus_dma_segment_t seg; 567 uint8_t state; 568#define BXE_TPA_STATE_START 1 569#define BXE_TPA_STATE_STOP 2 570 uint8_t placement_offset; 571 uint16_t parsing_flags; 572 uint16_t vlan_tag; 573 uint16_t len_on_bd; 574}; 575 576/* 577 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 578 * instances of the fastpath structure when using multiple queues. 579 */ 580struct bxe_fastpath { 581 /* pointer back to parent structure */ 582 struct bxe_softc *sc; 583 584 struct mtx tx_mtx; 585 char tx_mtx_name[32]; 586 struct mtx rx_mtx; 587 char rx_mtx_name[32]; 588 589#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 590#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 591#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 592 593#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 594#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 595#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 596 597 /* status block */ 598 struct bxe_dma sb_dma; 599 union bxe_host_hc_status_block status_block; 600 601 /* transmit chain (tx bds) */ 602 struct bxe_dma tx_dma; 603 union eth_tx_bd_types *tx_chain; 604 605 /* receive chain (rx bds) */ 606 struct bxe_dma rx_dma; 607 struct eth_rx_bd *rx_chain; 608 609 /* receive completion queue chain (rcq bds) */ 610 struct bxe_dma rcq_dma; 611 union eth_rx_cqe *rcq_chain; 612 613 /* receive scatter/gather entry chain (for TPA) */ 614 struct bxe_dma rx_sge_dma; 615 struct eth_rx_sge *rx_sge_chain; 616 617 /* tx mbufs */ 618 bus_dma_tag_t tx_mbuf_tag; 619 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 620 621 /* rx mbufs */ 622 bus_dma_tag_t rx_mbuf_tag; 623 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 624 bus_dmamap_t rx_mbuf_spare_map; 625 626 /* rx sge mbufs */ 627 bus_dma_tag_t rx_sge_mbuf_tag; 628 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 629 bus_dmamap_t rx_sge_mbuf_spare_map; 630 631 /* rx tpa mbufs (use the larger size for TPA queue length) */ 632 int tpa_enable; /* disabled per fastpath upon error */ 633 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 634 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 635 uint64_t rx_tpa_queue_used; 636#if 0 637 bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 638 bus_dmamap_t rx_tpa_mbuf_spare_map; 639 struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 640 bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 641 642 uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 643#endif 644 645 uint16_t *sb_index_values; 646 uint16_t *sb_running_index; 647 uint32_t ustorm_rx_prods_offset; 648 649 uint8_t igu_sb_id; /* status block number in HW */ 650 uint8_t fw_sb_id; /* status block number in FW */ 651 652 uint32_t rx_buf_size; 653 int mbuf_alloc_size; 654 655 int state; 656#define BXE_FP_STATE_CLOSED 0x01 657#define BXE_FP_STATE_IRQ 0x02 658#define BXE_FP_STATE_OPENING 0x04 659#define BXE_FP_STATE_OPEN 0x08 660#define BXE_FP_STATE_HALTING 0x10 661#define BXE_FP_STATE_HALTED 0x20 662 663 /* reference back to this fastpath queue number */ 664 uint8_t index; /* this is also the 'cid' */ 665#define FP_IDX(fp) (fp->index) 666 667 /* interrupt taskqueue (fast) */ 668 struct task tq_task; 669 struct taskqueue *tq; 670 char tq_name[32]; 671 672 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 673 uint8_t cl_id; 674#define FP_CL_ID(fp) (fp->cl_id) 675 uint8_t cl_qzone_id; 676 677 uint16_t fp_hc_idx; 678 679 /* driver copy of the receive buffer descriptor prod/cons indices */ 680 uint16_t rx_bd_prod; 681 uint16_t rx_bd_cons; 682 683 /* driver copy of the receive completion queue prod/cons indices */ 684 uint16_t rx_cq_prod; 685 uint16_t rx_cq_cons; 686 687 union bxe_db_prod tx_db; 688 689 /* Transmit packet producer index (used in eth_tx_bd). */ 690 uint16_t tx_pkt_prod; 691 uint16_t tx_pkt_cons; 692 693 /* Transmit buffer descriptor producer index. */ 694 uint16_t tx_bd_prod; 695 uint16_t tx_bd_cons; 696 697#if 0 698 /* status block number in hardware */ 699 uint8_t sb_id; 700#define FP_SB_ID(fp) (fp->sb_id) 701 702 /* driver copy of the fastpath CSTORM/USTORM indices */ 703 uint16_t fp_c_idx; 704 uint16_t fp_u_idx; 705#endif 706 707 uint64_t sge_mask[RX_SGE_MASK_LEN]; 708 uint16_t rx_sge_prod; 709 710 struct tstorm_per_queue_stats old_tclient; 711 struct ustorm_per_queue_stats old_uclient; 712 struct xstorm_per_queue_stats old_xclient; 713 struct bxe_eth_q_stats eth_q_stats; 714 struct bxe_eth_q_stats_old eth_q_stats_old; 715 716 /* Pointer to the receive consumer in the status block */ 717 uint16_t *rx_cq_cons_sb; 718 719 /* Pointer to the transmit consumer in the status block */ 720 uint16_t *tx_cons_sb; 721 722 /* transmit timeout until chip reset */ 723 int watchdog_timer; 724 725 /* Free/used buffer descriptor counters. */ 726 //uint16_t used_tx_bd; 727 728 /* Last maximal completed SGE */ 729 uint16_t last_max_sge; 730 731 //uint16_t rx_sge_free_idx; 732 733 //uint8_t segs; 734 735#if __FreeBSD_version >= 800000 736#define BXE_BR_SIZE 4096 737 struct buf_ring *tx_br; 738#endif 739}; /* struct bxe_fastpath */ 740 741/* sriov XXX */ 742#define BXE_MAX_NUM_OF_VFS 64 743#define BXE_VF_CID_WND 0 744#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 745#define BXE_CLIENTS_PER_VF 1 746#define BXE_FIRST_VF_CID 256 747#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 748#define BXE_VF_ID_INVALID 0xFF 749#define IS_SRIOV(sc) 0 750 751/* maximum number of fast-path interrupt contexts */ 752#define FP_SB_MAX_E1x 16 753#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 754 755union cdu_context { 756 struct eth_context eth; 757 char pad[1024]; 758}; 759 760/* CDU host DB constants */ 761#define CDU_ILT_PAGE_SZ_HW 2 762#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 763#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 764 765#define CNIC_ISCSI_CID_MAX 256 766#define CNIC_FCOE_CID_MAX 2048 767#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 768#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 769 770#define QM_ILT_PAGE_SZ_HW 0 771#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 772#define QM_CID_ROUND 1024 773 774/* TM (timers) host DB constants */ 775#define TM_ILT_PAGE_SZ_HW 0 776#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 777/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 778#define TM_CONN_NUM 1024 779#define TM_ILT_SZ (8 * TM_CONN_NUM) 780#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 781 782/* SRC (Searcher) host DB constants */ 783#define SRC_ILT_PAGE_SZ_HW 0 784#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 785#define SRC_HASH_BITS 10 786#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 787#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 788#define SRC_T2_SZ SRC_ILT_SZ 789#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 790 791struct hw_context { 792 struct bxe_dma vcxt_dma; 793 union cdu_context *vcxt; 794 //bus_addr_t cxt_mapping; 795 size_t size; 796}; 797 798#define SM_RX_ID 0 799#define SM_TX_ID 1 800 801/* defines for multiple tx priority indices */ 802#define FIRST_TX_ONLY_COS_INDEX 1 803#define FIRST_TX_COS_INDEX 0 804 805#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 806 807#define HC_INDEX_ETH_RX_CQ_CONS 1 808#define HC_INDEX_OOO_TX_CQ_CONS 4 809#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 810#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 811#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 812#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 813 814/* congestion management fairness mode */ 815#define CMNG_FNS_NONE 0 816#define CMNG_FNS_MINMAX 1 817 818/* CMNG constants, as derived from system spec calculations */ 819/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 820#define DEF_MIN_RATE 100 821/* resolution of the rate shaping timer - 400 usec */ 822#define RS_PERIODIC_TIMEOUT_USEC 400 823/* number of bytes in single QM arbitration cycle - 824 * coefficient for calculating the fairness timer */ 825#define QM_ARB_BYTES 160000 826/* resolution of Min algorithm 1:100 */ 827#define MIN_RES 100 828/* how many bytes above threshold for the minimal credit of Min algorithm*/ 829#define MIN_ABOVE_THRESH 32768 830/* fairness algorithm integration time coefficient - 831 * for calculating the actual Tfair */ 832#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 833/* memory of fairness algorithm - 2 cycles */ 834#define FAIR_MEM 2 835 836#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 837#define HC_SEG_ACCESS_ATTN 4 838#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 839 840/* 841 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 842 * control by the number of fast-path status blocks supported by the 843 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 844 * status block represents an independent interrupts context that can 845 * serve a regular L2 networking queue. However special L2 queues such 846 * as the FCoE queue do not require a FP-SB and other components like 847 * the CNIC may consume FP-SB reducing the number of possible L2 queues 848 * 849 * If the maximum number of FP-SB available is X then: 850 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 851 * regular L2 queues is Y=X-1 852 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 853 * c. If the FCoE L2 queue is supported the actual number of L2 queues 854 * is Y+1 855 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 856 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 857 * FP interrupt context for the CNIC). 858 * e. The number of HW context (CID count) is always X or X+1 if FCoE 859 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 860 * 861 * So this is quite simple for now as no ULPs are supported yet. :-) 862 */ 863#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 864#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 865#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 866#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 867 868#define FOR_EACH_QUEUE(sc, var) \ 869 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 870 871#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 872 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 873 874#define FOR_EACH_ETH_QUEUE(sc, var) \ 875 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 876 877#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 878 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 879 880#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 881 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 882 883#define FOR_EACH_CNIC_QUEUE(sc, var) \ 884 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 885 (var) < BXE_NUM_QUEUES(sc); \ 886 (var)++) 887 888enum { 889 OOO_IDX_OFFSET, 890 FCOE_IDX_OFFSET, 891 FWD_IDX_OFFSET, 892}; 893 894#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 895#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 896#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 897#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 898#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 899#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 900 901#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 902#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 903#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 904#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 905#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 906 907#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 908#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 909#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 910#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 911#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 912#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 913 914#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 915#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 916#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 917#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 918#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 919#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 920#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 921 922enum { 923 BXE_PORT_QUERY_IDX, 924 BXE_PF_QUERY_IDX, 925 BXE_FCOE_QUERY_IDX, 926 BXE_FIRST_QUEUE_QUERY_IDX, 927}; 928 929struct bxe_fw_stats_req { 930 struct stats_query_header hdr; 931 struct stats_query_entry query[FP_SB_MAX_E1x + 932 BXE_FIRST_QUEUE_QUERY_IDX]; 933}; 934 935struct bxe_fw_stats_data { 936 struct stats_counter storm_counters; 937 struct per_port_stats port; 938 struct per_pf_stats pf; 939 //struct fcoe_statistics_params fcoe; 940 struct per_queue_stats queue_stats[1]; 941}; 942 943/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 944#define BXE_IGU_STAS_MSG_VF_CNT 64 945#define BXE_IGU_STAS_MSG_PF_CNT 4 946 947#define MAX_DMAE_C 8 948 949/* 950 * For the main interface up/down code paths, a not-so-fine-grained CORE 951 * mutex lock is used. Inside this code are various calls to kernel routines 952 * that can cause a sleep to occur. Namely memory allocations and taskqueue 953 * handling. If using an MTX lock we are *not* allowed to sleep but we can 954 * with an SX lock. This define forces the CORE lock to use and SX lock. 955 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 956 * path can cause problems since it's called by a non-sleepable thread. To 957 * alleviate a potential sleep, any IOCTL processing that results in the 958 * chip/interface being started/stopped/reinitialized, the actual work is 959 * offloaded to a taskqueue. 960 */ 961#define BXE_CORE_LOCK_SX 962 963/* 964 * This is the slowpath data structure. It is mapped into non-paged memory 965 * so that the hardware can access it's contents directly and must be page 966 * aligned. 967 */ 968struct bxe_slowpath { 969 970#if 0 971 /* 972 * The cdu_context array MUST be the first element in this 973 * structure. It is used during the leading edge ramrod 974 * operation. 975 */ 976 union cdu_context context[MAX_CONTEXT]; 977 978 /* Used as a DMA source for MAC configuration. */ 979 struct mac_configuration_cmd mac_config; 980 struct mac_configuration_cmd mcast_config; 981#endif 982 983 /* used by the DMAE command executer */ 984 struct dmae_command dmae[MAX_DMAE_C]; 985 986 /* statistics completion */ 987 uint32_t stats_comp; 988 989 /* firmware defined statistics blocks */ 990 union mac_stats mac_stats; 991 struct nig_stats nig_stats; 992 struct host_port_stats port_stats; 993 struct host_func_stats func_stats; 994 //struct host_func_stats func_stats_base; 995 996 /* DMAE completion value and data source/sink */ 997 uint32_t wb_comp; 998 uint32_t wb_data[4]; 999 1000 union { 1001 struct mac_configuration_cmd e1x; 1002 struct eth_classify_rules_ramrod_data e2; 1003 } mac_rdata; 1004 1005 union { 1006 struct tstorm_eth_mac_filter_config e1x; 1007 struct eth_filter_rules_ramrod_data e2; 1008 } rx_mode_rdata; 1009 1010 struct eth_rss_update_ramrod_data rss_rdata; 1011 1012 union { 1013 struct mac_configuration_cmd e1; 1014 struct eth_multicast_rules_ramrod_data e2; 1015 } mcast_rdata; 1016 1017 union { 1018 struct function_start_data func_start; 1019 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 1020 } func_rdata; 1021 1022 /* Queue State related ramrods */ 1023 union { 1024 struct client_init_ramrod_data init_data; 1025 struct client_update_ramrod_data update_data; 1026 } q_rdata; 1027 1028 /* 1029 * AFEX ramrod can not be a part of func_rdata union because these 1030 * events might arrive in parallel to other events from func_rdata. 1031 * If they were defined in the same union the data can get corrupted. 1032 */ 1033 struct afex_vif_list_ramrod_data func_afex_rdata; 1034 1035 union drv_info_to_mcp drv_info_to_mcp; 1036}; /* struct bxe_slowpath */ 1037 1038/* 1039 * Port specifc data structure. 1040 */ 1041struct bxe_port { 1042 /* 1043 * Port Management Function (for 57711E only). 1044 * When this field is set the driver instance is 1045 * responsible for managing port specifc 1046 * configurations such as handling link attentions. 1047 */ 1048 uint32_t pmf; 1049 1050 /* Ethernet maximum transmission unit. */ 1051 uint16_t ether_mtu; 1052 1053 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1054 1055 uint32_t ext_phy_config; 1056 1057 /* Port feature config.*/ 1058 uint32_t config; 1059 1060 /* Defines the features supported by the PHY. */ 1061 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1062 1063 /* Defines the features advertised by the PHY. */ 1064 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1065#define ADVERTISED_10baseT_Half (1 << 1) 1066#define ADVERTISED_10baseT_Full (1 << 2) 1067#define ADVERTISED_100baseT_Half (1 << 3) 1068#define ADVERTISED_100baseT_Full (1 << 4) 1069#define ADVERTISED_1000baseT_Half (1 << 5) 1070#define ADVERTISED_1000baseT_Full (1 << 6) 1071#define ADVERTISED_TP (1 << 7) 1072#define ADVERTISED_FIBRE (1 << 8) 1073#define ADVERTISED_Autoneg (1 << 9) 1074#define ADVERTISED_Asym_Pause (1 << 10) 1075#define ADVERTISED_Pause (1 << 11) 1076#define ADVERTISED_2500baseX_Full (1 << 15) 1077#define ADVERTISED_10000baseT_Full (1 << 16) 1078 1079 uint32_t phy_addr; 1080 1081 /* Used to synchronize phy accesses. */ 1082 struct mtx phy_mtx; 1083 char phy_mtx_name[32]; 1084 1085#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1086#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1087#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1088 1089 /* 1090 * MCP scratchpad address for port specific statistics. 1091 * The device is responsible for writing statistcss 1092 * back to the MCP for use with management firmware such 1093 * as UMP/NC-SI. 1094 */ 1095 uint32_t port_stx; 1096 1097 struct nig_stats old_nig_stats; 1098}; /* struct bxe_port */ 1099 1100struct bxe_mf_info { 1101 uint32_t mf_config[E1HVN_MAX]; 1102 1103 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1104 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1105 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1106 1107#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1108#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1109#define VNICS_PER_PATH(sc) \ 1110 ((sc)->devinfo.mf_info.vnics_per_port * \ 1111 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1112 1113 uint8_t min_bw[MAX_VNIC_NUM]; 1114 uint8_t max_bw[MAX_VNIC_NUM]; 1115 1116 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1117#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1118#define INVALID_VIF_ID 0xFFFF 1119#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1120#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1121 1122 uint16_t default_vlan; 1123#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1124 1125 uint8_t niv_allowed_priorities; 1126#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1127 1128 uint8_t niv_default_cos; 1129#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1130 1131 uint8_t niv_mba_enabled; 1132 1133 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1134#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1135 int afex_def_vlan_tag; 1136 uint32_t pending_max; 1137 1138 uint16_t flags; 1139#define MF_INFO_VALID_MAC 0x0001 1140 1141 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1142#define IS_MF(sc) \ 1143 (IS_MULTI_VNIC(sc) && \ 1144 ((sc)->devinfo.mf_info.mf_mode != 0)) 1145#define IS_MF_SD(sc) \ 1146 (IS_MULTI_VNIC(sc) && \ 1147 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1148#define IS_MF_SI(sc) \ 1149 (IS_MULTI_VNIC(sc) && \ 1150 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1151#define IS_MF_AFEX(sc) \ 1152 (IS_MULTI_VNIC(sc) && \ 1153 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1154#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1155#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1156#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1157 1158 uint32_t mf_protos_supported; 1159 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1160 #define MF_PROTO_SUPPORT_ISCSI 0x2 1161 #define MF_PROTO_SUPPORT_FCOE 0x4 1162}; /* struct bxe_mf_info */ 1163 1164/* Device information data structure. */ 1165struct bxe_devinfo { 1166 /* PCIe info */ 1167 uint16_t vendor_id; 1168 uint16_t device_id; 1169 uint16_t subvendor_id; 1170 uint16_t subdevice_id; 1171 1172 /* 1173 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1174 * C = Chip Number (bits 16-31) 1175 * R = Chip Revision (bits 12-15) 1176 * M = Chip Metal (bits 4-11) 1177 * B = Chip Bond ID (bits 0-3) 1178 */ 1179 uint32_t chip_id; 1180#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1181#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1182/* device ids */ 1183#define CHIP_NUM_57710 0x164e 1184#define CHIP_NUM_57711 0x164f 1185#define CHIP_NUM_57711E 0x1650 1186#define CHIP_NUM_57712 0x1662 1187#define CHIP_NUM_57712_MF 0x1663 1188#define CHIP_NUM_57712_VF 0x166f 1189#define CHIP_NUM_57800 0x168a 1190#define CHIP_NUM_57800_MF 0x16a5 1191#define CHIP_NUM_57800_VF 0x16a9 1192#define CHIP_NUM_57810 0x168e 1193#define CHIP_NUM_57810_MF 0x16ae 1194#define CHIP_NUM_57810_VF 0x16af 1195#define CHIP_NUM_57811 0x163d 1196#define CHIP_NUM_57811_MF 0x163e 1197#define CHIP_NUM_57811_VF 0x163f 1198#define CHIP_NUM_57840_OBS 0x168d 1199#define CHIP_NUM_57840_OBS_MF 0x16ab 1200#define CHIP_NUM_57840_4_10 0x16a1 1201#define CHIP_NUM_57840_2_20 0x16a2 1202#define CHIP_NUM_57840_MF 0x16a4 1203#define CHIP_NUM_57840_VF 0x16ad 1204 1205#define CHIP_REV_SHIFT 12 1206#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1207#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1208 1209#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1210#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1211#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1212 1213#define CHIP_REV_IS_SLOW(sc) \ 1214 (CHIP_REV(sc) > 0x00005000) 1215#define CHIP_REV_IS_FPGA(sc) \ 1216 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1217#define CHIP_REV_IS_EMUL(sc) \ 1218 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1219#define CHIP_REV_IS_ASIC(sc) \ 1220 (!CHIP_REV_IS_SLOW(sc)) 1221 1222#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1223#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1224 1225#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1226#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1227#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1228#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1229#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1230 (CHIP_IS_57711E(sc))) 1231#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1232 CHIP_IS_E1H((sc))) 1233 1234#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1235#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1236#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1237#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1238 CHIP_IS_57712_MF(sc)) 1239 1240#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1241#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1242#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1243#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1244#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1245#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1246#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1247#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1248#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1249#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1250 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1251 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1252#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1253 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1254#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1255 1256#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1257 CHIP_IS_57800_MF(sc) || \ 1258 CHIP_IS_57800_VF(sc) || \ 1259 CHIP_IS_57810(sc) || \ 1260 CHIP_IS_57810_MF(sc) || \ 1261 CHIP_IS_57810_VF(sc) || \ 1262 CHIP_IS_57811(sc) || \ 1263 CHIP_IS_57811_MF(sc) || \ 1264 CHIP_IS_57811_VF(sc) || \ 1265 CHIP_IS_57840(sc) || \ 1266 CHIP_IS_57840_MF(sc) || \ 1267 CHIP_IS_57840_VF(sc)) 1268#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1269 (CHIP_REV(sc) == CHIP_REV_Ax)) 1270#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1271 (CHIP_REV(sc) == CHIP_REV_Bx)) 1272 1273#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1274#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1275 CHIP_IS_E3(sc)) 1276 1277#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1278 CHIP_IS_57712_MF(sc) || \ 1279 CHIP_IS_E3(sc)) 1280 1281#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1282 CHIP_IS_57800_VF(sc) || \ 1283 CHIP_IS_57810_VF(sc) || \ 1284 CHIP_IS_57840_VF(sc)) 1285#define IS_PF(sc) (!IS_VF(sc)) 1286 1287/* 1288 * This define is used in two main places: 1289 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1290 * to nic-only mode or to offload mode. Offload mode is configured if either 1291 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1292 * already registered for this port (which means that the user wants storage 1293 * services). 1294 * 2. During cnic-related load, to know if offload mode is already configured 1295 * in the HW or needs to be configrued. Since the transition from nic-mode to 1296 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1297 * in ports on which storage services where never requested. 1298 */ 1299#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1300 1301 uint8_t chip_port_mode; 1302#define CHIP_4_PORT_MODE 0x0 1303#define CHIP_2_PORT_MODE 0x1 1304#define CHIP_PORT_MODE_NONE 0x2 1305#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1306#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1307 1308 uint8_t int_block; 1309#define INT_BLOCK_HC 0 1310#define INT_BLOCK_IGU 1 1311#define INT_BLOCK_MODE_NORMAL 0 1312#define INT_BLOCK_MODE_BW_COMP 2 1313#define CHIP_INT_MODE_IS_NBC(sc) \ 1314 (!CHIP_IS_E1x(sc) && \ 1315 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1316#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1317 1318 uint32_t shmem_base; 1319 uint32_t shmem2_base; 1320 uint32_t bc_ver; 1321 char bc_ver_str[32]; 1322 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1323 struct bxe_mf_info mf_info; 1324 1325 int flash_size; 1326#define NVRAM_1MB_SIZE 0x20000 1327#define NVRAM_TIMEOUT_COUNT 30000 1328#define NVRAM_PAGE_SIZE 256 1329 1330 /* PCIe capability information */ 1331 uint32_t pcie_cap_flags; 1332#define BXE_PM_CAPABLE_FLAG 0x00000001 1333#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1334#define BXE_MSI_CAPABLE_FLAG 0x00000004 1335#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1336 uint16_t pcie_pm_cap_reg; 1337 uint16_t pcie_pcie_cap_reg; 1338 //uint16_t pcie_devctl; 1339 uint16_t pcie_link_width; 1340 uint16_t pcie_link_speed; 1341 uint16_t pcie_msi_cap_reg; 1342 uint16_t pcie_msix_cap_reg; 1343 1344 /* device configuration read from bootcode shared memory */ 1345 uint32_t hw_config; 1346 uint32_t hw_config2; 1347}; /* struct bxe_devinfo */ 1348 1349struct bxe_sp_objs { 1350 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1351 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1352}; /* struct bxe_sp_objs */ 1353 1354/* 1355 * Data that will be used to create a link report message. We will keep the 1356 * data used for the last link report in order to prevent reporting the same 1357 * link parameters twice. 1358 */ 1359struct bxe_link_report_data { 1360 uint16_t line_speed; /* Effective line speed */ 1361 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1362}; 1363enum { 1364 BXE_LINK_REPORT_FULL_DUPLEX, 1365 BXE_LINK_REPORT_LINK_DOWN, 1366 BXE_LINK_REPORT_RX_FC_ON, 1367 BXE_LINK_REPORT_TX_FC_ON 1368}; 1369 1370/* Top level device private data structure. */ 1371struct bxe_softc { 1372 /* 1373 * First entry must be a pointer to the BSD ifnet struct which 1374 * has a first element of 'void *if_softc' (which is us). 1375 */ 1376 struct ifnet *ifnet; 1377 struct ifmedia ifmedia; /* network interface media structure */ 1378 int media; 1379 1380 int state; /* device state */ 1381#define BXE_STATE_CLOSED 0x0000 1382#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1383#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1384#define BXE_STATE_OPEN 0x3000 1385#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1386#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1387#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1388#define BXE_STATE_DISABLED 0xD000 1389#define BXE_STATE_DIAG 0xE000 1390#define BXE_STATE_ERROR 0xF000 1391 1392 int flags; 1393#define BXE_ONE_PORT_FLAG 0x00000001 1394#define BXE_NO_ISCSI 0x00000002 1395#define BXE_NO_FCOE 0x00000004 1396#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1397//#define BXE_NO_WOL_FLAG 0x00000008 1398//#define BXE_USING_DAC_FLAG 0x00000010 1399//#define BXE_USING_MSIX_FLAG 0x00000020 1400//#define BXE_USING_MSI_FLAG 0x00000040 1401//#define BXE_DISABLE_MSI_FLAG 0x00000080 1402#define BXE_NO_MCP_FLAG 0x00000200 1403#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1404//#define BXE_SAFC_TX_FLAG 0x00000400 1405#define BXE_MF_FUNC_DIS 0x00000800 1406#define BXE_TX_SWITCHING 0x00001000 1407 1408 uint32_t debug; /* per-instance debug logging config */ 1409 1410#define MAX_BARS 5 1411 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1412 1413 uint16_t doorbell_size; 1414 1415 /* periodic timer callout */ 1416#define PERIODIC_STOP 0 1417#define PERIODIC_GO 1 1418 volatile unsigned long periodic_flags; 1419 struct callout periodic_callout; 1420 1421 /* chip start/stop/reset taskqueue */ 1422#define CHIP_TQ_NONE 0 1423#define CHIP_TQ_START 1 1424#define CHIP_TQ_STOP 2 1425#define CHIP_TQ_REINIT 3 1426 volatile unsigned long chip_tq_flags; 1427 struct task chip_tq_task; 1428 struct taskqueue *chip_tq; 1429 char chip_tq_name[32]; 1430 1431 /* slowpath interrupt taskqueue */ 1432 struct task sp_tq_task; 1433 struct taskqueue *sp_tq; 1434 char sp_tq_name[32]; 1435 1436 /* set rx_mode asynchronous taskqueue */ 1437 struct task rx_mode_tq_task; 1438 struct taskqueue *rx_mode_tq; 1439 char rx_mode_tq_name[32]; 1440 1441 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1442 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1443 1444 device_t dev; /* parent device handle */ 1445 uint8_t unit; /* driver instance number */ 1446 1447 int pcie_bus; /* PCIe bus number */ 1448 int pcie_device; /* PCIe device/slot number */ 1449 int pcie_func; /* PCIe function number */ 1450 1451 uint8_t pfunc_rel; /* function relative */ 1452 uint8_t pfunc_abs; /* function absolute */ 1453 uint8_t path_id; /* function absolute */ 1454#define SC_PATH(sc) (sc->path_id) 1455#define SC_PORT(sc) (sc->pfunc_rel & 1) 1456#define SC_FUNC(sc) (sc->pfunc_rel) 1457#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1458#define SC_VN(sc) (sc->pfunc_rel >> 1) 1459#define SC_L_ID(sc) (SC_VN(sc) << 2) 1460#define PORT_ID(sc) SC_PORT(sc) 1461#define PATH_ID(sc) SC_PATH(sc) 1462#define VNIC_ID(sc) SC_VN(sc) 1463#define FUNC_ID(sc) SC_FUNC(sc) 1464#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1465#define SC_FW_MB_IDX_VN(sc, vn) \ 1466 (SC_PORT(sc) + (vn) * \ 1467 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1468#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1469 1470 int if_capen; /* enabled interface capabilities */ 1471 1472 struct bxe_devinfo devinfo; 1473 char fw_ver_str[32]; 1474 char mf_mode_str[32]; 1475 char pci_link_str[32]; 1476 1477 const struct iro *iro_array; 1478 1479#ifdef BXE_CORE_LOCK_SX 1480 struct sx core_sx; 1481 char core_sx_name[32]; 1482#else 1483 struct mtx core_mtx; 1484 char core_mtx_name[32]; 1485#endif 1486 struct mtx sp_mtx; 1487 char sp_mtx_name[32]; 1488 struct mtx dmae_mtx; 1489 char dmae_mtx_name[32]; 1490 struct mtx fwmb_mtx; 1491 char fwmb_mtx_name[32]; 1492 struct mtx print_mtx; 1493 char print_mtx_name[32]; 1494 struct mtx stats_mtx; 1495 char stats_mtx_name[32]; 1496 struct mtx mcast_mtx; 1497 char mcast_mtx_name[32]; 1498 1499#ifdef BXE_CORE_LOCK_SX 1500#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1501#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1502#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1503#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1504#else 1505#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1506#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1507#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1508#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1509#endif 1510 1511#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1512#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1513#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1514 1515#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1516#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1517#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1518 1519#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1520#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1521#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1522 1523#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1524#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1525#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1526 1527#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1528#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1529#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1530 1531#if __FreeBSD_version < 800000 1532#define BXE_MCAST_LOCK(sc) \ 1533 do { \ 1534 mtx_lock(&sc->mcast_mtx); \ 1535 IF_ADDR_LOCK(sc->ifnet); \ 1536 } while (0) 1537#define BXE_MCAST_UNLOCK(sc) \ 1538 do { \ 1539 IF_ADDR_UNLOCK(sc->ifnet); \ 1540 mtx_unlock(&sc->mcast_mtx); \ 1541 } while (0) 1542#else 1543#define BXE_MCAST_LOCK(sc) \ 1544 do { \ 1545 mtx_lock(&sc->mcast_mtx); \ 1546 if_maddr_rlock(sc->ifnet); \ 1547 } while (0) 1548#define BXE_MCAST_UNLOCK(sc) \ 1549 do { \ 1550 if_maddr_runlock(sc->ifnet); \ 1551 mtx_unlock(&sc->mcast_mtx); \ 1552 } while (0) 1553#endif 1554#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1555 1556 int dmae_ready; 1557#define DMAE_READY(sc) (sc->dmae_ready) 1558 1559 struct ecore_credit_pool_obj vlans_pool; 1560 struct ecore_credit_pool_obj macs_pool; 1561 struct ecore_rx_mode_obj rx_mode_obj; 1562 struct ecore_mcast_obj mcast_obj; 1563 struct ecore_rss_config_obj rss_conf_obj; 1564 struct ecore_func_sp_obj func_obj; 1565 1566 uint16_t fw_seq; 1567 uint16_t fw_drv_pulse_wr_seq; 1568 uint32_t func_stx; 1569 1570 struct elink_params link_params; 1571 struct elink_vars link_vars; 1572 uint32_t link_cnt; 1573 struct bxe_link_report_data last_reported_link; 1574 char mac_addr_str[32]; 1575 1576 int last_reported_link_state; 1577 1578 int tx_ring_size; 1579 int rx_ring_size; 1580 int wol; 1581 1582 int is_leader; 1583 int recovery_state; 1584#define BXE_RECOVERY_DONE 1 1585#define BXE_RECOVERY_INIT 2 1586#define BXE_RECOVERY_WAIT 3 1587#define BXE_RECOVERY_FAILED 4 1588#define BXE_RECOVERY_NIC_LOADING 5 1589 1590 uint32_t rx_mode; 1591#define BXE_RX_MODE_NONE 0 1592#define BXE_RX_MODE_NORMAL 1 1593#define BXE_RX_MODE_ALLMULTI 2 1594#define BXE_RX_MODE_PROMISC 3 1595#define BXE_MAX_MULTICAST 64 1596 1597 struct bxe_port port; 1598 1599 struct cmng_init cmng; 1600 1601 /* user configs */ 1602 int num_queues; 1603 int max_rx_bufs; 1604 int hc_rx_ticks; 1605 int hc_tx_ticks; 1606 uint32_t rx_budget; 1607 int max_aggregation_size; 1608 int mrrs; 1609 int autogreeen; 1610#define AUTO_GREEN_HW_DEFAULT 0 1611#define AUTO_GREEN_FORCE_ON 1 1612#define AUTO_GREEN_FORCE_OFF 2 1613 int interrupt_mode; 1614#define INTR_MODE_INTX 0 1615#define INTR_MODE_MSI 1 1616#define INTR_MODE_MSIX 2 1617 int udp_rss; 1618 1619 /* interrupt allocations */ 1620 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1621 int intr_count; 1622 uint8_t igu_dsb_id; 1623 uint8_t igu_base_sb; 1624 uint8_t igu_sb_cnt; 1625 //uint8_t min_msix_vec_cnt; 1626 uint32_t igu_base_addr; 1627 //bus_addr_t def_status_blk_mapping; 1628 uint8_t base_fw_ndsb; 1629#define DEF_SB_IGU_ID 16 1630#define DEF_SB_ID HC_SP_SB_ID 1631 1632 /* parent bus DMA tag */ 1633 bus_dma_tag_t parent_dma_tag; 1634 1635 /* default status block */ 1636 struct bxe_dma def_sb_dma; 1637 struct host_sp_status_block *def_sb; 1638 uint16_t def_idx; 1639 uint16_t def_att_idx; 1640 uint32_t attn_state; 1641 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1642 1643/* general SP events - stats query, cfc delete, etc */ 1644#define HC_SP_INDEX_ETH_DEF_CONS 3 1645/* EQ completions */ 1646#define HC_SP_INDEX_EQ_CONS 7 1647/* FCoE L2 connection completions */ 1648#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1649#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1650/* iSCSI L2 */ 1651#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1652#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1653 1654 /* event queue */ 1655 struct bxe_dma eq_dma; 1656 union event_ring_elem *eq; 1657 uint16_t eq_prod; 1658 uint16_t eq_cons; 1659 uint16_t *eq_cons_sb; 1660#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1661#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1662#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1663#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1664#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1665#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1666/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1667#define NEXT_EQ_IDX(x) \ 1668 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1669 ((x) + 2) : ((x) + 1)) 1670/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1671#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1672 1673 /* slow path */ 1674 struct bxe_dma sp_dma; 1675 struct bxe_slowpath *sp; 1676 unsigned long sp_state; 1677 1678 /* slow path queue */ 1679 struct bxe_dma spq_dma; 1680 struct eth_spe *spq; 1681#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1682#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1683#define MAX_SPQ_PENDING 8 1684 1685 uint16_t spq_prod_idx; 1686 struct eth_spe *spq_prod_bd; 1687 struct eth_spe *spq_last_bd; 1688 uint16_t *dsb_sp_prod; 1689 //uint16_t *spq_hw_con; 1690 //uint16_t spq_left; 1691 1692 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1693 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1694 1695 /* fw decompression buffer */ 1696 struct bxe_dma gz_buf_dma; 1697 void *gz_buf; 1698 z_streamp gz_strm; 1699 uint32_t gz_outlen; 1700#define GUNZIP_BUF(sc) (sc->gz_buf) 1701#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1702#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1703#define FW_BUF_SIZE 0x40000 1704 1705 const struct raw_op *init_ops; 1706 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1707 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1708 uint32_t init_mode_flags; 1709#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1710 /* PRAM blobs - raw data */ 1711 const uint8_t *tsem_int_table_data; 1712 const uint8_t *tsem_pram_data; 1713 const uint8_t *usem_int_table_data; 1714 const uint8_t *usem_pram_data; 1715 const uint8_t *xsem_int_table_data; 1716 const uint8_t *xsem_pram_data; 1717 const uint8_t *csem_int_table_data; 1718 const uint8_t *csem_pram_data; 1719#define INIT_OPS(sc) (sc->init_ops) 1720#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1721#define INIT_DATA(sc) (sc->init_data) 1722#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1723#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1724#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1725#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1726#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1727#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1728#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1729#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1730 1731 /* ILT 1732 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1733 * context size we need 8 ILT entries. 1734 */ 1735#define ILT_MAX_L2_LINES 8 1736 struct hw_context context[ILT_MAX_L2_LINES]; 1737 struct ecore_ilt *ilt; 1738#define ILT_MAX_LINES 256 1739 1740/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1741#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1742/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1743#if 1 1744#define BXE_L2_MAX_CID(sc) \ 1745 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1746#else 1747#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1748 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1749#endif 1750#if 1 1751#define BXE_L2_CID_COUNT(sc) \ 1752 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1753#else 1754#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1755 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1756#endif 1757#define L2_ILT_LINES(sc) \ 1758 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1759 1760 int qm_cid_count; 1761 1762 uint8_t dropless_fc; 1763 1764#if 0 1765 struct bxe_dma *t2; 1766#endif 1767 1768 /* total number of FW statistics requests */ 1769 uint8_t fw_stats_num; 1770 /* 1771 * This is a memory buffer that will contain both statistics ramrod 1772 * request and data. 1773 */ 1774 struct bxe_dma fw_stats_dma; 1775 /* 1776 * FW statistics request shortcut (points at the beginning of fw_stats 1777 * buffer). 1778 */ 1779 int fw_stats_req_size; 1780 struct bxe_fw_stats_req *fw_stats_req; 1781 bus_addr_t fw_stats_req_mapping; 1782 /* 1783 * FW statistics data shortcut (points at the beginning of fw_stats 1784 * buffer + fw_stats_req_size). 1785 */ 1786 int fw_stats_data_size; 1787 struct bxe_fw_stats_data *fw_stats_data; 1788 bus_addr_t fw_stats_data_mapping; 1789 1790 /* tracking a pending STAT_QUERY ramrod */ 1791 uint16_t stats_pending; 1792 /* number of completed statistics ramrods */ 1793 uint16_t stats_comp; 1794 uint16_t stats_counter; 1795 uint8_t stats_init; 1796 int stats_state; 1797 1798 struct bxe_eth_stats eth_stats; 1799 struct host_func_stats func_stats; 1800 struct bxe_eth_stats_old eth_stats_old; 1801 struct bxe_net_stats_old net_stats_old; 1802 struct bxe_fw_port_stats_old fw_stats_old; 1803 1804 struct dmae_command stats_dmae; /* used by dmae command loader */ 1805 int executer_idx; 1806 1807 int mtu; 1808 1809 /* LLDP params */ 1810 struct bxe_config_lldp_params lldp_config_params; 1811 /* DCB support on/off */ 1812 int dcb_state; 1813#define BXE_DCB_STATE_OFF 0 1814#define BXE_DCB_STATE_ON 1 1815 /* DCBX engine mode */ 1816 int dcbx_enabled; 1817#define BXE_DCBX_ENABLED_OFF 0 1818#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1819#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1820#define BXE_DCBX_ENABLED_INVALID -1 1821 uint8_t dcbx_mode_uset; 1822 struct bxe_config_dcbx_params dcbx_config_params; 1823 struct bxe_dcbx_port_params dcbx_port_params; 1824 int dcb_version; 1825 1826 uint8_t cnic_support; 1827 uint8_t cnic_enabled; 1828 uint8_t cnic_loaded; 1829#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1830#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1831#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1832 1833 /* multiple tx classes of service */ 1834 uint8_t max_cos; 1835#define BXE_MAX_PRIORITY 8 1836 /* priority to cos mapping */ 1837 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1838 1839 int panic; 1840}; /* struct bxe_softc */ 1841 1842/* IOCTL sub-commands for edebug and firmware upgrade */ 1843#define BXE_IOC_RD_NVRAM 1 1844#define BXE_IOC_WR_NVRAM 2 1845#define BXE_IOC_STATS_SHOW_NUM 3 1846#define BXE_IOC_STATS_SHOW_STR 4 1847#define BXE_IOC_STATS_SHOW_CNT 5 1848 1849struct bxe_nvram_data { 1850 uint32_t op; /* ioctl sub-command */ 1851 uint32_t offset; 1852 uint32_t len; 1853 uint32_t value[1]; /* variable */ 1854}; 1855 1856union bxe_stats_show_data { 1857 uint32_t op; /* ioctl sub-command */ 1858 1859 struct { 1860 uint32_t num; /* return number of stats */ 1861 uint32_t len; /* length of each string item */ 1862 } desc; 1863 1864 /* variable length... */ 1865 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1866 1867 /* variable length... */ 1868 uint64_t stats[1]; /* holds all stats */ 1869}; 1870 1871/* function init flags */ 1872#define FUNC_FLG_RSS 0x0001 1873#define FUNC_FLG_STATS 0x0002 1874/* FUNC_FLG_UNMATCHED 0x0004 */ 1875#define FUNC_FLG_TPA 0x0008 1876#define FUNC_FLG_SPQ 0x0010 1877#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1878 1879struct bxe_func_init_params { 1880 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1881 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1882 uint16_t func_flgs; 1883 uint16_t func_id; /* abs function id */ 1884 uint16_t pf_id; 1885 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1886}; 1887 1888/* memory resources reside at BARs 0, 2, 4 */ 1889/* Run `pciconf -lb` to see mappings */ 1890#define BAR0 0 1891#define BAR1 2 1892#define BAR2 4 1893 1894#ifdef BXE_REG_NO_INLINE 1895 1896uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1897uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1898uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1899 1900void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1901void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1902void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1903 1904#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1905#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1906#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1907 1908#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1909#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1910#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1911 1912#else /* not BXE_REG_NO_INLINE */ 1913 1914#define REG_WR8(sc, offset, val) \ 1915 bus_space_write_1(sc->bar[BAR0].tag, \ 1916 sc->bar[BAR0].handle, \ 1917 offset, val) 1918 1919#define REG_WR16(sc, offset, val) \ 1920 bus_space_write_2(sc->bar[BAR0].tag, \ 1921 sc->bar[BAR0].handle, \ 1922 offset, val) 1923 1924#define REG_WR32(sc, offset, val) \ 1925 bus_space_write_4(sc->bar[BAR0].tag, \ 1926 sc->bar[BAR0].handle, \ 1927 offset, val) 1928 1929#define REG_RD8(sc, offset) \ 1930 bus_space_read_1(sc->bar[BAR0].tag, \ 1931 sc->bar[BAR0].handle, \ 1932 offset) 1933 1934#define REG_RD16(sc, offset) \ 1935 bus_space_read_2(sc->bar[BAR0].tag, \ 1936 sc->bar[BAR0].handle, \ 1937 offset) 1938 1939#define REG_RD32(sc, offset) \ 1940 bus_space_read_4(sc->bar[BAR0].tag, \ 1941 sc->bar[BAR0].handle, \ 1942 offset) 1943 1944#endif /* BXE_REG_NO_INLINE */ 1945 1946#define REG_RD(sc, offset) REG_RD32(sc, offset) 1947#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1948 1949#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1950#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1951 1952#define BXE_SP(sc, var) (&(sc)->sp->var) 1953#define BXE_SP_MAPPING(sc, var) \ 1954 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1955 1956#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1957#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1958 1959#if 0 1960#define bxe_fp(sc, nr, var) ((sc)->fp[nr].var) 1961#define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index]) 1962#define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index]) 1963#define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats) 1964#endif 1965 1966#define REG_RD_DMAE(sc, offset, valp, len32) \ 1967 do { \ 1968 bxe_read_dmae(sc, offset, len32); \ 1969 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1970 } while (0) 1971 1972#define REG_WR_DMAE(sc, offset, valp, len32) \ 1973 do { \ 1974 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1975 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1976 } while (0) 1977 1978#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1979 REG_WR_DMAE(sc, offset, valp, len32) 1980 1981#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1982 REG_RD_DMAE(sc, offset, valp, len32) 1983 1984#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1985 do { \ 1986 /* if (le32_swap) { */ \ 1987 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1988 /* } */ \ 1989 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1990 ecore_write_big_buf_wb(sc, addr, len32); \ 1991 } while (0) 1992 1993#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1994#define BXE_DB_SHIFT 7 /* 128 bytes */ 1995#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1996#error "Minimum DB doorbell stride is 8" 1997#endif 1998#define DPM_TRIGGER_TYPE 0x40 1999#define DOORBELL(sc, cid, val) \ 2000 do { \ 2001 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 2002 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 2003 (uint32_t)val); \ 2004 } while(0) 2005 2006#define SHMEM_ADDR(sc, field) \ 2007 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 2008#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 2009#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 2010#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 2011 2012#define SHMEM2_ADDR(sc, field) \ 2013 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 2014#define SHMEM2_HAS(sc, field) \ 2015 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 2016 offsetof(struct shmem2_region, field))) 2017#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 2018#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 2019 2020#define MFCFG_ADDR(sc, field) \ 2021 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 2022#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 2023#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 2024#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 2025 2026/* DMAE command defines */ 2027 2028#define DMAE_TIMEOUT -1 2029#define DMAE_PCI_ERROR -2 /* E2 and onward */ 2030#define DMAE_NOT_RDY -3 2031#define DMAE_PCI_ERR_FLAG 0x80000000 2032 2033#define DMAE_SRC_PCI 0 2034#define DMAE_SRC_GRC 1 2035 2036#define DMAE_DST_NONE 0 2037#define DMAE_DST_PCI 1 2038#define DMAE_DST_GRC 2 2039 2040#define DMAE_COMP_PCI 0 2041#define DMAE_COMP_GRC 1 2042 2043#define DMAE_COMP_REGULAR 0 2044#define DMAE_COM_SET_ERR 1 2045 2046#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT) 2047#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT) 2048#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT) 2049#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT) 2050 2051#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT) 2052#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT) 2053 2054#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2055#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2056#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2057#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2058 2059#define DMAE_CMD_PORT_0 0 2060#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2061 2062#define DMAE_SRC_PF 0 2063#define DMAE_SRC_VF 1 2064 2065#define DMAE_DST_PF 0 2066#define DMAE_DST_VF 1 2067 2068#define DMAE_C_SRC 0 2069#define DMAE_C_DST 1 2070 2071#define DMAE_LEN32_RD_MAX 0x80 2072#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2073 2074#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2075 2076#define MAX_DMAE_C_PER_PORT 8 2077#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2078#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2079 2080static const uint32_t dmae_reg_go_c[] = { 2081 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2082 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2083 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2084 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2085}; 2086 2087#define ATTN_NIG_FOR_FUNC (1L << 8) 2088#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2089#define GPIO_2_FUNC (1L << 10) 2090#define GPIO_3_FUNC (1L << 11) 2091#define GPIO_4_FUNC (1L << 12) 2092#define ATTN_GENERAL_ATTN_1 (1L << 13) 2093#define ATTN_GENERAL_ATTN_2 (1L << 14) 2094#define ATTN_GENERAL_ATTN_3 (1L << 15) 2095#define ATTN_GENERAL_ATTN_4 (1L << 13) 2096#define ATTN_GENERAL_ATTN_5 (1L << 14) 2097#define ATTN_GENERAL_ATTN_6 (1L << 15) 2098#define ATTN_HARD_WIRED_MASK 0xff00 2099#define ATTENTION_ID 4 2100 2101#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2102 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2103 2104#define MAX_IGU_ATTN_ACK_TO 100 2105 2106#define STORM_ASSERT_ARRAY_SIZE 50 2107 2108#define BXE_PMF_LINK_ASSERT(sc) \ 2109 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2110 2111#define BXE_MC_ASSERT_BITS \ 2112 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2113 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2114 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2115 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2116 2117#define BXE_MCP_ASSERT \ 2118 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2119 2120#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2121#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2122 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2123 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2124 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2125 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2126 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2127 2128#define MULTI_MASK 0x7f 2129 2130#define PFS_PER_PORT(sc) \ 2131 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2132#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2133 2134#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2135 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2136 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2137 2138#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2139 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2140 (i) < MAX_FUNC_NUM; \ 2141 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2142 2143#define BXE_SWCID_SHIFT 17 2144#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2145 2146#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2147#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2148 2149#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2150#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2151#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2152#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2153#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2154 2155/* must be used on a CID before placing it on a HW ring */ 2156#define HW_CID(sc, x) \ 2157 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2158 2159#define SPEED_10 10 2160#define SPEED_100 100 2161#define SPEED_1000 1000 2162#define SPEED_2500 2500 2163#define SPEED_10000 10000 2164 2165#define PCI_PM_D0 1 2166#define PCI_PM_D3hot 2 2167 2168int bxe_test_bit(int nr, volatile unsigned long * addr); 2169void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2170void bxe_clear_bit(int nr, volatile unsigned long * addr); 2171int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2172int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2173int bxe_cmpxchg(volatile int *addr, int old, int new); 2174 2175void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2176 uint32_t val); 2177uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2178 2179 2180int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2181 struct bxe_dma *dma, const char *msg); 2182void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2183 2184uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2185uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2186uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2187 uint8_t dst_type, uint8_t with_comp, 2188 uint8_t comp_type); 2189void bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx); 2190void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2191void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2192 uint32_t dst_addr, uint32_t len32); 2193void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2194 uint32_t addr, uint32_t len); 2195 2196void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2197 uint32_t cid); 2198void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2199 uint8_t sb_index, uint8_t disable, 2200 uint16_t usec); 2201 2202int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2203 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2204 2205void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2206 uint8_t segment, uint16_t index, uint8_t op, 2207 uint8_t update); 2208 2209void ecore_init_e1_firmware(struct bxe_softc *sc); 2210void ecore_init_e1h_firmware(struct bxe_softc *sc); 2211void ecore_init_e2_firmware(struct bxe_softc *sc); 2212 2213void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2214 size_t size, uint32_t *data); 2215 2216/*********************/ 2217/* LOGGING AND DEBUG */ 2218/*********************/ 2219 2220/* debug logging codepaths */ 2221#define DBG_LOAD 0x00000001 /* load and unload */ 2222#define DBG_INTR 0x00000002 /* interrupt handling */ 2223#define DBG_SP 0x00000004 /* slowpath handling */ 2224#define DBG_STATS 0x00000008 /* stats updates */ 2225#define DBG_TX 0x00000010 /* packet transmit */ 2226#define DBG_RX 0x00000020 /* packet receive */ 2227#define DBG_PHY 0x00000040 /* phy/link handling */ 2228#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2229#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2230#define DBG_REGS 0x00000200 /* register access */ 2231#define DBG_LRO 0x00000400 /* lro processing */ 2232#define DBG_ASSERT 0x80000000 /* debug assert */ 2233#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2234 2235#define DBASSERT(sc, exp, msg) \ 2236 do { \ 2237 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2238 if (__predict_false(!(exp))) { \ 2239 panic msg; \ 2240 } \ 2241 } \ 2242 } while (0) 2243 2244/* log a debug message */ 2245#define BLOGD(sc, codepath, format, args...) \ 2246 do { \ 2247 if (__predict_false(sc->debug & (codepath))) { \ 2248 device_printf((sc)->dev, \ 2249 "%s(%s:%d) " format, \ 2250 __FUNCTION__, \ 2251 __FILE__, \ 2252 __LINE__, \ 2253 ## args); \ 2254 } \ 2255 } while(0) 2256 2257/* log a info message */ 2258#define BLOGI(sc, format, args...) \ 2259 do { \ 2260 if (__predict_false(sc->debug)) { \ 2261 device_printf((sc)->dev, \ 2262 "%s(%s:%d) " format, \ 2263 __FUNCTION__, \ 2264 __FILE__, \ 2265 __LINE__, \ 2266 ## args); \ 2267 } else { \ 2268 device_printf((sc)->dev, \ 2269 format, \ 2270 ## args); \ 2271 } \ 2272 } while(0) 2273 2274/* log a warning message */ 2275#define BLOGW(sc, format, args...) \ 2276 do { \ 2277 if (__predict_false(sc->debug)) { \ 2278 device_printf((sc)->dev, \ 2279 "%s(%s:%d) WARNING: " format, \ 2280 __FUNCTION__, \ 2281 __FILE__, \ 2282 __LINE__, \ 2283 ## args); \ 2284 } else { \ 2285 device_printf((sc)->dev, \ 2286 "WARNING: " format, \ 2287 ## args); \ 2288 } \ 2289 } while(0) 2290 2291/* log a error message */ 2292#define BLOGE(sc, format, args...) \ 2293 do { \ 2294 if (__predict_false(sc->debug)) { \ 2295 device_printf((sc)->dev, \ 2296 "%s(%s:%d) ERROR: " format, \ 2297 __FUNCTION__, \ 2298 __FILE__, \ 2299 __LINE__, \ 2300 ## args); \ 2301 } else { \ 2302 device_printf((sc)->dev, \ 2303 "ERROR: " format, \ 2304 ## args); \ 2305 } \ 2306 } while(0) 2307 2308#define bxe_panic(sc, msg) \ 2309 do { \ 2310 panic msg; \ 2311 } while (0) 2312 2313#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2314#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2315 2316void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2317 uint8_t *mem, uint32_t len); 2318void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2319 struct mbuf *m, uint8_t contents); 2320 2321/***********/ 2322/* INLINES */ 2323/***********/ 2324 2325static inline uint32_t 2326reg_poll(struct bxe_softc *sc, 2327 uint32_t reg, 2328 uint32_t expected, 2329 int ms, 2330 int wait) 2331{ 2332 uint32_t val; 2333 2334 do { 2335 val = REG_RD(sc, reg); 2336 if (val == expected) { 2337 break; 2338 } 2339 ms -= wait; 2340 DELAY(wait * 1000); 2341 } while (ms > 0); 2342 2343 return (val); 2344} 2345 2346static inline void 2347bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2348{ 2349 mb(); /* status block is written to by the chip */ 2350 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2351} 2352 2353static inline void 2354bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2355 uint8_t igu_sb_id, 2356 uint8_t segment, 2357 uint16_t index, 2358 uint8_t op, 2359 uint8_t update, 2360 uint32_t igu_addr) 2361{ 2362 struct igu_regular cmd_data = {0}; 2363 2364 cmd_data.sb_id_and_flags = 2365 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2366 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2367 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2368 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2369 2370 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2371 cmd_data.sb_id_and_flags, igu_addr); 2372 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2373 2374 /* Make sure that ACK is written */ 2375 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2376 BUS_SPACE_BARRIER_WRITE); 2377 mb(); 2378} 2379 2380static inline void 2381bxe_hc_ack_sb(struct bxe_softc *sc, 2382 uint8_t sb_id, 2383 uint8_t storm, 2384 uint16_t index, 2385 uint8_t op, 2386 uint8_t update) 2387{ 2388 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2389 COMMAND_REG_INT_ACK); 2390 struct igu_ack_register igu_ack; 2391 2392 igu_ack.status_block_index = index; 2393 igu_ack.sb_id_and_flags = 2394 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2395 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2396 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2397 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2398 2399 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2400 2401 /* Make sure that ACK is written */ 2402 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2403 BUS_SPACE_BARRIER_WRITE); 2404 mb(); 2405} 2406 2407static inline void 2408bxe_ack_sb(struct bxe_softc *sc, 2409 uint8_t igu_sb_id, 2410 uint8_t storm, 2411 uint16_t index, 2412 uint8_t op, 2413 uint8_t update) 2414{ 2415 if (sc->devinfo.int_block == INT_BLOCK_HC) 2416 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2417 else { 2418 uint8_t segment; 2419 if (CHIP_INT_MODE_IS_BC(sc)) { 2420 segment = storm; 2421 } else if (igu_sb_id != sc->igu_dsb_id) { 2422 segment = IGU_SEG_ACCESS_DEF; 2423 } else if (storm == ATTENTION_ID) { 2424 segment = IGU_SEG_ACCESS_ATTN; 2425 } else { 2426 segment = IGU_SEG_ACCESS_DEF; 2427 } 2428 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2429 } 2430} 2431 2432static inline uint16_t 2433bxe_hc_ack_int(struct bxe_softc *sc) 2434{ 2435 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2436 COMMAND_REG_SIMD_MASK); 2437 uint32_t result = REG_RD(sc, hc_addr); 2438 2439 mb(); 2440 return (result); 2441} 2442 2443static inline uint16_t 2444bxe_igu_ack_int(struct bxe_softc *sc) 2445{ 2446 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2447 uint32_t result = REG_RD(sc, igu_addr); 2448 2449 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2450 result, igu_addr); 2451 2452 mb(); 2453 return (result); 2454} 2455 2456static inline uint16_t 2457bxe_ack_int(struct bxe_softc *sc) 2458{ 2459 mb(); 2460 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2461 return (bxe_hc_ack_int(sc)); 2462 } else { 2463 return (bxe_igu_ack_int(sc)); 2464 } 2465} 2466 2467static inline int 2468func_by_vn(struct bxe_softc *sc, 2469 int vn) 2470{ 2471 return (2 * vn + SC_PORT(sc)); 2472} 2473 2474/* 2475 * Statistics ID are global per chip/path, while Client IDs for E1x 2476 * are per port. 2477 */ 2478static inline uint8_t 2479bxe_stats_id(struct bxe_fastpath *fp) 2480{ 2481 struct bxe_softc *sc = fp->sc; 2482 2483 if (!CHIP_IS_E1x(sc)) { 2484#if 0 2485 /* there are special statistics counters for FCoE 136..140 */ 2486 if (IS_FCOE_FP(fp)) { 2487 return (sc->cnic_base_cl_id + (sc->pf_num >> 1)); 2488 } 2489#endif 2490 return (fp->cl_id); 2491 } 2492 2493 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2494} 2495 2496#endif /* __BXE_H__ */ 2497 2498