if_bwn.c revision 300194
1/*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 *    redistribution must be conditioned upon including a substantially
14 *    similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/bwn/if_bwn.c 300194 2016-05-19 05:06:48Z adrian $");
32
33/*
34 * The Broadcom Wireless LAN controller driver.
35 */
36
37#include "opt_bwn.h"
38#include "opt_wlan.h"
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/malloc.h>
44#include <sys/module.h>
45#include <sys/endian.h>
46#include <sys/errno.h>
47#include <sys/firmware.h>
48#include <sys/lock.h>
49#include <sys/mutex.h>
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/bus.h>
53#include <sys/rman.h>
54#include <sys/socket.h>
55#include <sys/sockio.h>
56
57#include <net/ethernet.h>
58#include <net/if.h>
59#include <net/if_var.h>
60#include <net/if_arp.h>
61#include <net/if_dl.h>
62#include <net/if_llc.h>
63#include <net/if_media.h>
64#include <net/if_types.h>
65
66#include <dev/pci/pcivar.h>
67#include <dev/pci/pcireg.h>
68#include <dev/siba/siba_ids.h>
69#include <dev/siba/sibareg.h>
70#include <dev/siba/sibavar.h>
71
72#include <net80211/ieee80211_var.h>
73#include <net80211/ieee80211_radiotap.h>
74#include <net80211/ieee80211_regdomain.h>
75#include <net80211/ieee80211_phy.h>
76#include <net80211/ieee80211_ratectl.h>
77
78#include <dev/bwn/if_bwnreg.h>
79#include <dev/bwn/if_bwnvar.h>
80
81#include <dev/bwn/if_bwn_debug.h>
82#include <dev/bwn/if_bwn_misc.h>
83#include <dev/bwn/if_bwn_util.h>
84#include <dev/bwn/if_bwn_phy_common.h>
85#include <dev/bwn/if_bwn_phy_g.h>
86#include <dev/bwn/if_bwn_phy_lp.h>
87#include <dev/bwn/if_bwn_phy_n.h>
88
89static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0,
90    "Broadcom driver parameters");
91
92/*
93 * Tunable & sysctl variables.
94 */
95
96#ifdef BWN_DEBUG
97static	int bwn_debug = 0;
98SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0,
99    "Broadcom debugging printfs");
100#endif
101
102static int	bwn_bfp = 0;		/* use "Bad Frames Preemption" */
103SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0,
104    "uses Bad Frames Preemption");
105static int	bwn_bluetooth = 1;
106SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0,
107    "turns on Bluetooth Coexistence");
108static int	bwn_hwpctl = 0;
109SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0,
110    "uses H/W power control");
111static int	bwn_msi_disable = 0;		/* MSI disabled  */
112TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable);
113static int	bwn_usedma = 1;
114SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0,
115    "uses DMA");
116TUNABLE_INT("hw.bwn.usedma", &bwn_usedma);
117static int	bwn_wme = 1;
118SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
119    "uses WME support");
120
121static void	bwn_attach_pre(struct bwn_softc *);
122static int	bwn_attach_post(struct bwn_softc *);
123static void	bwn_sprom_bugfixes(device_t);
124static int	bwn_init(struct bwn_softc *);
125static void	bwn_parent(struct ieee80211com *);
126static void	bwn_start(struct bwn_softc *);
127static int	bwn_transmit(struct ieee80211com *, struct mbuf *);
128static int	bwn_attach_core(struct bwn_mac *);
129static int	bwn_phy_getinfo(struct bwn_mac *, int);
130static int	bwn_chiptest(struct bwn_mac *);
131static int	bwn_setup_channels(struct bwn_mac *, int, int);
132static void	bwn_shm_ctlword(struct bwn_mac *, uint16_t,
133		    uint16_t);
134static void	bwn_addchannels(struct ieee80211_channel [], int, int *,
135		    const struct bwn_channelinfo *, const uint8_t []);
136static int	bwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
137		    const struct ieee80211_bpf_params *);
138static void	bwn_updateslot(struct ieee80211com *);
139static void	bwn_update_promisc(struct ieee80211com *);
140static void	bwn_wme_init(struct bwn_mac *);
141static int	bwn_wme_update(struct ieee80211com *);
142static void	bwn_wme_clear(struct bwn_softc *);
143static void	bwn_wme_load(struct bwn_mac *);
144static void	bwn_wme_loadparams(struct bwn_mac *,
145		    const struct wmeParams *, uint16_t);
146static void	bwn_scan_start(struct ieee80211com *);
147static void	bwn_scan_end(struct ieee80211com *);
148static void	bwn_set_channel(struct ieee80211com *);
149static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
150		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
151		    const uint8_t [IEEE80211_ADDR_LEN],
152		    const uint8_t [IEEE80211_ADDR_LEN]);
153static void	bwn_vap_delete(struct ieee80211vap *);
154static void	bwn_stop(struct bwn_softc *);
155static int	bwn_core_init(struct bwn_mac *);
156static void	bwn_core_start(struct bwn_mac *);
157static void	bwn_core_exit(struct bwn_mac *);
158static void	bwn_bt_disable(struct bwn_mac *);
159static int	bwn_chip_init(struct bwn_mac *);
160static void	bwn_set_txretry(struct bwn_mac *, int, int);
161static void	bwn_rate_init(struct bwn_mac *);
162static void	bwn_set_phytxctl(struct bwn_mac *);
163static void	bwn_spu_setdelay(struct bwn_mac *, int);
164static void	bwn_bt_enable(struct bwn_mac *);
165static void	bwn_set_macaddr(struct bwn_mac *);
166static void	bwn_crypt_init(struct bwn_mac *);
167static void	bwn_chip_exit(struct bwn_mac *);
168static int	bwn_fw_fillinfo(struct bwn_mac *);
169static int	bwn_fw_loaducode(struct bwn_mac *);
170static int	bwn_gpio_init(struct bwn_mac *);
171static int	bwn_fw_loadinitvals(struct bwn_mac *);
172static int	bwn_phy_init(struct bwn_mac *);
173static void	bwn_set_txantenna(struct bwn_mac *, int);
174static void	bwn_set_opmode(struct bwn_mac *);
175static void	bwn_rate_write(struct bwn_mac *, uint16_t, int);
176static uint8_t	bwn_plcp_getcck(const uint8_t);
177static uint8_t	bwn_plcp_getofdm(const uint8_t);
178static void	bwn_pio_init(struct bwn_mac *);
179static uint16_t	bwn_pio_idx2base(struct bwn_mac *, int);
180static void	bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *,
181		    int);
182static void	bwn_pio_setupqueue_rx(struct bwn_mac *,
183		    struct bwn_pio_rxqueue *, int);
184static void	bwn_destroy_queue_tx(struct bwn_pio_txqueue *);
185static uint16_t	bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *,
186		    uint16_t);
187static void	bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *);
188static int	bwn_pio_rx(struct bwn_pio_rxqueue *);
189static uint8_t	bwn_pio_rxeof(struct bwn_pio_rxqueue *);
190static void	bwn_pio_handle_txeof(struct bwn_mac *,
191		    const struct bwn_txstatus *);
192static uint16_t	bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t);
193static uint32_t	bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t);
194static void	bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t,
195		    uint16_t);
196static void	bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t,
197		    uint32_t);
198static int	bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *,
199		    struct mbuf *);
200static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t);
201static uint32_t	bwn_pio_write_multi_4(struct bwn_mac *,
202		    struct bwn_pio_txqueue *, uint32_t, const void *, int);
203static void	bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *,
204		    uint16_t, uint32_t);
205static uint16_t	bwn_pio_write_multi_2(struct bwn_mac *,
206		    struct bwn_pio_txqueue *, uint16_t, const void *, int);
207static uint16_t	bwn_pio_write_mbuf_2(struct bwn_mac *,
208		    struct bwn_pio_txqueue *, uint16_t, struct mbuf *);
209static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *,
210		    uint16_t, struct bwn_pio_txpkt **);
211static void	bwn_dma_init(struct bwn_mac *);
212static void	bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t);
213static int	bwn_dma_mask2type(uint64_t);
214static uint64_t	bwn_dma_mask(struct bwn_mac *);
215static uint16_t	bwn_dma_base(int, int);
216static void	bwn_dma_ringfree(struct bwn_dma_ring **);
217static void	bwn_dma_32_getdesc(struct bwn_dma_ring *,
218		    int, struct bwn_dmadesc_generic **,
219		    struct bwn_dmadesc_meta **);
220static void	bwn_dma_32_setdesc(struct bwn_dma_ring *,
221		    struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
222		    int, int);
223static void	bwn_dma_32_start_transfer(struct bwn_dma_ring *, int);
224static void	bwn_dma_32_suspend(struct bwn_dma_ring *);
225static void	bwn_dma_32_resume(struct bwn_dma_ring *);
226static int	bwn_dma_32_get_curslot(struct bwn_dma_ring *);
227static void	bwn_dma_32_set_curslot(struct bwn_dma_ring *, int);
228static void	bwn_dma_64_getdesc(struct bwn_dma_ring *,
229		    int, struct bwn_dmadesc_generic **,
230		    struct bwn_dmadesc_meta **);
231static void	bwn_dma_64_setdesc(struct bwn_dma_ring *,
232		    struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
233		    int, int);
234static void	bwn_dma_64_start_transfer(struct bwn_dma_ring *, int);
235static void	bwn_dma_64_suspend(struct bwn_dma_ring *);
236static void	bwn_dma_64_resume(struct bwn_dma_ring *);
237static int	bwn_dma_64_get_curslot(struct bwn_dma_ring *);
238static void	bwn_dma_64_set_curslot(struct bwn_dma_ring *, int);
239static int	bwn_dma_allocringmemory(struct bwn_dma_ring *);
240static void	bwn_dma_setup(struct bwn_dma_ring *);
241static void	bwn_dma_free_ringmemory(struct bwn_dma_ring *);
242static void	bwn_dma_cleanup(struct bwn_dma_ring *);
243static void	bwn_dma_free_descbufs(struct bwn_dma_ring *);
244static int	bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int);
245static void	bwn_dma_rx(struct bwn_dma_ring *);
246static int	bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int);
247static void	bwn_dma_free_descbuf(struct bwn_dma_ring *,
248		    struct bwn_dmadesc_meta *);
249static void	bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *);
250static int	bwn_dma_gettype(struct bwn_mac *);
251static void	bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
252static int	bwn_dma_freeslot(struct bwn_dma_ring *);
253static int	bwn_dma_nextslot(struct bwn_dma_ring *, int);
254static void	bwn_dma_rxeof(struct bwn_dma_ring *, int *);
255static int	bwn_dma_newbuf(struct bwn_dma_ring *,
256		    struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *,
257		    int);
258static void	bwn_dma_buf_addr(void *, bus_dma_segment_t *, int,
259		    bus_size_t, int);
260static uint8_t	bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *);
261static void	bwn_dma_handle_txeof(struct bwn_mac *,
262		    const struct bwn_txstatus *);
263static int	bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *,
264		    struct mbuf *);
265static int	bwn_dma_getslot(struct bwn_dma_ring *);
266static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *,
267		    uint8_t);
268static int	bwn_dma_attach(struct bwn_mac *);
269static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *,
270		    int, int, int);
271static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *,
272		    const struct bwn_txstatus *, uint16_t, int *);
273static void	bwn_dma_free(struct bwn_mac *);
274static int	bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype);
275static int	bwn_fw_get(struct bwn_mac *, enum bwn_fwtype,
276		    const char *, struct bwn_fwfile *);
277static void	bwn_release_firmware(struct bwn_mac *);
278static void	bwn_do_release_fw(struct bwn_fwfile *);
279static uint16_t	bwn_fwcaps_read(struct bwn_mac *);
280static int	bwn_fwinitvals_write(struct bwn_mac *,
281		    const struct bwn_fwinitvals *, size_t, size_t);
282static uint16_t	bwn_ant2phy(int);
283static void	bwn_mac_write_bssid(struct bwn_mac *);
284static void	bwn_mac_setfilter(struct bwn_mac *, uint16_t,
285		    const uint8_t *);
286static void	bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t,
287		    const uint8_t *, size_t, const uint8_t *);
288static void	bwn_key_macwrite(struct bwn_mac *, uint8_t,
289		    const uint8_t *);
290static void	bwn_key_write(struct bwn_mac *, uint8_t, uint8_t,
291		    const uint8_t *);
292static void	bwn_phy_exit(struct bwn_mac *);
293static void	bwn_core_stop(struct bwn_mac *);
294static int	bwn_switch_band(struct bwn_softc *,
295		    struct ieee80211_channel *);
296static void	bwn_phy_reset(struct bwn_mac *);
297static int	bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
298static void	bwn_set_pretbtt(struct bwn_mac *);
299static int	bwn_intr(void *);
300static void	bwn_intrtask(void *, int);
301static void	bwn_restart(struct bwn_mac *, const char *);
302static void	bwn_intr_ucode_debug(struct bwn_mac *);
303static void	bwn_intr_tbtt_indication(struct bwn_mac *);
304static void	bwn_intr_atim_end(struct bwn_mac *);
305static void	bwn_intr_beacon(struct bwn_mac *);
306static void	bwn_intr_pmq(struct bwn_mac *);
307static void	bwn_intr_noise(struct bwn_mac *);
308static void	bwn_intr_txeof(struct bwn_mac *);
309static void	bwn_hwreset(void *, int);
310static void	bwn_handle_fwpanic(struct bwn_mac *);
311static void	bwn_load_beacon0(struct bwn_mac *);
312static void	bwn_load_beacon1(struct bwn_mac *);
313static uint32_t	bwn_jssi_read(struct bwn_mac *);
314static void	bwn_noise_gensample(struct bwn_mac *);
315static void	bwn_handle_txeof(struct bwn_mac *,
316		    const struct bwn_txstatus *);
317static void	bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *);
318static void	bwn_phy_txpower_check(struct bwn_mac *, uint32_t);
319static int	bwn_tx_start(struct bwn_softc *, struct ieee80211_node *,
320		    struct mbuf *);
321static int	bwn_tx_isfull(struct bwn_softc *, struct mbuf *);
322static int	bwn_set_txhdr(struct bwn_mac *,
323		    struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *,
324		    uint16_t);
325static void	bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t,
326		    const uint8_t);
327static uint8_t	bwn_antenna_sanitize(struct bwn_mac *, uint8_t);
328static uint8_t	bwn_get_fbrate(uint8_t);
329static void	bwn_txpwr(void *, int);
330static void	bwn_tasks(void *);
331static void	bwn_task_15s(struct bwn_mac *);
332static void	bwn_task_30s(struct bwn_mac *);
333static void	bwn_task_60s(struct bwn_mac *);
334static int	bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *,
335		    uint8_t);
336static int	bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *);
337static void	bwn_rx_radiotap(struct bwn_mac *, struct mbuf *,
338		    const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int,
339		    int, int);
340static void	bwn_tsf_read(struct bwn_mac *, uint64_t *);
341static void	bwn_set_slot_time(struct bwn_mac *, uint16_t);
342static void	bwn_watchdog(void *);
343static void	bwn_dma_stop(struct bwn_mac *);
344static void	bwn_pio_stop(struct bwn_mac *);
345static void	bwn_dma_ringstop(struct bwn_dma_ring **);
346static void	bwn_led_attach(struct bwn_mac *);
347static void	bwn_led_newstate(struct bwn_mac *, enum ieee80211_state);
348static void	bwn_led_event(struct bwn_mac *, int);
349static void	bwn_led_blink_start(struct bwn_mac *, int, int);
350static void	bwn_led_blink_next(void *);
351static void	bwn_led_blink_end(void *);
352static void	bwn_rfswitch(void *);
353static void	bwn_rf_turnon(struct bwn_mac *);
354static void	bwn_rf_turnoff(struct bwn_mac *);
355static void	bwn_sysctl_node(struct bwn_softc *);
356
357static struct resource_spec bwn_res_spec_legacy[] = {
358	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
359	{ -1,			0,		0 }
360};
361
362static struct resource_spec bwn_res_spec_msi[] = {
363	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
364	{ -1,			0,		0 }
365};
366
367static const struct bwn_channelinfo bwn_chantable_bg = {
368	.channels = {
369		{ 2412,  1, 30 }, { 2417,  2, 30 }, { 2422,  3, 30 },
370		{ 2427,  4, 30 }, { 2432,  5, 30 }, { 2437,  6, 30 },
371		{ 2442,  7, 30 }, { 2447,  8, 30 }, { 2452,  9, 30 },
372		{ 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 },
373		{ 2472, 13, 30 }, { 2484, 14, 30 } },
374	.nchannels = 14
375};
376
377static const struct bwn_channelinfo bwn_chantable_a = {
378	.channels = {
379		{ 5170,  34, 30 }, { 5180,  36, 30 }, { 5190,  38, 30 },
380		{ 5200,  40, 30 }, { 5210,  42, 30 }, { 5220,  44, 30 },
381		{ 5230,  46, 30 }, { 5240,  48, 30 }, { 5260,  52, 30 },
382		{ 5280,  56, 30 }, { 5300,  60, 30 }, { 5320,  64, 30 },
383		{ 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 },
384		{ 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 },
385		{ 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 },
386		{ 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 },
387		{ 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 },
388		{ 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 },
389		{ 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 },
390		{ 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 },
391		{ 6080, 216, 30 } },
392	.nchannels = 37
393};
394
395#if 0
396static const struct bwn_channelinfo bwn_chantable_n = {
397	.channels = {
398		{ 5160,  32, 30 }, { 5170,  34, 30 }, { 5180,  36, 30 },
399		{ 5190,  38, 30 }, { 5200,  40, 30 }, { 5210,  42, 30 },
400		{ 5220,  44, 30 }, { 5230,  46, 30 }, { 5240,  48, 30 },
401		{ 5250,  50, 30 }, { 5260,  52, 30 }, { 5270,  54, 30 },
402		{ 5280,  56, 30 }, { 5290,  58, 30 }, { 5300,  60, 30 },
403		{ 5310,  62, 30 }, { 5320,  64, 30 }, { 5330,  66, 30 },
404		{ 5340,  68, 30 }, { 5350,  70, 30 }, { 5360,  72, 30 },
405		{ 5370,  74, 30 }, { 5380,  76, 30 }, { 5390,  78, 30 },
406		{ 5400,  80, 30 }, { 5410,  82, 30 }, { 5420,  84, 30 },
407		{ 5430,  86, 30 }, { 5440,  88, 30 }, { 5450,  90, 30 },
408		{ 5460,  92, 30 }, { 5470,  94, 30 }, { 5480,  96, 30 },
409		{ 5490,  98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 },
410		{ 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 },
411		{ 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 },
412		{ 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 },
413		{ 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 },
414		{ 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 },
415		{ 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 },
416		{ 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 },
417		{ 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 },
418		{ 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 },
419		{ 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 },
420		{ 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 },
421		{ 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 },
422		{ 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 },
423		{ 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 },
424		{ 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 },
425		{ 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 },
426		{ 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 },
427		{ 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 },
428		{ 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 },
429		{ 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 },
430		{ 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 },
431		{ 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 },
432		{ 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 },
433		{ 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 },
434		{ 6130, 226, 30 }, { 6140, 228, 30 } },
435	.nchannels = 110
436};
437#endif
438
439#define	VENDOR_LED_ACT(vendor)				\
440{							\
441	.vid = PCI_VENDOR_##vendor,			\
442	.led_act = { BWN_VENDOR_LED_ACT_##vendor }	\
443}
444
445static const struct {
446	uint16_t	vid;
447	uint8_t		led_act[BWN_LED_MAX];
448} bwn_vendor_led_act[] = {
449	VENDOR_LED_ACT(COMPAQ),
450	VENDOR_LED_ACT(ASUSTEK)
451};
452
453static const uint8_t bwn_default_led_act[BWN_LED_MAX] =
454	{ BWN_VENDOR_LED_ACT_DEFAULT };
455
456#undef VENDOR_LED_ACT
457
458static const struct {
459	int		on_dur;
460	int		off_dur;
461} bwn_led_duration[109] = {
462	[0]	= { 400, 100 },
463	[2]	= { 150, 75 },
464	[4]	= { 90, 45 },
465	[11]	= { 66, 34 },
466	[12]	= { 53, 26 },
467	[18]	= { 42, 21 },
468	[22]	= { 35, 17 },
469	[24]	= { 32, 16 },
470	[36]	= { 21, 10 },
471	[48]	= { 16, 8 },
472	[72]	= { 11, 5 },
473	[96]	= { 9, 4 },
474	[108]	= { 7, 3 }
475};
476
477static const uint16_t bwn_wme_shm_offsets[] = {
478	[0] = BWN_WME_BESTEFFORT,
479	[1] = BWN_WME_BACKGROUND,
480	[2] = BWN_WME_VOICE,
481	[3] = BWN_WME_VIDEO,
482};
483
484static const struct siba_devid bwn_devs[] = {
485	SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"),
486	SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"),
487	SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"),
488	SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"),
489	SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"),
490	SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"),
491	SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"),
492	SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"),
493	SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"),
494	SIBA_DEV(BROADCOM, 80211, 16, "Revision 16")
495};
496
497static int
498bwn_probe(device_t dev)
499{
500	int i;
501
502	for (i = 0; i < nitems(bwn_devs); i++) {
503		if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor &&
504		    siba_get_device(dev) == bwn_devs[i].sd_device &&
505		    siba_get_revid(dev) == bwn_devs[i].sd_rev)
506			return (BUS_PROBE_DEFAULT);
507	}
508
509	return (ENXIO);
510}
511
512static int
513bwn_attach(device_t dev)
514{
515	struct bwn_mac *mac;
516	struct bwn_softc *sc = device_get_softc(dev);
517	int error, i, msic, reg;
518
519	sc->sc_dev = dev;
520#ifdef BWN_DEBUG
521	sc->sc_debug = bwn_debug;
522#endif
523
524	if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
525		bwn_attach_pre(sc);
526		bwn_sprom_bugfixes(dev);
527		sc->sc_flags |= BWN_FLAG_ATTACHED;
528	}
529
530	if (!TAILQ_EMPTY(&sc->sc_maclist)) {
531		if (siba_get_pci_device(dev) != 0x4313 &&
532		    siba_get_pci_device(dev) != 0x431a &&
533		    siba_get_pci_device(dev) != 0x4321) {
534			device_printf(sc->sc_dev,
535			    "skip 802.11 cores\n");
536			return (ENODEV);
537		}
538	}
539
540	mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO);
541	mac->mac_sc = sc;
542	mac->mac_status = BWN_MAC_STATUS_UNINIT;
543	if (bwn_bfp != 0)
544		mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP;
545
546	TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac);
547	TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac);
548	TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac);
549
550	error = bwn_attach_core(mac);
551	if (error)
552		goto fail0;
553	bwn_led_attach(mac);
554
555	device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) "
556	    "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
557	    siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev),
558	    mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev,
559	    mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver,
560	    mac->mac_phy.rf_rev);
561	if (mac->mac_flags & BWN_MAC_FLAG_DMA)
562		device_printf(sc->sc_dev, "DMA (%d bits)\n",
563		    mac->mac_method.dma.dmatype);
564	else
565		device_printf(sc->sc_dev, "PIO\n");
566
567#ifdef	BWN_GPL_PHY
568	device_printf(sc->sc_dev,
569	    "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n");
570#endif
571
572	/*
573	 * setup PCI resources and interrupt.
574	 */
575	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
576		msic = pci_msi_count(dev);
577		if (bootverbose)
578			device_printf(sc->sc_dev, "MSI count : %d\n", msic);
579	} else
580		msic = 0;
581
582	mac->mac_intr_spec = bwn_res_spec_legacy;
583	if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) {
584		if (pci_alloc_msi(dev, &msic) == 0) {
585			device_printf(sc->sc_dev,
586			    "Using %d MSI messages\n", msic);
587			mac->mac_intr_spec = bwn_res_spec_msi;
588			mac->mac_msi = 1;
589		}
590	}
591
592	error = bus_alloc_resources(dev, mac->mac_intr_spec,
593	    mac->mac_res_irq);
594	if (error) {
595		device_printf(sc->sc_dev,
596		    "couldn't allocate IRQ resources (%d)\n", error);
597		goto fail1;
598	}
599
600	if (mac->mac_msi == 0)
601		error = bus_setup_intr(dev, mac->mac_res_irq[0],
602		    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
603		    &mac->mac_intrhand[0]);
604	else {
605		for (i = 0; i < BWN_MSI_MESSAGES; i++) {
606			error = bus_setup_intr(dev, mac->mac_res_irq[i],
607			    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
608			    &mac->mac_intrhand[i]);
609			if (error != 0) {
610				device_printf(sc->sc_dev,
611				    "couldn't setup interrupt (%d)\n", error);
612				break;
613			}
614		}
615	}
616
617	TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list);
618
619	/*
620	 * calls attach-post routine
621	 */
622	if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0)
623		bwn_attach_post(sc);
624
625	return (0);
626fail1:
627	if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0)
628		pci_release_msi(dev);
629fail0:
630	free(mac, M_DEVBUF);
631	return (error);
632}
633
634static int
635bwn_is_valid_ether_addr(uint8_t *addr)
636{
637	char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
638
639	if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN)))
640		return (FALSE);
641
642	return (TRUE);
643}
644
645static int
646bwn_attach_post(struct bwn_softc *sc)
647{
648	struct ieee80211com *ic = &sc->sc_ic;
649
650	ic->ic_softc = sc;
651	ic->ic_name = device_get_nameunit(sc->sc_dev);
652	/* XXX not right but it's not used anywhere important */
653	ic->ic_phytype = IEEE80211_T_OFDM;
654	ic->ic_opmode = IEEE80211_M_STA;
655	ic->ic_caps =
656		  IEEE80211_C_STA		/* station mode supported */
657		| IEEE80211_C_MONITOR		/* monitor mode */
658		| IEEE80211_C_AHDEMO		/* adhoc demo mode */
659		| IEEE80211_C_SHPREAMBLE	/* short preamble supported */
660		| IEEE80211_C_SHSLOT		/* short slot time supported */
661		| IEEE80211_C_WME		/* WME/WMM supported */
662		| IEEE80211_C_WPA		/* capable of WPA1+WPA2 */
663#if 0
664		| IEEE80211_C_BGSCAN		/* capable of bg scanning */
665#endif
666		| IEEE80211_C_TXPMGT		/* capable of txpow mgt */
667		;
668
669	ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;	/* s/w bmiss */
670
671	IEEE80211_ADDR_COPY(ic->ic_macaddr,
672	    bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ?
673	    siba_sprom_get_mac_80211a(sc->sc_dev) :
674	    siba_sprom_get_mac_80211bg(sc->sc_dev));
675
676	/* call MI attach routine. */
677	ieee80211_ifattach(ic);
678
679	ic->ic_headroom = sizeof(struct bwn_txhdr);
680
681	/* override default methods */
682	ic->ic_raw_xmit = bwn_raw_xmit;
683	ic->ic_updateslot = bwn_updateslot;
684	ic->ic_update_promisc = bwn_update_promisc;
685	ic->ic_wme.wme_update = bwn_wme_update;
686	ic->ic_scan_start = bwn_scan_start;
687	ic->ic_scan_end = bwn_scan_end;
688	ic->ic_set_channel = bwn_set_channel;
689	ic->ic_vap_create = bwn_vap_create;
690	ic->ic_vap_delete = bwn_vap_delete;
691	ic->ic_transmit = bwn_transmit;
692	ic->ic_parent = bwn_parent;
693
694	ieee80211_radiotap_attach(ic,
695	    &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
696	    BWN_TX_RADIOTAP_PRESENT,
697	    &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
698	    BWN_RX_RADIOTAP_PRESENT);
699
700	bwn_sysctl_node(sc);
701
702	if (bootverbose)
703		ieee80211_announce(ic);
704	return (0);
705}
706
707static void
708bwn_phy_detach(struct bwn_mac *mac)
709{
710
711	if (mac->mac_phy.detach != NULL)
712		mac->mac_phy.detach(mac);
713}
714
715static int
716bwn_detach(device_t dev)
717{
718	struct bwn_softc *sc = device_get_softc(dev);
719	struct bwn_mac *mac = sc->sc_curmac;
720	struct ieee80211com *ic = &sc->sc_ic;
721	int i;
722
723	sc->sc_flags |= BWN_FLAG_INVALID;
724
725	if (device_is_attached(sc->sc_dev)) {
726		BWN_LOCK(sc);
727		bwn_stop(sc);
728		BWN_UNLOCK(sc);
729		bwn_dma_free(mac);
730		callout_drain(&sc->sc_led_blink_ch);
731		callout_drain(&sc->sc_rfswitch_ch);
732		callout_drain(&sc->sc_task_ch);
733		callout_drain(&sc->sc_watchdog_ch);
734		bwn_phy_detach(mac);
735		ieee80211_draintask(ic, &mac->mac_hwreset);
736		ieee80211_draintask(ic, &mac->mac_txpower);
737		ieee80211_ifdetach(ic);
738	}
739	taskqueue_drain(sc->sc_tq, &mac->mac_intrtask);
740	taskqueue_free(sc->sc_tq);
741
742	for (i = 0; i < BWN_MSI_MESSAGES; i++) {
743		if (mac->mac_intrhand[i] != NULL) {
744			bus_teardown_intr(dev, mac->mac_res_irq[i],
745			    mac->mac_intrhand[i]);
746			mac->mac_intrhand[i] = NULL;
747		}
748	}
749	bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq);
750	if (mac->mac_msi != 0)
751		pci_release_msi(dev);
752	mbufq_drain(&sc->sc_snd);
753	BWN_LOCK_DESTROY(sc);
754	return (0);
755}
756
757static void
758bwn_attach_pre(struct bwn_softc *sc)
759{
760
761	BWN_LOCK_INIT(sc);
762	TAILQ_INIT(&sc->sc_maclist);
763	callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0);
764	callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0);
765	callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0);
766	mbufq_init(&sc->sc_snd, ifqmaxlen);
767	sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT,
768		taskqueue_thread_enqueue, &sc->sc_tq);
769	taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
770		"%s taskq", device_get_nameunit(sc->sc_dev));
771}
772
773static void
774bwn_sprom_bugfixes(device_t dev)
775{
776#define	BWN_ISDEV(_vendor, _device, _subvendor, _subdevice)		\
777	((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) &&		\
778	 (siba_get_pci_device(dev) == _device) &&			\
779	 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) &&	\
780	 (siba_get_pci_subdevice(dev) == _subdevice))
781
782	if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE &&
783	    siba_get_pci_subdevice(dev) == 0x4e &&
784	    siba_get_pci_revid(dev) > 0x40)
785		siba_sprom_set_bf_lo(dev,
786		    siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL);
787	if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL &&
788	    siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74)
789		siba_sprom_set_bf_lo(dev,
790		    siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST);
791	if (siba_get_type(dev) == SIBA_TYPE_PCI) {
792		if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) ||
793		    BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) ||
794		    BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) ||
795		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) ||
796		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) ||
797		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) ||
798		    BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010))
799			siba_sprom_set_bf_lo(dev,
800			    siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST);
801	}
802#undef	BWN_ISDEV
803}
804
805static void
806bwn_parent(struct ieee80211com *ic)
807{
808	struct bwn_softc *sc = ic->ic_softc;
809	int startall = 0;
810
811	BWN_LOCK(sc);
812	if (ic->ic_nrunning > 0) {
813		if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
814			bwn_init(sc);
815			startall = 1;
816		} else
817			bwn_update_promisc(ic);
818	} else if (sc->sc_flags & BWN_FLAG_RUNNING)
819		bwn_stop(sc);
820	BWN_UNLOCK(sc);
821
822	if (startall)
823		ieee80211_start_all(ic);
824}
825
826static int
827bwn_transmit(struct ieee80211com *ic, struct mbuf *m)
828{
829	struct bwn_softc *sc = ic->ic_softc;
830	int error;
831
832	BWN_LOCK(sc);
833	if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
834		BWN_UNLOCK(sc);
835		return (ENXIO);
836	}
837	error = mbufq_enqueue(&sc->sc_snd, m);
838	if (error) {
839		BWN_UNLOCK(sc);
840		return (error);
841	}
842	bwn_start(sc);
843	BWN_UNLOCK(sc);
844	return (0);
845}
846
847static void
848bwn_start(struct bwn_softc *sc)
849{
850	struct bwn_mac *mac = sc->sc_curmac;
851	struct ieee80211_frame *wh;
852	struct ieee80211_node *ni;
853	struct ieee80211_key *k;
854	struct mbuf *m;
855
856	BWN_ASSERT_LOCKED(sc);
857
858	if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL ||
859	    mac->mac_status < BWN_MAC_STATUS_STARTED)
860		return;
861
862	while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
863		if (bwn_tx_isfull(sc, m))
864			break;
865		ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
866		if (ni == NULL) {
867			device_printf(sc->sc_dev, "unexpected NULL ni\n");
868			m_freem(m);
869			counter_u64_add(sc->sc_ic.ic_oerrors, 1);
870			continue;
871		}
872		wh = mtod(m, struct ieee80211_frame *);
873		if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
874			k = ieee80211_crypto_encap(ni, m);
875			if (k == NULL) {
876				if_inc_counter(ni->ni_vap->iv_ifp,
877				    IFCOUNTER_OERRORS, 1);
878				ieee80211_free_node(ni);
879				m_freem(m);
880				continue;
881			}
882		}
883		wh = NULL;	/* Catch any invalid use */
884		if (bwn_tx_start(sc, ni, m) != 0) {
885			if (ni != NULL) {
886				if_inc_counter(ni->ni_vap->iv_ifp,
887				    IFCOUNTER_OERRORS, 1);
888				ieee80211_free_node(ni);
889			}
890			continue;
891		}
892		sc->sc_watchdog_timer = 5;
893	}
894}
895
896static int
897bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m)
898{
899	struct bwn_dma_ring *dr;
900	struct bwn_mac *mac = sc->sc_curmac;
901	struct bwn_pio_txqueue *tq;
902	int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
903
904	BWN_ASSERT_LOCKED(sc);
905
906	if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
907		dr = bwn_dma_select(mac, M_WME_GETAC(m));
908		if (dr->dr_stop == 1 ||
909		    bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) {
910			dr->dr_stop = 1;
911			goto full;
912		}
913	} else {
914		tq = bwn_pio_select(mac, M_WME_GETAC(m));
915		if (tq->tq_free == 0 || pktlen > tq->tq_size ||
916		    pktlen > (tq->tq_size - tq->tq_used))
917			goto full;
918	}
919	return (0);
920full:
921	mbufq_prepend(&sc->sc_snd, m);
922	return (1);
923}
924
925static int
926bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m)
927{
928	struct bwn_mac *mac = sc->sc_curmac;
929	int error;
930
931	BWN_ASSERT_LOCKED(sc);
932
933	if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) {
934		m_freem(m);
935		return (ENXIO);
936	}
937
938	error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ?
939	    bwn_dma_tx_start(mac, ni, m) : bwn_pio_tx_start(mac, ni, m);
940	if (error) {
941		m_freem(m);
942		return (error);
943	}
944	return (0);
945}
946
947static int
948bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m)
949{
950	struct bwn_pio_txpkt *tp;
951	struct bwn_pio_txqueue *tq = bwn_pio_select(mac, M_WME_GETAC(m));
952	struct bwn_softc *sc = mac->mac_sc;
953	struct bwn_txhdr txhdr;
954	struct mbuf *m_new;
955	uint32_t ctl32;
956	int error;
957	uint16_t ctl16;
958
959	BWN_ASSERT_LOCKED(sc);
960
961	/* XXX TODO send packets after DTIM */
962
963	KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__));
964	tp = TAILQ_FIRST(&tq->tq_pktlist);
965	tp->tp_ni = ni;
966	tp->tp_m = m;
967
968	error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp));
969	if (error) {
970		device_printf(sc->sc_dev, "tx fail\n");
971		return (error);
972	}
973
974	TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list);
975	tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
976	tq->tq_free--;
977
978	if (siba_get_revid(sc->sc_dev) >= 8) {
979		/*
980		 * XXX please removes m_defrag(9)
981		 */
982		m_new = m_defrag(m, M_NOWAIT);
983		if (m_new == NULL) {
984			device_printf(sc->sc_dev,
985			    "%s: can't defrag TX buffer\n",
986			    __func__);
987			return (ENOBUFS);
988		}
989		if (m_new->m_next != NULL)
990			device_printf(sc->sc_dev,
991			    "TODO: fragmented packets for PIO\n");
992		tp->tp_m = m_new;
993
994		/* send HEADER */
995		ctl32 = bwn_pio_write_multi_4(mac, tq,
996		    (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) |
997			BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF,
998		    (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
999		/* send BODY */
1000		ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32,
1001		    mtod(m_new, const void *), m_new->m_pkthdr.len);
1002		bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL,
1003		    ctl32 | BWN_PIO8_TXCTL_EOF);
1004	} else {
1005		ctl16 = bwn_pio_write_multi_2(mac, tq,
1006		    (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) |
1007			BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF,
1008		    (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1009		ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m);
1010		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL,
1011		    ctl16 | BWN_PIO_TXCTL_EOF);
1012	}
1013
1014	return (0);
1015}
1016
1017static struct bwn_pio_txqueue *
1018bwn_pio_select(struct bwn_mac *mac, uint8_t prio)
1019{
1020
1021	if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
1022		return (&mac->mac_method.pio.wme[WME_AC_BE]);
1023
1024	switch (prio) {
1025	case 0:
1026		return (&mac->mac_method.pio.wme[WME_AC_BE]);
1027	case 1:
1028		return (&mac->mac_method.pio.wme[WME_AC_BK]);
1029	case 2:
1030		return (&mac->mac_method.pio.wme[WME_AC_VI]);
1031	case 3:
1032		return (&mac->mac_method.pio.wme[WME_AC_VO]);
1033	}
1034	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
1035	return (NULL);
1036}
1037
1038static int
1039bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m)
1040{
1041#define	BWN_GET_TXHDRCACHE(slot)					\
1042	&(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)])
1043	struct bwn_dma *dma = &mac->mac_method.dma;
1044	struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(m));
1045	struct bwn_dmadesc_generic *desc;
1046	struct bwn_dmadesc_meta *mt;
1047	struct bwn_softc *sc = mac->mac_sc;
1048	uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache;
1049	int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot };
1050
1051	BWN_ASSERT_LOCKED(sc);
1052	KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__));
1053
1054	/* XXX send after DTIM */
1055
1056	slot = bwn_dma_getslot(dr);
1057	dr->getdesc(dr, slot, &desc, &mt);
1058	KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER,
1059	    ("%s:%d: fail", __func__, __LINE__));
1060
1061	error = bwn_set_txhdr(dr->dr_mac, ni, m,
1062	    (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot),
1063	    BWN_DMA_COOKIE(dr, slot));
1064	if (error)
1065		goto fail;
1066	error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap,
1067	    BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr,
1068	    &mt->mt_paddr, BUS_DMA_NOWAIT);
1069	if (error) {
1070		device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1071		    __func__, error);
1072		goto fail;
1073	}
1074	bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap,
1075	    BUS_DMASYNC_PREWRITE);
1076	dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0);
1077	bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1078	    BUS_DMASYNC_PREWRITE);
1079
1080	slot = bwn_dma_getslot(dr);
1081	dr->getdesc(dr, slot, &desc, &mt);
1082	KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY &&
1083	    mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__));
1084	mt->mt_m = m;
1085	mt->mt_ni = ni;
1086
1087	error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m,
1088	    bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1089	if (error && error != EFBIG) {
1090		device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1091		    __func__, error);
1092		goto fail;
1093	}
1094	if (error) {    /* error == EFBIG */
1095		struct mbuf *m_new;
1096
1097		m_new = m_defrag(m, M_NOWAIT);
1098		if (m_new == NULL) {
1099			device_printf(sc->sc_dev,
1100			    "%s: can't defrag TX buffer\n",
1101			    __func__);
1102			error = ENOBUFS;
1103			goto fail;
1104		} else {
1105			m = m_new;
1106		}
1107
1108		mt->mt_m = m;
1109		error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap,
1110		    m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1111		if (error) {
1112			device_printf(sc->sc_dev,
1113			    "%s: can't load TX buffer (2) %d\n",
1114			    __func__, error);
1115			goto fail;
1116		}
1117	}
1118	bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE);
1119	dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1);
1120	bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1121	    BUS_DMASYNC_PREWRITE);
1122
1123	/* XXX send after DTIM */
1124
1125	dr->start_transfer(dr, bwn_dma_nextslot(dr, slot));
1126	return (0);
1127fail:
1128	dr->dr_curslot = backup[0];
1129	dr->dr_usedslot = backup[1];
1130	return (error);
1131#undef BWN_GET_TXHDRCACHE
1132}
1133
1134static void
1135bwn_watchdog(void *arg)
1136{
1137	struct bwn_softc *sc = arg;
1138
1139	if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) {
1140		device_printf(sc->sc_dev, "device timeout\n");
1141		counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1142	}
1143	callout_schedule(&sc->sc_watchdog_ch, hz);
1144}
1145
1146static int
1147bwn_attach_core(struct bwn_mac *mac)
1148{
1149	struct bwn_softc *sc = mac->mac_sc;
1150	int error, have_bg = 0, have_a = 0;
1151	uint32_t high;
1152
1153	KASSERT(siba_get_revid(sc->sc_dev) >= 5,
1154	    ("unsupported revision %d", siba_get_revid(sc->sc_dev)));
1155
1156	siba_powerup(sc->sc_dev, 0);
1157
1158	high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
1159
1160	/*
1161	 * Guess at whether it has A-PHY or G-PHY.
1162	 * This is just used for resetting the core to probe things;
1163	 * we will re-guess once it's all up and working.
1164	 *
1165	 * XXX TODO: there's the TGSHIGH DUALPHY flag based on
1166	 * the PHY revision.
1167	 */
1168	bwn_reset_core(mac, !!(high & BWN_TGSHIGH_HAVE_2GHZ));
1169
1170	/*
1171	 * Get the PHY version.
1172	 */
1173	error = bwn_phy_getinfo(mac, high);
1174	if (error)
1175		goto fail;
1176
1177	/* XXX TODO need bhnd */
1178	if (bwn_is_bus_siba(mac)) {
1179		have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0;
1180		have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
1181		if (high & BWN_TGSHIGH_DUALPHY) {
1182			have_bg = 1;
1183			have_a = 1;
1184		}
1185	} else {
1186		device_printf(sc->sc_dev, "%s: not siba; bailing\n", __func__);
1187		error = ENXIO;
1188		goto fail;
1189	}
1190
1191#if 0
1192	device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d,"
1193	    " deviceid=0x%04x, siba_deviceid=0x%04x\n",
1194	    __func__,
1195	    high,
1196	    have_a,
1197	    have_bg,
1198	    siba_get_pci_device(sc->sc_dev),
1199	    siba_get_chipid(sc->sc_dev));
1200#endif
1201
1202	if (siba_get_pci_device(sc->sc_dev) != 0x4312 &&
1203	    siba_get_pci_device(sc->sc_dev) != 0x4319 &&
1204	    siba_get_pci_device(sc->sc_dev) != 0x4324 &&
1205	    siba_get_pci_device(sc->sc_dev) != 0x4328 &&
1206	    siba_get_pci_device(sc->sc_dev) != 0x432b) {
1207		have_a = have_bg = 0;
1208		if (mac->mac_phy.type == BWN_PHYTYPE_A)
1209			have_a = 1;
1210		else if (mac->mac_phy.type == BWN_PHYTYPE_G ||
1211		    mac->mac_phy.type == BWN_PHYTYPE_N ||
1212		    mac->mac_phy.type == BWN_PHYTYPE_LP)
1213			have_bg = 1;
1214		else
1215			KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__,
1216			    mac->mac_phy.type));
1217	}
1218
1219	/*
1220	 * XXX The PHY-G support doesn't do 5GHz operation.
1221	 */
1222	if (mac->mac_phy.type != BWN_PHYTYPE_LP &&
1223	    mac->mac_phy.type != BWN_PHYTYPE_N) {
1224		device_printf(sc->sc_dev,
1225		    "%s: forcing 2GHz only; no dual-band support for PHY\n",
1226		    __func__);
1227		have_a = 0;
1228		have_bg = 1;
1229	}
1230
1231	mac->mac_phy.phy_n = NULL;
1232
1233	if (mac->mac_phy.type == BWN_PHYTYPE_G) {
1234		mac->mac_phy.attach = bwn_phy_g_attach;
1235		mac->mac_phy.detach = bwn_phy_g_detach;
1236		mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw;
1237		mac->mac_phy.init_pre = bwn_phy_g_init_pre;
1238		mac->mac_phy.init = bwn_phy_g_init;
1239		mac->mac_phy.exit = bwn_phy_g_exit;
1240		mac->mac_phy.phy_read = bwn_phy_g_read;
1241		mac->mac_phy.phy_write = bwn_phy_g_write;
1242		mac->mac_phy.rf_read = bwn_phy_g_rf_read;
1243		mac->mac_phy.rf_write = bwn_phy_g_rf_write;
1244		mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl;
1245		mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff;
1246		mac->mac_phy.switch_analog = bwn_phy_switch_analog;
1247		mac->mac_phy.switch_channel = bwn_phy_g_switch_channel;
1248		mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan;
1249		mac->mac_phy.set_antenna = bwn_phy_g_set_antenna;
1250		mac->mac_phy.set_im = bwn_phy_g_im;
1251		mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr;
1252		mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr;
1253		mac->mac_phy.task_15s = bwn_phy_g_task_15s;
1254		mac->mac_phy.task_60s = bwn_phy_g_task_60s;
1255	} else if (mac->mac_phy.type == BWN_PHYTYPE_LP) {
1256		mac->mac_phy.init_pre = bwn_phy_lp_init_pre;
1257		mac->mac_phy.init = bwn_phy_lp_init;
1258		mac->mac_phy.phy_read = bwn_phy_lp_read;
1259		mac->mac_phy.phy_write = bwn_phy_lp_write;
1260		mac->mac_phy.phy_maskset = bwn_phy_lp_maskset;
1261		mac->mac_phy.rf_read = bwn_phy_lp_rf_read;
1262		mac->mac_phy.rf_write = bwn_phy_lp_rf_write;
1263		mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff;
1264		mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog;
1265		mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel;
1266		mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan;
1267		mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna;
1268		mac->mac_phy.task_60s = bwn_phy_lp_task_60s;
1269	} else if (mac->mac_phy.type == BWN_PHYTYPE_N) {
1270		mac->mac_phy.attach = bwn_phy_n_attach;
1271		mac->mac_phy.detach = bwn_phy_n_detach;
1272		mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw;
1273		mac->mac_phy.init_pre = bwn_phy_n_init_pre;
1274		mac->mac_phy.init = bwn_phy_n_init;
1275		mac->mac_phy.exit = bwn_phy_n_exit;
1276		mac->mac_phy.phy_read = bwn_phy_n_read;
1277		mac->mac_phy.phy_write = bwn_phy_n_write;
1278		mac->mac_phy.rf_read = bwn_phy_n_rf_read;
1279		mac->mac_phy.rf_write = bwn_phy_n_rf_write;
1280		mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl;
1281		mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff;
1282		mac->mac_phy.switch_analog = bwn_phy_n_switch_analog;
1283		mac->mac_phy.switch_channel = bwn_phy_n_switch_channel;
1284		mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan;
1285		mac->mac_phy.set_antenna = bwn_phy_n_set_antenna;
1286		mac->mac_phy.set_im = bwn_phy_n_im;
1287		mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr;
1288		mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr;
1289		mac->mac_phy.task_15s = bwn_phy_n_task_15s;
1290		mac->mac_phy.task_60s = bwn_phy_n_task_60s;
1291	} else {
1292		device_printf(sc->sc_dev, "unsupported PHY type (%d)\n",
1293		    mac->mac_phy.type);
1294		error = ENXIO;
1295		goto fail;
1296	}
1297
1298	mac->mac_phy.gmode = have_bg;
1299	if (mac->mac_phy.attach != NULL) {
1300		error = mac->mac_phy.attach(mac);
1301		if (error) {
1302			device_printf(sc->sc_dev, "failed\n");
1303			goto fail;
1304		}
1305	}
1306
1307	bwn_reset_core(mac, have_bg);
1308
1309	error = bwn_chiptest(mac);
1310	if (error)
1311		goto fail;
1312	error = bwn_setup_channels(mac, have_bg, have_a);
1313	if (error) {
1314		device_printf(sc->sc_dev, "failed to setup channels\n");
1315		goto fail;
1316	}
1317
1318	if (sc->sc_curmac == NULL)
1319		sc->sc_curmac = mac;
1320
1321	error = bwn_dma_attach(mac);
1322	if (error != 0) {
1323		device_printf(sc->sc_dev, "failed to initialize DMA\n");
1324		goto fail;
1325	}
1326
1327	mac->mac_phy.switch_analog(mac, 0);
1328
1329	siba_dev_down(sc->sc_dev, 0);
1330fail:
1331	siba_powerdown(sc->sc_dev);
1332	return (error);
1333}
1334
1335/*
1336 * Reset - SIBA.
1337 *
1338 * XXX TODO: implement BCMA version!
1339 */
1340void
1341bwn_reset_core(struct bwn_mac *mac, int g_mode)
1342{
1343	struct bwn_softc *sc = mac->mac_sc;
1344	uint32_t low, ctl;
1345	uint32_t flags = 0;
1346
1347	DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode);
1348
1349	flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET);
1350	if (g_mode)
1351		flags |= BWN_TGSLOW_SUPPORT_G;
1352
1353	/* XXX N-PHY only; and hard-code to 20MHz for now */
1354	if (mac->mac_phy.type == BWN_PHYTYPE_N)
1355		flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ;
1356
1357	siba_dev_up(sc->sc_dev, flags);
1358	DELAY(2000);
1359
1360	/* Take PHY out of reset */
1361	low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) &
1362	    ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE);
1363	siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
1364	siba_read_4(sc->sc_dev, SIBA_TGSLOW);
1365	DELAY(2000);
1366	low &= ~SIBA_TGSLOW_FGC;
1367	low |= BWN_TGSLOW_PHYCLOCK_ENABLE;
1368	siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
1369	siba_read_4(sc->sc_dev, SIBA_TGSLOW);
1370	DELAY(2000);
1371
1372	if (mac->mac_phy.switch_analog != NULL)
1373		mac->mac_phy.switch_analog(mac, 1);
1374
1375	ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE;
1376	if (g_mode)
1377		ctl |= BWN_MACCTL_GMODE;
1378	BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
1379}
1380
1381static int
1382bwn_phy_getinfo(struct bwn_mac *mac, int tgshigh)
1383{
1384	struct bwn_phy *phy = &mac->mac_phy;
1385	struct bwn_softc *sc = mac->mac_sc;
1386	uint32_t tmp;
1387
1388	/* PHY */
1389	tmp = BWN_READ_2(mac, BWN_PHYVER);
1390	phy->gmode = !! (tgshigh & BWN_TGSHIGH_HAVE_2GHZ);
1391	phy->rf_on = 1;
1392	phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1393	phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1394	phy->rev = (tmp & BWN_PHYVER_VERSION);
1395	if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1396	    (phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&
1397		phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||
1398	    (phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||
1399	    (phy->type == BWN_PHYTYPE_N && phy->rev > 4) ||
1400	    (phy->type == BWN_PHYTYPE_LP && phy->rev > 2))
1401		goto unsupphy;
1402
1403	/* RADIO */
1404	if (siba_get_chipid(sc->sc_dev) == 0x4317) {
1405		if (siba_get_chiprev(sc->sc_dev) == 0)
1406			tmp = 0x3205017f;
1407		else if (siba_get_chiprev(sc->sc_dev) == 1)
1408			tmp = 0x4205017f;
1409		else
1410			tmp = 0x5205017f;
1411	} else {
1412		BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1413		tmp = BWN_READ_2(mac, BWN_RFDATALO);
1414		BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1415		tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
1416	}
1417	phy->rf_rev = (tmp & 0xf0000000) >> 28;
1418	phy->rf_ver = (tmp & 0x0ffff000) >> 12;
1419	phy->rf_manuf = (tmp & 0x00000fff);
1420
1421	/*
1422	 * For now, just always do full init (ie, what bwn has traditionally
1423	 * done)
1424	 */
1425	phy->phy_do_full_init = 1;
1426
1427	if (phy->rf_manuf != 0x17f)	/* 0x17f is broadcom */
1428		goto unsupradio;
1429	if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 ||
1430	     phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) ||
1431	    (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) ||
1432	    (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) ||
1433	    (phy->type == BWN_PHYTYPE_N &&
1434	     phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) ||
1435	    (phy->type == BWN_PHYTYPE_LP &&
1436	     phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063))
1437		goto unsupradio;
1438
1439	return (0);
1440unsupphy:
1441	device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, "
1442	    "analog %#x)\n",
1443	    phy->type, phy->rev, phy->analog);
1444	return (ENXIO);
1445unsupradio:
1446	device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, "
1447	    "rev %#x)\n",
1448	    phy->rf_manuf, phy->rf_ver, phy->rf_rev);
1449	return (ENXIO);
1450}
1451
1452static int
1453bwn_chiptest(struct bwn_mac *mac)
1454{
1455#define	TESTVAL0	0x55aaaa55
1456#define	TESTVAL1	0xaa5555aa
1457	struct bwn_softc *sc = mac->mac_sc;
1458	uint32_t v, backup;
1459
1460	BWN_LOCK(sc);
1461
1462	backup = bwn_shm_read_4(mac, BWN_SHARED, 0);
1463
1464	bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0);
1465	if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0)
1466		goto error;
1467	bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1);
1468	if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1)
1469		goto error;
1470
1471	bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
1472
1473	if ((siba_get_revid(sc->sc_dev) >= 3) &&
1474	    (siba_get_revid(sc->sc_dev) <= 10)) {
1475		BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
1476		BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
1477		if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
1478			goto error;
1479		if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc)
1480			goto error;
1481	}
1482	BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0);
1483
1484	v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE;
1485	if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON))
1486		goto error;
1487
1488	BWN_UNLOCK(sc);
1489	return (0);
1490error:
1491	BWN_UNLOCK(sc);
1492	device_printf(sc->sc_dev, "failed to validate the chipaccess\n");
1493	return (ENODEV);
1494}
1495
1496static int
1497bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a)
1498{
1499	struct bwn_softc *sc = mac->mac_sc;
1500	struct ieee80211com *ic = &sc->sc_ic;
1501	uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)];
1502
1503	memset(ic->ic_channels, 0, sizeof(ic->ic_channels));
1504	ic->ic_nchans = 0;
1505
1506	DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n",
1507	    __func__,
1508	    have_bg,
1509	    have_a);
1510
1511	if (have_bg) {
1512		memset(bands, 0, sizeof(bands));
1513		setbit(bands, IEEE80211_MODE_11B);
1514		setbit(bands, IEEE80211_MODE_11G);
1515		bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1516		    &ic->ic_nchans, &bwn_chantable_bg, bands);
1517	}
1518
1519	if (have_a) {
1520		memset(bands, 0, sizeof(bands));
1521		setbit(bands, IEEE80211_MODE_11A);
1522		bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1523		    &ic->ic_nchans, &bwn_chantable_a, bands);
1524	}
1525
1526	mac->mac_phy.supports_2ghz = have_bg;
1527	mac->mac_phy.supports_5ghz = have_a;
1528
1529	return (ic->ic_nchans == 0 ? ENXIO : 0);
1530}
1531
1532uint32_t
1533bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1534{
1535	uint32_t ret;
1536
1537	BWN_ASSERT_LOCKED(mac->mac_sc);
1538
1539	if (way == BWN_SHARED) {
1540		KASSERT((offset & 0x0001) == 0,
1541		    ("%s:%d warn", __func__, __LINE__));
1542		if (offset & 0x0003) {
1543			bwn_shm_ctlword(mac, way, offset >> 2);
1544			ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1545			ret <<= 16;
1546			bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1547			ret |= BWN_READ_2(mac, BWN_SHM_DATA);
1548			goto out;
1549		}
1550		offset >>= 2;
1551	}
1552	bwn_shm_ctlword(mac, way, offset);
1553	ret = BWN_READ_4(mac, BWN_SHM_DATA);
1554out:
1555	return (ret);
1556}
1557
1558uint16_t
1559bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1560{
1561	uint16_t ret;
1562
1563	BWN_ASSERT_LOCKED(mac->mac_sc);
1564
1565	if (way == BWN_SHARED) {
1566		KASSERT((offset & 0x0001) == 0,
1567		    ("%s:%d warn", __func__, __LINE__));
1568		if (offset & 0x0003) {
1569			bwn_shm_ctlword(mac, way, offset >> 2);
1570			ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1571			goto out;
1572		}
1573		offset >>= 2;
1574	}
1575	bwn_shm_ctlword(mac, way, offset);
1576	ret = BWN_READ_2(mac, BWN_SHM_DATA);
1577out:
1578
1579	return (ret);
1580}
1581
1582static void
1583bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way,
1584    uint16_t offset)
1585{
1586	uint32_t control;
1587
1588	control = way;
1589	control <<= 16;
1590	control |= offset;
1591	BWN_WRITE_4(mac, BWN_SHM_CONTROL, control);
1592}
1593
1594void
1595bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1596    uint32_t value)
1597{
1598	BWN_ASSERT_LOCKED(mac->mac_sc);
1599
1600	if (way == BWN_SHARED) {
1601		KASSERT((offset & 0x0001) == 0,
1602		    ("%s:%d warn", __func__, __LINE__));
1603		if (offset & 0x0003) {
1604			bwn_shm_ctlword(mac, way, offset >> 2);
1605			BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED,
1606				    (value >> 16) & 0xffff);
1607			bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1608			BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff);
1609			return;
1610		}
1611		offset >>= 2;
1612	}
1613	bwn_shm_ctlword(mac, way, offset);
1614	BWN_WRITE_4(mac, BWN_SHM_DATA, value);
1615}
1616
1617void
1618bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1619    uint16_t value)
1620{
1621	BWN_ASSERT_LOCKED(mac->mac_sc);
1622
1623	if (way == BWN_SHARED) {
1624		KASSERT((offset & 0x0001) == 0,
1625		    ("%s:%d warn", __func__, __LINE__));
1626		if (offset & 0x0003) {
1627			bwn_shm_ctlword(mac, way, offset >> 2);
1628			BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value);
1629			return;
1630		}
1631		offset >>= 2;
1632	}
1633	bwn_shm_ctlword(mac, way, offset);
1634	BWN_WRITE_2(mac, BWN_SHM_DATA, value);
1635}
1636
1637static void
1638bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans,
1639    const struct bwn_channelinfo *ci, const uint8_t bands[])
1640{
1641	int i, error;
1642
1643	for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) {
1644		const struct bwn_channel *hc = &ci->channels[i];
1645
1646		error = ieee80211_add_channel(chans, maxchans, nchans,
1647		    hc->ieee, hc->freq, hc->maxTxPow, 0, bands);
1648	}
1649}
1650
1651static int
1652bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1653	const struct ieee80211_bpf_params *params)
1654{
1655	struct ieee80211com *ic = ni->ni_ic;
1656	struct bwn_softc *sc = ic->ic_softc;
1657	struct bwn_mac *mac = sc->sc_curmac;
1658	int error;
1659
1660	if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 ||
1661	    mac->mac_status < BWN_MAC_STATUS_STARTED) {
1662		m_freem(m);
1663		return (ENETDOWN);
1664	}
1665
1666	BWN_LOCK(sc);
1667	if (bwn_tx_isfull(sc, m)) {
1668		m_freem(m);
1669		BWN_UNLOCK(sc);
1670		return (ENOBUFS);
1671	}
1672
1673	error = bwn_tx_start(sc, ni, m);
1674	if (error == 0)
1675		sc->sc_watchdog_timer = 5;
1676	BWN_UNLOCK(sc);
1677	return (error);
1678}
1679
1680/*
1681 * Callback from the 802.11 layer to update the slot time
1682 * based on the current setting.  We use it to notify the
1683 * firmware of ERP changes and the f/w takes care of things
1684 * like slot time and preamble.
1685 */
1686static void
1687bwn_updateslot(struct ieee80211com *ic)
1688{
1689	struct bwn_softc *sc = ic->ic_softc;
1690	struct bwn_mac *mac;
1691
1692	BWN_LOCK(sc);
1693	if (sc->sc_flags & BWN_FLAG_RUNNING) {
1694		mac = (struct bwn_mac *)sc->sc_curmac;
1695		bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic));
1696	}
1697	BWN_UNLOCK(sc);
1698}
1699
1700/*
1701 * Callback from the 802.11 layer after a promiscuous mode change.
1702 * Note this interface does not check the operating mode as this
1703 * is an internal callback and we are expected to honor the current
1704 * state (e.g. this is used for setting the interface in promiscuous
1705 * mode when operating in hostap mode to do ACS).
1706 */
1707static void
1708bwn_update_promisc(struct ieee80211com *ic)
1709{
1710	struct bwn_softc *sc = ic->ic_softc;
1711	struct bwn_mac *mac = sc->sc_curmac;
1712
1713	BWN_LOCK(sc);
1714	mac = sc->sc_curmac;
1715	if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1716		if (ic->ic_promisc > 0)
1717			sc->sc_filters |= BWN_MACCTL_PROMISC;
1718		else
1719			sc->sc_filters &= ~BWN_MACCTL_PROMISC;
1720		bwn_set_opmode(mac);
1721	}
1722	BWN_UNLOCK(sc);
1723}
1724
1725/*
1726 * Callback from the 802.11 layer to update WME parameters.
1727 */
1728static int
1729bwn_wme_update(struct ieee80211com *ic)
1730{
1731	struct bwn_softc *sc = ic->ic_softc;
1732	struct bwn_mac *mac = sc->sc_curmac;
1733	struct wmeParams *wmep;
1734	int i;
1735
1736	BWN_LOCK(sc);
1737	mac = sc->sc_curmac;
1738	if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1739		bwn_mac_suspend(mac);
1740		for (i = 0; i < N(sc->sc_wmeParams); i++) {
1741			wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[i];
1742			bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]);
1743		}
1744		bwn_mac_enable(mac);
1745	}
1746	BWN_UNLOCK(sc);
1747	return (0);
1748}
1749
1750static void
1751bwn_scan_start(struct ieee80211com *ic)
1752{
1753	struct bwn_softc *sc = ic->ic_softc;
1754	struct bwn_mac *mac;
1755
1756	BWN_LOCK(sc);
1757	mac = sc->sc_curmac;
1758	if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1759		sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC;
1760		bwn_set_opmode(mac);
1761		/* disable CFP update during scan */
1762		bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE);
1763	}
1764	BWN_UNLOCK(sc);
1765}
1766
1767static void
1768bwn_scan_end(struct ieee80211com *ic)
1769{
1770	struct bwn_softc *sc = ic->ic_softc;
1771	struct bwn_mac *mac;
1772
1773	BWN_LOCK(sc);
1774	mac = sc->sc_curmac;
1775	if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1776		sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC;
1777		bwn_set_opmode(mac);
1778		bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE);
1779	}
1780	BWN_UNLOCK(sc);
1781}
1782
1783static void
1784bwn_set_channel(struct ieee80211com *ic)
1785{
1786	struct bwn_softc *sc = ic->ic_softc;
1787	struct bwn_mac *mac = sc->sc_curmac;
1788	struct bwn_phy *phy = &mac->mac_phy;
1789	int chan, error;
1790
1791	BWN_LOCK(sc);
1792
1793	error = bwn_switch_band(sc, ic->ic_curchan);
1794	if (error)
1795		goto fail;
1796	bwn_mac_suspend(mac);
1797	bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
1798	chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
1799	if (chan != phy->chan)
1800		bwn_switch_channel(mac, chan);
1801
1802	/* TX power level */
1803	if (ic->ic_curchan->ic_maxpower != 0 &&
1804	    ic->ic_curchan->ic_maxpower != phy->txpower) {
1805		phy->txpower = ic->ic_curchan->ic_maxpower / 2;
1806		bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME |
1807		    BWN_TXPWR_IGNORE_TSSI);
1808	}
1809
1810	bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
1811	if (phy->set_antenna)
1812		phy->set_antenna(mac, BWN_ANT_DEFAULT);
1813
1814	if (sc->sc_rf_enabled != phy->rf_on) {
1815		if (sc->sc_rf_enabled) {
1816			bwn_rf_turnon(mac);
1817			if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON))
1818				device_printf(sc->sc_dev,
1819				    "please turn on the RF switch\n");
1820		} else
1821			bwn_rf_turnoff(mac);
1822	}
1823
1824	bwn_mac_enable(mac);
1825
1826fail:
1827	/*
1828	 * Setup radio tap channel freq and flags
1829	 */
1830	sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
1831		htole16(ic->ic_curchan->ic_freq);
1832	sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
1833		htole16(ic->ic_curchan->ic_flags & 0xffff);
1834
1835	BWN_UNLOCK(sc);
1836}
1837
1838static struct ieee80211vap *
1839bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1840    enum ieee80211_opmode opmode, int flags,
1841    const uint8_t bssid[IEEE80211_ADDR_LEN],
1842    const uint8_t mac[IEEE80211_ADDR_LEN])
1843{
1844	struct ieee80211vap *vap;
1845	struct bwn_vap *bvp;
1846
1847	switch (opmode) {
1848	case IEEE80211_M_HOSTAP:
1849	case IEEE80211_M_MBSS:
1850	case IEEE80211_M_STA:
1851	case IEEE80211_M_WDS:
1852	case IEEE80211_M_MONITOR:
1853	case IEEE80211_M_IBSS:
1854	case IEEE80211_M_AHDEMO:
1855		break;
1856	default:
1857		return (NULL);
1858	}
1859
1860	bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1861	vap = &bvp->bv_vap;
1862	ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
1863	/* override with driver methods */
1864	bvp->bv_newstate = vap->iv_newstate;
1865	vap->iv_newstate = bwn_newstate;
1866
1867	/* override max aid so sta's cannot assoc when we're out of sta id's */
1868	vap->iv_max_aid = BWN_STAID_MAX;
1869
1870	ieee80211_ratectl_init(vap);
1871
1872	/* complete setup */
1873	ieee80211_vap_attach(vap, ieee80211_media_change,
1874	    ieee80211_media_status, mac);
1875	return (vap);
1876}
1877
1878static void
1879bwn_vap_delete(struct ieee80211vap *vap)
1880{
1881	struct bwn_vap *bvp = BWN_VAP(vap);
1882
1883	ieee80211_ratectl_deinit(vap);
1884	ieee80211_vap_detach(vap);
1885	free(bvp, M_80211_VAP);
1886}
1887
1888static int
1889bwn_init(struct bwn_softc *sc)
1890{
1891	struct bwn_mac *mac;
1892	int error;
1893
1894	BWN_ASSERT_LOCKED(sc);
1895
1896	DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
1897
1898	bzero(sc->sc_bssid, IEEE80211_ADDR_LEN);
1899	sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP;
1900	sc->sc_filters = 0;
1901	bwn_wme_clear(sc);
1902	sc->sc_beacons[0] = sc->sc_beacons[1] = 0;
1903	sc->sc_rf_enabled = 1;
1904
1905	mac = sc->sc_curmac;
1906	if (mac->mac_status == BWN_MAC_STATUS_UNINIT) {
1907		error = bwn_core_init(mac);
1908		if (error != 0)
1909			return (error);
1910	}
1911	if (mac->mac_status == BWN_MAC_STATUS_INITED)
1912		bwn_core_start(mac);
1913
1914	bwn_set_opmode(mac);
1915	bwn_set_pretbtt(mac);
1916	bwn_spu_setdelay(mac, 0);
1917	bwn_set_macaddr(mac);
1918
1919	sc->sc_flags |= BWN_FLAG_RUNNING;
1920	callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc);
1921	callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc);
1922
1923	return (0);
1924}
1925
1926static void
1927bwn_stop(struct bwn_softc *sc)
1928{
1929	struct bwn_mac *mac = sc->sc_curmac;
1930
1931	BWN_ASSERT_LOCKED(sc);
1932
1933	DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
1934
1935	if (mac->mac_status >= BWN_MAC_STATUS_INITED) {
1936		/* XXX FIXME opmode not based on VAP */
1937		bwn_set_opmode(mac);
1938		bwn_set_macaddr(mac);
1939	}
1940
1941	if (mac->mac_status >= BWN_MAC_STATUS_STARTED)
1942		bwn_core_stop(mac);
1943
1944	callout_stop(&sc->sc_led_blink_ch);
1945	sc->sc_led_blinking = 0;
1946
1947	bwn_core_exit(mac);
1948	sc->sc_rf_enabled = 0;
1949
1950	sc->sc_flags &= ~BWN_FLAG_RUNNING;
1951}
1952
1953static void
1954bwn_wme_clear(struct bwn_softc *sc)
1955{
1956#define	MS(_v, _f)	(((_v) & _f) >> _f##_S)
1957	struct wmeParams *p;
1958	unsigned int i;
1959
1960	KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
1961	    ("%s:%d: fail", __func__, __LINE__));
1962
1963	for (i = 0; i < N(sc->sc_wmeParams); i++) {
1964		p = &(sc->sc_wmeParams[i]);
1965
1966		switch (bwn_wme_shm_offsets[i]) {
1967		case BWN_WME_VOICE:
1968			p->wmep_txopLimit = 0;
1969			p->wmep_aifsn = 2;
1970			/* XXX FIXME: log2(cwmin) */
1971			p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1972			p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
1973			break;
1974		case BWN_WME_VIDEO:
1975			p->wmep_txopLimit = 0;
1976			p->wmep_aifsn = 2;
1977			/* XXX FIXME: log2(cwmin) */
1978			p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1979			p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
1980			break;
1981		case BWN_WME_BESTEFFORT:
1982			p->wmep_txopLimit = 0;
1983			p->wmep_aifsn = 3;
1984			/* XXX FIXME: log2(cwmin) */
1985			p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1986			p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
1987			break;
1988		case BWN_WME_BACKGROUND:
1989			p->wmep_txopLimit = 0;
1990			p->wmep_aifsn = 7;
1991			/* XXX FIXME: log2(cwmin) */
1992			p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1993			p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
1994			break;
1995		default:
1996			KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
1997		}
1998	}
1999}
2000
2001static int
2002bwn_core_init(struct bwn_mac *mac)
2003{
2004	struct bwn_softc *sc = mac->mac_sc;
2005	uint64_t hf;
2006	int error;
2007
2008	KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2009	    ("%s:%d: fail", __func__, __LINE__));
2010
2011	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2012
2013	siba_powerup(sc->sc_dev, 0);
2014	if (!siba_dev_isup(sc->sc_dev))
2015		bwn_reset_core(mac, mac->mac_phy.gmode);
2016
2017	mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
2018	mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
2019	mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0;
2020	BWN_GETTIME(mac->mac_phy.nexttime);
2021	mac->mac_phy.txerrors = BWN_TXERROR_MAX;
2022	bzero(&mac->mac_stats, sizeof(mac->mac_stats));
2023	mac->mac_stats.link_noise = -95;
2024	mac->mac_reason_intr = 0;
2025	bzero(mac->mac_reason, sizeof(mac->mac_reason));
2026	mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE;
2027#ifdef BWN_DEBUG
2028	if (sc->sc_debug & BWN_DEBUG_XMIT)
2029		mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR;
2030#endif
2031	mac->mac_suspended = 1;
2032	mac->mac_task_state = 0;
2033	memset(&mac->mac_noise, 0, sizeof(mac->mac_noise));
2034
2035	mac->mac_phy.init_pre(mac);
2036
2037	siba_pcicore_intr(sc->sc_dev);
2038
2039	siba_fix_imcfglobug(sc->sc_dev);
2040	bwn_bt_disable(mac);
2041	if (mac->mac_phy.prepare_hw) {
2042		error = mac->mac_phy.prepare_hw(mac);
2043		if (error)
2044			goto fail0;
2045	}
2046	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__);
2047	error = bwn_chip_init(mac);
2048	if (error)
2049		goto fail0;
2050	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
2051	    siba_get_revid(sc->sc_dev));
2052	hf = bwn_hf_read(mac);
2053	if (mac->mac_phy.type == BWN_PHYTYPE_G) {
2054		hf |= BWN_HF_GPHY_SYM_WORKAROUND;
2055		if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
2056			hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
2057		if (mac->mac_phy.rev == 1)
2058			hf |= BWN_HF_GPHY_DC_CANCELFILTER;
2059	}
2060	if (mac->mac_phy.rf_ver == 0x2050) {
2061		if (mac->mac_phy.rf_rev < 6)
2062			hf |= BWN_HF_FORCE_VCO_RECALC;
2063		if (mac->mac_phy.rf_rev == 6)
2064			hf |= BWN_HF_4318_TSSI;
2065	}
2066	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)
2067		hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
2068	if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) &&
2069	    (siba_get_pcicore_revid(sc->sc_dev) <= 10))
2070		hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
2071	hf &= ~BWN_HF_SKIP_CFP_UPDATE;
2072	bwn_hf_write(mac, hf);
2073
2074	/* Tell the firmware about the MAC capabilities */
2075	if (siba_get_revid(sc->sc_dev) >= 13) {
2076		uint32_t cap;
2077		cap = BWN_READ_4(mac, BWN_MAC_HW_CAP);
2078		DPRINTF(sc, BWN_DEBUG_RESET,
2079		    "%s: hw capabilities: 0x%08x\n",
2080		    __func__, cap);
2081		bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L,
2082		    cap & 0xffff);
2083		bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H,
2084		    (cap >> 16) & 0xffff);
2085	}
2086
2087	bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
2088	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3);
2089	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2);
2090	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1);
2091
2092	bwn_rate_init(mac);
2093	bwn_set_phytxctl(mac);
2094
2095	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN,
2096	    (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
2097	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
2098
2099	if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
2100		bwn_pio_init(mac);
2101	else
2102		bwn_dma_init(mac);
2103	bwn_wme_init(mac);
2104	bwn_spu_setdelay(mac, 1);
2105	bwn_bt_enable(mac);
2106
2107	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__);
2108	siba_powerup(sc->sc_dev,
2109	    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW));
2110	bwn_set_macaddr(mac);
2111	bwn_crypt_init(mac);
2112
2113	/* XXX LED initializatin */
2114
2115	mac->mac_status = BWN_MAC_STATUS_INITED;
2116
2117	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__);
2118	return (error);
2119
2120fail0:
2121	siba_powerdown(sc->sc_dev);
2122	KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2123	    ("%s:%d: fail", __func__, __LINE__));
2124	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__);
2125	return (error);
2126}
2127
2128static void
2129bwn_core_start(struct bwn_mac *mac)
2130{
2131	struct bwn_softc *sc = mac->mac_sc;
2132	uint32_t tmp;
2133
2134	KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
2135	    ("%s:%d: fail", __func__, __LINE__));
2136
2137	if (siba_get_revid(sc->sc_dev) < 5)
2138		return;
2139
2140	while (1) {
2141		tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
2142		if (!(tmp & 0x00000001))
2143			break;
2144		tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
2145	}
2146
2147	bwn_mac_enable(mac);
2148	BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
2149	callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
2150
2151	mac->mac_status = BWN_MAC_STATUS_STARTED;
2152}
2153
2154static void
2155bwn_core_exit(struct bwn_mac *mac)
2156{
2157	struct bwn_softc *sc = mac->mac_sc;
2158	uint32_t macctl;
2159
2160	BWN_ASSERT_LOCKED(mac->mac_sc);
2161
2162	KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED,
2163	    ("%s:%d: fail", __func__, __LINE__));
2164
2165	if (mac->mac_status != BWN_MAC_STATUS_INITED)
2166		return;
2167	mac->mac_status = BWN_MAC_STATUS_UNINIT;
2168
2169	macctl = BWN_READ_4(mac, BWN_MACCTL);
2170	macctl &= ~BWN_MACCTL_MCODE_RUN;
2171	macctl |= BWN_MACCTL_MCODE_JMP0;
2172	BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2173
2174	bwn_dma_stop(mac);
2175	bwn_pio_stop(mac);
2176	bwn_chip_exit(mac);
2177	mac->mac_phy.switch_analog(mac, 0);
2178	siba_dev_down(sc->sc_dev, 0);
2179	siba_powerdown(sc->sc_dev);
2180}
2181
2182static void
2183bwn_bt_disable(struct bwn_mac *mac)
2184{
2185	struct bwn_softc *sc = mac->mac_sc;
2186
2187	(void)sc;
2188	/* XXX do nothing yet */
2189}
2190
2191static int
2192bwn_chip_init(struct bwn_mac *mac)
2193{
2194	struct bwn_softc *sc = mac->mac_sc;
2195	struct bwn_phy *phy = &mac->mac_phy;
2196	uint32_t macctl;
2197	int error;
2198
2199	macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
2200	if (phy->gmode)
2201		macctl |= BWN_MACCTL_GMODE;
2202	BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2203
2204	error = bwn_fw_fillinfo(mac);
2205	if (error)
2206		return (error);
2207	error = bwn_fw_loaducode(mac);
2208	if (error)
2209		return (error);
2210
2211	error = bwn_gpio_init(mac);
2212	if (error)
2213		return (error);
2214
2215	error = bwn_fw_loadinitvals(mac);
2216	if (error) {
2217		siba_gpio_set(sc->sc_dev, 0);
2218		return (error);
2219	}
2220	phy->switch_analog(mac, 1);
2221	error = bwn_phy_init(mac);
2222	if (error) {
2223		siba_gpio_set(sc->sc_dev, 0);
2224		return (error);
2225	}
2226	if (phy->set_im)
2227		phy->set_im(mac, BWN_IMMODE_NONE);
2228	if (phy->set_antenna)
2229		phy->set_antenna(mac, BWN_ANT_DEFAULT);
2230	bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
2231
2232	if (phy->type == BWN_PHYTYPE_B)
2233		BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
2234	BWN_WRITE_4(mac, 0x0100, 0x01000000);
2235	if (siba_get_revid(sc->sc_dev) < 5)
2236		BWN_WRITE_4(mac, 0x010c, 0x01000000);
2237
2238	BWN_WRITE_4(mac, BWN_MACCTL,
2239	    BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA);
2240	BWN_WRITE_4(mac, BWN_MACCTL,
2241	    BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA);
2242	bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
2243
2244	bwn_set_opmode(mac);
2245	if (siba_get_revid(sc->sc_dev) < 3) {
2246		BWN_WRITE_2(mac, 0x060e, 0x0000);
2247		BWN_WRITE_2(mac, 0x0610, 0x8000);
2248		BWN_WRITE_2(mac, 0x0604, 0x0000);
2249		BWN_WRITE_2(mac, 0x0606, 0x0200);
2250	} else {
2251		BWN_WRITE_4(mac, 0x0188, 0x80000000);
2252		BWN_WRITE_4(mac, 0x018c, 0x02000000);
2253	}
2254	BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000);
2255	BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00);
2256	BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00);
2257	BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00);
2258	BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00);
2259	BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00);
2260	BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00);
2261
2262	bwn_mac_phy_clock_set(mac, true);
2263
2264	/* SIBA powerup */
2265	/* XXX TODO: BCMA powerup */
2266	BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev));
2267	return (error);
2268}
2269
2270/* read hostflags */
2271uint64_t
2272bwn_hf_read(struct bwn_mac *mac)
2273{
2274	uint64_t ret;
2275
2276	ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI);
2277	ret <<= 16;
2278	ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI);
2279	ret <<= 16;
2280	ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO);
2281	return (ret);
2282}
2283
2284void
2285bwn_hf_write(struct bwn_mac *mac, uint64_t value)
2286{
2287
2288	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO,
2289	    (value & 0x00000000ffffull));
2290	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI,
2291	    (value & 0x0000ffff0000ull) >> 16);
2292	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI,
2293	    (value & 0xffff00000000ULL) >> 32);
2294}
2295
2296static void
2297bwn_set_txretry(struct bwn_mac *mac, int s, int l)
2298{
2299
2300	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf));
2301	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf));
2302}
2303
2304static void
2305bwn_rate_init(struct bwn_mac *mac)
2306{
2307
2308	switch (mac->mac_phy.type) {
2309	case BWN_PHYTYPE_A:
2310	case BWN_PHYTYPE_G:
2311	case BWN_PHYTYPE_LP:
2312	case BWN_PHYTYPE_N:
2313		bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1);
2314		bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1);
2315		bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1);
2316		bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1);
2317		bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1);
2318		bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1);
2319		bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1);
2320		if (mac->mac_phy.type == BWN_PHYTYPE_A)
2321			break;
2322		/* FALLTHROUGH */
2323	case BWN_PHYTYPE_B:
2324		bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0);
2325		bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0);
2326		bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0);
2327		bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0);
2328		break;
2329	default:
2330		KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2331	}
2332}
2333
2334static void
2335bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm)
2336{
2337	uint16_t offset;
2338
2339	if (ofdm) {
2340		offset = 0x480;
2341		offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2;
2342	} else {
2343		offset = 0x4c0;
2344		offset += (bwn_plcp_getcck(rate) & 0x000f) * 2;
2345	}
2346	bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20,
2347	    bwn_shm_read_2(mac, BWN_SHARED, offset));
2348}
2349
2350static uint8_t
2351bwn_plcp_getcck(const uint8_t bitrate)
2352{
2353
2354	switch (bitrate) {
2355	case BWN_CCK_RATE_1MB:
2356		return (0x0a);
2357	case BWN_CCK_RATE_2MB:
2358		return (0x14);
2359	case BWN_CCK_RATE_5MB:
2360		return (0x37);
2361	case BWN_CCK_RATE_11MB:
2362		return (0x6e);
2363	}
2364	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2365	return (0);
2366}
2367
2368static uint8_t
2369bwn_plcp_getofdm(const uint8_t bitrate)
2370{
2371
2372	switch (bitrate) {
2373	case BWN_OFDM_RATE_6MB:
2374		return (0xb);
2375	case BWN_OFDM_RATE_9MB:
2376		return (0xf);
2377	case BWN_OFDM_RATE_12MB:
2378		return (0xa);
2379	case BWN_OFDM_RATE_18MB:
2380		return (0xe);
2381	case BWN_OFDM_RATE_24MB:
2382		return (0x9);
2383	case BWN_OFDM_RATE_36MB:
2384		return (0xd);
2385	case BWN_OFDM_RATE_48MB:
2386		return (0x8);
2387	case BWN_OFDM_RATE_54MB:
2388		return (0xc);
2389	}
2390	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2391	return (0);
2392}
2393
2394static void
2395bwn_set_phytxctl(struct bwn_mac *mac)
2396{
2397	uint16_t ctl;
2398
2399	ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO |
2400	    BWN_TX_PHY_TXPWR);
2401	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl);
2402	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl);
2403	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl);
2404}
2405
2406static void
2407bwn_pio_init(struct bwn_mac *mac)
2408{
2409	struct bwn_pio *pio = &mac->mac_method.pio;
2410
2411	BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL)
2412	    & ~BWN_MACCTL_BIGENDIAN);
2413	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0);
2414
2415	bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0);
2416	bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1);
2417	bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2);
2418	bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3);
2419	bwn_pio_set_txqueue(mac, &pio->mcast, 4);
2420	bwn_pio_setupqueue_rx(mac, &pio->rx, 0);
2421}
2422
2423static void
2424bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2425    int index)
2426{
2427	struct bwn_pio_txpkt *tp;
2428	struct bwn_softc *sc = mac->mac_sc;
2429	unsigned int i;
2430
2431	tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac);
2432	tq->tq_index = index;
2433
2434	tq->tq_free = BWN_PIO_MAX_TXPACKETS;
2435	if (siba_get_revid(sc->sc_dev) >= 8)
2436		tq->tq_size = 1920;
2437	else {
2438		tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
2439		tq->tq_size -= 80;
2440	}
2441
2442	TAILQ_INIT(&tq->tq_pktlist);
2443	for (i = 0; i < N(tq->tq_pkts); i++) {
2444		tp = &(tq->tq_pkts[i]);
2445		tp->tp_index = i;
2446		tp->tp_queue = tq;
2447		TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
2448	}
2449}
2450
2451static uint16_t
2452bwn_pio_idx2base(struct bwn_mac *mac, int index)
2453{
2454	struct bwn_softc *sc = mac->mac_sc;
2455	static const uint16_t bases[] = {
2456		BWN_PIO_BASE0,
2457		BWN_PIO_BASE1,
2458		BWN_PIO_BASE2,
2459		BWN_PIO_BASE3,
2460		BWN_PIO_BASE4,
2461		BWN_PIO_BASE5,
2462		BWN_PIO_BASE6,
2463		BWN_PIO_BASE7,
2464	};
2465	static const uint16_t bases_rev11[] = {
2466		BWN_PIO11_BASE0,
2467		BWN_PIO11_BASE1,
2468		BWN_PIO11_BASE2,
2469		BWN_PIO11_BASE3,
2470		BWN_PIO11_BASE4,
2471		BWN_PIO11_BASE5,
2472	};
2473
2474	if (siba_get_revid(sc->sc_dev) >= 11) {
2475		if (index >= N(bases_rev11))
2476			device_printf(sc->sc_dev, "%s: warning\n", __func__);
2477		return (bases_rev11[index]);
2478	}
2479	if (index >= N(bases))
2480		device_printf(sc->sc_dev, "%s: warning\n", __func__);
2481	return (bases[index]);
2482}
2483
2484static void
2485bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
2486    int index)
2487{
2488	struct bwn_softc *sc = mac->mac_sc;
2489
2490	prq->prq_mac = mac;
2491	prq->prq_rev = siba_get_revid(sc->sc_dev);
2492	prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
2493	bwn_dma_rxdirectfifo(mac, index, 1);
2494}
2495
2496static void
2497bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq)
2498{
2499	if (tq == NULL)
2500		return;
2501	bwn_pio_cancel_tx_packets(tq);
2502}
2503
2504static void
2505bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio)
2506{
2507
2508	bwn_destroy_pioqueue_tx(pio);
2509}
2510
2511static uint16_t
2512bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2513    uint16_t offset)
2514{
2515
2516	return (BWN_READ_2(mac, tq->tq_base + offset));
2517}
2518
2519static void
2520bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
2521{
2522	uint32_t ctl;
2523	int type;
2524	uint16_t base;
2525
2526	type = bwn_dma_mask2type(bwn_dma_mask(mac));
2527	base = bwn_dma_base(type, idx);
2528	if (type == BWN_DMA_64BIT) {
2529		ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL);
2530		ctl &= ~BWN_DMA64_RXDIRECTFIFO;
2531		if (enable)
2532			ctl |= BWN_DMA64_RXDIRECTFIFO;
2533		BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl);
2534	} else {
2535		ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL);
2536		ctl &= ~BWN_DMA32_RXDIRECTFIFO;
2537		if (enable)
2538			ctl |= BWN_DMA32_RXDIRECTFIFO;
2539		BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl);
2540	}
2541}
2542
2543static uint64_t
2544bwn_dma_mask(struct bwn_mac *mac)
2545{
2546	uint32_t tmp;
2547	uint16_t base;
2548
2549	tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
2550	if (tmp & SIBA_TGSHIGH_DMA64)
2551		return (BWN_DMA_BIT_MASK(64));
2552	base = bwn_dma_base(0, 0);
2553	BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
2554	tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
2555	if (tmp & BWN_DMA32_TXADDREXT_MASK)
2556		return (BWN_DMA_BIT_MASK(32));
2557
2558	return (BWN_DMA_BIT_MASK(30));
2559}
2560
2561static int
2562bwn_dma_mask2type(uint64_t dmamask)
2563{
2564
2565	if (dmamask == BWN_DMA_BIT_MASK(30))
2566		return (BWN_DMA_30BIT);
2567	if (dmamask == BWN_DMA_BIT_MASK(32))
2568		return (BWN_DMA_32BIT);
2569	if (dmamask == BWN_DMA_BIT_MASK(64))
2570		return (BWN_DMA_64BIT);
2571	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2572	return (BWN_DMA_30BIT);
2573}
2574
2575static void
2576bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq)
2577{
2578	struct bwn_pio_txpkt *tp;
2579	unsigned int i;
2580
2581	for (i = 0; i < N(tq->tq_pkts); i++) {
2582		tp = &(tq->tq_pkts[i]);
2583		if (tp->tp_m) {
2584			m_freem(tp->tp_m);
2585			tp->tp_m = NULL;
2586		}
2587	}
2588}
2589
2590static uint16_t
2591bwn_dma_base(int type, int controller_idx)
2592{
2593	static const uint16_t map64[] = {
2594		BWN_DMA64_BASE0,
2595		BWN_DMA64_BASE1,
2596		BWN_DMA64_BASE2,
2597		BWN_DMA64_BASE3,
2598		BWN_DMA64_BASE4,
2599		BWN_DMA64_BASE5,
2600	};
2601	static const uint16_t map32[] = {
2602		BWN_DMA32_BASE0,
2603		BWN_DMA32_BASE1,
2604		BWN_DMA32_BASE2,
2605		BWN_DMA32_BASE3,
2606		BWN_DMA32_BASE4,
2607		BWN_DMA32_BASE5,
2608	};
2609
2610	if (type == BWN_DMA_64BIT) {
2611		KASSERT(controller_idx >= 0 && controller_idx < N(map64),
2612		    ("%s:%d: fail", __func__, __LINE__));
2613		return (map64[controller_idx]);
2614	}
2615	KASSERT(controller_idx >= 0 && controller_idx < N(map32),
2616	    ("%s:%d: fail", __func__, __LINE__));
2617	return (map32[controller_idx]);
2618}
2619
2620static void
2621bwn_dma_init(struct bwn_mac *mac)
2622{
2623	struct bwn_dma *dma = &mac->mac_method.dma;
2624
2625	/* setup TX DMA channels. */
2626	bwn_dma_setup(dma->wme[WME_AC_BK]);
2627	bwn_dma_setup(dma->wme[WME_AC_BE]);
2628	bwn_dma_setup(dma->wme[WME_AC_VI]);
2629	bwn_dma_setup(dma->wme[WME_AC_VO]);
2630	bwn_dma_setup(dma->mcast);
2631	/* setup RX DMA channel. */
2632	bwn_dma_setup(dma->rx);
2633}
2634
2635static struct bwn_dma_ring *
2636bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
2637    int for_tx, int type)
2638{
2639	struct bwn_dma *dma = &mac->mac_method.dma;
2640	struct bwn_dma_ring *dr;
2641	struct bwn_dmadesc_generic *desc;
2642	struct bwn_dmadesc_meta *mt;
2643	struct bwn_softc *sc = mac->mac_sc;
2644	int error, i;
2645
2646	dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO);
2647	if (dr == NULL)
2648		goto out;
2649	dr->dr_numslots = BWN_RXRING_SLOTS;
2650	if (for_tx)
2651		dr->dr_numslots = BWN_TXRING_SLOTS;
2652
2653	dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta),
2654	    M_DEVBUF, M_NOWAIT | M_ZERO);
2655	if (dr->dr_meta == NULL)
2656		goto fail0;
2657
2658	dr->dr_type = type;
2659	dr->dr_mac = mac;
2660	dr->dr_base = bwn_dma_base(type, controller_index);
2661	dr->dr_index = controller_index;
2662	if (type == BWN_DMA_64BIT) {
2663		dr->getdesc = bwn_dma_64_getdesc;
2664		dr->setdesc = bwn_dma_64_setdesc;
2665		dr->start_transfer = bwn_dma_64_start_transfer;
2666		dr->suspend = bwn_dma_64_suspend;
2667		dr->resume = bwn_dma_64_resume;
2668		dr->get_curslot = bwn_dma_64_get_curslot;
2669		dr->set_curslot = bwn_dma_64_set_curslot;
2670	} else {
2671		dr->getdesc = bwn_dma_32_getdesc;
2672		dr->setdesc = bwn_dma_32_setdesc;
2673		dr->start_transfer = bwn_dma_32_start_transfer;
2674		dr->suspend = bwn_dma_32_suspend;
2675		dr->resume = bwn_dma_32_resume;
2676		dr->get_curslot = bwn_dma_32_get_curslot;
2677		dr->set_curslot = bwn_dma_32_set_curslot;
2678	}
2679	if (for_tx) {
2680		dr->dr_tx = 1;
2681		dr->dr_curslot = -1;
2682	} else {
2683		if (dr->dr_index == 0) {
2684			switch (mac->mac_fw.fw_hdr_format) {
2685			case BWN_FW_HDR_351:
2686			case BWN_FW_HDR_410:
2687				dr->dr_rx_bufsize =
2688				    BWN_DMA0_RX_BUFFERSIZE_FW351;
2689				dr->dr_frameoffset =
2690				    BWN_DMA0_RX_FRAMEOFFSET_FW351;
2691				break;
2692			case BWN_FW_HDR_598:
2693				dr->dr_rx_bufsize =
2694				    BWN_DMA0_RX_BUFFERSIZE_FW598;
2695				dr->dr_frameoffset =
2696				    BWN_DMA0_RX_FRAMEOFFSET_FW598;
2697				break;
2698			}
2699		} else
2700			KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2701	}
2702
2703	error = bwn_dma_allocringmemory(dr);
2704	if (error)
2705		goto fail2;
2706
2707	if (for_tx) {
2708		/*
2709		 * Assumption: BWN_TXRING_SLOTS can be divided by
2710		 * BWN_TX_SLOTS_PER_FRAME
2711		 */
2712		KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0,
2713		    ("%s:%d: fail", __func__, __LINE__));
2714
2715		dr->dr_txhdr_cache = contigmalloc(
2716		    (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2717		    BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO,
2718		    0, BUS_SPACE_MAXADDR, 8, 0);
2719		if (dr->dr_txhdr_cache == NULL) {
2720			device_printf(sc->sc_dev,
2721			    "can't allocate TX header DMA memory\n");
2722			goto fail1;
2723		}
2724
2725		/*
2726		 * Create TX ring DMA stuffs
2727		 */
2728		error = bus_dma_tag_create(dma->parent_dtag,
2729				    BWN_ALIGN, 0,
2730				    BUS_SPACE_MAXADDR,
2731				    BUS_SPACE_MAXADDR,
2732				    NULL, NULL,
2733				    BWN_HDRSIZE(mac),
2734				    1,
2735				    BUS_SPACE_MAXSIZE_32BIT,
2736				    0,
2737				    NULL, NULL,
2738				    &dr->dr_txring_dtag);
2739		if (error) {
2740			device_printf(sc->sc_dev,
2741			    "can't create TX ring DMA tag: TODO frees\n");
2742			goto fail2;
2743		}
2744
2745		for (i = 0; i < dr->dr_numslots; i += 2) {
2746			dr->getdesc(dr, i, &desc, &mt);
2747
2748			mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER;
2749			mt->mt_m = NULL;
2750			mt->mt_ni = NULL;
2751			mt->mt_islast = 0;
2752			error = bus_dmamap_create(dr->dr_txring_dtag, 0,
2753			    &mt->mt_dmap);
2754			if (error) {
2755				device_printf(sc->sc_dev,
2756				     "can't create RX buf DMA map\n");
2757				goto fail2;
2758			}
2759
2760			dr->getdesc(dr, i + 1, &desc, &mt);
2761
2762			mt->mt_txtype = BWN_DMADESC_METATYPE_BODY;
2763			mt->mt_m = NULL;
2764			mt->mt_ni = NULL;
2765			mt->mt_islast = 1;
2766			error = bus_dmamap_create(dma->txbuf_dtag, 0,
2767			    &mt->mt_dmap);
2768			if (error) {
2769				device_printf(sc->sc_dev,
2770				     "can't create RX buf DMA map\n");
2771				goto fail2;
2772			}
2773		}
2774	} else {
2775		error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2776		    &dr->dr_spare_dmap);
2777		if (error) {
2778			device_printf(sc->sc_dev,
2779			    "can't create RX buf DMA map\n");
2780			goto out;		/* XXX wrong! */
2781		}
2782
2783		for (i = 0; i < dr->dr_numslots; i++) {
2784			dr->getdesc(dr, i, &desc, &mt);
2785
2786			error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2787			    &mt->mt_dmap);
2788			if (error) {
2789				device_printf(sc->sc_dev,
2790				    "can't create RX buf DMA map\n");
2791				goto out;	/* XXX wrong! */
2792			}
2793			error = bwn_dma_newbuf(dr, desc, mt, 1);
2794			if (error) {
2795				device_printf(sc->sc_dev,
2796				    "failed to allocate RX buf\n");
2797				goto out;	/* XXX wrong! */
2798			}
2799		}
2800
2801		bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
2802		    BUS_DMASYNC_PREWRITE);
2803
2804		dr->dr_usedslot = dr->dr_numslots;
2805	}
2806
2807      out:
2808	return (dr);
2809
2810fail2:
2811	if (dr->dr_txhdr_cache != NULL) {
2812		contigfree(dr->dr_txhdr_cache,
2813		    (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2814		    BWN_MAXTXHDRSIZE, M_DEVBUF);
2815	}
2816fail1:
2817	free(dr->dr_meta, M_DEVBUF);
2818fail0:
2819	free(dr, M_DEVBUF);
2820	return (NULL);
2821}
2822
2823static void
2824bwn_dma_ringfree(struct bwn_dma_ring **dr)
2825{
2826
2827	if (dr == NULL)
2828		return;
2829
2830	bwn_dma_free_descbufs(*dr);
2831	bwn_dma_free_ringmemory(*dr);
2832
2833	if ((*dr)->dr_txhdr_cache != NULL) {
2834		contigfree((*dr)->dr_txhdr_cache,
2835		    ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2836		    BWN_MAXTXHDRSIZE, M_DEVBUF);
2837	}
2838	free((*dr)->dr_meta, M_DEVBUF);
2839	free(*dr, M_DEVBUF);
2840
2841	*dr = NULL;
2842}
2843
2844static void
2845bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot,
2846    struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
2847{
2848	struct bwn_dmadesc32 *desc;
2849
2850	*meta = &(dr->dr_meta[slot]);
2851	desc = dr->dr_ring_descbase;
2852	desc = &(desc[slot]);
2853
2854	*gdesc = (struct bwn_dmadesc_generic *)desc;
2855}
2856
2857static void
2858bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
2859    struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
2860    int start, int end, int irq)
2861{
2862	struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase;
2863	struct bwn_softc *sc = dr->dr_mac->mac_sc;
2864	uint32_t addr, addrext, ctl;
2865	int slot;
2866
2867	slot = (int)(&(desc->dma.dma32) - descbase);
2868	KASSERT(slot >= 0 && slot < dr->dr_numslots,
2869	    ("%s:%d: fail", __func__, __LINE__));
2870
2871	addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK);
2872	addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30;
2873	addr |= siba_dma_translation(sc->sc_dev);
2874	ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
2875	if (slot == dr->dr_numslots - 1)
2876		ctl |= BWN_DMA32_DCTL_DTABLEEND;
2877	if (start)
2878		ctl |= BWN_DMA32_DCTL_FRAMESTART;
2879	if (end)
2880		ctl |= BWN_DMA32_DCTL_FRAMEEND;
2881	if (irq)
2882		ctl |= BWN_DMA32_DCTL_IRQ;
2883	ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT)
2884	    & BWN_DMA32_DCTL_ADDREXT_MASK;
2885
2886	desc->dma.dma32.control = htole32(ctl);
2887	desc->dma.dma32.address = htole32(addr);
2888}
2889
2890static void
2891bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot)
2892{
2893
2894	BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX,
2895	    (uint32_t)(slot * sizeof(struct bwn_dmadesc32)));
2896}
2897
2898static void
2899bwn_dma_32_suspend(struct bwn_dma_ring *dr)
2900{
2901
2902	BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
2903	    BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND);
2904}
2905
2906static void
2907bwn_dma_32_resume(struct bwn_dma_ring *dr)
2908{
2909
2910	BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
2911	    BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND);
2912}
2913
2914static int
2915bwn_dma_32_get_curslot(struct bwn_dma_ring *dr)
2916{
2917	uint32_t val;
2918
2919	val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS);
2920	val &= BWN_DMA32_RXDPTR;
2921
2922	return (val / sizeof(struct bwn_dmadesc32));
2923}
2924
2925static void
2926bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot)
2927{
2928
2929	BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX,
2930	    (uint32_t) (slot * sizeof(struct bwn_dmadesc32)));
2931}
2932
2933static void
2934bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot,
2935    struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
2936{
2937	struct bwn_dmadesc64 *desc;
2938
2939	*meta = &(dr->dr_meta[slot]);
2940	desc = dr->dr_ring_descbase;
2941	desc = &(desc[slot]);
2942
2943	*gdesc = (struct bwn_dmadesc_generic *)desc;
2944}
2945
2946static void
2947bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
2948    struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
2949    int start, int end, int irq)
2950{
2951	struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase;
2952	struct bwn_softc *sc = dr->dr_mac->mac_sc;
2953	int slot;
2954	uint32_t ctl0 = 0, ctl1 = 0;
2955	uint32_t addrlo, addrhi;
2956	uint32_t addrext;
2957
2958	slot = (int)(&(desc->dma.dma64) - descbase);
2959	KASSERT(slot >= 0 && slot < dr->dr_numslots,
2960	    ("%s:%d: fail", __func__, __LINE__));
2961
2962	addrlo = (uint32_t) (dmaaddr & 0xffffffff);
2963	addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK);
2964	addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >>
2965	    30;
2966	addrhi |= (siba_dma_translation(sc->sc_dev) << 1);
2967	if (slot == dr->dr_numslots - 1)
2968		ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
2969	if (start)
2970		ctl0 |= BWN_DMA64_DCTL0_FRAMESTART;
2971	if (end)
2972		ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
2973	if (irq)
2974		ctl0 |= BWN_DMA64_DCTL0_IRQ;
2975	ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT;
2976	ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT)
2977	    & BWN_DMA64_DCTL1_ADDREXT_MASK;
2978
2979	desc->dma.dma64.control0 = htole32(ctl0);
2980	desc->dma.dma64.control1 = htole32(ctl1);
2981	desc->dma.dma64.address_low = htole32(addrlo);
2982	desc->dma.dma64.address_high = htole32(addrhi);
2983}
2984
2985static void
2986bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot)
2987{
2988
2989	BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX,
2990	    (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
2991}
2992
2993static void
2994bwn_dma_64_suspend(struct bwn_dma_ring *dr)
2995{
2996
2997	BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
2998	    BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND);
2999}
3000
3001static void
3002bwn_dma_64_resume(struct bwn_dma_ring *dr)
3003{
3004
3005	BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3006	    BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND);
3007}
3008
3009static int
3010bwn_dma_64_get_curslot(struct bwn_dma_ring *dr)
3011{
3012	uint32_t val;
3013
3014	val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS);
3015	val &= BWN_DMA64_RXSTATDPTR;
3016
3017	return (val / sizeof(struct bwn_dmadesc64));
3018}
3019
3020static void
3021bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot)
3022{
3023
3024	BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX,
3025	    (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
3026}
3027
3028static int
3029bwn_dma_allocringmemory(struct bwn_dma_ring *dr)
3030{
3031	struct bwn_mac *mac = dr->dr_mac;
3032	struct bwn_dma *dma = &mac->mac_method.dma;
3033	struct bwn_softc *sc = mac->mac_sc;
3034	int error;
3035
3036	error = bus_dma_tag_create(dma->parent_dtag,
3037			    BWN_ALIGN, 0,
3038			    BUS_SPACE_MAXADDR,
3039			    BUS_SPACE_MAXADDR,
3040			    NULL, NULL,
3041			    BWN_DMA_RINGMEMSIZE,
3042			    1,
3043			    BUS_SPACE_MAXSIZE_32BIT,
3044			    0,
3045			    NULL, NULL,
3046			    &dr->dr_ring_dtag);
3047	if (error) {
3048		device_printf(sc->sc_dev,
3049		    "can't create TX ring DMA tag: TODO frees\n");
3050		return (-1);
3051	}
3052
3053	error = bus_dmamem_alloc(dr->dr_ring_dtag,
3054	    &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3055	    &dr->dr_ring_dmap);
3056	if (error) {
3057		device_printf(sc->sc_dev,
3058		    "can't allocate DMA mem: TODO frees\n");
3059		return (-1);
3060	}
3061	error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap,
3062	    dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE,
3063	    bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT);
3064	if (error) {
3065		device_printf(sc->sc_dev,
3066		    "can't load DMA mem: TODO free\n");
3067		return (-1);
3068	}
3069
3070	return (0);
3071}
3072
3073static void
3074bwn_dma_setup(struct bwn_dma_ring *dr)
3075{
3076	struct bwn_softc *sc = dr->dr_mac->mac_sc;
3077	uint64_t ring64;
3078	uint32_t addrext, ring32, value;
3079	uint32_t trans = siba_dma_translation(sc->sc_dev);
3080
3081	if (dr->dr_tx) {
3082		dr->dr_curslot = -1;
3083
3084		if (dr->dr_type == BWN_DMA_64BIT) {
3085			ring64 = (uint64_t)(dr->dr_ring_dmabase);
3086			addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK)
3087			    >> 30;
3088			value = BWN_DMA64_TXENABLE;
3089			value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT)
3090			    & BWN_DMA64_TXADDREXT_MASK;
3091			BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value);
3092			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO,
3093			    (ring64 & 0xffffffff));
3094			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI,
3095			    ((ring64 >> 32) &
3096			    ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1));
3097		} else {
3098			ring32 = (uint32_t)(dr->dr_ring_dmabase);
3099			addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
3100			value = BWN_DMA32_TXENABLE;
3101			value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT)
3102			    & BWN_DMA32_TXADDREXT_MASK;
3103			BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value);
3104			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING,
3105			    (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
3106		}
3107		return;
3108	}
3109
3110	/*
3111	 * set for RX
3112	 */
3113	dr->dr_usedslot = dr->dr_numslots;
3114
3115	if (dr->dr_type == BWN_DMA_64BIT) {
3116		ring64 = (uint64_t)(dr->dr_ring_dmabase);
3117		addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30;
3118		value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT);
3119		value |= BWN_DMA64_RXENABLE;
3120		value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT)
3121		    & BWN_DMA64_RXADDREXT_MASK;
3122		BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value);
3123		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff));
3124		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI,
3125		    ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK)
3126		    | (trans << 1));
3127		BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots *
3128		    sizeof(struct bwn_dmadesc64));
3129	} else {
3130		ring32 = (uint32_t)(dr->dr_ring_dmabase);
3131		addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
3132		value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT);
3133		value |= BWN_DMA32_RXENABLE;
3134		value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT)
3135		    & BWN_DMA32_RXADDREXT_MASK;
3136		BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value);
3137		BWN_DMA_WRITE(dr, BWN_DMA32_RXRING,
3138		    (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
3139		BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots *
3140		    sizeof(struct bwn_dmadesc32));
3141	}
3142}
3143
3144static void
3145bwn_dma_free_ringmemory(struct bwn_dma_ring *dr)
3146{
3147
3148	bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap);
3149	bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase,
3150	    dr->dr_ring_dmap);
3151}
3152
3153static void
3154bwn_dma_cleanup(struct bwn_dma_ring *dr)
3155{
3156
3157	if (dr->dr_tx) {
3158		bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3159		if (dr->dr_type == BWN_DMA_64BIT) {
3160			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0);
3161			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0);
3162		} else
3163			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0);
3164	} else {
3165		bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3166		if (dr->dr_type == BWN_DMA_64BIT) {
3167			BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0);
3168			BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0);
3169		} else
3170			BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0);
3171	}
3172}
3173
3174static void
3175bwn_dma_free_descbufs(struct bwn_dma_ring *dr)
3176{
3177	struct bwn_dmadesc_generic *desc;
3178	struct bwn_dmadesc_meta *meta;
3179	struct bwn_mac *mac = dr->dr_mac;
3180	struct bwn_dma *dma = &mac->mac_method.dma;
3181	struct bwn_softc *sc = mac->mac_sc;
3182	int i;
3183
3184	if (!dr->dr_usedslot)
3185		return;
3186	for (i = 0; i < dr->dr_numslots; i++) {
3187		dr->getdesc(dr, i, &desc, &meta);
3188
3189		if (meta->mt_m == NULL) {
3190			if (!dr->dr_tx)
3191				device_printf(sc->sc_dev, "%s: not TX?\n",
3192				    __func__);
3193			continue;
3194		}
3195		if (dr->dr_tx) {
3196			if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
3197				bus_dmamap_unload(dr->dr_txring_dtag,
3198				    meta->mt_dmap);
3199			else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
3200				bus_dmamap_unload(dma->txbuf_dtag,
3201				    meta->mt_dmap);
3202		} else
3203			bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
3204		bwn_dma_free_descbuf(dr, meta);
3205	}
3206}
3207
3208static int
3209bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
3210    int type)
3211{
3212	struct bwn_softc *sc = mac->mac_sc;
3213	uint32_t value;
3214	int i;
3215	uint16_t offset;
3216
3217	for (i = 0; i < 10; i++) {
3218		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
3219		    BWN_DMA32_TXSTATUS;
3220		value = BWN_READ_4(mac, base + offset);
3221		if (type == BWN_DMA_64BIT) {
3222			value &= BWN_DMA64_TXSTAT;
3223			if (value == BWN_DMA64_TXSTAT_DISABLED ||
3224			    value == BWN_DMA64_TXSTAT_IDLEWAIT ||
3225			    value == BWN_DMA64_TXSTAT_STOPPED)
3226				break;
3227		} else {
3228			value &= BWN_DMA32_TXSTATE;
3229			if (value == BWN_DMA32_TXSTAT_DISABLED ||
3230			    value == BWN_DMA32_TXSTAT_IDLEWAIT ||
3231			    value == BWN_DMA32_TXSTAT_STOPPED)
3232				break;
3233		}
3234		DELAY(1000);
3235	}
3236	offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL;
3237	BWN_WRITE_4(mac, base + offset, 0);
3238	for (i = 0; i < 10; i++) {
3239		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
3240						   BWN_DMA32_TXSTATUS;
3241		value = BWN_READ_4(mac, base + offset);
3242		if (type == BWN_DMA_64BIT) {
3243			value &= BWN_DMA64_TXSTAT;
3244			if (value == BWN_DMA64_TXSTAT_DISABLED) {
3245				i = -1;
3246				break;
3247			}
3248		} else {
3249			value &= BWN_DMA32_TXSTATE;
3250			if (value == BWN_DMA32_TXSTAT_DISABLED) {
3251				i = -1;
3252				break;
3253			}
3254		}
3255		DELAY(1000);
3256	}
3257	if (i != -1) {
3258		device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3259		return (ENODEV);
3260	}
3261	DELAY(1000);
3262
3263	return (0);
3264}
3265
3266static int
3267bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base,
3268    int type)
3269{
3270	struct bwn_softc *sc = mac->mac_sc;
3271	uint32_t value;
3272	int i;
3273	uint16_t offset;
3274
3275	offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL;
3276	BWN_WRITE_4(mac, base + offset, 0);
3277	for (i = 0; i < 10; i++) {
3278		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS :
3279		    BWN_DMA32_RXSTATUS;
3280		value = BWN_READ_4(mac, base + offset);
3281		if (type == BWN_DMA_64BIT) {
3282			value &= BWN_DMA64_RXSTAT;
3283			if (value == BWN_DMA64_RXSTAT_DISABLED) {
3284				i = -1;
3285				break;
3286			}
3287		} else {
3288			value &= BWN_DMA32_RXSTATE;
3289			if (value == BWN_DMA32_RXSTAT_DISABLED) {
3290				i = -1;
3291				break;
3292			}
3293		}
3294		DELAY(1000);
3295	}
3296	if (i != -1) {
3297		device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3298		return (ENODEV);
3299	}
3300
3301	return (0);
3302}
3303
3304static void
3305bwn_dma_free_descbuf(struct bwn_dma_ring *dr,
3306    struct bwn_dmadesc_meta *meta)
3307{
3308
3309	if (meta->mt_m != NULL) {
3310		m_freem(meta->mt_m);
3311		meta->mt_m = NULL;
3312	}
3313	if (meta->mt_ni != NULL) {
3314		ieee80211_free_node(meta->mt_ni);
3315		meta->mt_ni = NULL;
3316	}
3317}
3318
3319static void
3320bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3321{
3322	struct bwn_rxhdr4 *rxhdr;
3323	unsigned char *frame;
3324
3325	rxhdr = mtod(m, struct bwn_rxhdr4 *);
3326	rxhdr->frame_len = 0;
3327
3328	KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset +
3329	    sizeof(struct bwn_plcp6) + 2,
3330	    ("%s:%d: fail", __func__, __LINE__));
3331	frame = mtod(m, char *) + dr->dr_frameoffset;
3332	memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */);
3333}
3334
3335static uint8_t
3336bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3337{
3338	unsigned char *f = mtod(m, char *) + dr->dr_frameoffset;
3339
3340	return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7])
3341	    == 0xff);
3342}
3343
3344static void
3345bwn_wme_init(struct bwn_mac *mac)
3346{
3347
3348	bwn_wme_load(mac);
3349
3350	/* enable WME support. */
3351	bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF);
3352	BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) |
3353	    BWN_IFSCTL_USE_EDCF);
3354}
3355
3356static void
3357bwn_spu_setdelay(struct bwn_mac *mac, int idle)
3358{
3359	struct bwn_softc *sc = mac->mac_sc;
3360	struct ieee80211com *ic = &sc->sc_ic;
3361	uint16_t delay;	/* microsec */
3362
3363	delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050;
3364	if (ic->ic_opmode == IEEE80211_M_IBSS || idle)
3365		delay = 500;
3366	if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8))
3367		delay = max(delay, (uint16_t)2400);
3368
3369	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay);
3370}
3371
3372static void
3373bwn_bt_enable(struct bwn_mac *mac)
3374{
3375	struct bwn_softc *sc = mac->mac_sc;
3376	uint64_t hf;
3377
3378	if (bwn_bluetooth == 0)
3379		return;
3380	if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0)
3381		return;
3382	if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
3383		return;
3384
3385	hf = bwn_hf_read(mac);
3386	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD)
3387		hf |= BWN_HF_BT_COEXISTALT;
3388	else
3389		hf |= BWN_HF_BT_COEXIST;
3390	bwn_hf_write(mac, hf);
3391}
3392
3393static void
3394bwn_set_macaddr(struct bwn_mac *mac)
3395{
3396
3397	bwn_mac_write_bssid(mac);
3398	bwn_mac_setfilter(mac, BWN_MACFILTER_SELF,
3399	    mac->mac_sc->sc_ic.ic_macaddr);
3400}
3401
3402static void
3403bwn_clear_keys(struct bwn_mac *mac)
3404{
3405	int i;
3406
3407	for (i = 0; i < mac->mac_max_nr_keys; i++) {
3408		KASSERT(i >= 0 && i < mac->mac_max_nr_keys,
3409		    ("%s:%d: fail", __func__, __LINE__));
3410
3411		bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE,
3412		    NULL, BWN_SEC_KEYSIZE, NULL);
3413		if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) {
3414			bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE,
3415			    NULL, BWN_SEC_KEYSIZE, NULL);
3416		}
3417		mac->mac_key[i].keyconf = NULL;
3418	}
3419}
3420
3421static void
3422bwn_crypt_init(struct bwn_mac *mac)
3423{
3424	struct bwn_softc *sc = mac->mac_sc;
3425
3426	mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20;
3427	KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
3428	    ("%s:%d: fail", __func__, __LINE__));
3429	mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
3430	mac->mac_ktp *= 2;
3431	if (siba_get_revid(sc->sc_dev) >= 5)
3432		BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
3433	bwn_clear_keys(mac);
3434}
3435
3436static void
3437bwn_chip_exit(struct bwn_mac *mac)
3438{
3439	struct bwn_softc *sc = mac->mac_sc;
3440
3441	bwn_phy_exit(mac);
3442	siba_gpio_set(sc->sc_dev, 0);
3443}
3444
3445static int
3446bwn_fw_fillinfo(struct bwn_mac *mac)
3447{
3448	int error;
3449
3450	error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT);
3451	if (error == 0)
3452		return (0);
3453	error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE);
3454	if (error == 0)
3455		return (0);
3456	return (error);
3457}
3458
3459static int
3460bwn_gpio_init(struct bwn_mac *mac)
3461{
3462	struct bwn_softc *sc = mac->mac_sc;
3463	uint32_t mask = 0x1f, set = 0xf, value;
3464
3465	BWN_WRITE_4(mac, BWN_MACCTL,
3466	    BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
3467	BWN_WRITE_2(mac, BWN_GPIO_MASK,
3468	    BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f);
3469
3470	if (siba_get_chipid(sc->sc_dev) == 0x4301) {
3471		mask |= 0x0060;
3472		set |= 0x0060;
3473	}
3474	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) {
3475		BWN_WRITE_2(mac, BWN_GPIO_MASK,
3476		    BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200);
3477		mask |= 0x0200;
3478		set |= 0x0200;
3479	}
3480	if (siba_get_revid(sc->sc_dev) >= 2)
3481		mask |= 0x0010;
3482
3483	value = siba_gpio_get(sc->sc_dev);
3484	if (value == -1)
3485		return (0);
3486	siba_gpio_set(sc->sc_dev, (value & mask) | set);
3487
3488	return (0);
3489}
3490
3491static int
3492bwn_fw_loadinitvals(struct bwn_mac *mac)
3493{
3494#define	GETFWOFFSET(fwp, offset)				\
3495	((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset))
3496	const size_t hdr_len = sizeof(struct bwn_fwhdr);
3497	const struct bwn_fwhdr *hdr;
3498	struct bwn_fw *fw = &mac->mac_fw;
3499	int error;
3500
3501	hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data);
3502	error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len),
3503	    be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len);
3504	if (error)
3505		return (error);
3506	if (fw->initvals_band.fw) {
3507		hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data);
3508		error = bwn_fwinitvals_write(mac,
3509		    GETFWOFFSET(fw->initvals_band, hdr_len),
3510		    be32toh(hdr->size),
3511		    fw->initvals_band.fw->datasize - hdr_len);
3512	}
3513	return (error);
3514#undef GETFWOFFSET
3515}
3516
3517static int
3518bwn_phy_init(struct bwn_mac *mac)
3519{
3520	struct bwn_softc *sc = mac->mac_sc;
3521	int error;
3522
3523	mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac);
3524	mac->mac_phy.rf_onoff(mac, 1);
3525	error = mac->mac_phy.init(mac);
3526	if (error) {
3527		device_printf(sc->sc_dev, "PHY init failed\n");
3528		goto fail0;
3529	}
3530	error = bwn_switch_channel(mac,
3531	    mac->mac_phy.get_default_chan(mac));
3532	if (error) {
3533		device_printf(sc->sc_dev,
3534		    "failed to switch default channel\n");
3535		goto fail1;
3536	}
3537	return (0);
3538fail1:
3539	if (mac->mac_phy.exit)
3540		mac->mac_phy.exit(mac);
3541fail0:
3542	mac->mac_phy.rf_onoff(mac, 0);
3543
3544	return (error);
3545}
3546
3547static void
3548bwn_set_txantenna(struct bwn_mac *mac, int antenna)
3549{
3550	uint16_t ant;
3551	uint16_t tmp;
3552
3553	ant = bwn_ant2phy(antenna);
3554
3555	/* For ACK/CTS */
3556	tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL);
3557	tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3558	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp);
3559	/* For Probe Resposes */
3560	tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL);
3561	tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3562	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp);
3563}
3564
3565static void
3566bwn_set_opmode(struct bwn_mac *mac)
3567{
3568	struct bwn_softc *sc = mac->mac_sc;
3569	struct ieee80211com *ic = &sc->sc_ic;
3570	uint32_t ctl;
3571	uint16_t cfp_pretbtt;
3572
3573	ctl = BWN_READ_4(mac, BWN_MACCTL);
3574	ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL |
3575	    BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS |
3576	    BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC);
3577	ctl |= BWN_MACCTL_STA;
3578
3579	if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3580	    ic->ic_opmode == IEEE80211_M_MBSS)
3581		ctl |= BWN_MACCTL_HOSTAP;
3582	else if (ic->ic_opmode == IEEE80211_M_IBSS)
3583		ctl &= ~BWN_MACCTL_STA;
3584	ctl |= sc->sc_filters;
3585
3586	if (siba_get_revid(sc->sc_dev) <= 4)
3587		ctl |= BWN_MACCTL_PROMISC;
3588
3589	BWN_WRITE_4(mac, BWN_MACCTL, ctl);
3590
3591	cfp_pretbtt = 2;
3592	if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
3593		if (siba_get_chipid(sc->sc_dev) == 0x4306 &&
3594		    siba_get_chiprev(sc->sc_dev) == 3)
3595			cfp_pretbtt = 100;
3596		else
3597			cfp_pretbtt = 50;
3598	}
3599	BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
3600}
3601
3602static int
3603bwn_dma_gettype(struct bwn_mac *mac)
3604{
3605	uint32_t tmp;
3606	uint16_t base;
3607
3608	tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
3609	if (tmp & SIBA_TGSHIGH_DMA64)
3610		return (BWN_DMA_64BIT);
3611	base = bwn_dma_base(0, 0);
3612	BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
3613	tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
3614	if (tmp & BWN_DMA32_TXADDREXT_MASK)
3615		return (BWN_DMA_32BIT);
3616
3617	return (BWN_DMA_30BIT);
3618}
3619
3620static void
3621bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3622{
3623	if (!error) {
3624		KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
3625		*((bus_addr_t *)arg) = seg->ds_addr;
3626	}
3627}
3628
3629void
3630bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
3631{
3632	struct bwn_phy *phy = &mac->mac_phy;
3633	struct bwn_softc *sc = mac->mac_sc;
3634	unsigned int i, max_loop;
3635	uint16_t value;
3636	uint32_t buffer[5] = {
3637		0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000
3638	};
3639
3640	if (ofdm) {
3641		max_loop = 0x1e;
3642		buffer[0] = 0x000201cc;
3643	} else {
3644		max_loop = 0xfa;
3645		buffer[0] = 0x000b846e;
3646	}
3647
3648	BWN_ASSERT_LOCKED(mac->mac_sc);
3649
3650	for (i = 0; i < 5; i++)
3651		bwn_ram_write(mac, i * 4, buffer[i]);
3652
3653	BWN_WRITE_2(mac, 0x0568, 0x0000);
3654	BWN_WRITE_2(mac, 0x07c0,
3655	    (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
3656
3657	value = (ofdm ? 0x41 : 0x40);
3658	BWN_WRITE_2(mac, 0x050c, value);
3659
3660	if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP ||
3661	    phy->type == BWN_PHYTYPE_LCN)
3662		BWN_WRITE_2(mac, 0x0514, 0x1a02);
3663	BWN_WRITE_2(mac, 0x0508, 0x0000);
3664	BWN_WRITE_2(mac, 0x050a, 0x0000);
3665	BWN_WRITE_2(mac, 0x054c, 0x0000);
3666	BWN_WRITE_2(mac, 0x056a, 0x0014);
3667	BWN_WRITE_2(mac, 0x0568, 0x0826);
3668	BWN_WRITE_2(mac, 0x0500, 0x0000);
3669
3670	/* XXX TODO: n phy pa override? */
3671
3672	switch (phy->type) {
3673	case BWN_PHYTYPE_N:
3674	case BWN_PHYTYPE_LCN:
3675		BWN_WRITE_2(mac, 0x0502, 0x00d0);
3676		break;
3677	case BWN_PHYTYPE_LP:
3678		BWN_WRITE_2(mac, 0x0502, 0x0050);
3679		break;
3680	default:
3681		BWN_WRITE_2(mac, 0x0502, 0x0030);
3682		break;
3683	}
3684
3685	/* flush */
3686	BWN_READ_2(mac, 0x0502);
3687
3688	if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3689		BWN_RF_WRITE(mac, 0x0051, 0x0017);
3690	for (i = 0x00; i < max_loop; i++) {
3691		value = BWN_READ_2(mac, 0x050e);
3692		if (value & 0x0080)
3693			break;
3694		DELAY(10);
3695	}
3696	for (i = 0x00; i < 0x0a; i++) {
3697		value = BWN_READ_2(mac, 0x050e);
3698		if (value & 0x0400)
3699			break;
3700		DELAY(10);
3701	}
3702	for (i = 0x00; i < 0x19; i++) {
3703		value = BWN_READ_2(mac, 0x0690);
3704		if (!(value & 0x0100))
3705			break;
3706		DELAY(10);
3707	}
3708	if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3709		BWN_RF_WRITE(mac, 0x0051, 0x0037);
3710}
3711
3712void
3713bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val)
3714{
3715	uint32_t macctl;
3716
3717	KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__));
3718
3719	macctl = BWN_READ_4(mac, BWN_MACCTL);
3720	if (macctl & BWN_MACCTL_BIGENDIAN)
3721		printf("TODO: need swap\n");
3722
3723	BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset);
3724	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
3725	BWN_WRITE_4(mac, BWN_RAM_DATA, val);
3726}
3727
3728void
3729bwn_mac_suspend(struct bwn_mac *mac)
3730{
3731	struct bwn_softc *sc = mac->mac_sc;
3732	int i;
3733	uint32_t tmp;
3734
3735	KASSERT(mac->mac_suspended >= 0,
3736	    ("%s:%d: fail", __func__, __LINE__));
3737
3738	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3739	    __func__, mac->mac_suspended);
3740
3741	if (mac->mac_suspended == 0) {
3742		bwn_psctl(mac, BWN_PS_AWAKE);
3743		BWN_WRITE_4(mac, BWN_MACCTL,
3744			    BWN_READ_4(mac, BWN_MACCTL)
3745			    & ~BWN_MACCTL_ON);
3746		BWN_READ_4(mac, BWN_MACCTL);
3747		for (i = 35; i; i--) {
3748			tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3749			if (tmp & BWN_INTR_MAC_SUSPENDED)
3750				goto out;
3751			DELAY(10);
3752		}
3753		for (i = 40; i; i--) {
3754			tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3755			if (tmp & BWN_INTR_MAC_SUSPENDED)
3756				goto out;
3757			DELAY(1000);
3758		}
3759		device_printf(sc->sc_dev, "MAC suspend failed\n");
3760	}
3761out:
3762	mac->mac_suspended++;
3763}
3764
3765void
3766bwn_mac_enable(struct bwn_mac *mac)
3767{
3768	struct bwn_softc *sc = mac->mac_sc;
3769	uint16_t state;
3770
3771	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3772	    __func__, mac->mac_suspended);
3773
3774	state = bwn_shm_read_2(mac, BWN_SHARED,
3775	    BWN_SHARED_UCODESTAT);
3776	if (state != BWN_SHARED_UCODESTAT_SUSPEND &&
3777	    state != BWN_SHARED_UCODESTAT_SLEEP)
3778		device_printf(sc->sc_dev, "warn: firmware state (%d)\n", state);
3779
3780	mac->mac_suspended--;
3781	KASSERT(mac->mac_suspended >= 0,
3782	    ("%s:%d: fail", __func__, __LINE__));
3783	if (mac->mac_suspended == 0) {
3784		BWN_WRITE_4(mac, BWN_MACCTL,
3785		    BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON);
3786		BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED);
3787		BWN_READ_4(mac, BWN_MACCTL);
3788		BWN_READ_4(mac, BWN_INTR_REASON);
3789		bwn_psctl(mac, 0);
3790	}
3791}
3792
3793void
3794bwn_psctl(struct bwn_mac *mac, uint32_t flags)
3795{
3796	struct bwn_softc *sc = mac->mac_sc;
3797	int i;
3798	uint16_t ucstat;
3799
3800	KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)),
3801	    ("%s:%d: fail", __func__, __LINE__));
3802	KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)),
3803	    ("%s:%d: fail", __func__, __LINE__));
3804
3805	/* XXX forcibly awake and hwps-off */
3806
3807	BWN_WRITE_4(mac, BWN_MACCTL,
3808	    (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
3809	    ~BWN_MACCTL_HWPS);
3810	BWN_READ_4(mac, BWN_MACCTL);
3811	if (siba_get_revid(sc->sc_dev) >= 5) {
3812		for (i = 0; i < 100; i++) {
3813			ucstat = bwn_shm_read_2(mac, BWN_SHARED,
3814			    BWN_SHARED_UCODESTAT);
3815			if (ucstat != BWN_SHARED_UCODESTAT_SLEEP)
3816				break;
3817			DELAY(10);
3818		}
3819	}
3820	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__,
3821	    ucstat);
3822}
3823
3824static int
3825bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
3826{
3827	struct bwn_softc *sc = mac->mac_sc;
3828	struct bwn_fw *fw = &mac->mac_fw;
3829	const uint8_t rev = siba_get_revid(sc->sc_dev);
3830	const char *filename;
3831	uint32_t high;
3832	int error;
3833
3834	/* microcode */
3835	filename = NULL;
3836	switch (rev) {
3837	case 42:
3838		if (mac->mac_phy.type == BWN_PHYTYPE_AC)
3839			filename = "ucode42";
3840		break;
3841	case 40:
3842		if (mac->mac_phy.type == BWN_PHYTYPE_AC)
3843			filename = "ucode40";
3844		break;
3845	case 33:
3846		if (mac->mac_phy.type == BWN_PHYTYPE_LCN40)
3847			filename = "ucode33_lcn40";
3848		break;
3849	case 30:
3850		if (mac->mac_phy.type == BWN_PHYTYPE_N)
3851			filename = "ucode30_mimo";
3852		break;
3853	case 29:
3854		if (mac->mac_phy.type == BWN_PHYTYPE_HT)
3855			filename = "ucode29_mimo";
3856		break;
3857	case 26:
3858		if (mac->mac_phy.type == BWN_PHYTYPE_HT)
3859			filename = "ucode26_mimo";
3860		break;
3861	case 28:
3862	case 25:
3863		if (mac->mac_phy.type == BWN_PHYTYPE_N)
3864			filename = "ucode25_mimo";
3865		else if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
3866			filename = "ucode25_lcn";
3867		break;
3868	case 24:
3869		if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
3870			filename = "ucode24_lcn";
3871		break;
3872	case 23:
3873		if (mac->mac_phy.type == BWN_PHYTYPE_N)
3874			filename = "ucode16_mimo";
3875		break;
3876	case 16:
3877	case 17:
3878	case 18:
3879	case 19:
3880		if (mac->mac_phy.type == BWN_PHYTYPE_N)
3881			filename = "ucode16_mimo";
3882		else if (mac->mac_phy.type == BWN_PHYTYPE_LP)
3883			filename = "ucode16_lp";
3884		break;
3885	case 15:
3886		filename = "ucode15";
3887		break;
3888	case 14:
3889		filename = "ucode14";
3890		break;
3891	case 13:
3892		filename = "ucode13";
3893		break;
3894	case 12:
3895	case 11:
3896		filename = "ucode11";
3897		break;
3898	case 10:
3899	case 9:
3900	case 8:
3901	case 7:
3902	case 6:
3903	case 5:
3904		filename = "ucode5";
3905		break;
3906	default:
3907		device_printf(sc->sc_dev, "no ucode for rev %d\n", rev);
3908		bwn_release_firmware(mac);
3909		return (EOPNOTSUPP);
3910	}
3911
3912	device_printf(sc->sc_dev, "ucode fw: %s\n", filename);
3913	error = bwn_fw_get(mac, type, filename, &fw->ucode);
3914	if (error) {
3915		bwn_release_firmware(mac);
3916		return (error);
3917	}
3918
3919	/* PCM */
3920	KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__));
3921	if (rev >= 5 && rev <= 10) {
3922		error = bwn_fw_get(mac, type, "pcm5", &fw->pcm);
3923		if (error == ENOENT)
3924			fw->no_pcmfile = 1;
3925		else if (error) {
3926			bwn_release_firmware(mac);
3927			return (error);
3928		}
3929	} else if (rev < 11) {
3930		device_printf(sc->sc_dev, "no PCM for rev %d\n", rev);
3931		return (EOPNOTSUPP);
3932	}
3933
3934	/* initvals */
3935	high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
3936	switch (mac->mac_phy.type) {
3937	case BWN_PHYTYPE_A:
3938		if (rev < 5 || rev > 10)
3939			goto fail1;
3940		if (high & BWN_TGSHIGH_HAVE_2GHZ)
3941			filename = "a0g1initvals5";
3942		else
3943			filename = "a0g0initvals5";
3944		break;
3945	case BWN_PHYTYPE_G:
3946		if (rev >= 5 && rev <= 10)
3947			filename = "b0g0initvals5";
3948		else if (rev >= 13)
3949			filename = "b0g0initvals13";
3950		else
3951			goto fail1;
3952		break;
3953	case BWN_PHYTYPE_LP:
3954		if (rev == 13)
3955			filename = "lp0initvals13";
3956		else if (rev == 14)
3957			filename = "lp0initvals14";
3958		else if (rev >= 15)
3959			filename = "lp0initvals15";
3960		else
3961			goto fail1;
3962		break;
3963	case BWN_PHYTYPE_N:
3964		if (rev == 30)
3965			filename = "n16initvals30";
3966		else if (rev == 28 || rev == 25)
3967			filename = "n0initvals25";
3968		else if (rev == 24)
3969			filename = "n0initvals24";
3970		else if (rev == 23)
3971			filename = "n0initvals16";
3972		else if (rev >= 16 && rev <= 18)
3973			filename = "n0initvals16";
3974		else if (rev >= 11 && rev <= 12)
3975			filename = "n0initvals11";
3976		else
3977			goto fail1;
3978		break;
3979	default:
3980		goto fail1;
3981	}
3982	error = bwn_fw_get(mac, type, filename, &fw->initvals);
3983	if (error) {
3984		bwn_release_firmware(mac);
3985		return (error);
3986	}
3987
3988	/* bandswitch initvals */
3989	switch (mac->mac_phy.type) {
3990	case BWN_PHYTYPE_A:
3991		if (rev >= 5 && rev <= 10) {
3992			if (high & BWN_TGSHIGH_HAVE_2GHZ)
3993				filename = "a0g1bsinitvals5";
3994			else
3995				filename = "a0g0bsinitvals5";
3996		} else if (rev >= 11)
3997			filename = NULL;
3998		else
3999			goto fail1;
4000		break;
4001	case BWN_PHYTYPE_G:
4002		if (rev >= 5 && rev <= 10)
4003			filename = "b0g0bsinitvals5";
4004		else if (rev >= 11)
4005			filename = NULL;
4006		else
4007			goto fail1;
4008		break;
4009	case BWN_PHYTYPE_LP:
4010		if (rev == 13)
4011			filename = "lp0bsinitvals13";
4012		else if (rev == 14)
4013			filename = "lp0bsinitvals14";
4014		else if (rev >= 15)
4015			filename = "lp0bsinitvals15";
4016		else
4017			goto fail1;
4018		break;
4019	case BWN_PHYTYPE_N:
4020		if (rev == 30)
4021			filename = "n16bsinitvals30";
4022		else if (rev == 28 || rev == 25)
4023			filename = "n0bsinitvals25";
4024		else if (rev == 24)
4025			filename = "n0bsinitvals24";
4026		else if (rev == 23)
4027			filename = "n0bsinitvals16";
4028		else if (rev >= 16 && rev <= 18)
4029			filename = "n0bsinitvals16";
4030		else if (rev >= 11 && rev <= 12)
4031			filename = "n0bsinitvals11";
4032		else
4033			goto fail1;
4034		break;
4035	default:
4036		device_printf(sc->sc_dev, "unknown phy (%d)\n",
4037		    mac->mac_phy.type);
4038		goto fail1;
4039	}
4040	error = bwn_fw_get(mac, type, filename, &fw->initvals_band);
4041	if (error) {
4042		bwn_release_firmware(mac);
4043		return (error);
4044	}
4045	return (0);
4046fail1:
4047	device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n",
4048	    rev, mac->mac_phy.type);
4049	bwn_release_firmware(mac);
4050	return (EOPNOTSUPP);
4051}
4052
4053static int
4054bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type,
4055    const char *name, struct bwn_fwfile *bfw)
4056{
4057	const struct bwn_fwhdr *hdr;
4058	struct bwn_softc *sc = mac->mac_sc;
4059	const struct firmware *fw;
4060	char namebuf[64];
4061
4062	if (name == NULL) {
4063		bwn_do_release_fw(bfw);
4064		return (0);
4065	}
4066	if (bfw->filename != NULL) {
4067		if (bfw->type == type && (strcmp(bfw->filename, name) == 0))
4068			return (0);
4069		bwn_do_release_fw(bfw);
4070	}
4071
4072	snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s",
4073	    (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "",
4074	    (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name);
4075	/* XXX Sleeping on "fwload" with the non-sleepable locks held */
4076	fw = firmware_get(namebuf);
4077	if (fw == NULL) {
4078		device_printf(sc->sc_dev, "the fw file(%s) not found\n",
4079		    namebuf);
4080		return (ENOENT);
4081	}
4082	if (fw->datasize < sizeof(struct bwn_fwhdr))
4083		goto fail;
4084	hdr = (const struct bwn_fwhdr *)(fw->data);
4085	switch (hdr->type) {
4086	case BWN_FWTYPE_UCODE:
4087	case BWN_FWTYPE_PCM:
4088		if (be32toh(hdr->size) !=
4089		    (fw->datasize - sizeof(struct bwn_fwhdr)))
4090			goto fail;
4091		/* FALLTHROUGH */
4092	case BWN_FWTYPE_IV:
4093		if (hdr->ver != 1)
4094			goto fail;
4095		break;
4096	default:
4097		goto fail;
4098	}
4099	bfw->filename = name;
4100	bfw->fw = fw;
4101	bfw->type = type;
4102	return (0);
4103fail:
4104	device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf);
4105	if (fw != NULL)
4106		firmware_put(fw, FIRMWARE_UNLOAD);
4107	return (EPROTO);
4108}
4109
4110static void
4111bwn_release_firmware(struct bwn_mac *mac)
4112{
4113
4114	bwn_do_release_fw(&mac->mac_fw.ucode);
4115	bwn_do_release_fw(&mac->mac_fw.pcm);
4116	bwn_do_release_fw(&mac->mac_fw.initvals);
4117	bwn_do_release_fw(&mac->mac_fw.initvals_band);
4118}
4119
4120static void
4121bwn_do_release_fw(struct bwn_fwfile *bfw)
4122{
4123
4124	if (bfw->fw != NULL)
4125		firmware_put(bfw->fw, FIRMWARE_UNLOAD);
4126	bfw->fw = NULL;
4127	bfw->filename = NULL;
4128}
4129
4130static int
4131bwn_fw_loaducode(struct bwn_mac *mac)
4132{
4133#define	GETFWOFFSET(fwp, offset)	\
4134	((const uint32_t *)((const char *)fwp.fw->data + offset))
4135#define	GETFWSIZE(fwp, offset)	\
4136	((fwp.fw->datasize - offset) / sizeof(uint32_t))
4137	struct bwn_softc *sc = mac->mac_sc;
4138	const uint32_t *data;
4139	unsigned int i;
4140	uint32_t ctl;
4141	uint16_t date, fwcaps, time;
4142	int error = 0;
4143
4144	ctl = BWN_READ_4(mac, BWN_MACCTL);
4145	ctl |= BWN_MACCTL_MCODE_JMP0;
4146	KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__,
4147	    __LINE__));
4148	BWN_WRITE_4(mac, BWN_MACCTL, ctl);
4149	for (i = 0; i < 64; i++)
4150		bwn_shm_write_2(mac, BWN_SCRATCH, i, 0);
4151	for (i = 0; i < 4096; i += 2)
4152		bwn_shm_write_2(mac, BWN_SHARED, i, 0);
4153
4154	data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4155	bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000);
4156	for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4157	     i++) {
4158		BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4159		DELAY(10);
4160	}
4161
4162	if (mac->mac_fw.pcm.fw) {
4163		data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr));
4164		bwn_shm_ctlword(mac, BWN_HW, 0x01ea);
4165		BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000);
4166		bwn_shm_ctlword(mac, BWN_HW, 0x01eb);
4167		for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm,
4168		    sizeof(struct bwn_fwhdr)); i++) {
4169			BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4170			DELAY(10);
4171		}
4172	}
4173
4174	BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL);
4175	BWN_WRITE_4(mac, BWN_MACCTL,
4176	    (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) |
4177	    BWN_MACCTL_MCODE_RUN);
4178
4179	for (i = 0; i < 21; i++) {
4180		if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED)
4181			break;
4182		if (i >= 20) {
4183			device_printf(sc->sc_dev, "ucode timeout\n");
4184			error = ENXIO;
4185			goto error;
4186		}
4187		DELAY(50000);
4188	}
4189	BWN_READ_4(mac, BWN_INTR_REASON);
4190
4191	mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV);
4192	if (mac->mac_fw.rev <= 0x128) {
4193		device_printf(sc->sc_dev, "the firmware is too old\n");
4194		error = EOPNOTSUPP;
4195		goto error;
4196	}
4197
4198	/*
4199	 * Determine firmware header version; needed for TX/RX packet
4200	 * handling.
4201	 */
4202	if (mac->mac_fw.rev >= 598)
4203		mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598;
4204	else if (mac->mac_fw.rev >= 410)
4205		mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410;
4206	else
4207		mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351;
4208
4209	/*
4210	 * We don't support rev 598 or later; that requires
4211	 * another round of changes to the TX/RX descriptor
4212	 * and status layout.
4213	 *
4214	 * So, complain this is the case and exit out, rather
4215	 * than attaching and then failing.
4216	 */
4217#if 0
4218	if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) {
4219		device_printf(sc->sc_dev,
4220		    "firmware is too new (>=598); not supported\n");
4221		error = EOPNOTSUPP;
4222		goto error;
4223	}
4224#endif
4225
4226	mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED,
4227	    BWN_SHARED_UCODE_PATCH);
4228	date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE);
4229	mac->mac_fw.opensource = (date == 0xffff);
4230	if (bwn_wme != 0)
4231		mac->mac_flags |= BWN_MAC_FLAG_WME;
4232	mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO;
4233
4234	time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME);
4235	if (mac->mac_fw.opensource == 0) {
4236		device_printf(sc->sc_dev,
4237		    "firmware version (rev %u patch %u date %#x time %#x)\n",
4238		    mac->mac_fw.rev, mac->mac_fw.patch, date, time);
4239		if (mac->mac_fw.no_pcmfile)
4240			device_printf(sc->sc_dev,
4241			    "no HW crypto acceleration due to pcm5\n");
4242	} else {
4243		mac->mac_fw.patch = time;
4244		fwcaps = bwn_fwcaps_read(mac);
4245		if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) {
4246			device_printf(sc->sc_dev,
4247			    "disabling HW crypto acceleration\n");
4248			mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO;
4249		}
4250		if (!(fwcaps & BWN_FWCAPS_WME)) {
4251			device_printf(sc->sc_dev, "disabling WME support\n");
4252			mac->mac_flags &= ~BWN_MAC_FLAG_WME;
4253		}
4254	}
4255
4256	if (BWN_ISOLDFMT(mac))
4257		device_printf(sc->sc_dev, "using old firmware image\n");
4258
4259	return (0);
4260
4261error:
4262	BWN_WRITE_4(mac, BWN_MACCTL,
4263	    (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) |
4264	    BWN_MACCTL_MCODE_JMP0);
4265
4266	return (error);
4267#undef GETFWSIZE
4268#undef GETFWOFFSET
4269}
4270
4271/* OpenFirmware only */
4272static uint16_t
4273bwn_fwcaps_read(struct bwn_mac *mac)
4274{
4275
4276	KASSERT(mac->mac_fw.opensource == 1,
4277	    ("%s:%d: fail", __func__, __LINE__));
4278	return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS));
4279}
4280
4281static int
4282bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals,
4283    size_t count, size_t array_size)
4284{
4285#define	GET_NEXTIV16(iv)						\
4286	((const struct bwn_fwinitvals *)((const uint8_t *)(iv) +	\
4287	    sizeof(uint16_t) + sizeof(uint16_t)))
4288#define	GET_NEXTIV32(iv)						\
4289	((const struct bwn_fwinitvals *)((const uint8_t *)(iv) +	\
4290	    sizeof(uint16_t) + sizeof(uint32_t)))
4291	struct bwn_softc *sc = mac->mac_sc;
4292	const struct bwn_fwinitvals *iv;
4293	uint16_t offset;
4294	size_t i;
4295	uint8_t bit32;
4296
4297	KASSERT(sizeof(struct bwn_fwinitvals) == 6,
4298	    ("%s:%d: fail", __func__, __LINE__));
4299	iv = ivals;
4300	for (i = 0; i < count; i++) {
4301		if (array_size < sizeof(iv->offset_size))
4302			goto fail;
4303		array_size -= sizeof(iv->offset_size);
4304		offset = be16toh(iv->offset_size);
4305		bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0;
4306		offset &= BWN_FWINITVALS_OFFSET_MASK;
4307		if (offset >= 0x1000)
4308			goto fail;
4309		if (bit32) {
4310			if (array_size < sizeof(iv->data.d32))
4311				goto fail;
4312			array_size -= sizeof(iv->data.d32);
4313			BWN_WRITE_4(mac, offset, be32toh(iv->data.d32));
4314			iv = GET_NEXTIV32(iv);
4315		} else {
4316
4317			if (array_size < sizeof(iv->data.d16))
4318				goto fail;
4319			array_size -= sizeof(iv->data.d16);
4320			BWN_WRITE_2(mac, offset, be16toh(iv->data.d16));
4321
4322			iv = GET_NEXTIV16(iv);
4323		}
4324	}
4325	if (array_size != 0)
4326		goto fail;
4327	return (0);
4328fail:
4329	device_printf(sc->sc_dev, "initvals: invalid format\n");
4330	return (EPROTO);
4331#undef GET_NEXTIV16
4332#undef GET_NEXTIV32
4333}
4334
4335int
4336bwn_switch_channel(struct bwn_mac *mac, int chan)
4337{
4338	struct bwn_phy *phy = &(mac->mac_phy);
4339	struct bwn_softc *sc = mac->mac_sc;
4340	struct ieee80211com *ic = &sc->sc_ic;
4341	uint16_t channelcookie, savedcookie;
4342	int error;
4343
4344	if (chan == 0xffff)
4345		chan = phy->get_default_chan(mac);
4346
4347	channelcookie = chan;
4348	if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4349		channelcookie |= 0x100;
4350	savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN);
4351	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie);
4352	error = phy->switch_channel(mac, chan);
4353	if (error)
4354		goto fail;
4355
4356	mac->mac_phy.chan = chan;
4357	DELAY(8000);
4358	return (0);
4359fail:
4360	device_printf(sc->sc_dev, "failed to switch channel\n");
4361	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie);
4362	return (error);
4363}
4364
4365static uint16_t
4366bwn_ant2phy(int antenna)
4367{
4368
4369	switch (antenna) {
4370	case BWN_ANT0:
4371		return (BWN_TX_PHY_ANT0);
4372	case BWN_ANT1:
4373		return (BWN_TX_PHY_ANT1);
4374	case BWN_ANT2:
4375		return (BWN_TX_PHY_ANT2);
4376	case BWN_ANT3:
4377		return (BWN_TX_PHY_ANT3);
4378	case BWN_ANTAUTO:
4379		return (BWN_TX_PHY_ANT01AUTO);
4380	}
4381	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4382	return (0);
4383}
4384
4385static void
4386bwn_wme_load(struct bwn_mac *mac)
4387{
4388	struct bwn_softc *sc = mac->mac_sc;
4389	int i;
4390
4391	KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
4392	    ("%s:%d: fail", __func__, __LINE__));
4393
4394	bwn_mac_suspend(mac);
4395	for (i = 0; i < N(sc->sc_wmeParams); i++)
4396		bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]),
4397		    bwn_wme_shm_offsets[i]);
4398	bwn_mac_enable(mac);
4399}
4400
4401static void
4402bwn_wme_loadparams(struct bwn_mac *mac,
4403    const struct wmeParams *p, uint16_t shm_offset)
4404{
4405#define	SM(_v, _f)      (((_v) << _f##_S) & _f)
4406	struct bwn_softc *sc = mac->mac_sc;
4407	uint16_t params[BWN_NR_WMEPARAMS];
4408	int slot, tmp;
4409	unsigned int i;
4410
4411	slot = BWN_READ_2(mac, BWN_RNG) &
4412	    SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4413
4414	memset(&params, 0, sizeof(params));
4415
4416	DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d "
4417	    "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit,
4418	    p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn);
4419
4420	params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32;
4421	params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4422	params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX);
4423	params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4424	params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn;
4425	params[BWN_WMEPARAM_BSLOTS] = slot;
4426	params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn;
4427
4428	for (i = 0; i < N(params); i++) {
4429		if (i == BWN_WMEPARAM_STATUS) {
4430			tmp = bwn_shm_read_2(mac, BWN_SHARED,
4431			    shm_offset + (i * 2));
4432			tmp |= 0x100;
4433			bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4434			    tmp);
4435		} else {
4436			bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4437			    params[i]);
4438		}
4439	}
4440}
4441
4442static void
4443bwn_mac_write_bssid(struct bwn_mac *mac)
4444{
4445	struct bwn_softc *sc = mac->mac_sc;
4446	uint32_t tmp;
4447	int i;
4448	uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2];
4449
4450	bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid);
4451	memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN);
4452	memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid,
4453	    IEEE80211_ADDR_LEN);
4454
4455	for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) {
4456		tmp = (uint32_t) (mac_bssid[i + 0]);
4457		tmp |= (uint32_t) (mac_bssid[i + 1]) << 8;
4458		tmp |= (uint32_t) (mac_bssid[i + 2]) << 16;
4459		tmp |= (uint32_t) (mac_bssid[i + 3]) << 24;
4460		bwn_ram_write(mac, 0x20 + i, tmp);
4461	}
4462}
4463
4464static void
4465bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset,
4466    const uint8_t *macaddr)
4467{
4468	static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 };
4469	uint16_t data;
4470
4471	if (!mac)
4472		macaddr = zero;
4473
4474	offset |= 0x0020;
4475	BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset);
4476
4477	data = macaddr[0];
4478	data |= macaddr[1] << 8;
4479	BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4480	data = macaddr[2];
4481	data |= macaddr[3] << 8;
4482	BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4483	data = macaddr[4];
4484	data |= macaddr[5] << 8;
4485	BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4486}
4487
4488static void
4489bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4490    const uint8_t *key, size_t key_len, const uint8_t *mac_addr)
4491{
4492	uint8_t buf[BWN_SEC_KEYSIZE] = { 0, };
4493	uint8_t per_sta_keys_start = 8;
4494
4495	if (BWN_SEC_NEWAPI(mac))
4496		per_sta_keys_start = 4;
4497
4498	KASSERT(index < mac->mac_max_nr_keys,
4499	    ("%s:%d: fail", __func__, __LINE__));
4500	KASSERT(key_len <= BWN_SEC_KEYSIZE,
4501	    ("%s:%d: fail", __func__, __LINE__));
4502
4503	if (index >= per_sta_keys_start)
4504		bwn_key_macwrite(mac, index, NULL);
4505	if (key)
4506		memcpy(buf, key, key_len);
4507	bwn_key_write(mac, index, algorithm, buf);
4508	if (index >= per_sta_keys_start)
4509		bwn_key_macwrite(mac, index, mac_addr);
4510
4511	mac->mac_key[index].algorithm = algorithm;
4512}
4513
4514static void
4515bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
4516{
4517	struct bwn_softc *sc = mac->mac_sc;
4518	uint32_t addrtmp[2] = { 0, 0 };
4519	uint8_t start = 8;
4520
4521	if (BWN_SEC_NEWAPI(mac))
4522		start = 4;
4523
4524	KASSERT(index >= start,
4525	    ("%s:%d: fail", __func__, __LINE__));
4526	index -= start;
4527
4528	if (addr) {
4529		addrtmp[0] = addr[0];
4530		addrtmp[0] |= ((uint32_t) (addr[1]) << 8);
4531		addrtmp[0] |= ((uint32_t) (addr[2]) << 16);
4532		addrtmp[0] |= ((uint32_t) (addr[3]) << 24);
4533		addrtmp[1] = addr[4];
4534		addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
4535	}
4536
4537	if (siba_get_revid(sc->sc_dev) >= 5) {
4538		bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
4539		bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
4540	} else {
4541		if (index >= 8) {
4542			bwn_shm_write_4(mac, BWN_SHARED,
4543			    BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]);
4544			bwn_shm_write_2(mac, BWN_SHARED,
4545			    BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]);
4546		}
4547	}
4548}
4549
4550static void
4551bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4552    const uint8_t *key)
4553{
4554	unsigned int i;
4555	uint32_t offset;
4556	uint16_t kidx, value;
4557
4558	kidx = BWN_SEC_KEY2FW(mac, index);
4559	bwn_shm_write_2(mac, BWN_SHARED,
4560	    BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm);
4561
4562	offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE);
4563	for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) {
4564		value = key[i];
4565		value |= (uint16_t)(key[i + 1]) << 8;
4566		bwn_shm_write_2(mac, BWN_SHARED, offset + i, value);
4567	}
4568}
4569
4570static void
4571bwn_phy_exit(struct bwn_mac *mac)
4572{
4573
4574	mac->mac_phy.rf_onoff(mac, 0);
4575	if (mac->mac_phy.exit != NULL)
4576		mac->mac_phy.exit(mac);
4577}
4578
4579static void
4580bwn_dma_free(struct bwn_mac *mac)
4581{
4582	struct bwn_dma *dma;
4583
4584	if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
4585		return;
4586	dma = &mac->mac_method.dma;
4587
4588	bwn_dma_ringfree(&dma->rx);
4589	bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
4590	bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
4591	bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
4592	bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
4593	bwn_dma_ringfree(&dma->mcast);
4594}
4595
4596static void
4597bwn_core_stop(struct bwn_mac *mac)
4598{
4599	struct bwn_softc *sc = mac->mac_sc;
4600
4601	BWN_ASSERT_LOCKED(sc);
4602
4603	if (mac->mac_status < BWN_MAC_STATUS_STARTED)
4604		return;
4605
4606	callout_stop(&sc->sc_rfswitch_ch);
4607	callout_stop(&sc->sc_task_ch);
4608	callout_stop(&sc->sc_watchdog_ch);
4609	sc->sc_watchdog_timer = 0;
4610	BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
4611	BWN_READ_4(mac, BWN_INTR_MASK);
4612	bwn_mac_suspend(mac);
4613
4614	mac->mac_status = BWN_MAC_STATUS_INITED;
4615}
4616
4617static int
4618bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan)
4619{
4620	struct bwn_mac *up_dev = NULL;
4621	struct bwn_mac *down_dev;
4622	struct bwn_mac *mac;
4623	int err, status;
4624	uint8_t gmode;
4625
4626	BWN_ASSERT_LOCKED(sc);
4627
4628	TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) {
4629		if (IEEE80211_IS_CHAN_2GHZ(chan) &&
4630		    mac->mac_phy.supports_2ghz) {
4631			up_dev = mac;
4632			gmode = 1;
4633		} else if (IEEE80211_IS_CHAN_5GHZ(chan) &&
4634		    mac->mac_phy.supports_5ghz) {
4635			up_dev = mac;
4636			gmode = 0;
4637		} else {
4638			KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4639			return (EINVAL);
4640		}
4641		if (up_dev != NULL)
4642			break;
4643	}
4644	if (up_dev == NULL) {
4645		device_printf(sc->sc_dev, "Could not find a device\n");
4646		return (ENODEV);
4647	}
4648	if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode)
4649		return (0);
4650
4651	DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET,
4652	    "switching to %s-GHz band\n",
4653	    IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4654
4655	down_dev = sc->sc_curmac;
4656	status = down_dev->mac_status;
4657	if (status >= BWN_MAC_STATUS_STARTED)
4658		bwn_core_stop(down_dev);
4659	if (status >= BWN_MAC_STATUS_INITED)
4660		bwn_core_exit(down_dev);
4661
4662	if (down_dev != up_dev)
4663		bwn_phy_reset(down_dev);
4664
4665	up_dev->mac_phy.gmode = gmode;
4666	if (status >= BWN_MAC_STATUS_INITED) {
4667		err = bwn_core_init(up_dev);
4668		if (err) {
4669			device_printf(sc->sc_dev,
4670			    "fatal: failed to initialize for %s-GHz\n",
4671			    IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4672			goto fail;
4673		}
4674	}
4675	if (status >= BWN_MAC_STATUS_STARTED)
4676		bwn_core_start(up_dev);
4677	KASSERT(up_dev->mac_status == status, ("%s: fail", __func__));
4678	sc->sc_curmac = up_dev;
4679
4680	return (0);
4681fail:
4682	sc->sc_curmac = NULL;
4683	return (err);
4684}
4685
4686static void
4687bwn_rf_turnon(struct bwn_mac *mac)
4688{
4689
4690	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4691
4692	bwn_mac_suspend(mac);
4693	mac->mac_phy.rf_onoff(mac, 1);
4694	mac->mac_phy.rf_on = 1;
4695	bwn_mac_enable(mac);
4696}
4697
4698static void
4699bwn_rf_turnoff(struct bwn_mac *mac)
4700{
4701
4702	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4703
4704	bwn_mac_suspend(mac);
4705	mac->mac_phy.rf_onoff(mac, 0);
4706	mac->mac_phy.rf_on = 0;
4707	bwn_mac_enable(mac);
4708}
4709
4710/*
4711 * SSB PHY reset.
4712 *
4713 * XXX TODO: BCMA PHY reset.
4714 */
4715static void
4716bwn_phy_reset(struct bwn_mac *mac)
4717{
4718	struct bwn_softc *sc = mac->mac_sc;
4719
4720	siba_write_4(sc->sc_dev, SIBA_TGSLOW,
4721	    ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) |
4722	     BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC);
4723	DELAY(1000);
4724	siba_write_4(sc->sc_dev, SIBA_TGSLOW,
4725	    (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC));
4726	DELAY(1000);
4727}
4728
4729static int
4730bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
4731{
4732	struct bwn_vap *bvp = BWN_VAP(vap);
4733	struct ieee80211com *ic= vap->iv_ic;
4734	enum ieee80211_state ostate = vap->iv_state;
4735	struct bwn_softc *sc = ic->ic_softc;
4736	struct bwn_mac *mac = sc->sc_curmac;
4737	int error;
4738
4739	DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4740	    ieee80211_state_name[vap->iv_state],
4741	    ieee80211_state_name[nstate]);
4742
4743	error = bvp->bv_newstate(vap, nstate, arg);
4744	if (error != 0)
4745		return (error);
4746
4747	BWN_LOCK(sc);
4748
4749	bwn_led_newstate(mac, nstate);
4750
4751	/*
4752	 * Clear the BSSID when we stop a STA
4753	 */
4754	if (vap->iv_opmode == IEEE80211_M_STA) {
4755		if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
4756			/*
4757			 * Clear out the BSSID.  If we reassociate to
4758			 * the same AP, this will reinialize things
4759			 * correctly...
4760			 */
4761			if (ic->ic_opmode == IEEE80211_M_STA &&
4762			    (sc->sc_flags & BWN_FLAG_INVALID) == 0) {
4763				memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN);
4764				bwn_set_macaddr(mac);
4765			}
4766		}
4767	}
4768
4769	if (vap->iv_opmode == IEEE80211_M_MONITOR ||
4770	    vap->iv_opmode == IEEE80211_M_AHDEMO) {
4771		/* XXX nothing to do? */
4772	} else if (nstate == IEEE80211_S_RUN) {
4773		memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN);
4774		bwn_set_opmode(mac);
4775		bwn_set_pretbtt(mac);
4776		bwn_spu_setdelay(mac, 0);
4777		bwn_set_macaddr(mac);
4778	}
4779
4780	BWN_UNLOCK(sc);
4781
4782	return (error);
4783}
4784
4785static void
4786bwn_set_pretbtt(struct bwn_mac *mac)
4787{
4788	struct bwn_softc *sc = mac->mac_sc;
4789	struct ieee80211com *ic = &sc->sc_ic;
4790	uint16_t pretbtt;
4791
4792	if (ic->ic_opmode == IEEE80211_M_IBSS)
4793		pretbtt = 2;
4794	else
4795		pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250;
4796	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt);
4797	BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt);
4798}
4799
4800static int
4801bwn_intr(void *arg)
4802{
4803	struct bwn_mac *mac = arg;
4804	struct bwn_softc *sc = mac->mac_sc;
4805	uint32_t reason;
4806
4807	if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
4808	    (sc->sc_flags & BWN_FLAG_INVALID))
4809		return (FILTER_STRAY);
4810
4811	DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__);
4812
4813	reason = BWN_READ_4(mac, BWN_INTR_REASON);
4814	if (reason == 0xffffffff)	/* shared IRQ */
4815		return (FILTER_STRAY);
4816	reason &= mac->mac_intr_mask;
4817	if (reason == 0)
4818		return (FILTER_HANDLED);
4819	DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason);
4820
4821	mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00;
4822	mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00;
4823	mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00;
4824	mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00;
4825	mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00;
4826	BWN_WRITE_4(mac, BWN_INTR_REASON, reason);
4827	BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]);
4828	BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]);
4829	BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]);
4830	BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]);
4831	BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]);
4832
4833	/* Disable interrupts. */
4834	BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
4835
4836	mac->mac_reason_intr = reason;
4837
4838	BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
4839	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
4840
4841	taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask);
4842	return (FILTER_HANDLED);
4843}
4844
4845static void
4846bwn_intrtask(void *arg, int npending)
4847{
4848	struct bwn_mac *mac = arg;
4849	struct bwn_softc *sc = mac->mac_sc;
4850	uint32_t merged = 0;
4851	int i, tx = 0, rx = 0;
4852
4853	BWN_LOCK(sc);
4854	if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
4855	    (sc->sc_flags & BWN_FLAG_INVALID)) {
4856		BWN_UNLOCK(sc);
4857		return;
4858	}
4859
4860	for (i = 0; i < N(mac->mac_reason); i++)
4861		merged |= mac->mac_reason[i];
4862
4863	if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR)
4864		device_printf(sc->sc_dev, "MAC trans error\n");
4865
4866	if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) {
4867		DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__);
4868		mac->mac_phy.txerrors--;
4869		if (mac->mac_phy.txerrors == 0) {
4870			mac->mac_phy.txerrors = BWN_TXERROR_MAX;
4871			bwn_restart(mac, "PHY TX errors");
4872		}
4873	}
4874
4875	if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) {
4876		if (merged & BWN_DMAINTR_FATALMASK) {
4877			device_printf(sc->sc_dev,
4878			    "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n",
4879			    mac->mac_reason[0], mac->mac_reason[1],
4880			    mac->mac_reason[2], mac->mac_reason[3],
4881			    mac->mac_reason[4], mac->mac_reason[5]);
4882			bwn_restart(mac, "DMA error");
4883			BWN_UNLOCK(sc);
4884			return;
4885		}
4886		if (merged & BWN_DMAINTR_NONFATALMASK) {
4887			device_printf(sc->sc_dev,
4888			    "DMA error: %#x %#x %#x %#x %#x %#x\n",
4889			    mac->mac_reason[0], mac->mac_reason[1],
4890			    mac->mac_reason[2], mac->mac_reason[3],
4891			    mac->mac_reason[4], mac->mac_reason[5]);
4892		}
4893	}
4894
4895	if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG)
4896		bwn_intr_ucode_debug(mac);
4897	if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI)
4898		bwn_intr_tbtt_indication(mac);
4899	if (mac->mac_reason_intr & BWN_INTR_ATIM_END)
4900		bwn_intr_atim_end(mac);
4901	if (mac->mac_reason_intr & BWN_INTR_BEACON)
4902		bwn_intr_beacon(mac);
4903	if (mac->mac_reason_intr & BWN_INTR_PMQ)
4904		bwn_intr_pmq(mac);
4905	if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK)
4906		bwn_intr_noise(mac);
4907
4908	if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
4909		if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) {
4910			bwn_dma_rx(mac->mac_method.dma.rx);
4911			rx = 1;
4912		}
4913	} else
4914		rx = bwn_pio_rx(&mac->mac_method.pio.rx);
4915
4916	KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4917	KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4918	KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4919	KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4920	KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4921
4922	if (mac->mac_reason_intr & BWN_INTR_TX_OK) {
4923		bwn_intr_txeof(mac);
4924		tx = 1;
4925	}
4926
4927	BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
4928
4929	if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
4930		int evt = BWN_LED_EVENT_NONE;
4931
4932		if (tx && rx) {
4933			if (sc->sc_rx_rate > sc->sc_tx_rate)
4934				evt = BWN_LED_EVENT_RX;
4935			else
4936				evt = BWN_LED_EVENT_TX;
4937		} else if (tx) {
4938			evt = BWN_LED_EVENT_TX;
4939		} else if (rx) {
4940			evt = BWN_LED_EVENT_RX;
4941		} else if (rx == 0) {
4942			evt = BWN_LED_EVENT_POLL;
4943		}
4944
4945		if (evt != BWN_LED_EVENT_NONE)
4946			bwn_led_event(mac, evt);
4947       }
4948
4949	if (mbufq_first(&sc->sc_snd) != NULL)
4950		bwn_start(sc);
4951
4952	BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
4953	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
4954
4955	BWN_UNLOCK(sc);
4956}
4957
4958static void
4959bwn_restart(struct bwn_mac *mac, const char *msg)
4960{
4961	struct bwn_softc *sc = mac->mac_sc;
4962	struct ieee80211com *ic = &sc->sc_ic;
4963
4964	if (mac->mac_status < BWN_MAC_STATUS_INITED)
4965		return;
4966
4967	device_printf(sc->sc_dev, "HW reset: %s\n", msg);
4968	ieee80211_runtask(ic, &mac->mac_hwreset);
4969}
4970
4971static void
4972bwn_intr_ucode_debug(struct bwn_mac *mac)
4973{
4974	struct bwn_softc *sc = mac->mac_sc;
4975	uint16_t reason;
4976
4977	if (mac->mac_fw.opensource == 0)
4978		return;
4979
4980	reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG);
4981	switch (reason) {
4982	case BWN_DEBUGINTR_PANIC:
4983		bwn_handle_fwpanic(mac);
4984		break;
4985	case BWN_DEBUGINTR_DUMP_SHM:
4986		device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n");
4987		break;
4988	case BWN_DEBUGINTR_DUMP_REGS:
4989		device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n");
4990		break;
4991	case BWN_DEBUGINTR_MARKER:
4992		device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n");
4993		break;
4994	default:
4995		device_printf(sc->sc_dev,
4996		    "ucode debug unknown reason: %#x\n", reason);
4997	}
4998
4999	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG,
5000	    BWN_DEBUGINTR_ACK);
5001}
5002
5003static void
5004bwn_intr_tbtt_indication(struct bwn_mac *mac)
5005{
5006	struct bwn_softc *sc = mac->mac_sc;
5007	struct ieee80211com *ic = &sc->sc_ic;
5008
5009	if (ic->ic_opmode != IEEE80211_M_HOSTAP)
5010		bwn_psctl(mac, 0);
5011	if (ic->ic_opmode == IEEE80211_M_IBSS)
5012		mac->mac_flags |= BWN_MAC_FLAG_DFQVALID;
5013}
5014
5015static void
5016bwn_intr_atim_end(struct bwn_mac *mac)
5017{
5018
5019	if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) {
5020		BWN_WRITE_4(mac, BWN_MACCMD,
5021		    BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID);
5022		mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
5023	}
5024}
5025
5026static void
5027bwn_intr_beacon(struct bwn_mac *mac)
5028{
5029	struct bwn_softc *sc = mac->mac_sc;
5030	struct ieee80211com *ic = &sc->sc_ic;
5031	uint32_t cmd, beacon0, beacon1;
5032
5033	if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
5034	    ic->ic_opmode == IEEE80211_M_MBSS)
5035		return;
5036
5037	mac->mac_intr_mask &= ~BWN_INTR_BEACON;
5038
5039	cmd = BWN_READ_4(mac, BWN_MACCMD);
5040	beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID);
5041	beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID);
5042
5043	if (beacon0 && beacon1) {
5044		BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON);
5045		mac->mac_intr_mask |= BWN_INTR_BEACON;
5046		return;
5047	}
5048
5049	if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) {
5050		sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP;
5051		bwn_load_beacon0(mac);
5052		bwn_load_beacon1(mac);
5053		cmd = BWN_READ_4(mac, BWN_MACCMD);
5054		cmd |= BWN_MACCMD_BEACON0_VALID;
5055		BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5056	} else {
5057		if (!beacon0) {
5058			bwn_load_beacon0(mac);
5059			cmd = BWN_READ_4(mac, BWN_MACCMD);
5060			cmd |= BWN_MACCMD_BEACON0_VALID;
5061			BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5062		} else if (!beacon1) {
5063			bwn_load_beacon1(mac);
5064			cmd = BWN_READ_4(mac, BWN_MACCMD);
5065			cmd |= BWN_MACCMD_BEACON1_VALID;
5066			BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5067		}
5068	}
5069}
5070
5071static void
5072bwn_intr_pmq(struct bwn_mac *mac)
5073{
5074	uint32_t tmp;
5075
5076	while (1) {
5077		tmp = BWN_READ_4(mac, BWN_PS_STATUS);
5078		if (!(tmp & 0x00000008))
5079			break;
5080	}
5081	BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002);
5082}
5083
5084static void
5085bwn_intr_noise(struct bwn_mac *mac)
5086{
5087	struct bwn_phy_g *pg = &mac->mac_phy.phy_g;
5088	uint16_t tmp;
5089	uint8_t noise[4];
5090	uint8_t i, j;
5091	int32_t average;
5092
5093	if (mac->mac_phy.type != BWN_PHYTYPE_G)
5094		return;
5095
5096	KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__));
5097	*((uint32_t *)noise) = htole32(bwn_jssi_read(mac));
5098	if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f ||
5099	    noise[3] == 0x7f)
5100		goto new;
5101
5102	KASSERT(mac->mac_noise.noi_nsamples < 8,
5103	    ("%s:%d: fail", __func__, __LINE__));
5104	i = mac->mac_noise.noi_nsamples;
5105	noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1);
5106	noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1);
5107	noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1);
5108	noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1);
5109	mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]];
5110	mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]];
5111	mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]];
5112	mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]];
5113	mac->mac_noise.noi_nsamples++;
5114	if (mac->mac_noise.noi_nsamples == 8) {
5115		average = 0;
5116		for (i = 0; i < 8; i++) {
5117			for (j = 0; j < 4; j++)
5118				average += mac->mac_noise.noi_samples[i][j];
5119		}
5120		average = (((average / 32) * 125) + 64) / 128;
5121		tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f;
5122		if (tmp >= 8)
5123			average += 2;
5124		else
5125			average -= 25;
5126		average -= (tmp == 8) ? 72 : 48;
5127
5128		mac->mac_stats.link_noise = average;
5129		mac->mac_noise.noi_running = 0;
5130		return;
5131	}
5132new:
5133	bwn_noise_gensample(mac);
5134}
5135
5136static int
5137bwn_pio_rx(struct bwn_pio_rxqueue *prq)
5138{
5139	struct bwn_mac *mac = prq->prq_mac;
5140	struct bwn_softc *sc = mac->mac_sc;
5141	unsigned int i;
5142
5143	BWN_ASSERT_LOCKED(sc);
5144
5145	if (mac->mac_status < BWN_MAC_STATUS_STARTED)
5146		return (0);
5147
5148	for (i = 0; i < 5000; i++) {
5149		if (bwn_pio_rxeof(prq) == 0)
5150			break;
5151	}
5152	if (i >= 5000)
5153		device_printf(sc->sc_dev, "too many RX frames in PIO mode\n");
5154	return ((i > 0) ? 1 : 0);
5155}
5156
5157static void
5158bwn_dma_rx(struct bwn_dma_ring *dr)
5159{
5160	int slot, curslot;
5161
5162	KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
5163	curslot = dr->get_curslot(dr);
5164	KASSERT(curslot >= 0 && curslot < dr->dr_numslots,
5165	    ("%s:%d: fail", __func__, __LINE__));
5166
5167	slot = dr->dr_curslot;
5168	for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot))
5169		bwn_dma_rxeof(dr, &slot);
5170
5171	bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
5172	    BUS_DMASYNC_PREWRITE);
5173
5174	dr->set_curslot(dr, slot);
5175	dr->dr_curslot = slot;
5176}
5177
5178static void
5179bwn_intr_txeof(struct bwn_mac *mac)
5180{
5181	struct bwn_txstatus stat;
5182	uint32_t stat0, stat1;
5183	uint16_t tmp;
5184
5185	BWN_ASSERT_LOCKED(mac->mac_sc);
5186
5187	while (1) {
5188		stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0);
5189		if (!(stat0 & 0x00000001))
5190			break;
5191		stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1);
5192
5193		DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5194		    "%s: stat0=0x%08x, stat1=0x%08x\n",
5195		    __func__,
5196		    stat0,
5197		    stat1);
5198
5199		stat.cookie = (stat0 >> 16);
5200		stat.seq = (stat1 & 0x0000ffff);
5201		stat.phy_stat = ((stat1 & 0x00ff0000) >> 16);
5202		tmp = (stat0 & 0x0000ffff);
5203		stat.framecnt = ((tmp & 0xf000) >> 12);
5204		stat.rtscnt = ((tmp & 0x0f00) >> 8);
5205		stat.sreason = ((tmp & 0x001c) >> 2);
5206		stat.pm = (tmp & 0x0080) ? 1 : 0;
5207		stat.im = (tmp & 0x0040) ? 1 : 0;
5208		stat.ampdu = (tmp & 0x0020) ? 1 : 0;
5209		stat.ack = (tmp & 0x0002) ? 1 : 0;
5210
5211		DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5212		    "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, "
5213		    "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n",
5214		    __func__,
5215		    stat.cookie,
5216		    stat.seq,
5217		    stat.phy_stat,
5218		    stat.framecnt,
5219		    stat.rtscnt,
5220		    stat.sreason,
5221		    stat.pm,
5222		    stat.im,
5223		    stat.ampdu,
5224		    stat.ack);
5225
5226		bwn_handle_txeof(mac, &stat);
5227	}
5228}
5229
5230static void
5231bwn_hwreset(void *arg, int npending)
5232{
5233	struct bwn_mac *mac = arg;
5234	struct bwn_softc *sc = mac->mac_sc;
5235	int error = 0;
5236	int prev_status;
5237
5238	BWN_LOCK(sc);
5239
5240	prev_status = mac->mac_status;
5241	if (prev_status >= BWN_MAC_STATUS_STARTED)
5242		bwn_core_stop(mac);
5243	if (prev_status >= BWN_MAC_STATUS_INITED)
5244		bwn_core_exit(mac);
5245
5246	if (prev_status >= BWN_MAC_STATUS_INITED) {
5247		error = bwn_core_init(mac);
5248		if (error)
5249			goto out;
5250	}
5251	if (prev_status >= BWN_MAC_STATUS_STARTED)
5252		bwn_core_start(mac);
5253out:
5254	if (error) {
5255		device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error);
5256		sc->sc_curmac = NULL;
5257	}
5258	BWN_UNLOCK(sc);
5259}
5260
5261static void
5262bwn_handle_fwpanic(struct bwn_mac *mac)
5263{
5264	struct bwn_softc *sc = mac->mac_sc;
5265	uint16_t reason;
5266
5267	reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG);
5268	device_printf(sc->sc_dev,"fw panic (%u)\n", reason);
5269
5270	if (reason == BWN_FWPANIC_RESTART)
5271		bwn_restart(mac, "ucode panic");
5272}
5273
5274static void
5275bwn_load_beacon0(struct bwn_mac *mac)
5276{
5277
5278	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5279}
5280
5281static void
5282bwn_load_beacon1(struct bwn_mac *mac)
5283{
5284
5285	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5286}
5287
5288static uint32_t
5289bwn_jssi_read(struct bwn_mac *mac)
5290{
5291	uint32_t val = 0;
5292
5293	val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a);
5294	val <<= 16;
5295	val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088);
5296
5297	return (val);
5298}
5299
5300static void
5301bwn_noise_gensample(struct bwn_mac *mac)
5302{
5303	uint32_t jssi = 0x7f7f7f7f;
5304
5305	bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff));
5306	bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16);
5307	BWN_WRITE_4(mac, BWN_MACCMD,
5308	    BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE);
5309}
5310
5311static int
5312bwn_dma_freeslot(struct bwn_dma_ring *dr)
5313{
5314	BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5315
5316	return (dr->dr_numslots - dr->dr_usedslot);
5317}
5318
5319static int
5320bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot)
5321{
5322	BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5323
5324	KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1,
5325	    ("%s:%d: fail", __func__, __LINE__));
5326	if (slot == dr->dr_numslots - 1)
5327		return (0);
5328	return (slot + 1);
5329}
5330
5331static void
5332bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot)
5333{
5334	struct bwn_mac *mac = dr->dr_mac;
5335	struct bwn_softc *sc = mac->mac_sc;
5336	struct bwn_dma *dma = &mac->mac_method.dma;
5337	struct bwn_dmadesc_generic *desc;
5338	struct bwn_dmadesc_meta *meta;
5339	struct bwn_rxhdr4 *rxhdr;
5340	struct mbuf *m;
5341	uint32_t macstat;
5342	int32_t tmp;
5343	int cnt = 0;
5344	uint16_t len;
5345
5346	dr->getdesc(dr, *slot, &desc, &meta);
5347
5348	bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD);
5349	m = meta->mt_m;
5350
5351	if (bwn_dma_newbuf(dr, desc, meta, 0)) {
5352		counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5353		return;
5354	}
5355
5356	rxhdr = mtod(m, struct bwn_rxhdr4 *);
5357	len = le16toh(rxhdr->frame_len);
5358	if (len <= 0) {
5359		counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5360		return;
5361	}
5362	if (bwn_dma_check_redzone(dr, m)) {
5363		device_printf(sc->sc_dev, "redzone error.\n");
5364		bwn_dma_set_redzone(dr, m);
5365		bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5366		    BUS_DMASYNC_PREWRITE);
5367		return;
5368	}
5369	if (len > dr->dr_rx_bufsize) {
5370		tmp = len;
5371		while (1) {
5372			dr->getdesc(dr, *slot, &desc, &meta);
5373			bwn_dma_set_redzone(dr, meta->mt_m);
5374			bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5375			    BUS_DMASYNC_PREWRITE);
5376			*slot = bwn_dma_nextslot(dr, *slot);
5377			cnt++;
5378			tmp -= dr->dr_rx_bufsize;
5379			if (tmp <= 0)
5380				break;
5381		}
5382		device_printf(sc->sc_dev, "too small buffer "
5383		       "(len %u buffer %u dropped %d)\n",
5384		       len, dr->dr_rx_bufsize, cnt);
5385		return;
5386	}
5387
5388	switch (mac->mac_fw.fw_hdr_format) {
5389	case BWN_FW_HDR_351:
5390	case BWN_FW_HDR_410:
5391		macstat = le32toh(rxhdr->ps4.r351.mac_status);
5392		break;
5393	case BWN_FW_HDR_598:
5394		macstat = le32toh(rxhdr->ps4.r598.mac_status);
5395		break;
5396	}
5397
5398	if (macstat & BWN_RX_MAC_FCSERR) {
5399		if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5400			device_printf(sc->sc_dev, "RX drop\n");
5401			return;
5402		}
5403	}
5404
5405	m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset;
5406	m_adj(m, dr->dr_frameoffset);
5407
5408	bwn_rxeof(dr->dr_mac, m, rxhdr);
5409}
5410
5411static void
5412bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status)
5413{
5414	struct bwn_softc *sc = mac->mac_sc;
5415	struct bwn_stats *stats = &mac->mac_stats;
5416
5417	BWN_ASSERT_LOCKED(mac->mac_sc);
5418
5419	if (status->im)
5420		device_printf(sc->sc_dev, "TODO: STATUS IM\n");
5421	if (status->ampdu)
5422		device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n");
5423	if (status->rtscnt) {
5424		if (status->rtscnt == 0xf)
5425			stats->rtsfail++;
5426		else
5427			stats->rts++;
5428	}
5429
5430	if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
5431		bwn_dma_handle_txeof(mac, status);
5432	} else {
5433		bwn_pio_handle_txeof(mac, status);
5434	}
5435
5436	bwn_phy_txpower_check(mac, 0);
5437}
5438
5439static uint8_t
5440bwn_pio_rxeof(struct bwn_pio_rxqueue *prq)
5441{
5442	struct bwn_mac *mac = prq->prq_mac;
5443	struct bwn_softc *sc = mac->mac_sc;
5444	struct bwn_rxhdr4 rxhdr;
5445	struct mbuf *m;
5446	uint32_t ctl32, macstat, v32;
5447	unsigned int i, padding;
5448	uint16_t ctl16, len, totlen, v16;
5449	unsigned char *mp;
5450	char *data;
5451
5452	memset(&rxhdr, 0, sizeof(rxhdr));
5453
5454	if (prq->prq_rev >= 8) {
5455		ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5456		if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY))
5457			return (0);
5458		bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5459		    BWN_PIO8_RXCTL_FRAMEREADY);
5460		for (i = 0; i < 10; i++) {
5461			ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5462			if (ctl32 & BWN_PIO8_RXCTL_DATAREADY)
5463				goto ready;
5464			DELAY(10);
5465		}
5466	} else {
5467		ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5468		if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY))
5469			return (0);
5470		bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL,
5471		    BWN_PIO_RXCTL_FRAMEREADY);
5472		for (i = 0; i < 10; i++) {
5473			ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5474			if (ctl16 & BWN_PIO_RXCTL_DATAREADY)
5475				goto ready;
5476			DELAY(10);
5477		}
5478	}
5479	device_printf(sc->sc_dev, "%s: timed out\n", __func__);
5480	return (1);
5481ready:
5482	if (prq->prq_rev >= 8)
5483		siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr),
5484		    prq->prq_base + BWN_PIO8_RXDATA);
5485	else
5486		siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr),
5487		    prq->prq_base + BWN_PIO_RXDATA);
5488	len = le16toh(rxhdr.frame_len);
5489	if (len > 0x700) {
5490		device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
5491		goto error;
5492	}
5493	if (len == 0) {
5494		device_printf(sc->sc_dev, "%s: len is 0\n", __func__);
5495		goto error;
5496	}
5497
5498	switch (mac->mac_fw.fw_hdr_format) {
5499	case BWN_FW_HDR_351:
5500	case BWN_FW_HDR_410:
5501		macstat = le32toh(rxhdr.ps4.r351.mac_status);
5502		break;
5503	case BWN_FW_HDR_598:
5504		macstat = le32toh(rxhdr.ps4.r598.mac_status);
5505		break;
5506	}
5507
5508	if (macstat & BWN_RX_MAC_FCSERR) {
5509		if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5510			device_printf(sc->sc_dev, "%s: FCS error", __func__);
5511			goto error;
5512		}
5513	}
5514
5515	padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
5516	totlen = len + padding;
5517	KASSERT(totlen <= MCLBYTES, ("too big..\n"));
5518	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5519	if (m == NULL) {
5520		device_printf(sc->sc_dev, "%s: out of memory", __func__);
5521		goto error;
5522	}
5523	mp = mtod(m, unsigned char *);
5524	if (prq->prq_rev >= 8) {
5525		siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3),
5526		    prq->prq_base + BWN_PIO8_RXDATA);
5527		if (totlen & 3) {
5528			v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
5529			data = &(mp[totlen - 1]);
5530			switch (totlen & 3) {
5531			case 3:
5532				*data = (v32 >> 16);
5533				data--;
5534			case 2:
5535				*data = (v32 >> 8);
5536				data--;
5537			case 1:
5538				*data = v32;
5539			}
5540		}
5541	} else {
5542		siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1),
5543		    prq->prq_base + BWN_PIO_RXDATA);
5544		if (totlen & 1) {
5545			v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
5546			mp[totlen - 1] = v16;
5547		}
5548	}
5549
5550	m->m_len = m->m_pkthdr.len = totlen;
5551
5552	bwn_rxeof(prq->prq_mac, m, &rxhdr);
5553
5554	return (1);
5555error:
5556	if (prq->prq_rev >= 8)
5557		bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5558		    BWN_PIO8_RXCTL_DATAREADY);
5559	else
5560		bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY);
5561	return (1);
5562}
5563
5564static int
5565bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc,
5566    struct bwn_dmadesc_meta *meta, int init)
5567{
5568	struct bwn_mac *mac = dr->dr_mac;
5569	struct bwn_dma *dma = &mac->mac_method.dma;
5570	struct bwn_rxhdr4 *hdr;
5571	bus_dmamap_t map;
5572	bus_addr_t paddr;
5573	struct mbuf *m;
5574	int error;
5575
5576	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5577	if (m == NULL) {
5578		error = ENOBUFS;
5579
5580		/*
5581		 * If the NIC is up and running, we need to:
5582		 * - Clear RX buffer's header.
5583		 * - Restore RX descriptor settings.
5584		 */
5585		if (init)
5586			return (error);
5587		else
5588			goto back;
5589	}
5590	m->m_len = m->m_pkthdr.len = MCLBYTES;
5591
5592	bwn_dma_set_redzone(dr, m);
5593
5594	/*
5595	 * Try to load RX buf into temporary DMA map
5596	 */
5597	error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m,
5598	    bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
5599	if (error) {
5600		m_freem(m);
5601
5602		/*
5603		 * See the comment above
5604		 */
5605		if (init)
5606			return (error);
5607		else
5608			goto back;
5609	}
5610
5611	if (!init)
5612		bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
5613	meta->mt_m = m;
5614	meta->mt_paddr = paddr;
5615
5616	/*
5617	 * Swap RX buf's DMA map with the loaded temporary one
5618	 */
5619	map = meta->mt_dmap;
5620	meta->mt_dmap = dr->dr_spare_dmap;
5621	dr->dr_spare_dmap = map;
5622
5623back:
5624	/*
5625	 * Clear RX buf header
5626	 */
5627	hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *);
5628	bzero(hdr, sizeof(*hdr));
5629	bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5630	    BUS_DMASYNC_PREWRITE);
5631
5632	/*
5633	 * Setup RX buf descriptor
5634	 */
5635	dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len -
5636	    sizeof(*hdr), 0, 0, 0);
5637	return (error);
5638}
5639
5640static void
5641bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
5642		 bus_size_t mapsz __unused, int error)
5643{
5644
5645	if (!error) {
5646		KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
5647		*((bus_addr_t *)arg) = seg->ds_addr;
5648	}
5649}
5650
5651static int
5652bwn_hwrate2ieeerate(int rate)
5653{
5654
5655	switch (rate) {
5656	case BWN_CCK_RATE_1MB:
5657		return (2);
5658	case BWN_CCK_RATE_2MB:
5659		return (4);
5660	case BWN_CCK_RATE_5MB:
5661		return (11);
5662	case BWN_CCK_RATE_11MB:
5663		return (22);
5664	case BWN_OFDM_RATE_6MB:
5665		return (12);
5666	case BWN_OFDM_RATE_9MB:
5667		return (18);
5668	case BWN_OFDM_RATE_12MB:
5669		return (24);
5670	case BWN_OFDM_RATE_18MB:
5671		return (36);
5672	case BWN_OFDM_RATE_24MB:
5673		return (48);
5674	case BWN_OFDM_RATE_36MB:
5675		return (72);
5676	case BWN_OFDM_RATE_48MB:
5677		return (96);
5678	case BWN_OFDM_RATE_54MB:
5679		return (108);
5680	default:
5681		printf("Ooops\n");
5682		return (0);
5683	}
5684}
5685
5686/*
5687 * Post process the RX provided RSSI.
5688 *
5689 * Valid for A, B, G, LP PHYs.
5690 */
5691static int8_t
5692bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi,
5693    int ofdm, int adjust_2053, int adjust_2050)
5694{
5695	struct bwn_phy *phy = &mac->mac_phy;
5696	struct bwn_phy_g *gphy = &phy->phy_g;
5697	int tmp;
5698
5699	switch (phy->rf_ver) {
5700	case 0x2050:
5701		if (ofdm) {
5702			tmp = in_rssi;
5703			if (tmp > 127)
5704				tmp -= 256;
5705			tmp = tmp * 73 / 64;
5706			if (adjust_2050)
5707				tmp += 25;
5708			else
5709				tmp -= 3;
5710		} else {
5711			if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev)
5712			    & BWN_BFL_RSSI) {
5713				if (in_rssi > 63)
5714					in_rssi = 63;
5715				tmp = gphy->pg_nrssi_lt[in_rssi];
5716				tmp = (31 - tmp) * -131 / 128 - 57;
5717			} else {
5718				tmp = in_rssi;
5719				tmp = (31 - tmp) * -149 / 128 - 68;
5720			}
5721			if (phy->type == BWN_PHYTYPE_G && adjust_2050)
5722				tmp += 25;
5723		}
5724		break;
5725	case 0x2060:
5726		if (in_rssi > 127)
5727			tmp = in_rssi - 256;
5728		else
5729			tmp = in_rssi;
5730		break;
5731	default:
5732		tmp = in_rssi;
5733		tmp = (tmp - 11) * 103 / 64;
5734		if (adjust_2053)
5735			tmp -= 109;
5736		else
5737			tmp -= 83;
5738	}
5739
5740	return (tmp);
5741}
5742
5743static void
5744bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr)
5745{
5746	const struct bwn_rxhdr4 *rxhdr = _rxhdr;
5747	struct bwn_plcp6 *plcp;
5748	struct bwn_softc *sc = mac->mac_sc;
5749	struct ieee80211_frame_min *wh;
5750	struct ieee80211_node *ni;
5751	struct ieee80211com *ic = &sc->sc_ic;
5752	uint32_t macstat;
5753	int padding, rate, rssi = 0, noise = 0, type;
5754	uint16_t phytype, phystat0, phystat3, chanstat;
5755	unsigned char *mp = mtod(m, unsigned char *);
5756	static int rx_mac_dec_rpt = 0;
5757
5758	BWN_ASSERT_LOCKED(sc);
5759
5760	phystat0 = le16toh(rxhdr->phy_status0);
5761
5762	/*
5763	 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only
5764	 * used for LP-PHY.
5765	 */
5766	phystat3 = le16toh(rxhdr->ps3.lp.phy_status3);
5767
5768	switch (mac->mac_fw.fw_hdr_format) {
5769	case BWN_FW_HDR_351:
5770	case BWN_FW_HDR_410:
5771		macstat = le32toh(rxhdr->ps4.r351.mac_status);
5772		chanstat = le16toh(rxhdr->ps4.r351.channel);
5773		break;
5774	case BWN_FW_HDR_598:
5775		macstat = le32toh(rxhdr->ps4.r598.mac_status);
5776		chanstat = le16toh(rxhdr->ps4.r598.channel);
5777		break;
5778	}
5779
5780
5781	phytype = chanstat & BWN_RX_CHAN_PHYTYPE;
5782
5783	if (macstat & BWN_RX_MAC_FCSERR)
5784		device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n");
5785	if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV))
5786		device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n");
5787	if (macstat & BWN_RX_MAC_DECERR)
5788		goto drop;
5789
5790	padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
5791	if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) {
5792		device_printf(sc->sc_dev, "frame too short (length=%d)\n",
5793		    m->m_pkthdr.len);
5794		goto drop;
5795	}
5796	plcp = (struct bwn_plcp6 *)(mp + padding);
5797	m_adj(m, sizeof(struct bwn_plcp6) + padding);
5798	if (m->m_pkthdr.len < IEEE80211_MIN_LEN) {
5799		device_printf(sc->sc_dev, "frame too short (length=%d)\n",
5800		    m->m_pkthdr.len);
5801		goto drop;
5802	}
5803	wh = mtod(m, struct ieee80211_frame_min *);
5804
5805	if (macstat & BWN_RX_MAC_DEC && rx_mac_dec_rpt++ < 50)
5806		device_printf(sc->sc_dev,
5807		    "RX decryption attempted (old %d keyidx %#x)\n",
5808		    BWN_ISOLDFMT(mac),
5809		    (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT);
5810
5811	if (phystat0 & BWN_RX_PHYST0_OFDM)
5812		rate = bwn_plcp_get_ofdmrate(mac, plcp,
5813		    phytype == BWN_PHYTYPE_A);
5814	else
5815		rate = bwn_plcp_get_cckrate(mac, plcp);
5816	if (rate == -1) {
5817		if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP))
5818			goto drop;
5819	}
5820	sc->sc_rx_rate = bwn_hwrate2ieeerate(rate);
5821
5822	/* rssi/noise */
5823	switch (phytype) {
5824	case BWN_PHYTYPE_A:
5825	case BWN_PHYTYPE_B:
5826	case BWN_PHYTYPE_G:
5827	case BWN_PHYTYPE_LP:
5828		rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi,
5829		    !! (phystat0 & BWN_RX_PHYST0_OFDM),
5830		    !! (phystat0 & BWN_RX_PHYST0_GAINCTL),
5831		    !! (phystat3 & BWN_RX_PHYST3_TRSTATE));
5832		break;
5833	case BWN_PHYTYPE_N:
5834		/* Broadcom has code for min/avg, but always used max */
5835		if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32)
5836			rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2);
5837		else
5838			rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1);
5839#if 0
5840		DPRINTF(mac->mac_sc, BWN_DEBUG_RECV,
5841		    "%s: power0=%d, power1=%d, power2=%d\n",
5842		    __func__,
5843		    rxhdr->phy.n.power0,
5844		    rxhdr->phy.n.power1,
5845		    rxhdr->ps2.n.power2);
5846#endif
5847		break;
5848	default:
5849		/* XXX TODO: implement rssi for other PHYs */
5850		break;
5851	}
5852
5853	/*
5854	 * RSSI here is absolute, not relative to the noise floor.
5855	 */
5856	noise = mac->mac_stats.link_noise;
5857	rssi = rssi - noise;
5858
5859	/* RX radio tap */
5860	if (ieee80211_radiotap_active(ic))
5861		bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise);
5862	m_adj(m, -IEEE80211_CRC_LEN);
5863
5864	BWN_UNLOCK(sc);
5865
5866	ni = ieee80211_find_rxnode(ic, wh);
5867	if (ni != NULL) {
5868		type = ieee80211_input(ni, m, rssi, noise);
5869		ieee80211_free_node(ni);
5870	} else
5871		type = ieee80211_input_all(ic, m, rssi, noise);
5872
5873	BWN_LOCK(sc);
5874	return;
5875drop:
5876	device_printf(sc->sc_dev, "%s: dropped\n", __func__);
5877}
5878
5879static void
5880bwn_dma_handle_txeof(struct bwn_mac *mac,
5881    const struct bwn_txstatus *status)
5882{
5883	struct bwn_dma *dma = &mac->mac_method.dma;
5884	struct bwn_dma_ring *dr;
5885	struct bwn_dmadesc_generic *desc;
5886	struct bwn_dmadesc_meta *meta;
5887	struct bwn_softc *sc = mac->mac_sc;
5888	int slot;
5889	int retrycnt = 0;
5890
5891	BWN_ASSERT_LOCKED(sc);
5892
5893	dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot);
5894	if (dr == NULL) {
5895		device_printf(sc->sc_dev, "failed to parse cookie\n");
5896		return;
5897	}
5898	KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
5899
5900	while (1) {
5901		KASSERT(slot >= 0 && slot < dr->dr_numslots,
5902		    ("%s:%d: fail", __func__, __LINE__));
5903		dr->getdesc(dr, slot, &desc, &meta);
5904
5905		if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
5906			bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap);
5907		else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
5908			bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap);
5909
5910		if (meta->mt_islast) {
5911			KASSERT(meta->mt_m != NULL,
5912			    ("%s:%d: fail", __func__, __LINE__));
5913
5914			/*
5915			 * If we don't get an ACK, then we should log the
5916			 * full framecnt.  That may be 0 if it's a PHY
5917			 * failure, so ensure that gets logged as some
5918			 * retry attempt.
5919			 */
5920			if (status->ack) {
5921				retrycnt = status->framecnt - 1;
5922			} else {
5923				retrycnt = status->framecnt;
5924				if (retrycnt == 0)
5925					retrycnt = 1;
5926			}
5927			ieee80211_ratectl_tx_complete(meta->mt_ni->ni_vap, meta->mt_ni,
5928			    status->ack ?
5929			      IEEE80211_RATECTL_TX_SUCCESS :
5930			      IEEE80211_RATECTL_TX_FAILURE,
5931			    &retrycnt, 0);
5932			ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0);
5933			meta->mt_ni = NULL;
5934			meta->mt_m = NULL;
5935		} else
5936			KASSERT(meta->mt_m == NULL,
5937			    ("%s:%d: fail", __func__, __LINE__));
5938
5939		dr->dr_usedslot--;
5940		if (meta->mt_islast)
5941			break;
5942		slot = bwn_dma_nextslot(dr, slot);
5943	}
5944	sc->sc_watchdog_timer = 0;
5945	if (dr->dr_stop) {
5946		KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME,
5947		    ("%s:%d: fail", __func__, __LINE__));
5948		dr->dr_stop = 0;
5949	}
5950}
5951
5952static void
5953bwn_pio_handle_txeof(struct bwn_mac *mac,
5954    const struct bwn_txstatus *status)
5955{
5956	struct bwn_pio_txqueue *tq;
5957	struct bwn_pio_txpkt *tp = NULL;
5958	struct bwn_softc *sc = mac->mac_sc;
5959	int retrycnt = 0;
5960
5961	BWN_ASSERT_LOCKED(sc);
5962
5963	tq = bwn_pio_parse_cookie(mac, status->cookie, &tp);
5964	if (tq == NULL)
5965		return;
5966
5967	tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
5968	tq->tq_free++;
5969
5970	if (tp->tp_ni != NULL) {
5971		/*
5972		 * Do any tx complete callback.  Note this must
5973		 * be done before releasing the node reference.
5974		 */
5975
5976		/*
5977		 * If we don't get an ACK, then we should log the
5978		 * full framecnt.  That may be 0 if it's a PHY
5979		 * failure, so ensure that gets logged as some
5980		 * retry attempt.
5981		 */
5982		if (status->ack) {
5983			retrycnt = status->framecnt - 1;
5984		} else {
5985			retrycnt = status->framecnt;
5986			if (retrycnt == 0)
5987				retrycnt = 1;
5988		}
5989		ieee80211_ratectl_tx_complete(tp->tp_ni->ni_vap, tp->tp_ni,
5990		    status->ack ?
5991		      IEEE80211_RATECTL_TX_SUCCESS :
5992		      IEEE80211_RATECTL_TX_FAILURE,
5993		    &retrycnt, 0);
5994
5995		if (tp->tp_m->m_flags & M_TXCB)
5996			ieee80211_process_callback(tp->tp_ni, tp->tp_m, 0);
5997		ieee80211_free_node(tp->tp_ni);
5998		tp->tp_ni = NULL;
5999	}
6000	m_freem(tp->tp_m);
6001	tp->tp_m = NULL;
6002	TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
6003
6004	sc->sc_watchdog_timer = 0;
6005}
6006
6007static void
6008bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
6009{
6010	struct bwn_softc *sc = mac->mac_sc;
6011	struct bwn_phy *phy = &mac->mac_phy;
6012	struct ieee80211com *ic = &sc->sc_ic;
6013	unsigned long now;
6014	bwn_txpwr_result_t result;
6015
6016	BWN_GETTIME(now);
6017
6018	if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime))
6019		return;
6020	phy->nexttime = now + 2 * 1000;
6021
6022	if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
6023	    siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306)
6024		return;
6025
6026	if (phy->recalc_txpwr != NULL) {
6027		result = phy->recalc_txpwr(mac,
6028		    (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0);
6029		if (result == BWN_TXPWR_RES_DONE)
6030			return;
6031		KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST,
6032		    ("%s: fail", __func__));
6033		KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__));
6034
6035		ieee80211_runtask(ic, &mac->mac_txpower);
6036	}
6037}
6038
6039static uint16_t
6040bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset)
6041{
6042
6043	return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset));
6044}
6045
6046static uint32_t
6047bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset)
6048{
6049
6050	return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset));
6051}
6052
6053static void
6054bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value)
6055{
6056
6057	BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value);
6058}
6059
6060static void
6061bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value)
6062{
6063
6064	BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value);
6065}
6066
6067static int
6068bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate)
6069{
6070
6071	switch (rate) {
6072	/* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
6073	case 12:
6074		return (BWN_OFDM_RATE_6MB);
6075	case 18:
6076		return (BWN_OFDM_RATE_9MB);
6077	case 24:
6078		return (BWN_OFDM_RATE_12MB);
6079	case 36:
6080		return (BWN_OFDM_RATE_18MB);
6081	case 48:
6082		return (BWN_OFDM_RATE_24MB);
6083	case 72:
6084		return (BWN_OFDM_RATE_36MB);
6085	case 96:
6086		return (BWN_OFDM_RATE_48MB);
6087	case 108:
6088		return (BWN_OFDM_RATE_54MB);
6089	/* CCK rates (NB: not IEEE std, device-specific) */
6090	case 2:
6091		return (BWN_CCK_RATE_1MB);
6092	case 4:
6093		return (BWN_CCK_RATE_2MB);
6094	case 11:
6095		return (BWN_CCK_RATE_5MB);
6096	case 22:
6097		return (BWN_CCK_RATE_11MB);
6098	}
6099
6100	device_printf(sc->sc_dev, "unsupported rate %d\n", rate);
6101	return (BWN_CCK_RATE_1MB);
6102}
6103
6104static uint16_t
6105bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate)
6106{
6107	struct bwn_phy *phy = &mac->mac_phy;
6108	uint16_t control = 0;
6109	uint16_t bw;
6110
6111	/* XXX TODO: this is for LP phy, what about N-PHY, etc? */
6112	bw = BWN_TXH_PHY1_BW_20;
6113
6114	if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) {
6115		control = bw;
6116	} else {
6117		control = bw;
6118		/* Figure out coding rate and modulation */
6119		/* XXX TODO: table-ize, for MCS transmit */
6120		/* Note: this is BWN_*_RATE values */
6121		switch (bitrate) {
6122		case BWN_CCK_RATE_1MB:
6123			control |= 0;
6124			break;
6125		case BWN_CCK_RATE_2MB:
6126			control |= 1;
6127			break;
6128		case BWN_CCK_RATE_5MB:
6129			control |= 2;
6130			break;
6131		case BWN_CCK_RATE_11MB:
6132			control |= 3;
6133			break;
6134		case BWN_OFDM_RATE_6MB:
6135			control |= BWN_TXH_PHY1_CRATE_1_2;
6136			control |= BWN_TXH_PHY1_MODUL_BPSK;
6137			break;
6138		case BWN_OFDM_RATE_9MB:
6139			control |= BWN_TXH_PHY1_CRATE_3_4;
6140			control |= BWN_TXH_PHY1_MODUL_BPSK;
6141			break;
6142		case BWN_OFDM_RATE_12MB:
6143			control |= BWN_TXH_PHY1_CRATE_1_2;
6144			control |= BWN_TXH_PHY1_MODUL_QPSK;
6145			break;
6146		case BWN_OFDM_RATE_18MB:
6147			control |= BWN_TXH_PHY1_CRATE_3_4;
6148			control |= BWN_TXH_PHY1_MODUL_QPSK;
6149			break;
6150		case BWN_OFDM_RATE_24MB:
6151			control |= BWN_TXH_PHY1_CRATE_1_2;
6152			control |= BWN_TXH_PHY1_MODUL_QAM16;
6153			break;
6154		case BWN_OFDM_RATE_36MB:
6155			control |= BWN_TXH_PHY1_CRATE_3_4;
6156			control |= BWN_TXH_PHY1_MODUL_QAM16;
6157			break;
6158		case BWN_OFDM_RATE_48MB:
6159			control |= BWN_TXH_PHY1_CRATE_1_2;
6160			control |= BWN_TXH_PHY1_MODUL_QAM64;
6161			break;
6162		case BWN_OFDM_RATE_54MB:
6163			control |= BWN_TXH_PHY1_CRATE_3_4;
6164			control |= BWN_TXH_PHY1_MODUL_QAM64;
6165			break;
6166		default:
6167			break;
6168		}
6169		control |= BWN_TXH_PHY1_MODE_SISO;
6170	}
6171
6172	return control;
6173}
6174
6175static int
6176bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni,
6177    struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie)
6178{
6179	const struct bwn_phy *phy = &mac->mac_phy;
6180	struct bwn_softc *sc = mac->mac_sc;
6181	struct ieee80211_frame *wh;
6182	struct ieee80211_frame *protwh;
6183	struct ieee80211_frame_cts *cts;
6184	struct ieee80211_frame_rts *rts;
6185	const struct ieee80211_txparam *tp;
6186	struct ieee80211vap *vap = ni->ni_vap;
6187	struct ieee80211com *ic = &sc->sc_ic;
6188	struct mbuf *mprot;
6189	unsigned int len;
6190	uint32_t macctl = 0;
6191	int protdur, rts_rate, rts_rate_fb, ismcast, isshort, rix, type;
6192	uint16_t phyctl = 0;
6193	uint8_t rate, rate_fb;
6194	int fill_phy_ctl1 = 0;
6195
6196	wh = mtod(m, struct ieee80211_frame *);
6197	memset(txhdr, 0, sizeof(*txhdr));
6198
6199	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
6200	ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6201	isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
6202
6203	if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP)
6204	    || (phy->type == BWN_PHYTYPE_HT))
6205		fill_phy_ctl1 = 1;
6206
6207	/*
6208	 * Find TX rate
6209	 */
6210	tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
6211	if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL))
6212		rate = rate_fb = tp->mgmtrate;
6213	else if (ismcast)
6214		rate = rate_fb = tp->mcastrate;
6215	else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
6216		rate = rate_fb = tp->ucastrate;
6217	else {
6218		/* XXX TODO: don't fall back to CCK rates for OFDM */
6219		rix = ieee80211_ratectl_rate(ni, NULL, 0);
6220		rate = ni->ni_txrate;
6221
6222		if (rix > 0)
6223			rate_fb = ni->ni_rates.rs_rates[rix - 1] &
6224			    IEEE80211_RATE_VAL;
6225		else
6226			rate_fb = rate;
6227	}
6228
6229	sc->sc_tx_rate = rate;
6230
6231	/* Note: this maps the select ieee80211 rate to hardware rate */
6232	rate = bwn_ieeerate2hwrate(sc, rate);
6233	rate_fb = bwn_ieeerate2hwrate(sc, rate_fb);
6234
6235	txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) :
6236	    bwn_plcp_getcck(rate);
6237	bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc));
6238	bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN);
6239
6240	/* XXX rate/rate_fb is the hardware rate */
6241	if ((rate_fb == rate) ||
6242	    (*(u_int16_t *)wh->i_dur & htole16(0x8000)) ||
6243	    (*(u_int16_t *)wh->i_dur == htole16(0)))
6244		txhdr->dur_fb = *(u_int16_t *)wh->i_dur;
6245	else
6246		txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt,
6247		    m->m_pkthdr.len, rate, isshort);
6248
6249	/* XXX TX encryption */
6250
6251	switch (mac->mac_fw.fw_hdr_format) {
6252	case BWN_FW_HDR_351:
6253		bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp),
6254		    m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6255		break;
6256	case BWN_FW_HDR_410:
6257		bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp),
6258		    m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6259		break;
6260	case BWN_FW_HDR_598:
6261		bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp),
6262		    m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6263		break;
6264	}
6265
6266	bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb),
6267	    m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb);
6268
6269	txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM :
6270	    BWN_TX_EFT_FB_CCK;
6271	txhdr->chan = phy->chan;
6272	phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM :
6273	    BWN_TX_PHY_ENC_CCK;
6274	/* XXX preamble? obey net80211 */
6275	if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6276	     rate == BWN_CCK_RATE_11MB))
6277		phyctl |= BWN_TX_PHY_SHORTPRMBL;
6278
6279	if (! phy->gmode)
6280		macctl |= BWN_TX_MAC_5GHZ;
6281
6282	/* XXX TX antenna selection */
6283
6284	switch (bwn_antenna_sanitize(mac, 0)) {
6285	case 0:
6286		phyctl |= BWN_TX_PHY_ANT01AUTO;
6287		break;
6288	case 1:
6289		phyctl |= BWN_TX_PHY_ANT0;
6290		break;
6291	case 2:
6292		phyctl |= BWN_TX_PHY_ANT1;
6293		break;
6294	case 3:
6295		phyctl |= BWN_TX_PHY_ANT2;
6296		break;
6297	case 4:
6298		phyctl |= BWN_TX_PHY_ANT3;
6299		break;
6300	default:
6301		KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6302	}
6303
6304	if (!ismcast)
6305		macctl |= BWN_TX_MAC_ACK;
6306
6307	macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU);
6308	if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
6309	    m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
6310		macctl |= BWN_TX_MAC_LONGFRAME;
6311
6312	if (ic->ic_flags & IEEE80211_F_USEPROT) {
6313		/* XXX RTS rate is always 1MB??? */
6314		/* XXX TODO: don't fall back to CCK rates for OFDM */
6315		rts_rate = BWN_CCK_RATE_1MB;
6316		rts_rate_fb = bwn_get_fbrate(rts_rate);
6317
6318		/* XXX 'rate' here is hardware rate now, not the net80211 rate */
6319		protdur = ieee80211_compute_duration(ic->ic_rt,
6320		    m->m_pkthdr.len, rate, isshort) +
6321		    + ieee80211_ack_duration(ic->ic_rt, rate, isshort);
6322
6323		if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
6324
6325			switch (mac->mac_fw.fw_hdr_format) {
6326			case BWN_FW_HDR_351:
6327				cts = (struct ieee80211_frame_cts *)
6328				    txhdr->body.r351.rts_frame;
6329				break;
6330			case BWN_FW_HDR_410:
6331				cts = (struct ieee80211_frame_cts *)
6332				    txhdr->body.r410.rts_frame;
6333				break;
6334			case BWN_FW_HDR_598:
6335				cts = (struct ieee80211_frame_cts *)
6336				    txhdr->body.r598.rts_frame;
6337				break;
6338			}
6339
6340			mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr,
6341			    protdur);
6342			KASSERT(mprot != NULL, ("failed to alloc mbuf\n"));
6343			bcopy(mtod(mprot, uint8_t *), (uint8_t *)cts,
6344			    mprot->m_pkthdr.len);
6345			m_freem(mprot);
6346			macctl |= BWN_TX_MAC_SEND_CTSTOSELF;
6347			len = sizeof(struct ieee80211_frame_cts);
6348		} else {
6349			switch (mac->mac_fw.fw_hdr_format) {
6350			case BWN_FW_HDR_351:
6351				rts = (struct ieee80211_frame_rts *)
6352				    txhdr->body.r351.rts_frame;
6353				break;
6354			case BWN_FW_HDR_410:
6355				rts = (struct ieee80211_frame_rts *)
6356				    txhdr->body.r410.rts_frame;
6357				break;
6358			case BWN_FW_HDR_598:
6359				rts = (struct ieee80211_frame_rts *)
6360				    txhdr->body.r598.rts_frame;
6361				break;
6362			}
6363
6364			/* XXX rate/rate_fb is the hardware rate */
6365			protdur += ieee80211_ack_duration(ic->ic_rt, rate,
6366			    isshort);
6367			mprot = ieee80211_alloc_rts(ic, wh->i_addr1,
6368			    wh->i_addr2, protdur);
6369			KASSERT(mprot != NULL, ("failed to alloc mbuf\n"));
6370			bcopy(mtod(mprot, uint8_t *), (uint8_t *)rts,
6371			    mprot->m_pkthdr.len);
6372			m_freem(mprot);
6373			macctl |= BWN_TX_MAC_SEND_RTSCTS;
6374			len = sizeof(struct ieee80211_frame_rts);
6375		}
6376		len += IEEE80211_CRC_LEN;
6377
6378		switch (mac->mac_fw.fw_hdr_format) {
6379		case BWN_FW_HDR_351:
6380			bwn_plcp_genhdr((struct bwn_plcp4 *)
6381			    &txhdr->body.r351.rts_plcp, len, rts_rate);
6382			break;
6383		case BWN_FW_HDR_410:
6384			bwn_plcp_genhdr((struct bwn_plcp4 *)
6385			    &txhdr->body.r410.rts_plcp, len, rts_rate);
6386			break;
6387		case BWN_FW_HDR_598:
6388			bwn_plcp_genhdr((struct bwn_plcp4 *)
6389			    &txhdr->body.r598.rts_plcp, len, rts_rate);
6390			break;
6391		}
6392
6393		bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len,
6394		    rts_rate_fb);
6395
6396		switch (mac->mac_fw.fw_hdr_format) {
6397		case BWN_FW_HDR_351:
6398			protwh = (struct ieee80211_frame *)
6399			    &txhdr->body.r351.rts_frame;
6400			break;
6401		case BWN_FW_HDR_410:
6402			protwh = (struct ieee80211_frame *)
6403			    &txhdr->body.r410.rts_frame;
6404			break;
6405		case BWN_FW_HDR_598:
6406			protwh = (struct ieee80211_frame *)
6407			    &txhdr->body.r598.rts_frame;
6408			break;
6409		}
6410
6411		txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur;
6412
6413		if (BWN_ISOFDMRATE(rts_rate)) {
6414			txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM;
6415			txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate);
6416		} else {
6417			txhdr->eftypes |= BWN_TX_EFT_RTS_CCK;
6418			txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate);
6419		}
6420		txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ?
6421		    BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK;
6422
6423		if (fill_phy_ctl1) {
6424			txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate));
6425			txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb));
6426		}
6427	}
6428
6429	if (fill_phy_ctl1) {
6430		txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate));
6431		txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb));
6432	}
6433
6434	switch (mac->mac_fw.fw_hdr_format) {
6435	case BWN_FW_HDR_351:
6436		txhdr->body.r351.cookie = htole16(cookie);
6437		break;
6438	case BWN_FW_HDR_410:
6439		txhdr->body.r410.cookie = htole16(cookie);
6440		break;
6441	case BWN_FW_HDR_598:
6442		txhdr->body.r598.cookie = htole16(cookie);
6443		break;
6444	}
6445
6446	txhdr->macctl = htole32(macctl);
6447	txhdr->phyctl = htole16(phyctl);
6448
6449	/*
6450	 * TX radio tap
6451	 */
6452	if (ieee80211_radiotap_active_vap(vap)) {
6453		sc->sc_tx_th.wt_flags = 0;
6454		if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
6455			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6456		if (isshort &&
6457		    (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6458		     rate == BWN_CCK_RATE_11MB))
6459			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6460		sc->sc_tx_th.wt_rate = rate;
6461
6462		ieee80211_radiotap_tx(vap, m);
6463	}
6464
6465	return (0);
6466}
6467
6468static void
6469bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets,
6470    const uint8_t rate)
6471{
6472	uint32_t d, plen;
6473	uint8_t *raw = plcp->o.raw;
6474
6475	if (BWN_ISOFDMRATE(rate)) {
6476		d = bwn_plcp_getofdm(rate);
6477		KASSERT(!(octets & 0xf000),
6478		    ("%s:%d: fail", __func__, __LINE__));
6479		d |= (octets << 5);
6480		plcp->o.data = htole32(d);
6481	} else {
6482		plen = octets * 16 / rate;
6483		if ((octets * 16 % rate) > 0) {
6484			plen++;
6485			if ((rate == BWN_CCK_RATE_11MB)
6486			    && ((octets * 8 % 11) < 4)) {
6487				raw[1] = 0x84;
6488			} else
6489				raw[1] = 0x04;
6490		} else
6491			raw[1] = 0x04;
6492		plcp->o.data |= htole32(plen << 16);
6493		raw[0] = bwn_plcp_getcck(rate);
6494	}
6495}
6496
6497static uint8_t
6498bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
6499{
6500	struct bwn_softc *sc = mac->mac_sc;
6501	uint8_t mask;
6502
6503	if (n == 0)
6504		return (0);
6505	if (mac->mac_phy.gmode)
6506		mask = siba_sprom_get_ant_bg(sc->sc_dev);
6507	else
6508		mask = siba_sprom_get_ant_a(sc->sc_dev);
6509	if (!(mask & (1 << (n - 1))))
6510		return (0);
6511	return (n);
6512}
6513
6514/*
6515 * Return a fallback rate for the given rate.
6516 *
6517 * Note: Don't fall back from OFDM to CCK.
6518 */
6519static uint8_t
6520bwn_get_fbrate(uint8_t bitrate)
6521{
6522	switch (bitrate) {
6523	/* CCK */
6524	case BWN_CCK_RATE_1MB:
6525		return (BWN_CCK_RATE_1MB);
6526	case BWN_CCK_RATE_2MB:
6527		return (BWN_CCK_RATE_1MB);
6528	case BWN_CCK_RATE_5MB:
6529		return (BWN_CCK_RATE_2MB);
6530	case BWN_CCK_RATE_11MB:
6531		return (BWN_CCK_RATE_5MB);
6532
6533	/* OFDM */
6534	case BWN_OFDM_RATE_6MB:
6535		return (BWN_OFDM_RATE_6MB);
6536	case BWN_OFDM_RATE_9MB:
6537		return (BWN_OFDM_RATE_6MB);
6538	case BWN_OFDM_RATE_12MB:
6539		return (BWN_OFDM_RATE_9MB);
6540	case BWN_OFDM_RATE_18MB:
6541		return (BWN_OFDM_RATE_12MB);
6542	case BWN_OFDM_RATE_24MB:
6543		return (BWN_OFDM_RATE_18MB);
6544	case BWN_OFDM_RATE_36MB:
6545		return (BWN_OFDM_RATE_24MB);
6546	case BWN_OFDM_RATE_48MB:
6547		return (BWN_OFDM_RATE_36MB);
6548	case BWN_OFDM_RATE_54MB:
6549		return (BWN_OFDM_RATE_48MB);
6550	}
6551	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6552	return (0);
6553}
6554
6555static uint32_t
6556bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6557    uint32_t ctl, const void *_data, int len)
6558{
6559	struct bwn_softc *sc = mac->mac_sc;
6560	uint32_t value = 0;
6561	const uint8_t *data = _data;
6562
6563	ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 |
6564	    BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
6565	bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6566
6567	siba_write_multi_4(sc->sc_dev, data, (len & ~3),
6568	    tq->tq_base + BWN_PIO8_TXDATA);
6569	if (len & 3) {
6570		ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
6571		    BWN_PIO8_TXCTL_24_31);
6572		data = &(data[len - 1]);
6573		switch (len & 3) {
6574		case 3:
6575			ctl |= BWN_PIO8_TXCTL_16_23;
6576			value |= (uint32_t)(*data) << 16;
6577			data--;
6578		case 2:
6579			ctl |= BWN_PIO8_TXCTL_8_15;
6580			value |= (uint32_t)(*data) << 8;
6581			data--;
6582		case 1:
6583			value |= (uint32_t)(*data);
6584		}
6585		bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6586		bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value);
6587	}
6588
6589	return (ctl);
6590}
6591
6592static void
6593bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6594    uint16_t offset, uint32_t value)
6595{
6596
6597	BWN_WRITE_4(mac, tq->tq_base + offset, value);
6598}
6599
6600static uint16_t
6601bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6602    uint16_t ctl, const void *_data, int len)
6603{
6604	struct bwn_softc *sc = mac->mac_sc;
6605	const uint8_t *data = _data;
6606
6607	ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6608	BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6609
6610	siba_write_multi_2(sc->sc_dev, data, (len & ~1),
6611	    tq->tq_base + BWN_PIO_TXDATA);
6612	if (len & 1) {
6613		ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6614		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6615		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]);
6616	}
6617
6618	return (ctl);
6619}
6620
6621static uint16_t
6622bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6623    uint16_t ctl, struct mbuf *m0)
6624{
6625	int i, j = 0;
6626	uint16_t data = 0;
6627	const uint8_t *buf;
6628	struct mbuf *m = m0;
6629
6630	ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6631	BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6632
6633	for (; m != NULL; m = m->m_next) {
6634		buf = mtod(m, const uint8_t *);
6635		for (i = 0; i < m->m_len; i++) {
6636			if (!((j++) % 2))
6637				data |= buf[i];
6638			else {
6639				data |= (buf[i] << 8);
6640				BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6641				data = 0;
6642			}
6643		}
6644	}
6645	if (m0->m_pkthdr.len % 2) {
6646		ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6647		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6648		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6649	}
6650
6651	return (ctl);
6652}
6653
6654static void
6655bwn_set_slot_time(struct bwn_mac *mac, uint16_t time)
6656{
6657
6658	/* XXX should exit if 5GHz band .. */
6659	if (mac->mac_phy.type != BWN_PHYTYPE_G)
6660		return;
6661
6662	BWN_WRITE_2(mac, 0x684, 510 + time);
6663	/* Disabled in Linux b43, can adversely effect performance */
6664#if 0
6665	bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time);
6666#endif
6667}
6668
6669static struct bwn_dma_ring *
6670bwn_dma_select(struct bwn_mac *mac, uint8_t prio)
6671{
6672
6673	if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
6674		return (mac->mac_method.dma.wme[WME_AC_BE]);
6675
6676	switch (prio) {
6677	case 3:
6678		return (mac->mac_method.dma.wme[WME_AC_VO]);
6679	case 2:
6680		return (mac->mac_method.dma.wme[WME_AC_VI]);
6681	case 0:
6682		return (mac->mac_method.dma.wme[WME_AC_BE]);
6683	case 1:
6684		return (mac->mac_method.dma.wme[WME_AC_BK]);
6685	}
6686	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6687	return (NULL);
6688}
6689
6690static int
6691bwn_dma_getslot(struct bwn_dma_ring *dr)
6692{
6693	int slot;
6694
6695	BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
6696
6697	KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
6698	KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__));
6699	KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__));
6700
6701	slot = bwn_dma_nextslot(dr, dr->dr_curslot);
6702	KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__));
6703	dr->dr_curslot = slot;
6704	dr->dr_usedslot++;
6705
6706	return (slot);
6707}
6708
6709static struct bwn_pio_txqueue *
6710bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie,
6711    struct bwn_pio_txpkt **pack)
6712{
6713	struct bwn_pio *pio = &mac->mac_method.pio;
6714	struct bwn_pio_txqueue *tq = NULL;
6715	unsigned int index;
6716
6717	switch (cookie & 0xf000) {
6718	case 0x1000:
6719		tq = &pio->wme[WME_AC_BK];
6720		break;
6721	case 0x2000:
6722		tq = &pio->wme[WME_AC_BE];
6723		break;
6724	case 0x3000:
6725		tq = &pio->wme[WME_AC_VI];
6726		break;
6727	case 0x4000:
6728		tq = &pio->wme[WME_AC_VO];
6729		break;
6730	case 0x5000:
6731		tq = &pio->mcast;
6732		break;
6733	}
6734	KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__));
6735	if (tq == NULL)
6736		return (NULL);
6737	index = (cookie & 0x0fff);
6738	KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__));
6739	if (index >= N(tq->tq_pkts))
6740		return (NULL);
6741	*pack = &tq->tq_pkts[index];
6742	KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__));
6743	return (tq);
6744}
6745
6746static void
6747bwn_txpwr(void *arg, int npending)
6748{
6749	struct bwn_mac *mac = arg;
6750	struct bwn_softc *sc = mac->mac_sc;
6751
6752	BWN_LOCK(sc);
6753	if (mac && mac->mac_status >= BWN_MAC_STATUS_STARTED &&
6754	    mac->mac_phy.set_txpwr != NULL)
6755		mac->mac_phy.set_txpwr(mac);
6756	BWN_UNLOCK(sc);
6757}
6758
6759static void
6760bwn_task_15s(struct bwn_mac *mac)
6761{
6762	uint16_t reg;
6763
6764	if (mac->mac_fw.opensource) {
6765		reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG);
6766		if (reg) {
6767			bwn_restart(mac, "fw watchdog");
6768			return;
6769		}
6770		bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1);
6771	}
6772	if (mac->mac_phy.task_15s)
6773		mac->mac_phy.task_15s(mac);
6774
6775	mac->mac_phy.txerrors = BWN_TXERROR_MAX;
6776}
6777
6778static void
6779bwn_task_30s(struct bwn_mac *mac)
6780{
6781
6782	if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running)
6783		return;
6784	mac->mac_noise.noi_running = 1;
6785	mac->mac_noise.noi_nsamples = 0;
6786
6787	bwn_noise_gensample(mac);
6788}
6789
6790static void
6791bwn_task_60s(struct bwn_mac *mac)
6792{
6793
6794	if (mac->mac_phy.task_60s)
6795		mac->mac_phy.task_60s(mac);
6796	bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME);
6797}
6798
6799static void
6800bwn_tasks(void *arg)
6801{
6802	struct bwn_mac *mac = arg;
6803	struct bwn_softc *sc = mac->mac_sc;
6804
6805	BWN_ASSERT_LOCKED(sc);
6806	if (mac->mac_status != BWN_MAC_STATUS_STARTED)
6807		return;
6808
6809	if (mac->mac_task_state % 4 == 0)
6810		bwn_task_60s(mac);
6811	if (mac->mac_task_state % 2 == 0)
6812		bwn_task_30s(mac);
6813	bwn_task_15s(mac);
6814
6815	mac->mac_task_state++;
6816	callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
6817}
6818
6819static int
6820bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a)
6821{
6822	struct bwn_softc *sc = mac->mac_sc;
6823
6824	KASSERT(a == 0, ("not support APHY\n"));
6825
6826	switch (plcp->o.raw[0] & 0xf) {
6827	case 0xb:
6828		return (BWN_OFDM_RATE_6MB);
6829	case 0xf:
6830		return (BWN_OFDM_RATE_9MB);
6831	case 0xa:
6832		return (BWN_OFDM_RATE_12MB);
6833	case 0xe:
6834		return (BWN_OFDM_RATE_18MB);
6835	case 0x9:
6836		return (BWN_OFDM_RATE_24MB);
6837	case 0xd:
6838		return (BWN_OFDM_RATE_36MB);
6839	case 0x8:
6840		return (BWN_OFDM_RATE_48MB);
6841	case 0xc:
6842		return (BWN_OFDM_RATE_54MB);
6843	}
6844	device_printf(sc->sc_dev, "incorrect OFDM rate %d\n",
6845	    plcp->o.raw[0] & 0xf);
6846	return (-1);
6847}
6848
6849static int
6850bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp)
6851{
6852	struct bwn_softc *sc = mac->mac_sc;
6853
6854	switch (plcp->o.raw[0]) {
6855	case 0x0a:
6856		return (BWN_CCK_RATE_1MB);
6857	case 0x14:
6858		return (BWN_CCK_RATE_2MB);
6859	case 0x37:
6860		return (BWN_CCK_RATE_5MB);
6861	case 0x6e:
6862		return (BWN_CCK_RATE_11MB);
6863	}
6864	device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]);
6865	return (-1);
6866}
6867
6868static void
6869bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m,
6870    const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate,
6871    int rssi, int noise)
6872{
6873	struct bwn_softc *sc = mac->mac_sc;
6874	const struct ieee80211_frame_min *wh;
6875	uint64_t tsf;
6876	uint16_t low_mactime_now;
6877	uint16_t mt;
6878
6879	if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL)
6880		sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6881
6882	wh = mtod(m, const struct ieee80211_frame_min *);
6883	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
6884		sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
6885
6886	bwn_tsf_read(mac, &tsf);
6887	low_mactime_now = tsf;
6888	tsf = tsf & ~0xffffULL;
6889
6890	switch (mac->mac_fw.fw_hdr_format) {
6891	case BWN_FW_HDR_351:
6892	case BWN_FW_HDR_410:
6893		mt = le16toh(rxhdr->ps4.r351.mac_time);
6894		break;
6895	case BWN_FW_HDR_598:
6896		mt = le16toh(rxhdr->ps4.r598.mac_time);
6897		break;
6898	}
6899
6900	tsf += mt;
6901	if (low_mactime_now < mt)
6902		tsf -= 0x10000;
6903
6904	sc->sc_rx_th.wr_tsf = tsf;
6905	sc->sc_rx_th.wr_rate = rate;
6906	sc->sc_rx_th.wr_antsignal = rssi;
6907	sc->sc_rx_th.wr_antnoise = noise;
6908}
6909
6910static void
6911bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
6912{
6913	uint32_t low, high;
6914
6915	KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3,
6916	    ("%s:%d: fail", __func__, __LINE__));
6917
6918	low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
6919	high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH);
6920	*tsf = high;
6921	*tsf <<= 32;
6922	*tsf |= low;
6923}
6924
6925static int
6926bwn_dma_attach(struct bwn_mac *mac)
6927{
6928	struct bwn_dma *dma = &mac->mac_method.dma;
6929	struct bwn_softc *sc = mac->mac_sc;
6930	bus_addr_t lowaddr = 0;
6931	int error;
6932
6933	if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
6934		return (0);
6935
6936	KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__));
6937
6938	mac->mac_flags |= BWN_MAC_FLAG_DMA;
6939
6940	dma->dmatype = bwn_dma_gettype(mac);
6941	if (dma->dmatype == BWN_DMA_30BIT)
6942		lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT;
6943	else if (dma->dmatype == BWN_DMA_32BIT)
6944		lowaddr = BUS_SPACE_MAXADDR_32BIT;
6945	else
6946		lowaddr = BUS_SPACE_MAXADDR;
6947
6948	/*
6949	 * Create top level DMA tag
6950	 */
6951	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),	/* parent */
6952			       BWN_ALIGN, 0,		/* alignment, bounds */
6953			       lowaddr,			/* lowaddr */
6954			       BUS_SPACE_MAXADDR,	/* highaddr */
6955			       NULL, NULL,		/* filter, filterarg */
6956			       BUS_SPACE_MAXSIZE,	/* maxsize */
6957			       BUS_SPACE_UNRESTRICTED,	/* nsegments */
6958			       BUS_SPACE_MAXSIZE,	/* maxsegsize */
6959			       0,			/* flags */
6960			       NULL, NULL,		/* lockfunc, lockarg */
6961			       &dma->parent_dtag);
6962	if (error) {
6963		device_printf(sc->sc_dev, "can't create parent DMA tag\n");
6964		return (error);
6965	}
6966
6967	/*
6968	 * Create TX/RX mbuf DMA tag
6969	 */
6970	error = bus_dma_tag_create(dma->parent_dtag,
6971				1,
6972				0,
6973				BUS_SPACE_MAXADDR,
6974				BUS_SPACE_MAXADDR,
6975				NULL, NULL,
6976				MCLBYTES,
6977				1,
6978				BUS_SPACE_MAXSIZE_32BIT,
6979				0,
6980				NULL, NULL,
6981				&dma->rxbuf_dtag);
6982	if (error) {
6983		device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
6984		goto fail0;
6985	}
6986	error = bus_dma_tag_create(dma->parent_dtag,
6987				1,
6988				0,
6989				BUS_SPACE_MAXADDR,
6990				BUS_SPACE_MAXADDR,
6991				NULL, NULL,
6992				MCLBYTES,
6993				1,
6994				BUS_SPACE_MAXSIZE_32BIT,
6995				0,
6996				NULL, NULL,
6997				&dma->txbuf_dtag);
6998	if (error) {
6999		device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
7000		goto fail1;
7001	}
7002
7003	dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype);
7004	if (!dma->wme[WME_AC_BK])
7005		goto fail2;
7006
7007	dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype);
7008	if (!dma->wme[WME_AC_BE])
7009		goto fail3;
7010
7011	dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype);
7012	if (!dma->wme[WME_AC_VI])
7013		goto fail4;
7014
7015	dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype);
7016	if (!dma->wme[WME_AC_VO])
7017		goto fail5;
7018
7019	dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype);
7020	if (!dma->mcast)
7021		goto fail6;
7022	dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype);
7023	if (!dma->rx)
7024		goto fail7;
7025
7026	return (error);
7027
7028fail7:	bwn_dma_ringfree(&dma->mcast);
7029fail6:	bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
7030fail5:	bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
7031fail4:	bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
7032fail3:	bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
7033fail2:	bus_dma_tag_destroy(dma->txbuf_dtag);
7034fail1:	bus_dma_tag_destroy(dma->rxbuf_dtag);
7035fail0:	bus_dma_tag_destroy(dma->parent_dtag);
7036	return (error);
7037}
7038
7039static struct bwn_dma_ring *
7040bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status,
7041    uint16_t cookie, int *slot)
7042{
7043	struct bwn_dma *dma = &mac->mac_method.dma;
7044	struct bwn_dma_ring *dr;
7045	struct bwn_softc *sc = mac->mac_sc;
7046
7047	BWN_ASSERT_LOCKED(mac->mac_sc);
7048
7049	switch (cookie & 0xf000) {
7050	case 0x1000:
7051		dr = dma->wme[WME_AC_BK];
7052		break;
7053	case 0x2000:
7054		dr = dma->wme[WME_AC_BE];
7055		break;
7056	case 0x3000:
7057		dr = dma->wme[WME_AC_VI];
7058		break;
7059	case 0x4000:
7060		dr = dma->wme[WME_AC_VO];
7061		break;
7062	case 0x5000:
7063		dr = dma->mcast;
7064		break;
7065	default:
7066		dr = NULL;
7067		KASSERT(0 == 1,
7068		    ("invalid cookie value %d", cookie & 0xf000));
7069	}
7070	*slot = (cookie & 0x0fff);
7071	if (*slot < 0 || *slot >= dr->dr_numslots) {
7072		/*
7073		 * XXX FIXME: sometimes H/W returns TX DONE events duplicately
7074		 * that it occurs events which have same H/W sequence numbers.
7075		 * When it's occurred just prints a WARNING msgs and ignores.
7076		 */
7077		KASSERT(status->seq == dma->lastseq,
7078		    ("%s:%d: fail", __func__, __LINE__));
7079		device_printf(sc->sc_dev,
7080		    "out of slot ranges (0 < %d < %d)\n", *slot,
7081		    dr->dr_numslots);
7082		return (NULL);
7083	}
7084	dma->lastseq = status->seq;
7085	return (dr);
7086}
7087
7088static void
7089bwn_dma_stop(struct bwn_mac *mac)
7090{
7091	struct bwn_dma *dma;
7092
7093	if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
7094		return;
7095	dma = &mac->mac_method.dma;
7096
7097	bwn_dma_ringstop(&dma->rx);
7098	bwn_dma_ringstop(&dma->wme[WME_AC_BK]);
7099	bwn_dma_ringstop(&dma->wme[WME_AC_BE]);
7100	bwn_dma_ringstop(&dma->wme[WME_AC_VI]);
7101	bwn_dma_ringstop(&dma->wme[WME_AC_VO]);
7102	bwn_dma_ringstop(&dma->mcast);
7103}
7104
7105static void
7106bwn_dma_ringstop(struct bwn_dma_ring **dr)
7107{
7108
7109	if (dr == NULL)
7110		return;
7111
7112	bwn_dma_cleanup(*dr);
7113}
7114
7115static void
7116bwn_pio_stop(struct bwn_mac *mac)
7117{
7118	struct bwn_pio *pio;
7119
7120	if (mac->mac_flags & BWN_MAC_FLAG_DMA)
7121		return;
7122	pio = &mac->mac_method.pio;
7123
7124	bwn_destroy_queue_tx(&pio->mcast);
7125	bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]);
7126	bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]);
7127	bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]);
7128	bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
7129}
7130
7131static void
7132bwn_led_attach(struct bwn_mac *mac)
7133{
7134	struct bwn_softc *sc = mac->mac_sc;
7135	const uint8_t *led_act = NULL;
7136	uint16_t val[BWN_LED_MAX];
7137	int i;
7138
7139	sc->sc_led_idle = (2350 * hz) / 1000;
7140	sc->sc_led_blink = 1;
7141
7142	for (i = 0; i < N(bwn_vendor_led_act); ++i) {
7143		if (siba_get_pci_subvendor(sc->sc_dev) ==
7144		    bwn_vendor_led_act[i].vid) {
7145			led_act = bwn_vendor_led_act[i].led_act;
7146			break;
7147		}
7148	}
7149	if (led_act == NULL)
7150		led_act = bwn_default_led_act;
7151
7152	val[0] = siba_sprom_get_gpio0(sc->sc_dev);
7153	val[1] = siba_sprom_get_gpio1(sc->sc_dev);
7154	val[2] = siba_sprom_get_gpio2(sc->sc_dev);
7155	val[3] = siba_sprom_get_gpio3(sc->sc_dev);
7156
7157	for (i = 0; i < BWN_LED_MAX; ++i) {
7158		struct bwn_led *led = &sc->sc_leds[i];
7159
7160		if (val[i] == 0xff) {
7161			led->led_act = led_act[i];
7162		} else {
7163			if (val[i] & BWN_LED_ACT_LOW)
7164				led->led_flags |= BWN_LED_F_ACTLOW;
7165			led->led_act = val[i] & BWN_LED_ACT_MASK;
7166		}
7167		led->led_mask = (1 << i);
7168
7169		if (led->led_act == BWN_LED_ACT_BLINK_SLOW ||
7170		    led->led_act == BWN_LED_ACT_BLINK_POLL ||
7171		    led->led_act == BWN_LED_ACT_BLINK) {
7172			led->led_flags |= BWN_LED_F_BLINK;
7173			if (led->led_act == BWN_LED_ACT_BLINK_POLL)
7174				led->led_flags |= BWN_LED_F_POLLABLE;
7175			else if (led->led_act == BWN_LED_ACT_BLINK_SLOW)
7176				led->led_flags |= BWN_LED_F_SLOW;
7177
7178			if (sc->sc_blink_led == NULL) {
7179				sc->sc_blink_led = led;
7180				if (led->led_flags & BWN_LED_F_SLOW)
7181					BWN_LED_SLOWDOWN(sc->sc_led_idle);
7182			}
7183		}
7184
7185		DPRINTF(sc, BWN_DEBUG_LED,
7186		    "%dth led, act %d, lowact %d\n", i,
7187		    led->led_act, led->led_flags & BWN_LED_F_ACTLOW);
7188	}
7189	callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
7190}
7191
7192static __inline uint16_t
7193bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on)
7194{
7195
7196	if (led->led_flags & BWN_LED_F_ACTLOW)
7197		on = !on;
7198	if (on)
7199		val |= led->led_mask;
7200	else
7201		val &= ~led->led_mask;
7202	return val;
7203}
7204
7205static void
7206bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate)
7207{
7208	struct bwn_softc *sc = mac->mac_sc;
7209	struct ieee80211com *ic = &sc->sc_ic;
7210	uint16_t val;
7211	int i;
7212
7213	if (nstate == IEEE80211_S_INIT) {
7214		callout_stop(&sc->sc_led_blink_ch);
7215		sc->sc_led_blinking = 0;
7216	}
7217
7218	if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0)
7219		return;
7220
7221	val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7222	for (i = 0; i < BWN_LED_MAX; ++i) {
7223		struct bwn_led *led = &sc->sc_leds[i];
7224		int on;
7225
7226		if (led->led_act == BWN_LED_ACT_UNKN ||
7227		    led->led_act == BWN_LED_ACT_NULL)
7228			continue;
7229
7230		if ((led->led_flags & BWN_LED_F_BLINK) &&
7231		    nstate != IEEE80211_S_INIT)
7232			continue;
7233
7234		switch (led->led_act) {
7235		case BWN_LED_ACT_ON:    /* Always on */
7236			on = 1;
7237			break;
7238		case BWN_LED_ACT_OFF:   /* Always off */
7239		case BWN_LED_ACT_5GHZ:  /* TODO: 11A */
7240			on = 0;
7241			break;
7242		default:
7243			on = 1;
7244			switch (nstate) {
7245			case IEEE80211_S_INIT:
7246				on = 0;
7247				break;
7248			case IEEE80211_S_RUN:
7249				if (led->led_act == BWN_LED_ACT_11G &&
7250				    ic->ic_curmode != IEEE80211_MODE_11G)
7251					on = 0;
7252				break;
7253			default:
7254				if (led->led_act == BWN_LED_ACT_ASSOC)
7255					on = 0;
7256				break;
7257			}
7258			break;
7259		}
7260
7261		val = bwn_led_onoff(led, val, on);
7262	}
7263	BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7264}
7265
7266static void
7267bwn_led_event(struct bwn_mac *mac, int event)
7268{
7269	struct bwn_softc *sc = mac->mac_sc;
7270	struct bwn_led *led = sc->sc_blink_led;
7271	int rate;
7272
7273	if (event == BWN_LED_EVENT_POLL) {
7274		if ((led->led_flags & BWN_LED_F_POLLABLE) == 0)
7275			return;
7276		if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
7277			return;
7278	}
7279
7280	sc->sc_led_ticks = ticks;
7281	if (sc->sc_led_blinking)
7282		return;
7283
7284	switch (event) {
7285	case BWN_LED_EVENT_RX:
7286		rate = sc->sc_rx_rate;
7287		break;
7288	case BWN_LED_EVENT_TX:
7289		rate = sc->sc_tx_rate;
7290		break;
7291	case BWN_LED_EVENT_POLL:
7292		rate = 0;
7293		break;
7294	default:
7295		panic("unknown LED event %d\n", event);
7296		break;
7297	}
7298	bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur,
7299	    bwn_led_duration[rate].off_dur);
7300}
7301
7302static void
7303bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur)
7304{
7305	struct bwn_softc *sc = mac->mac_sc;
7306	struct bwn_led *led = sc->sc_blink_led;
7307	uint16_t val;
7308
7309	val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7310	val = bwn_led_onoff(led, val, 1);
7311	BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7312
7313	if (led->led_flags & BWN_LED_F_SLOW) {
7314		BWN_LED_SLOWDOWN(on_dur);
7315		BWN_LED_SLOWDOWN(off_dur);
7316	}
7317
7318	sc->sc_led_blinking = 1;
7319	sc->sc_led_blink_offdur = off_dur;
7320
7321	callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac);
7322}
7323
7324static void
7325bwn_led_blink_next(void *arg)
7326{
7327	struct bwn_mac *mac = arg;
7328	struct bwn_softc *sc = mac->mac_sc;
7329	uint16_t val;
7330
7331	val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7332	val = bwn_led_onoff(sc->sc_blink_led, val, 0);
7333	BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7334
7335	callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
7336	    bwn_led_blink_end, mac);
7337}
7338
7339static void
7340bwn_led_blink_end(void *arg)
7341{
7342	struct bwn_mac *mac = arg;
7343	struct bwn_softc *sc = mac->mac_sc;
7344
7345	sc->sc_led_blinking = 0;
7346}
7347
7348static int
7349bwn_suspend(device_t dev)
7350{
7351	struct bwn_softc *sc = device_get_softc(dev);
7352
7353	BWN_LOCK(sc);
7354	bwn_stop(sc);
7355	BWN_UNLOCK(sc);
7356	return (0);
7357}
7358
7359static int
7360bwn_resume(device_t dev)
7361{
7362	struct bwn_softc *sc = device_get_softc(dev);
7363	int error = EDOOFUS;
7364
7365	BWN_LOCK(sc);
7366	if (sc->sc_ic.ic_nrunning > 0)
7367		error = bwn_init(sc);
7368	BWN_UNLOCK(sc);
7369	if (error == 0)
7370		ieee80211_start_all(&sc->sc_ic);
7371	return (0);
7372}
7373
7374static void
7375bwn_rfswitch(void *arg)
7376{
7377	struct bwn_softc *sc = arg;
7378	struct bwn_mac *mac = sc->sc_curmac;
7379	int cur = 0, prev = 0;
7380
7381	KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED,
7382	    ("%s: invalid MAC status %d", __func__, mac->mac_status));
7383
7384	if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP
7385	    || mac->mac_phy.type == BWN_PHYTYPE_N) {
7386		if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI)
7387			& BWN_RF_HWENABLED_HI_MASK))
7388			cur = 1;
7389	} else {
7390		if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO)
7391		    & BWN_RF_HWENABLED_LO_MASK)
7392			cur = 1;
7393	}
7394
7395	if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)
7396		prev = 1;
7397
7398	DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n",
7399	    __func__, cur, prev);
7400
7401	if (cur != prev) {
7402		if (cur)
7403			mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
7404		else
7405			mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON;
7406
7407		device_printf(sc->sc_dev,
7408		    "status of RF switch is changed to %s\n",
7409		    cur ? "ON" : "OFF");
7410		if (cur != mac->mac_phy.rf_on) {
7411			if (cur)
7412				bwn_rf_turnon(mac);
7413			else
7414				bwn_rf_turnoff(mac);
7415		}
7416	}
7417
7418	callout_schedule(&sc->sc_rfswitch_ch, hz);
7419}
7420
7421static void
7422bwn_sysctl_node(struct bwn_softc *sc)
7423{
7424	device_t dev = sc->sc_dev;
7425	struct bwn_mac *mac;
7426	struct bwn_stats *stats;
7427
7428	/* XXX assume that count of MAC is only 1. */
7429
7430	if ((mac = sc->sc_curmac) == NULL)
7431		return;
7432	stats = &mac->mac_stats;
7433
7434	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7435	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7436	    "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level");
7437	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7438	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7439	    "rts", CTLFLAG_RW, &stats->rts, 0, "RTS");
7440	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7441	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7442	    "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send");
7443
7444#ifdef BWN_DEBUG
7445	SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
7446	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7447	    "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
7448#endif
7449}
7450
7451static device_method_t bwn_methods[] = {
7452	/* Device interface */
7453	DEVMETHOD(device_probe,		bwn_probe),
7454	DEVMETHOD(device_attach,	bwn_attach),
7455	DEVMETHOD(device_detach,	bwn_detach),
7456	DEVMETHOD(device_suspend,	bwn_suspend),
7457	DEVMETHOD(device_resume,	bwn_resume),
7458	DEVMETHOD_END
7459};
7460static driver_t bwn_driver = {
7461	"bwn",
7462	bwn_methods,
7463	sizeof(struct bwn_softc)
7464};
7465static devclass_t bwn_devclass;
7466DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0);
7467MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1);
7468MODULE_DEPEND(bwn, wlan, 1, 1, 1);		/* 802.11 media layer */
7469MODULE_DEPEND(bwn, firmware, 1, 1, 1);		/* firmware support */
7470MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1);
7471MODULE_VERSION(bwn, 1);
7472