if_bwn.c revision 298948
1/*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bwn/if_bwn.c 298948 2016-05-02 22:58:11Z adrian $"); 32 33/* 34 * The Broadcom Wireless LAN controller driver. 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/endian.h> 43#include <sys/errno.h> 44#include <sys/firmware.h> 45#include <sys/lock.h> 46#include <sys/mutex.h> 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <sys/bus.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53 54#include <net/ethernet.h> 55#include <net/if.h> 56#include <net/if_var.h> 57#include <net/if_arp.h> 58#include <net/if_dl.h> 59#include <net/if_llc.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62 63#include <dev/pci/pcivar.h> 64#include <dev/pci/pcireg.h> 65#include <dev/siba/siba_ids.h> 66#include <dev/siba/sibareg.h> 67#include <dev/siba/sibavar.h> 68 69#include <net80211/ieee80211_var.h> 70#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_regdomain.h> 72#include <net80211/ieee80211_phy.h> 73#include <net80211/ieee80211_ratectl.h> 74 75#include <dev/bwn/if_bwnreg.h> 76#include <dev/bwn/if_bwnvar.h> 77 78#include <dev/bwn/if_bwn_debug.h> 79#include <dev/bwn/if_bwn_misc.h> 80#include <dev/bwn/if_bwn_phy_g.h> 81#include <dev/bwn/if_bwn_phy_lp.h> 82 83static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0, 84 "Broadcom driver parameters"); 85 86/* 87 * Tunable & sysctl variables. 88 */ 89 90#ifdef BWN_DEBUG 91static int bwn_debug = 0; 92SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0, 93 "Broadcom debugging printfs"); 94#endif 95 96static int bwn_bfp = 0; /* use "Bad Frames Preemption" */ 97SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0, 98 "uses Bad Frames Preemption"); 99static int bwn_bluetooth = 1; 100SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0, 101 "turns on Bluetooth Coexistence"); 102static int bwn_hwpctl = 0; 103SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0, 104 "uses H/W power control"); 105static int bwn_msi_disable = 0; /* MSI disabled */ 106TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable); 107static int bwn_usedma = 1; 108SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0, 109 "uses DMA"); 110TUNABLE_INT("hw.bwn.usedma", &bwn_usedma); 111static int bwn_wme = 1; 112SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0, 113 "uses WME support"); 114 115static void bwn_attach_pre(struct bwn_softc *); 116static int bwn_attach_post(struct bwn_softc *); 117static void bwn_sprom_bugfixes(device_t); 118static int bwn_init(struct bwn_softc *); 119static void bwn_parent(struct ieee80211com *); 120static void bwn_start(struct bwn_softc *); 121static int bwn_transmit(struct ieee80211com *, struct mbuf *); 122static int bwn_attach_core(struct bwn_mac *); 123static int bwn_phy_getinfo(struct bwn_mac *, int); 124static int bwn_chiptest(struct bwn_mac *); 125static int bwn_setup_channels(struct bwn_mac *, int, int); 126static void bwn_shm_ctlword(struct bwn_mac *, uint16_t, 127 uint16_t); 128static void bwn_addchannels(struct ieee80211_channel [], int, int *, 129 const struct bwn_channelinfo *, int); 130static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 131 const struct ieee80211_bpf_params *); 132static void bwn_updateslot(struct ieee80211com *); 133static void bwn_update_promisc(struct ieee80211com *); 134static void bwn_wme_init(struct bwn_mac *); 135static int bwn_wme_update(struct ieee80211com *); 136static void bwn_wme_clear(struct bwn_softc *); 137static void bwn_wme_load(struct bwn_mac *); 138static void bwn_wme_loadparams(struct bwn_mac *, 139 const struct wmeParams *, uint16_t); 140static void bwn_scan_start(struct ieee80211com *); 141static void bwn_scan_end(struct ieee80211com *); 142static void bwn_set_channel(struct ieee80211com *); 143static struct ieee80211vap *bwn_vap_create(struct ieee80211com *, 144 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 145 const uint8_t [IEEE80211_ADDR_LEN], 146 const uint8_t [IEEE80211_ADDR_LEN]); 147static void bwn_vap_delete(struct ieee80211vap *); 148static void bwn_stop(struct bwn_softc *); 149static int bwn_core_init(struct bwn_mac *); 150static void bwn_core_start(struct bwn_mac *); 151static void bwn_core_exit(struct bwn_mac *); 152static void bwn_bt_disable(struct bwn_mac *); 153static int bwn_chip_init(struct bwn_mac *); 154static void bwn_set_txretry(struct bwn_mac *, int, int); 155static void bwn_rate_init(struct bwn_mac *); 156static void bwn_set_phytxctl(struct bwn_mac *); 157static void bwn_spu_setdelay(struct bwn_mac *, int); 158static void bwn_bt_enable(struct bwn_mac *); 159static void bwn_set_macaddr(struct bwn_mac *); 160static void bwn_crypt_init(struct bwn_mac *); 161static void bwn_chip_exit(struct bwn_mac *); 162static int bwn_fw_fillinfo(struct bwn_mac *); 163static int bwn_fw_loaducode(struct bwn_mac *); 164static int bwn_gpio_init(struct bwn_mac *); 165static int bwn_fw_loadinitvals(struct bwn_mac *); 166static int bwn_phy_init(struct bwn_mac *); 167static void bwn_set_txantenna(struct bwn_mac *, int); 168static void bwn_set_opmode(struct bwn_mac *); 169static void bwn_rate_write(struct bwn_mac *, uint16_t, int); 170static uint8_t bwn_plcp_getcck(const uint8_t); 171static uint8_t bwn_plcp_getofdm(const uint8_t); 172static void bwn_pio_init(struct bwn_mac *); 173static uint16_t bwn_pio_idx2base(struct bwn_mac *, int); 174static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *, 175 int); 176static void bwn_pio_setupqueue_rx(struct bwn_mac *, 177 struct bwn_pio_rxqueue *, int); 178static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *); 179static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *, 180 uint16_t); 181static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *); 182static int bwn_pio_rx(struct bwn_pio_rxqueue *); 183static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *); 184static void bwn_pio_handle_txeof(struct bwn_mac *, 185 const struct bwn_txstatus *); 186static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t); 187static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t); 188static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t, 189 uint16_t); 190static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t, 191 uint32_t); 192static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *, 193 struct mbuf *); 194static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t); 195static uint32_t bwn_pio_write_multi_4(struct bwn_mac *, 196 struct bwn_pio_txqueue *, uint32_t, const void *, int); 197static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *, 198 uint16_t, uint32_t); 199static uint16_t bwn_pio_write_multi_2(struct bwn_mac *, 200 struct bwn_pio_txqueue *, uint16_t, const void *, int); 201static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *, 202 struct bwn_pio_txqueue *, uint16_t, struct mbuf *); 203static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *, 204 uint16_t, struct bwn_pio_txpkt **); 205static void bwn_dma_init(struct bwn_mac *); 206static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t); 207static int bwn_dma_mask2type(uint64_t); 208static uint64_t bwn_dma_mask(struct bwn_mac *); 209static uint16_t bwn_dma_base(int, int); 210static void bwn_dma_ringfree(struct bwn_dma_ring **); 211static void bwn_dma_32_getdesc(struct bwn_dma_ring *, 212 int, struct bwn_dmadesc_generic **, 213 struct bwn_dmadesc_meta **); 214static void bwn_dma_32_setdesc(struct bwn_dma_ring *, 215 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 216 int, int); 217static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int); 218static void bwn_dma_32_suspend(struct bwn_dma_ring *); 219static void bwn_dma_32_resume(struct bwn_dma_ring *); 220static int bwn_dma_32_get_curslot(struct bwn_dma_ring *); 221static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int); 222static void bwn_dma_64_getdesc(struct bwn_dma_ring *, 223 int, struct bwn_dmadesc_generic **, 224 struct bwn_dmadesc_meta **); 225static void bwn_dma_64_setdesc(struct bwn_dma_ring *, 226 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 227 int, int); 228static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int); 229static void bwn_dma_64_suspend(struct bwn_dma_ring *); 230static void bwn_dma_64_resume(struct bwn_dma_ring *); 231static int bwn_dma_64_get_curslot(struct bwn_dma_ring *); 232static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int); 233static int bwn_dma_allocringmemory(struct bwn_dma_ring *); 234static void bwn_dma_setup(struct bwn_dma_ring *); 235static void bwn_dma_free_ringmemory(struct bwn_dma_ring *); 236static void bwn_dma_cleanup(struct bwn_dma_ring *); 237static void bwn_dma_free_descbufs(struct bwn_dma_ring *); 238static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int); 239static void bwn_dma_rx(struct bwn_dma_ring *); 240static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int); 241static void bwn_dma_free_descbuf(struct bwn_dma_ring *, 242 struct bwn_dmadesc_meta *); 243static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *); 244static int bwn_dma_gettype(struct bwn_mac *); 245static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 246static int bwn_dma_freeslot(struct bwn_dma_ring *); 247static int bwn_dma_nextslot(struct bwn_dma_ring *, int); 248static void bwn_dma_rxeof(struct bwn_dma_ring *, int *); 249static int bwn_dma_newbuf(struct bwn_dma_ring *, 250 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *, 251 int); 252static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int, 253 bus_size_t, int); 254static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *); 255static void bwn_dma_handle_txeof(struct bwn_mac *, 256 const struct bwn_txstatus *); 257static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *, 258 struct mbuf *); 259static int bwn_dma_getslot(struct bwn_dma_ring *); 260static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *, 261 uint8_t); 262static int bwn_dma_attach(struct bwn_mac *); 263static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *, 264 int, int, int); 265static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *, 266 const struct bwn_txstatus *, uint16_t, int *); 267static void bwn_dma_free(struct bwn_mac *); 268static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype); 269static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype, 270 const char *, struct bwn_fwfile *); 271static void bwn_release_firmware(struct bwn_mac *); 272static void bwn_do_release_fw(struct bwn_fwfile *); 273static uint16_t bwn_fwcaps_read(struct bwn_mac *); 274static int bwn_fwinitvals_write(struct bwn_mac *, 275 const struct bwn_fwinitvals *, size_t, size_t); 276static uint16_t bwn_ant2phy(int); 277static void bwn_mac_write_bssid(struct bwn_mac *); 278static void bwn_mac_setfilter(struct bwn_mac *, uint16_t, 279 const uint8_t *); 280static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t, 281 const uint8_t *, size_t, const uint8_t *); 282static void bwn_key_macwrite(struct bwn_mac *, uint8_t, 283 const uint8_t *); 284static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t, 285 const uint8_t *); 286static void bwn_phy_exit(struct bwn_mac *); 287static void bwn_core_stop(struct bwn_mac *); 288static int bwn_switch_band(struct bwn_softc *, 289 struct ieee80211_channel *); 290static void bwn_phy_reset(struct bwn_mac *); 291static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 292static void bwn_set_pretbtt(struct bwn_mac *); 293static int bwn_intr(void *); 294static void bwn_intrtask(void *, int); 295static void bwn_restart(struct bwn_mac *, const char *); 296static void bwn_intr_ucode_debug(struct bwn_mac *); 297static void bwn_intr_tbtt_indication(struct bwn_mac *); 298static void bwn_intr_atim_end(struct bwn_mac *); 299static void bwn_intr_beacon(struct bwn_mac *); 300static void bwn_intr_pmq(struct bwn_mac *); 301static void bwn_intr_noise(struct bwn_mac *); 302static void bwn_intr_txeof(struct bwn_mac *); 303static void bwn_hwreset(void *, int); 304static void bwn_handle_fwpanic(struct bwn_mac *); 305static void bwn_load_beacon0(struct bwn_mac *); 306static void bwn_load_beacon1(struct bwn_mac *); 307static uint32_t bwn_jssi_read(struct bwn_mac *); 308static void bwn_noise_gensample(struct bwn_mac *); 309static void bwn_handle_txeof(struct bwn_mac *, 310 const struct bwn_txstatus *); 311static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *); 312static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t); 313static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *, 314 struct mbuf *); 315static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *); 316static int bwn_set_txhdr(struct bwn_mac *, 317 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *, 318 uint16_t); 319static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t, 320 const uint8_t); 321static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t); 322static uint8_t bwn_get_fbrate(uint8_t); 323static void bwn_txpwr(void *, int); 324static void bwn_tasks(void *); 325static void bwn_task_15s(struct bwn_mac *); 326static void bwn_task_30s(struct bwn_mac *); 327static void bwn_task_60s(struct bwn_mac *); 328static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *, 329 uint8_t); 330static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *); 331static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *, 332 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int, 333 int, int); 334static void bwn_tsf_read(struct bwn_mac *, uint64_t *); 335static void bwn_set_slot_time(struct bwn_mac *, uint16_t); 336static void bwn_watchdog(void *); 337static void bwn_dma_stop(struct bwn_mac *); 338static void bwn_pio_stop(struct bwn_mac *); 339static void bwn_dma_ringstop(struct bwn_dma_ring **); 340static void bwn_led_attach(struct bwn_mac *); 341static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state); 342static void bwn_led_event(struct bwn_mac *, int); 343static void bwn_led_blink_start(struct bwn_mac *, int, int); 344static void bwn_led_blink_next(void *); 345static void bwn_led_blink_end(void *); 346static void bwn_rfswitch(void *); 347static void bwn_rf_turnon(struct bwn_mac *); 348static void bwn_rf_turnoff(struct bwn_mac *); 349static void bwn_sysctl_node(struct bwn_softc *); 350 351static struct resource_spec bwn_res_spec_legacy[] = { 352 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 353 { -1, 0, 0 } 354}; 355 356static struct resource_spec bwn_res_spec_msi[] = { 357 { SYS_RES_IRQ, 1, RF_ACTIVE }, 358 { -1, 0, 0 } 359}; 360 361static const struct bwn_channelinfo bwn_chantable_bg = { 362 .channels = { 363 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 }, 364 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 }, 365 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 }, 366 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 }, 367 { 2472, 13, 30 }, { 2484, 14, 30 } }, 368 .nchannels = 14 369}; 370 371static const struct bwn_channelinfo bwn_chantable_a = { 372 .channels = { 373 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 }, 374 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 }, 375 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 }, 376 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 }, 377 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 }, 378 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 }, 379 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 }, 380 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 }, 381 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 }, 382 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 }, 383 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 }, 384 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 }, 385 { 6080, 216, 30 } }, 386 .nchannels = 37 387}; 388 389static const struct bwn_channelinfo bwn_chantable_n = { 390 .channels = { 391 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 }, 392 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 }, 393 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 }, 394 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 }, 395 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 }, 396 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 }, 397 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 }, 398 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 }, 399 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 }, 400 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 }, 401 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 }, 402 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 }, 403 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 }, 404 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 }, 405 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 }, 406 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 }, 407 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 }, 408 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 }, 409 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 }, 410 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 }, 411 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 }, 412 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 }, 413 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 }, 414 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 }, 415 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 }, 416 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 }, 417 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 }, 418 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 }, 419 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 }, 420 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 }, 421 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 }, 422 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 }, 423 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 }, 424 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 }, 425 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 }, 426 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 }, 427 { 6130, 226, 30 }, { 6140, 228, 30 } }, 428 .nchannels = 110 429}; 430 431#define VENDOR_LED_ACT(vendor) \ 432{ \ 433 .vid = PCI_VENDOR_##vendor, \ 434 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \ 435} 436 437static const struct { 438 uint16_t vid; 439 uint8_t led_act[BWN_LED_MAX]; 440} bwn_vendor_led_act[] = { 441 VENDOR_LED_ACT(COMPAQ), 442 VENDOR_LED_ACT(ASUSTEK) 443}; 444 445static const uint8_t bwn_default_led_act[BWN_LED_MAX] = 446 { BWN_VENDOR_LED_ACT_DEFAULT }; 447 448#undef VENDOR_LED_ACT 449 450static const struct { 451 int on_dur; 452 int off_dur; 453} bwn_led_duration[109] = { 454 [0] = { 400, 100 }, 455 [2] = { 150, 75 }, 456 [4] = { 90, 45 }, 457 [11] = { 66, 34 }, 458 [12] = { 53, 26 }, 459 [18] = { 42, 21 }, 460 [22] = { 35, 17 }, 461 [24] = { 32, 16 }, 462 [36] = { 21, 10 }, 463 [48] = { 16, 8 }, 464 [72] = { 11, 5 }, 465 [96] = { 9, 4 }, 466 [108] = { 7, 3 } 467}; 468 469static const uint16_t bwn_wme_shm_offsets[] = { 470 [0] = BWN_WME_BESTEFFORT, 471 [1] = BWN_WME_BACKGROUND, 472 [2] = BWN_WME_VOICE, 473 [3] = BWN_WME_VIDEO, 474}; 475 476static const struct siba_devid bwn_devs[] = { 477 SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"), 478 SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"), 479 SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"), 480 SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"), 481 SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"), 482 SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"), 483 SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"), 484 SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"), 485 SIBA_DEV(BROADCOM, 80211, 16, "Revision 16") 486}; 487 488static int 489bwn_probe(device_t dev) 490{ 491 int i; 492 493 for (i = 0; i < nitems(bwn_devs); i++) { 494 if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor && 495 siba_get_device(dev) == bwn_devs[i].sd_device && 496 siba_get_revid(dev) == bwn_devs[i].sd_rev) 497 return (BUS_PROBE_DEFAULT); 498 } 499 500 return (ENXIO); 501} 502 503static int 504bwn_attach(device_t dev) 505{ 506 struct bwn_mac *mac; 507 struct bwn_softc *sc = device_get_softc(dev); 508 int error, i, msic, reg; 509 510 sc->sc_dev = dev; 511#ifdef BWN_DEBUG 512 sc->sc_debug = bwn_debug; 513#endif 514 515 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) { 516 bwn_attach_pre(sc); 517 bwn_sprom_bugfixes(dev); 518 sc->sc_flags |= BWN_FLAG_ATTACHED; 519 } 520 521 if (!TAILQ_EMPTY(&sc->sc_maclist)) { 522 if (siba_get_pci_device(dev) != 0x4313 && 523 siba_get_pci_device(dev) != 0x431a && 524 siba_get_pci_device(dev) != 0x4321) { 525 device_printf(sc->sc_dev, 526 "skip 802.11 cores\n"); 527 return (ENODEV); 528 } 529 } 530 531 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO); 532 mac->mac_sc = sc; 533 mac->mac_status = BWN_MAC_STATUS_UNINIT; 534 if (bwn_bfp != 0) 535 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP; 536 537 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac); 538 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac); 539 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac); 540 541 error = bwn_attach_core(mac); 542 if (error) 543 goto fail0; 544 bwn_led_attach(mac); 545 546 device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) " 547 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n", 548 siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev), 549 mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev, 550 mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver, 551 mac->mac_phy.rf_rev); 552 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 553 device_printf(sc->sc_dev, "DMA (%d bits)\n", 554 mac->mac_method.dma.dmatype); 555 else 556 device_printf(sc->sc_dev, "PIO\n"); 557 558 /* 559 * setup PCI resources and interrupt. 560 */ 561 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 562 msic = pci_msi_count(dev); 563 if (bootverbose) 564 device_printf(sc->sc_dev, "MSI count : %d\n", msic); 565 } else 566 msic = 0; 567 568 mac->mac_intr_spec = bwn_res_spec_legacy; 569 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) { 570 if (pci_alloc_msi(dev, &msic) == 0) { 571 device_printf(sc->sc_dev, 572 "Using %d MSI messages\n", msic); 573 mac->mac_intr_spec = bwn_res_spec_msi; 574 mac->mac_msi = 1; 575 } 576 } 577 578 error = bus_alloc_resources(dev, mac->mac_intr_spec, 579 mac->mac_res_irq); 580 if (error) { 581 device_printf(sc->sc_dev, 582 "couldn't allocate IRQ resources (%d)\n", error); 583 goto fail1; 584 } 585 586 if (mac->mac_msi == 0) 587 error = bus_setup_intr(dev, mac->mac_res_irq[0], 588 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 589 &mac->mac_intrhand[0]); 590 else { 591 for (i = 0; i < BWN_MSI_MESSAGES; i++) { 592 error = bus_setup_intr(dev, mac->mac_res_irq[i], 593 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 594 &mac->mac_intrhand[i]); 595 if (error != 0) { 596 device_printf(sc->sc_dev, 597 "couldn't setup interrupt (%d)\n", error); 598 break; 599 } 600 } 601 } 602 603 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list); 604 605 /* 606 * calls attach-post routine 607 */ 608 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0) 609 bwn_attach_post(sc); 610 611 return (0); 612fail1: 613 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) 614 pci_release_msi(dev); 615fail0: 616 free(mac, M_DEVBUF); 617 return (error); 618} 619 620static int 621bwn_is_valid_ether_addr(uint8_t *addr) 622{ 623 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 624 625 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) 626 return (FALSE); 627 628 return (TRUE); 629} 630 631static int 632bwn_attach_post(struct bwn_softc *sc) 633{ 634 struct ieee80211com *ic = &sc->sc_ic; 635 636 ic->ic_softc = sc; 637 ic->ic_name = device_get_nameunit(sc->sc_dev); 638 /* XXX not right but it's not used anywhere important */ 639 ic->ic_phytype = IEEE80211_T_OFDM; 640 ic->ic_opmode = IEEE80211_M_STA; 641 ic->ic_caps = 642 IEEE80211_C_STA /* station mode supported */ 643 | IEEE80211_C_MONITOR /* monitor mode */ 644 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 645 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 646 | IEEE80211_C_SHSLOT /* short slot time supported */ 647 | IEEE80211_C_WME /* WME/WMM supported */ 648 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 649 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 650 | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 651 ; 652 653 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */ 654 655 IEEE80211_ADDR_COPY(ic->ic_macaddr, 656 bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ? 657 siba_sprom_get_mac_80211a(sc->sc_dev) : 658 siba_sprom_get_mac_80211bg(sc->sc_dev)); 659 660 /* call MI attach routine. */ 661 ieee80211_ifattach(ic); 662 663 ic->ic_headroom = sizeof(struct bwn_txhdr); 664 665 /* override default methods */ 666 ic->ic_raw_xmit = bwn_raw_xmit; 667 ic->ic_updateslot = bwn_updateslot; 668 ic->ic_update_promisc = bwn_update_promisc; 669 ic->ic_wme.wme_update = bwn_wme_update; 670 ic->ic_scan_start = bwn_scan_start; 671 ic->ic_scan_end = bwn_scan_end; 672 ic->ic_set_channel = bwn_set_channel; 673 ic->ic_vap_create = bwn_vap_create; 674 ic->ic_vap_delete = bwn_vap_delete; 675 ic->ic_transmit = bwn_transmit; 676 ic->ic_parent = bwn_parent; 677 678 ieee80211_radiotap_attach(ic, 679 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 680 BWN_TX_RADIOTAP_PRESENT, 681 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 682 BWN_RX_RADIOTAP_PRESENT); 683 684 bwn_sysctl_node(sc); 685 686 if (bootverbose) 687 ieee80211_announce(ic); 688 return (0); 689} 690 691static void 692bwn_phy_detach(struct bwn_mac *mac) 693{ 694 695 if (mac->mac_phy.detach != NULL) 696 mac->mac_phy.detach(mac); 697} 698 699static int 700bwn_detach(device_t dev) 701{ 702 struct bwn_softc *sc = device_get_softc(dev); 703 struct bwn_mac *mac = sc->sc_curmac; 704 struct ieee80211com *ic = &sc->sc_ic; 705 int i; 706 707 sc->sc_flags |= BWN_FLAG_INVALID; 708 709 if (device_is_attached(sc->sc_dev)) { 710 BWN_LOCK(sc); 711 bwn_stop(sc); 712 BWN_UNLOCK(sc); 713 bwn_dma_free(mac); 714 callout_drain(&sc->sc_led_blink_ch); 715 callout_drain(&sc->sc_rfswitch_ch); 716 callout_drain(&sc->sc_task_ch); 717 callout_drain(&sc->sc_watchdog_ch); 718 bwn_phy_detach(mac); 719 ieee80211_draintask(ic, &mac->mac_hwreset); 720 ieee80211_draintask(ic, &mac->mac_txpower); 721 ieee80211_ifdetach(ic); 722 } 723 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask); 724 taskqueue_free(sc->sc_tq); 725 726 for (i = 0; i < BWN_MSI_MESSAGES; i++) { 727 if (mac->mac_intrhand[i] != NULL) { 728 bus_teardown_intr(dev, mac->mac_res_irq[i], 729 mac->mac_intrhand[i]); 730 mac->mac_intrhand[i] = NULL; 731 } 732 } 733 bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq); 734 if (mac->mac_msi != 0) 735 pci_release_msi(dev); 736 mbufq_drain(&sc->sc_snd); 737 BWN_LOCK_DESTROY(sc); 738 return (0); 739} 740 741static void 742bwn_attach_pre(struct bwn_softc *sc) 743{ 744 745 BWN_LOCK_INIT(sc); 746 TAILQ_INIT(&sc->sc_maclist); 747 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0); 748 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0); 749 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0); 750 mbufq_init(&sc->sc_snd, ifqmaxlen); 751 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT, 752 taskqueue_thread_enqueue, &sc->sc_tq); 753 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 754 "%s taskq", device_get_nameunit(sc->sc_dev)); 755} 756 757static void 758bwn_sprom_bugfixes(device_t dev) 759{ 760#define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \ 761 ((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) && \ 762 (siba_get_pci_device(dev) == _device) && \ 763 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) && \ 764 (siba_get_pci_subdevice(dev) == _subdevice)) 765 766 if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE && 767 siba_get_pci_subdevice(dev) == 0x4e && 768 siba_get_pci_revid(dev) > 0x40) 769 siba_sprom_set_bf_lo(dev, 770 siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL); 771 if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL && 772 siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74) 773 siba_sprom_set_bf_lo(dev, 774 siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST); 775 if (siba_get_type(dev) == SIBA_TYPE_PCI) { 776 if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) || 777 BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) || 778 BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) || 779 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) || 780 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) || 781 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) || 782 BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010)) 783 siba_sprom_set_bf_lo(dev, 784 siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST); 785 } 786#undef BWN_ISDEV 787} 788 789static void 790bwn_parent(struct ieee80211com *ic) 791{ 792 struct bwn_softc *sc = ic->ic_softc; 793 int startall = 0; 794 795 BWN_LOCK(sc); 796 if (ic->ic_nrunning > 0) { 797 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 798 bwn_init(sc); 799 startall = 1; 800 } else 801 bwn_update_promisc(ic); 802 } else if (sc->sc_flags & BWN_FLAG_RUNNING) 803 bwn_stop(sc); 804 BWN_UNLOCK(sc); 805 806 if (startall) 807 ieee80211_start_all(ic); 808} 809 810static int 811bwn_transmit(struct ieee80211com *ic, struct mbuf *m) 812{ 813 struct bwn_softc *sc = ic->ic_softc; 814 int error; 815 816 BWN_LOCK(sc); 817 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 818 BWN_UNLOCK(sc); 819 return (ENXIO); 820 } 821 error = mbufq_enqueue(&sc->sc_snd, m); 822 if (error) { 823 BWN_UNLOCK(sc); 824 return (error); 825 } 826 bwn_start(sc); 827 BWN_UNLOCK(sc); 828 return (0); 829} 830 831static void 832bwn_start(struct bwn_softc *sc) 833{ 834 struct bwn_mac *mac = sc->sc_curmac; 835 struct ieee80211_frame *wh; 836 struct ieee80211_node *ni; 837 struct ieee80211_key *k; 838 struct mbuf *m; 839 840 BWN_ASSERT_LOCKED(sc); 841 842 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL || 843 mac->mac_status < BWN_MAC_STATUS_STARTED) 844 return; 845 846 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 847 if (bwn_tx_isfull(sc, m)) 848 break; 849 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 850 if (ni == NULL) { 851 device_printf(sc->sc_dev, "unexpected NULL ni\n"); 852 m_freem(m); 853 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 854 continue; 855 } 856 wh = mtod(m, struct ieee80211_frame *); 857 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 858 k = ieee80211_crypto_encap(ni, m); 859 if (k == NULL) { 860 if_inc_counter(ni->ni_vap->iv_ifp, 861 IFCOUNTER_OERRORS, 1); 862 ieee80211_free_node(ni); 863 m_freem(m); 864 continue; 865 } 866 } 867 wh = NULL; /* Catch any invalid use */ 868 if (bwn_tx_start(sc, ni, m) != 0) { 869 if (ni != NULL) { 870 if_inc_counter(ni->ni_vap->iv_ifp, 871 IFCOUNTER_OERRORS, 1); 872 ieee80211_free_node(ni); 873 } 874 continue; 875 } 876 sc->sc_watchdog_timer = 5; 877 } 878} 879 880static int 881bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m) 882{ 883 struct bwn_dma_ring *dr; 884 struct bwn_mac *mac = sc->sc_curmac; 885 struct bwn_pio_txqueue *tq; 886 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 887 888 BWN_ASSERT_LOCKED(sc); 889 890 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 891 dr = bwn_dma_select(mac, M_WME_GETAC(m)); 892 if (dr->dr_stop == 1 || 893 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) { 894 dr->dr_stop = 1; 895 goto full; 896 } 897 } else { 898 tq = bwn_pio_select(mac, M_WME_GETAC(m)); 899 if (tq->tq_free == 0 || pktlen > tq->tq_size || 900 pktlen > (tq->tq_size - tq->tq_used)) 901 goto full; 902 } 903 return (0); 904full: 905 mbufq_prepend(&sc->sc_snd, m); 906 return (1); 907} 908 909static int 910bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m) 911{ 912 struct bwn_mac *mac = sc->sc_curmac; 913 int error; 914 915 BWN_ASSERT_LOCKED(sc); 916 917 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) { 918 m_freem(m); 919 return (ENXIO); 920 } 921 922 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ? 923 bwn_dma_tx_start(mac, ni, m) : bwn_pio_tx_start(mac, ni, m); 924 if (error) { 925 m_freem(m); 926 return (error); 927 } 928 return (0); 929} 930 931static int 932bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m) 933{ 934 struct bwn_pio_txpkt *tp; 935 struct bwn_pio_txqueue *tq = bwn_pio_select(mac, M_WME_GETAC(m)); 936 struct bwn_softc *sc = mac->mac_sc; 937 struct bwn_txhdr txhdr; 938 struct mbuf *m_new; 939 uint32_t ctl32; 940 int error; 941 uint16_t ctl16; 942 943 BWN_ASSERT_LOCKED(sc); 944 945 /* XXX TODO send packets after DTIM */ 946 947 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__)); 948 tp = TAILQ_FIRST(&tq->tq_pktlist); 949 tp->tp_ni = ni; 950 tp->tp_m = m; 951 952 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp)); 953 if (error) { 954 device_printf(sc->sc_dev, "tx fail\n"); 955 return (error); 956 } 957 958 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list); 959 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 960 tq->tq_free--; 961 962 if (siba_get_revid(sc->sc_dev) >= 8) { 963 /* 964 * XXX please removes m_defrag(9) 965 */ 966 m_new = m_defrag(m, M_NOWAIT); 967 if (m_new == NULL) { 968 device_printf(sc->sc_dev, 969 "%s: can't defrag TX buffer\n", 970 __func__); 971 return (ENOBUFS); 972 } 973 if (m_new->m_next != NULL) 974 device_printf(sc->sc_dev, 975 "TODO: fragmented packets for PIO\n"); 976 tp->tp_m = m_new; 977 978 /* send HEADER */ 979 ctl32 = bwn_pio_write_multi_4(mac, tq, 980 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) | 981 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF, 982 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 983 /* send BODY */ 984 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32, 985 mtod(m_new, const void *), m_new->m_pkthdr.len); 986 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL, 987 ctl32 | BWN_PIO8_TXCTL_EOF); 988 } else { 989 ctl16 = bwn_pio_write_multi_2(mac, tq, 990 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) | 991 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF, 992 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 993 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m); 994 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, 995 ctl16 | BWN_PIO_TXCTL_EOF); 996 } 997 998 return (0); 999} 1000 1001static struct bwn_pio_txqueue * 1002bwn_pio_select(struct bwn_mac *mac, uint8_t prio) 1003{ 1004 1005 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 1006 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1007 1008 switch (prio) { 1009 case 0: 1010 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1011 case 1: 1012 return (&mac->mac_method.pio.wme[WME_AC_BK]); 1013 case 2: 1014 return (&mac->mac_method.pio.wme[WME_AC_VI]); 1015 case 3: 1016 return (&mac->mac_method.pio.wme[WME_AC_VO]); 1017 } 1018 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1019 return (NULL); 1020} 1021 1022static int 1023bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m) 1024{ 1025#define BWN_GET_TXHDRCACHE(slot) \ 1026 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)]) 1027 struct bwn_dma *dma = &mac->mac_method.dma; 1028 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(m)); 1029 struct bwn_dmadesc_generic *desc; 1030 struct bwn_dmadesc_meta *mt; 1031 struct bwn_softc *sc = mac->mac_sc; 1032 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache; 1033 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot }; 1034 1035 BWN_ASSERT_LOCKED(sc); 1036 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__)); 1037 1038 /* XXX send after DTIM */ 1039 1040 slot = bwn_dma_getslot(dr); 1041 dr->getdesc(dr, slot, &desc, &mt); 1042 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER, 1043 ("%s:%d: fail", __func__, __LINE__)); 1044 1045 error = bwn_set_txhdr(dr->dr_mac, ni, m, 1046 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot), 1047 BWN_DMA_COOKIE(dr, slot)); 1048 if (error) 1049 goto fail; 1050 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap, 1051 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr, 1052 &mt->mt_paddr, BUS_DMA_NOWAIT); 1053 if (error) { 1054 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1055 __func__, error); 1056 goto fail; 1057 } 1058 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap, 1059 BUS_DMASYNC_PREWRITE); 1060 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0); 1061 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1062 BUS_DMASYNC_PREWRITE); 1063 1064 slot = bwn_dma_getslot(dr); 1065 dr->getdesc(dr, slot, &desc, &mt); 1066 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY && 1067 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__)); 1068 mt->mt_m = m; 1069 mt->mt_ni = ni; 1070 1071 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m, 1072 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1073 if (error && error != EFBIG) { 1074 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1075 __func__, error); 1076 goto fail; 1077 } 1078 if (error) { /* error == EFBIG */ 1079 struct mbuf *m_new; 1080 1081 m_new = m_defrag(m, M_NOWAIT); 1082 if (m_new == NULL) { 1083 device_printf(sc->sc_dev, 1084 "%s: can't defrag TX buffer\n", 1085 __func__); 1086 error = ENOBUFS; 1087 goto fail; 1088 } else { 1089 m = m_new; 1090 } 1091 1092 mt->mt_m = m; 1093 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, 1094 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1095 if (error) { 1096 device_printf(sc->sc_dev, 1097 "%s: can't load TX buffer (2) %d\n", 1098 __func__, error); 1099 goto fail; 1100 } 1101 } 1102 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE); 1103 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1); 1104 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1105 BUS_DMASYNC_PREWRITE); 1106 1107 /* XXX send after DTIM */ 1108 1109 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot)); 1110 return (0); 1111fail: 1112 dr->dr_curslot = backup[0]; 1113 dr->dr_usedslot = backup[1]; 1114 return (error); 1115#undef BWN_GET_TXHDRCACHE 1116} 1117 1118static void 1119bwn_watchdog(void *arg) 1120{ 1121 struct bwn_softc *sc = arg; 1122 1123 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) { 1124 device_printf(sc->sc_dev, "device timeout\n"); 1125 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1126 } 1127 callout_schedule(&sc->sc_watchdog_ch, hz); 1128} 1129 1130static int 1131bwn_attach_core(struct bwn_mac *mac) 1132{ 1133 struct bwn_softc *sc = mac->mac_sc; 1134 int error, have_bg = 0, have_a = 0; 1135 uint32_t high; 1136 1137 KASSERT(siba_get_revid(sc->sc_dev) >= 5, 1138 ("unsupported revision %d", siba_get_revid(sc->sc_dev))); 1139 1140 siba_powerup(sc->sc_dev, 0); 1141 1142 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); 1143 bwn_reset_core(mac, 1144 (high & BWN_TGSHIGH_HAVE_2GHZ) ? BWN_TGSLOW_SUPPORT_G : 0); 1145 error = bwn_phy_getinfo(mac, high); 1146 if (error) 1147 goto fail; 1148 1149 have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0; 1150 have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; 1151 if (siba_get_pci_device(sc->sc_dev) != 0x4312 && 1152 siba_get_pci_device(sc->sc_dev) != 0x4319 && 1153 siba_get_pci_device(sc->sc_dev) != 0x4324) { 1154 have_a = have_bg = 0; 1155 if (mac->mac_phy.type == BWN_PHYTYPE_A) 1156 have_a = 1; 1157 else if (mac->mac_phy.type == BWN_PHYTYPE_G || 1158 mac->mac_phy.type == BWN_PHYTYPE_N || 1159 mac->mac_phy.type == BWN_PHYTYPE_LP) 1160 have_bg = 1; 1161 else 1162 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__, 1163 mac->mac_phy.type)); 1164 } 1165 /* XXX turns off PHY A because it's not supported */ 1166 if (mac->mac_phy.type != BWN_PHYTYPE_LP && 1167 mac->mac_phy.type != BWN_PHYTYPE_N) { 1168 have_a = 0; 1169 have_bg = 1; 1170 } 1171 1172 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 1173 mac->mac_phy.attach = bwn_phy_g_attach; 1174 mac->mac_phy.detach = bwn_phy_g_detach; 1175 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw; 1176 mac->mac_phy.init_pre = bwn_phy_g_init_pre; 1177 mac->mac_phy.init = bwn_phy_g_init; 1178 mac->mac_phy.exit = bwn_phy_g_exit; 1179 mac->mac_phy.phy_read = bwn_phy_g_read; 1180 mac->mac_phy.phy_write = bwn_phy_g_write; 1181 mac->mac_phy.rf_read = bwn_phy_g_rf_read; 1182 mac->mac_phy.rf_write = bwn_phy_g_rf_write; 1183 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl; 1184 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff; 1185 mac->mac_phy.switch_analog = bwn_phy_switch_analog; 1186 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel; 1187 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan; 1188 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna; 1189 mac->mac_phy.set_im = bwn_phy_g_im; 1190 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr; 1191 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr; 1192 mac->mac_phy.task_15s = bwn_phy_g_task_15s; 1193 mac->mac_phy.task_60s = bwn_phy_g_task_60s; 1194 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) { 1195 mac->mac_phy.init_pre = bwn_phy_lp_init_pre; 1196 mac->mac_phy.init = bwn_phy_lp_init; 1197 mac->mac_phy.phy_read = bwn_phy_lp_read; 1198 mac->mac_phy.phy_write = bwn_phy_lp_write; 1199 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset; 1200 mac->mac_phy.rf_read = bwn_phy_lp_rf_read; 1201 mac->mac_phy.rf_write = bwn_phy_lp_rf_write; 1202 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff; 1203 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog; 1204 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel; 1205 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan; 1206 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna; 1207 mac->mac_phy.task_60s = bwn_phy_lp_task_60s; 1208 } else { 1209 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n", 1210 mac->mac_phy.type); 1211 error = ENXIO; 1212 goto fail; 1213 } 1214 1215 mac->mac_phy.gmode = have_bg; 1216 if (mac->mac_phy.attach != NULL) { 1217 error = mac->mac_phy.attach(mac); 1218 if (error) { 1219 device_printf(sc->sc_dev, "failed\n"); 1220 goto fail; 1221 } 1222 } 1223 1224 bwn_reset_core(mac, have_bg ? BWN_TGSLOW_SUPPORT_G : 0); 1225 1226 error = bwn_chiptest(mac); 1227 if (error) 1228 goto fail; 1229 error = bwn_setup_channels(mac, have_bg, have_a); 1230 if (error) { 1231 device_printf(sc->sc_dev, "failed to setup channels\n"); 1232 goto fail; 1233 } 1234 1235 if (sc->sc_curmac == NULL) 1236 sc->sc_curmac = mac; 1237 1238 error = bwn_dma_attach(mac); 1239 if (error != 0) { 1240 device_printf(sc->sc_dev, "failed to initialize DMA\n"); 1241 goto fail; 1242 } 1243 1244 mac->mac_phy.switch_analog(mac, 0); 1245 1246 siba_dev_down(sc->sc_dev, 0); 1247fail: 1248 siba_powerdown(sc->sc_dev); 1249 return (error); 1250} 1251 1252void 1253bwn_reset_core(struct bwn_mac *mac, uint32_t flags) 1254{ 1255 struct bwn_softc *sc = mac->mac_sc; 1256 uint32_t low, ctl; 1257 1258 flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET); 1259 1260 siba_dev_up(sc->sc_dev, flags); 1261 DELAY(2000); 1262 1263 low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) & 1264 ~BWN_TGSLOW_PHYRESET; 1265 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); 1266 siba_read_4(sc->sc_dev, SIBA_TGSLOW); 1267 DELAY(1000); 1268 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low & ~SIBA_TGSLOW_FGC); 1269 siba_read_4(sc->sc_dev, SIBA_TGSLOW); 1270 DELAY(1000); 1271 1272 if (mac->mac_phy.switch_analog != NULL) 1273 mac->mac_phy.switch_analog(mac, 1); 1274 1275 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE; 1276 if (flags & BWN_TGSLOW_SUPPORT_G) 1277 ctl |= BWN_MACCTL_GMODE; 1278 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON); 1279} 1280 1281static int 1282bwn_phy_getinfo(struct bwn_mac *mac, int tgshigh) 1283{ 1284 struct bwn_phy *phy = &mac->mac_phy; 1285 struct bwn_softc *sc = mac->mac_sc; 1286 uint32_t tmp; 1287 1288 /* PHY */ 1289 tmp = BWN_READ_2(mac, BWN_PHYVER); 1290 phy->gmode = (tgshigh & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; 1291 phy->rf_on = 1; 1292 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12; 1293 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8; 1294 phy->rev = (tmp & BWN_PHYVER_VERSION); 1295 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) || 1296 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 && 1297 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) || 1298 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) || 1299 (phy->type == BWN_PHYTYPE_N && phy->rev > 4) || 1300 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2)) 1301 goto unsupphy; 1302 1303 /* RADIO */ 1304 if (siba_get_chipid(sc->sc_dev) == 0x4317) { 1305 if (siba_get_chiprev(sc->sc_dev) == 0) 1306 tmp = 0x3205017f; 1307 else if (siba_get_chiprev(sc->sc_dev) == 1) 1308 tmp = 0x4205017f; 1309 else 1310 tmp = 0x5205017f; 1311 } else { 1312 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1313 tmp = BWN_READ_2(mac, BWN_RFDATALO); 1314 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1315 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16; 1316 } 1317 phy->rf_rev = (tmp & 0xf0000000) >> 28; 1318 phy->rf_ver = (tmp & 0x0ffff000) >> 12; 1319 phy->rf_manuf = (tmp & 0x00000fff); 1320 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */ 1321 goto unsupradio; 1322 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 || 1323 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) || 1324 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) || 1325 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) || 1326 (phy->type == BWN_PHYTYPE_N && 1327 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) || 1328 (phy->type == BWN_PHYTYPE_LP && 1329 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063)) 1330 goto unsupradio; 1331 1332 return (0); 1333unsupphy: 1334 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, " 1335 "analog %#x)\n", 1336 phy->type, phy->rev, phy->analog); 1337 return (ENXIO); 1338unsupradio: 1339 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, " 1340 "rev %#x)\n", 1341 phy->rf_manuf, phy->rf_ver, phy->rf_rev); 1342 return (ENXIO); 1343} 1344 1345static int 1346bwn_chiptest(struct bwn_mac *mac) 1347{ 1348#define TESTVAL0 0x55aaaa55 1349#define TESTVAL1 0xaa5555aa 1350 struct bwn_softc *sc = mac->mac_sc; 1351 uint32_t v, backup; 1352 1353 BWN_LOCK(sc); 1354 1355 backup = bwn_shm_read_4(mac, BWN_SHARED, 0); 1356 1357 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0); 1358 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0) 1359 goto error; 1360 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1); 1361 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1) 1362 goto error; 1363 1364 bwn_shm_write_4(mac, BWN_SHARED, 0, backup); 1365 1366 if ((siba_get_revid(sc->sc_dev) >= 3) && 1367 (siba_get_revid(sc->sc_dev) <= 10)) { 1368 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa); 1369 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb); 1370 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb) 1371 goto error; 1372 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc) 1373 goto error; 1374 } 1375 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0); 1376 1377 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE; 1378 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON)) 1379 goto error; 1380 1381 BWN_UNLOCK(sc); 1382 return (0); 1383error: 1384 BWN_UNLOCK(sc); 1385 device_printf(sc->sc_dev, "failed to validate the chipaccess\n"); 1386 return (ENODEV); 1387} 1388 1389#define IEEE80211_CHAN_HTG (IEEE80211_CHAN_HT | IEEE80211_CHAN_G) 1390#define IEEE80211_CHAN_HTA (IEEE80211_CHAN_HT | IEEE80211_CHAN_A) 1391 1392static int 1393bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) 1394{ 1395 struct bwn_softc *sc = mac->mac_sc; 1396 struct ieee80211com *ic = &sc->sc_ic; 1397 1398 memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 1399 ic->ic_nchans = 0; 1400 1401 if (have_bg) 1402 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1403 &ic->ic_nchans, &bwn_chantable_bg, IEEE80211_CHAN_G); 1404 if (mac->mac_phy.type == BWN_PHYTYPE_N) { 1405 if (have_a) 1406 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1407 &ic->ic_nchans, &bwn_chantable_n, 1408 IEEE80211_CHAN_HTA); 1409 } else { 1410 if (have_a) 1411 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1412 &ic->ic_nchans, &bwn_chantable_a, 1413 IEEE80211_CHAN_A); 1414 } 1415 1416 mac->mac_phy.supports_2ghz = have_bg; 1417 mac->mac_phy.supports_5ghz = have_a; 1418 1419 return (ic->ic_nchans == 0 ? ENXIO : 0); 1420} 1421 1422uint32_t 1423bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1424{ 1425 uint32_t ret; 1426 1427 BWN_ASSERT_LOCKED(mac->mac_sc); 1428 1429 if (way == BWN_SHARED) { 1430 KASSERT((offset & 0x0001) == 0, 1431 ("%s:%d warn", __func__, __LINE__)); 1432 if (offset & 0x0003) { 1433 bwn_shm_ctlword(mac, way, offset >> 2); 1434 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1435 ret <<= 16; 1436 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1437 ret |= BWN_READ_2(mac, BWN_SHM_DATA); 1438 goto out; 1439 } 1440 offset >>= 2; 1441 } 1442 bwn_shm_ctlword(mac, way, offset); 1443 ret = BWN_READ_4(mac, BWN_SHM_DATA); 1444out: 1445 return (ret); 1446} 1447 1448uint16_t 1449bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1450{ 1451 uint16_t ret; 1452 1453 BWN_ASSERT_LOCKED(mac->mac_sc); 1454 1455 if (way == BWN_SHARED) { 1456 KASSERT((offset & 0x0001) == 0, 1457 ("%s:%d warn", __func__, __LINE__)); 1458 if (offset & 0x0003) { 1459 bwn_shm_ctlword(mac, way, offset >> 2); 1460 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1461 goto out; 1462 } 1463 offset >>= 2; 1464 } 1465 bwn_shm_ctlword(mac, way, offset); 1466 ret = BWN_READ_2(mac, BWN_SHM_DATA); 1467out: 1468 1469 return (ret); 1470} 1471 1472static void 1473bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way, 1474 uint16_t offset) 1475{ 1476 uint32_t control; 1477 1478 control = way; 1479 control <<= 16; 1480 control |= offset; 1481 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control); 1482} 1483 1484void 1485bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1486 uint32_t value) 1487{ 1488 BWN_ASSERT_LOCKED(mac->mac_sc); 1489 1490 if (way == BWN_SHARED) { 1491 KASSERT((offset & 0x0001) == 0, 1492 ("%s:%d warn", __func__, __LINE__)); 1493 if (offset & 0x0003) { 1494 bwn_shm_ctlword(mac, way, offset >> 2); 1495 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, 1496 (value >> 16) & 0xffff); 1497 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1498 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff); 1499 return; 1500 } 1501 offset >>= 2; 1502 } 1503 bwn_shm_ctlword(mac, way, offset); 1504 BWN_WRITE_4(mac, BWN_SHM_DATA, value); 1505} 1506 1507void 1508bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1509 uint16_t value) 1510{ 1511 BWN_ASSERT_LOCKED(mac->mac_sc); 1512 1513 if (way == BWN_SHARED) { 1514 KASSERT((offset & 0x0001) == 0, 1515 ("%s:%d warn", __func__, __LINE__)); 1516 if (offset & 0x0003) { 1517 bwn_shm_ctlword(mac, way, offset >> 2); 1518 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value); 1519 return; 1520 } 1521 offset >>= 2; 1522 } 1523 bwn_shm_ctlword(mac, way, offset); 1524 BWN_WRITE_2(mac, BWN_SHM_DATA, value); 1525} 1526 1527static void 1528bwn_addchan(struct ieee80211_channel *c, int freq, int flags, int ieee, 1529 int txpow) 1530{ 1531 1532 c->ic_freq = freq; 1533 c->ic_flags = flags; 1534 c->ic_ieee = ieee; 1535 c->ic_minpower = 0; 1536 c->ic_maxpower = 2 * txpow; 1537 c->ic_maxregpower = txpow; 1538} 1539 1540static void 1541bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, 1542 const struct bwn_channelinfo *ci, int flags) 1543{ 1544 struct ieee80211_channel *c; 1545 int i; 1546 1547 c = &chans[*nchans]; 1548 1549 for (i = 0; i < ci->nchannels; i++) { 1550 const struct bwn_channel *hc; 1551 1552 hc = &ci->channels[i]; 1553 if (*nchans >= maxchans) 1554 break; 1555 bwn_addchan(c, hc->freq, flags, hc->ieee, hc->maxTxPow); 1556 c++, (*nchans)++; 1557 if (flags == IEEE80211_CHAN_G || flags == IEEE80211_CHAN_HTG) { 1558 /* g channel have a separate b-only entry */ 1559 if (*nchans >= maxchans) 1560 break; 1561 c[0] = c[-1]; 1562 c[-1].ic_flags = IEEE80211_CHAN_B; 1563 c++, (*nchans)++; 1564 } 1565 if (flags == IEEE80211_CHAN_HTG) { 1566 /* HT g channel have a separate g-only entry */ 1567 if (*nchans >= maxchans) 1568 break; 1569 c[-1].ic_flags = IEEE80211_CHAN_G; 1570 c[0] = c[-1]; 1571 c[0].ic_flags &= ~IEEE80211_CHAN_HT; 1572 c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */ 1573 c++, (*nchans)++; 1574 } 1575 if (flags == IEEE80211_CHAN_HTA) { 1576 /* HT a channel have a separate a-only entry */ 1577 if (*nchans >= maxchans) 1578 break; 1579 c[-1].ic_flags = IEEE80211_CHAN_A; 1580 c[0] = c[-1]; 1581 c[0].ic_flags &= ~IEEE80211_CHAN_HT; 1582 c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */ 1583 c++, (*nchans)++; 1584 } 1585 } 1586} 1587 1588static int 1589bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1590 const struct ieee80211_bpf_params *params) 1591{ 1592 struct ieee80211com *ic = ni->ni_ic; 1593 struct bwn_softc *sc = ic->ic_softc; 1594 struct bwn_mac *mac = sc->sc_curmac; 1595 int error; 1596 1597 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || 1598 mac->mac_status < BWN_MAC_STATUS_STARTED) { 1599 m_freem(m); 1600 return (ENETDOWN); 1601 } 1602 1603 BWN_LOCK(sc); 1604 if (bwn_tx_isfull(sc, m)) { 1605 m_freem(m); 1606 BWN_UNLOCK(sc); 1607 return (ENOBUFS); 1608 } 1609 1610 error = bwn_tx_start(sc, ni, m); 1611 if (error == 0) 1612 sc->sc_watchdog_timer = 5; 1613 BWN_UNLOCK(sc); 1614 return (error); 1615} 1616 1617/* 1618 * Callback from the 802.11 layer to update the slot time 1619 * based on the current setting. We use it to notify the 1620 * firmware of ERP changes and the f/w takes care of things 1621 * like slot time and preamble. 1622 */ 1623static void 1624bwn_updateslot(struct ieee80211com *ic) 1625{ 1626 struct bwn_softc *sc = ic->ic_softc; 1627 struct bwn_mac *mac; 1628 1629 BWN_LOCK(sc); 1630 if (sc->sc_flags & BWN_FLAG_RUNNING) { 1631 mac = (struct bwn_mac *)sc->sc_curmac; 1632 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic)); 1633 } 1634 BWN_UNLOCK(sc); 1635} 1636 1637/* 1638 * Callback from the 802.11 layer after a promiscuous mode change. 1639 * Note this interface does not check the operating mode as this 1640 * is an internal callback and we are expected to honor the current 1641 * state (e.g. this is used for setting the interface in promiscuous 1642 * mode when operating in hostap mode to do ACS). 1643 */ 1644static void 1645bwn_update_promisc(struct ieee80211com *ic) 1646{ 1647 struct bwn_softc *sc = ic->ic_softc; 1648 struct bwn_mac *mac = sc->sc_curmac; 1649 1650 BWN_LOCK(sc); 1651 mac = sc->sc_curmac; 1652 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1653 if (ic->ic_promisc > 0) 1654 sc->sc_filters |= BWN_MACCTL_PROMISC; 1655 else 1656 sc->sc_filters &= ~BWN_MACCTL_PROMISC; 1657 bwn_set_opmode(mac); 1658 } 1659 BWN_UNLOCK(sc); 1660} 1661 1662/* 1663 * Callback from the 802.11 layer to update WME parameters. 1664 */ 1665static int 1666bwn_wme_update(struct ieee80211com *ic) 1667{ 1668 struct bwn_softc *sc = ic->ic_softc; 1669 struct bwn_mac *mac = sc->sc_curmac; 1670 struct wmeParams *wmep; 1671 int i; 1672 1673 BWN_LOCK(sc); 1674 mac = sc->sc_curmac; 1675 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1676 bwn_mac_suspend(mac); 1677 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1678 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 1679 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]); 1680 } 1681 bwn_mac_enable(mac); 1682 } 1683 BWN_UNLOCK(sc); 1684 return (0); 1685} 1686 1687static void 1688bwn_scan_start(struct ieee80211com *ic) 1689{ 1690 struct bwn_softc *sc = ic->ic_softc; 1691 struct bwn_mac *mac; 1692 1693 BWN_LOCK(sc); 1694 mac = sc->sc_curmac; 1695 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1696 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC; 1697 bwn_set_opmode(mac); 1698 /* disable CFP update during scan */ 1699 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE); 1700 } 1701 BWN_UNLOCK(sc); 1702} 1703 1704static void 1705bwn_scan_end(struct ieee80211com *ic) 1706{ 1707 struct bwn_softc *sc = ic->ic_softc; 1708 struct bwn_mac *mac; 1709 1710 BWN_LOCK(sc); 1711 mac = sc->sc_curmac; 1712 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1713 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC; 1714 bwn_set_opmode(mac); 1715 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE); 1716 } 1717 BWN_UNLOCK(sc); 1718} 1719 1720static void 1721bwn_set_channel(struct ieee80211com *ic) 1722{ 1723 struct bwn_softc *sc = ic->ic_softc; 1724 struct bwn_mac *mac = sc->sc_curmac; 1725 struct bwn_phy *phy = &mac->mac_phy; 1726 int chan, error; 1727 1728 BWN_LOCK(sc); 1729 1730 error = bwn_switch_band(sc, ic->ic_curchan); 1731 if (error) 1732 goto fail; 1733 bwn_mac_suspend(mac); 1734 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 1735 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1736 if (chan != phy->chan) 1737 bwn_switch_channel(mac, chan); 1738 1739 /* TX power level */ 1740 if (ic->ic_curchan->ic_maxpower != 0 && 1741 ic->ic_curchan->ic_maxpower != phy->txpower) { 1742 phy->txpower = ic->ic_curchan->ic_maxpower / 2; 1743 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME | 1744 BWN_TXPWR_IGNORE_TSSI); 1745 } 1746 1747 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 1748 if (phy->set_antenna) 1749 phy->set_antenna(mac, BWN_ANT_DEFAULT); 1750 1751 if (sc->sc_rf_enabled != phy->rf_on) { 1752 if (sc->sc_rf_enabled) { 1753 bwn_rf_turnon(mac); 1754 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)) 1755 device_printf(sc->sc_dev, 1756 "please turn on the RF switch\n"); 1757 } else 1758 bwn_rf_turnoff(mac); 1759 } 1760 1761 bwn_mac_enable(mac); 1762 1763fail: 1764 /* 1765 * Setup radio tap channel freq and flags 1766 */ 1767 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1768 htole16(ic->ic_curchan->ic_freq); 1769 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1770 htole16(ic->ic_curchan->ic_flags & 0xffff); 1771 1772 BWN_UNLOCK(sc); 1773} 1774 1775static struct ieee80211vap * 1776bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1777 enum ieee80211_opmode opmode, int flags, 1778 const uint8_t bssid[IEEE80211_ADDR_LEN], 1779 const uint8_t mac[IEEE80211_ADDR_LEN]) 1780{ 1781 struct ieee80211vap *vap; 1782 struct bwn_vap *bvp; 1783 1784 switch (opmode) { 1785 case IEEE80211_M_HOSTAP: 1786 case IEEE80211_M_MBSS: 1787 case IEEE80211_M_STA: 1788 case IEEE80211_M_WDS: 1789 case IEEE80211_M_MONITOR: 1790 case IEEE80211_M_IBSS: 1791 case IEEE80211_M_AHDEMO: 1792 break; 1793 default: 1794 return (NULL); 1795 } 1796 1797 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1798 vap = &bvp->bv_vap; 1799 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1800 /* override with driver methods */ 1801 bvp->bv_newstate = vap->iv_newstate; 1802 vap->iv_newstate = bwn_newstate; 1803 1804 /* override max aid so sta's cannot assoc when we're out of sta id's */ 1805 vap->iv_max_aid = BWN_STAID_MAX; 1806 1807 ieee80211_ratectl_init(vap); 1808 1809 /* complete setup */ 1810 ieee80211_vap_attach(vap, ieee80211_media_change, 1811 ieee80211_media_status, mac); 1812 return (vap); 1813} 1814 1815static void 1816bwn_vap_delete(struct ieee80211vap *vap) 1817{ 1818 struct bwn_vap *bvp = BWN_VAP(vap); 1819 1820 ieee80211_ratectl_deinit(vap); 1821 ieee80211_vap_detach(vap); 1822 free(bvp, M_80211_VAP); 1823} 1824 1825static int 1826bwn_init(struct bwn_softc *sc) 1827{ 1828 struct bwn_mac *mac; 1829 int error; 1830 1831 BWN_ASSERT_LOCKED(sc); 1832 1833 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN); 1834 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP; 1835 sc->sc_filters = 0; 1836 bwn_wme_clear(sc); 1837 sc->sc_beacons[0] = sc->sc_beacons[1] = 0; 1838 sc->sc_rf_enabled = 1; 1839 1840 mac = sc->sc_curmac; 1841 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) { 1842 error = bwn_core_init(mac); 1843 if (error != 0) 1844 return (error); 1845 } 1846 if (mac->mac_status == BWN_MAC_STATUS_INITED) 1847 bwn_core_start(mac); 1848 1849 bwn_set_opmode(mac); 1850 bwn_set_pretbtt(mac); 1851 bwn_spu_setdelay(mac, 0); 1852 bwn_set_macaddr(mac); 1853 1854 sc->sc_flags |= BWN_FLAG_RUNNING; 1855 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc); 1856 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc); 1857 1858 return (0); 1859} 1860 1861static void 1862bwn_stop(struct bwn_softc *sc) 1863{ 1864 struct bwn_mac *mac = sc->sc_curmac; 1865 1866 BWN_ASSERT_LOCKED(sc); 1867 1868 if (mac->mac_status >= BWN_MAC_STATUS_INITED) { 1869 /* XXX FIXME opmode not based on VAP */ 1870 bwn_set_opmode(mac); 1871 bwn_set_macaddr(mac); 1872 } 1873 1874 if (mac->mac_status >= BWN_MAC_STATUS_STARTED) 1875 bwn_core_stop(mac); 1876 1877 callout_stop(&sc->sc_led_blink_ch); 1878 sc->sc_led_blinking = 0; 1879 1880 bwn_core_exit(mac); 1881 sc->sc_rf_enabled = 0; 1882 1883 sc->sc_flags &= ~BWN_FLAG_RUNNING; 1884} 1885 1886static void 1887bwn_wme_clear(struct bwn_softc *sc) 1888{ 1889#define MS(_v, _f) (((_v) & _f) >> _f##_S) 1890 struct wmeParams *p; 1891 unsigned int i; 1892 1893 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 1894 ("%s:%d: fail", __func__, __LINE__)); 1895 1896 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1897 p = &(sc->sc_wmeParams[i]); 1898 1899 switch (bwn_wme_shm_offsets[i]) { 1900 case BWN_WME_VOICE: 1901 p->wmep_txopLimit = 0; 1902 p->wmep_aifsn = 2; 1903 /* XXX FIXME: log2(cwmin) */ 1904 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1905 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 1906 break; 1907 case BWN_WME_VIDEO: 1908 p->wmep_txopLimit = 0; 1909 p->wmep_aifsn = 2; 1910 /* XXX FIXME: log2(cwmin) */ 1911 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1912 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 1913 break; 1914 case BWN_WME_BESTEFFORT: 1915 p->wmep_txopLimit = 0; 1916 p->wmep_aifsn = 3; 1917 /* XXX FIXME: log2(cwmin) */ 1918 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1919 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 1920 break; 1921 case BWN_WME_BACKGROUND: 1922 p->wmep_txopLimit = 0; 1923 p->wmep_aifsn = 7; 1924 /* XXX FIXME: log2(cwmin) */ 1925 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1926 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 1927 break; 1928 default: 1929 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1930 } 1931 } 1932} 1933 1934static int 1935bwn_core_init(struct bwn_mac *mac) 1936{ 1937 struct bwn_softc *sc = mac->mac_sc; 1938 uint64_t hf; 1939 int error; 1940 1941 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 1942 ("%s:%d: fail", __func__, __LINE__)); 1943 1944 siba_powerup(sc->sc_dev, 0); 1945 if (!siba_dev_isup(sc->sc_dev)) 1946 bwn_reset_core(mac, 1947 mac->mac_phy.gmode ? BWN_TGSLOW_SUPPORT_G : 0); 1948 1949 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 1950 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 1951 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0; 1952 BWN_GETTIME(mac->mac_phy.nexttime); 1953 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 1954 bzero(&mac->mac_stats, sizeof(mac->mac_stats)); 1955 mac->mac_stats.link_noise = -95; 1956 mac->mac_reason_intr = 0; 1957 bzero(mac->mac_reason, sizeof(mac->mac_reason)); 1958 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE; 1959#ifdef BWN_DEBUG 1960 if (sc->sc_debug & BWN_DEBUG_XMIT) 1961 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR; 1962#endif 1963 mac->mac_suspended = 1; 1964 mac->mac_task_state = 0; 1965 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise)); 1966 1967 mac->mac_phy.init_pre(mac); 1968 1969 siba_pcicore_intr(sc->sc_dev); 1970 1971 siba_fix_imcfglobug(sc->sc_dev); 1972 bwn_bt_disable(mac); 1973 if (mac->mac_phy.prepare_hw) { 1974 error = mac->mac_phy.prepare_hw(mac); 1975 if (error) 1976 goto fail0; 1977 } 1978 error = bwn_chip_init(mac); 1979 if (error) 1980 goto fail0; 1981 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV, 1982 siba_get_revid(sc->sc_dev)); 1983 hf = bwn_hf_read(mac); 1984 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 1985 hf |= BWN_HF_GPHY_SYM_WORKAROUND; 1986 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) 1987 hf |= BWN_HF_PAGAINBOOST_OFDM_ON; 1988 if (mac->mac_phy.rev == 1) 1989 hf |= BWN_HF_GPHY_DC_CANCELFILTER; 1990 } 1991 if (mac->mac_phy.rf_ver == 0x2050) { 1992 if (mac->mac_phy.rf_rev < 6) 1993 hf |= BWN_HF_FORCE_VCO_RECALC; 1994 if (mac->mac_phy.rf_rev == 6) 1995 hf |= BWN_HF_4318_TSSI; 1996 } 1997 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW) 1998 hf |= BWN_HF_SLOWCLOCK_REQ_OFF; 1999 if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) && 2000 (siba_get_pcicore_revid(sc->sc_dev) <= 10)) 2001 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND; 2002 hf &= ~BWN_HF_SKIP_CFP_UPDATE; 2003 bwn_hf_write(mac, hf); 2004 2005 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 2006 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3); 2007 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2); 2008 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1); 2009 2010 bwn_rate_init(mac); 2011 bwn_set_phytxctl(mac); 2012 2013 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN, 2014 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf); 2015 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff); 2016 2017 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) 2018 bwn_pio_init(mac); 2019 else 2020 bwn_dma_init(mac); 2021 bwn_wme_init(mac); 2022 bwn_spu_setdelay(mac, 1); 2023 bwn_bt_enable(mac); 2024 2025 siba_powerup(sc->sc_dev, 2026 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)); 2027 bwn_set_macaddr(mac); 2028 bwn_crypt_init(mac); 2029 2030 /* XXX LED initializatin */ 2031 2032 mac->mac_status = BWN_MAC_STATUS_INITED; 2033 2034 return (error); 2035 2036fail0: 2037 siba_powerdown(sc->sc_dev); 2038 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2039 ("%s:%d: fail", __func__, __LINE__)); 2040 return (error); 2041} 2042 2043static void 2044bwn_core_start(struct bwn_mac *mac) 2045{ 2046 struct bwn_softc *sc = mac->mac_sc; 2047 uint32_t tmp; 2048 2049 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED, 2050 ("%s:%d: fail", __func__, __LINE__)); 2051 2052 if (siba_get_revid(sc->sc_dev) < 5) 2053 return; 2054 2055 while (1) { 2056 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0); 2057 if (!(tmp & 0x00000001)) 2058 break; 2059 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1); 2060 } 2061 2062 bwn_mac_enable(mac); 2063 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 2064 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 2065 2066 mac->mac_status = BWN_MAC_STATUS_STARTED; 2067} 2068 2069static void 2070bwn_core_exit(struct bwn_mac *mac) 2071{ 2072 struct bwn_softc *sc = mac->mac_sc; 2073 uint32_t macctl; 2074 2075 BWN_ASSERT_LOCKED(mac->mac_sc); 2076 2077 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED, 2078 ("%s:%d: fail", __func__, __LINE__)); 2079 2080 if (mac->mac_status != BWN_MAC_STATUS_INITED) 2081 return; 2082 mac->mac_status = BWN_MAC_STATUS_UNINIT; 2083 2084 macctl = BWN_READ_4(mac, BWN_MACCTL); 2085 macctl &= ~BWN_MACCTL_MCODE_RUN; 2086 macctl |= BWN_MACCTL_MCODE_JMP0; 2087 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2088 2089 bwn_dma_stop(mac); 2090 bwn_pio_stop(mac); 2091 bwn_chip_exit(mac); 2092 mac->mac_phy.switch_analog(mac, 0); 2093 siba_dev_down(sc->sc_dev, 0); 2094 siba_powerdown(sc->sc_dev); 2095} 2096 2097static void 2098bwn_bt_disable(struct bwn_mac *mac) 2099{ 2100 struct bwn_softc *sc = mac->mac_sc; 2101 2102 (void)sc; 2103 /* XXX do nothing yet */ 2104} 2105 2106static int 2107bwn_chip_init(struct bwn_mac *mac) 2108{ 2109 struct bwn_softc *sc = mac->mac_sc; 2110 struct bwn_phy *phy = &mac->mac_phy; 2111 uint32_t macctl; 2112 int error; 2113 2114 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA; 2115 if (phy->gmode) 2116 macctl |= BWN_MACCTL_GMODE; 2117 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2118 2119 error = bwn_fw_fillinfo(mac); 2120 if (error) 2121 return (error); 2122 error = bwn_fw_loaducode(mac); 2123 if (error) 2124 return (error); 2125 2126 error = bwn_gpio_init(mac); 2127 if (error) 2128 return (error); 2129 2130 error = bwn_fw_loadinitvals(mac); 2131 if (error) { 2132 siba_gpio_set(sc->sc_dev, 0); 2133 return (error); 2134 } 2135 phy->switch_analog(mac, 1); 2136 error = bwn_phy_init(mac); 2137 if (error) { 2138 siba_gpio_set(sc->sc_dev, 0); 2139 return (error); 2140 } 2141 if (phy->set_im) 2142 phy->set_im(mac, BWN_IMMODE_NONE); 2143 if (phy->set_antenna) 2144 phy->set_antenna(mac, BWN_ANT_DEFAULT); 2145 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 2146 2147 if (phy->type == BWN_PHYTYPE_B) 2148 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004); 2149 BWN_WRITE_4(mac, 0x0100, 0x01000000); 2150 if (siba_get_revid(sc->sc_dev) < 5) 2151 BWN_WRITE_4(mac, 0x010c, 0x01000000); 2152 2153 BWN_WRITE_4(mac, BWN_MACCTL, 2154 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA); 2155 BWN_WRITE_4(mac, BWN_MACCTL, 2156 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA); 2157 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000); 2158 2159 bwn_set_opmode(mac); 2160 if (siba_get_revid(sc->sc_dev) < 3) { 2161 BWN_WRITE_2(mac, 0x060e, 0x0000); 2162 BWN_WRITE_2(mac, 0x0610, 0x8000); 2163 BWN_WRITE_2(mac, 0x0604, 0x0000); 2164 BWN_WRITE_2(mac, 0x0606, 0x0200); 2165 } else { 2166 BWN_WRITE_4(mac, 0x0188, 0x80000000); 2167 BWN_WRITE_4(mac, 0x018c, 0x02000000); 2168 } 2169 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000); 2170 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00); 2171 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00); 2172 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00); 2173 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00); 2174 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00); 2175 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00); 2176 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 2177 siba_read_4(sc->sc_dev, SIBA_TGSLOW) | 0x00100000); 2178 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev)); 2179 return (error); 2180} 2181 2182/* read hostflags */ 2183uint64_t 2184bwn_hf_read(struct bwn_mac *mac) 2185{ 2186 uint64_t ret; 2187 2188 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI); 2189 ret <<= 16; 2190 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI); 2191 ret <<= 16; 2192 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO); 2193 return (ret); 2194} 2195 2196void 2197bwn_hf_write(struct bwn_mac *mac, uint64_t value) 2198{ 2199 2200 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO, 2201 (value & 0x00000000ffffull)); 2202 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI, 2203 (value & 0x0000ffff0000ull) >> 16); 2204 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI, 2205 (value & 0xffff00000000ULL) >> 32); 2206} 2207 2208static void 2209bwn_set_txretry(struct bwn_mac *mac, int s, int l) 2210{ 2211 2212 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf)); 2213 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf)); 2214} 2215 2216static void 2217bwn_rate_init(struct bwn_mac *mac) 2218{ 2219 2220 switch (mac->mac_phy.type) { 2221 case BWN_PHYTYPE_A: 2222 case BWN_PHYTYPE_G: 2223 case BWN_PHYTYPE_LP: 2224 case BWN_PHYTYPE_N: 2225 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1); 2226 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1); 2227 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1); 2228 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1); 2229 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1); 2230 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1); 2231 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1); 2232 if (mac->mac_phy.type == BWN_PHYTYPE_A) 2233 break; 2234 /* FALLTHROUGH */ 2235 case BWN_PHYTYPE_B: 2236 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0); 2237 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0); 2238 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0); 2239 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0); 2240 break; 2241 default: 2242 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2243 } 2244} 2245 2246static void 2247bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm) 2248{ 2249 uint16_t offset; 2250 2251 if (ofdm) { 2252 offset = 0x480; 2253 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2; 2254 } else { 2255 offset = 0x4c0; 2256 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2; 2257 } 2258 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20, 2259 bwn_shm_read_2(mac, BWN_SHARED, offset)); 2260} 2261 2262static uint8_t 2263bwn_plcp_getcck(const uint8_t bitrate) 2264{ 2265 2266 switch (bitrate) { 2267 case BWN_CCK_RATE_1MB: 2268 return (0x0a); 2269 case BWN_CCK_RATE_2MB: 2270 return (0x14); 2271 case BWN_CCK_RATE_5MB: 2272 return (0x37); 2273 case BWN_CCK_RATE_11MB: 2274 return (0x6e); 2275 } 2276 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2277 return (0); 2278} 2279 2280static uint8_t 2281bwn_plcp_getofdm(const uint8_t bitrate) 2282{ 2283 2284 switch (bitrate) { 2285 case BWN_OFDM_RATE_6MB: 2286 return (0xb); 2287 case BWN_OFDM_RATE_9MB: 2288 return (0xf); 2289 case BWN_OFDM_RATE_12MB: 2290 return (0xa); 2291 case BWN_OFDM_RATE_18MB: 2292 return (0xe); 2293 case BWN_OFDM_RATE_24MB: 2294 return (0x9); 2295 case BWN_OFDM_RATE_36MB: 2296 return (0xd); 2297 case BWN_OFDM_RATE_48MB: 2298 return (0x8); 2299 case BWN_OFDM_RATE_54MB: 2300 return (0xc); 2301 } 2302 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2303 return (0); 2304} 2305 2306static void 2307bwn_set_phytxctl(struct bwn_mac *mac) 2308{ 2309 uint16_t ctl; 2310 2311 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO | 2312 BWN_TX_PHY_TXPWR); 2313 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl); 2314 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl); 2315 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl); 2316} 2317 2318static void 2319bwn_pio_init(struct bwn_mac *mac) 2320{ 2321 struct bwn_pio *pio = &mac->mac_method.pio; 2322 2323 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) 2324 & ~BWN_MACCTL_BIGENDIAN); 2325 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0); 2326 2327 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0); 2328 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1); 2329 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2); 2330 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3); 2331 bwn_pio_set_txqueue(mac, &pio->mcast, 4); 2332 bwn_pio_setupqueue_rx(mac, &pio->rx, 0); 2333} 2334 2335static void 2336bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2337 int index) 2338{ 2339 struct bwn_pio_txpkt *tp; 2340 struct bwn_softc *sc = mac->mac_sc; 2341 unsigned int i; 2342 2343 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac); 2344 tq->tq_index = index; 2345 2346 tq->tq_free = BWN_PIO_MAX_TXPACKETS; 2347 if (siba_get_revid(sc->sc_dev) >= 8) 2348 tq->tq_size = 1920; 2349 else { 2350 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE); 2351 tq->tq_size -= 80; 2352 } 2353 2354 TAILQ_INIT(&tq->tq_pktlist); 2355 for (i = 0; i < N(tq->tq_pkts); i++) { 2356 tp = &(tq->tq_pkts[i]); 2357 tp->tp_index = i; 2358 tp->tp_queue = tq; 2359 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 2360 } 2361} 2362 2363static uint16_t 2364bwn_pio_idx2base(struct bwn_mac *mac, int index) 2365{ 2366 struct bwn_softc *sc = mac->mac_sc; 2367 static const uint16_t bases[] = { 2368 BWN_PIO_BASE0, 2369 BWN_PIO_BASE1, 2370 BWN_PIO_BASE2, 2371 BWN_PIO_BASE3, 2372 BWN_PIO_BASE4, 2373 BWN_PIO_BASE5, 2374 BWN_PIO_BASE6, 2375 BWN_PIO_BASE7, 2376 }; 2377 static const uint16_t bases_rev11[] = { 2378 BWN_PIO11_BASE0, 2379 BWN_PIO11_BASE1, 2380 BWN_PIO11_BASE2, 2381 BWN_PIO11_BASE3, 2382 BWN_PIO11_BASE4, 2383 BWN_PIO11_BASE5, 2384 }; 2385 2386 if (siba_get_revid(sc->sc_dev) >= 11) { 2387 if (index >= N(bases_rev11)) 2388 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2389 return (bases_rev11[index]); 2390 } 2391 if (index >= N(bases)) 2392 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2393 return (bases[index]); 2394} 2395 2396static void 2397bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq, 2398 int index) 2399{ 2400 struct bwn_softc *sc = mac->mac_sc; 2401 2402 prq->prq_mac = mac; 2403 prq->prq_rev = siba_get_revid(sc->sc_dev); 2404 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac); 2405 bwn_dma_rxdirectfifo(mac, index, 1); 2406} 2407 2408static void 2409bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq) 2410{ 2411 if (tq == NULL) 2412 return; 2413 bwn_pio_cancel_tx_packets(tq); 2414} 2415 2416static void 2417bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio) 2418{ 2419 2420 bwn_destroy_pioqueue_tx(pio); 2421} 2422 2423static uint16_t 2424bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2425 uint16_t offset) 2426{ 2427 2428 return (BWN_READ_2(mac, tq->tq_base + offset)); 2429} 2430 2431static void 2432bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable) 2433{ 2434 uint32_t ctl; 2435 int type; 2436 uint16_t base; 2437 2438 type = bwn_dma_mask2type(bwn_dma_mask(mac)); 2439 base = bwn_dma_base(type, idx); 2440 if (type == BWN_DMA_64BIT) { 2441 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL); 2442 ctl &= ~BWN_DMA64_RXDIRECTFIFO; 2443 if (enable) 2444 ctl |= BWN_DMA64_RXDIRECTFIFO; 2445 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl); 2446 } else { 2447 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL); 2448 ctl &= ~BWN_DMA32_RXDIRECTFIFO; 2449 if (enable) 2450 ctl |= BWN_DMA32_RXDIRECTFIFO; 2451 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl); 2452 } 2453} 2454 2455static uint64_t 2456bwn_dma_mask(struct bwn_mac *mac) 2457{ 2458 uint32_t tmp; 2459 uint16_t base; 2460 2461 tmp = BWN_READ_4(mac, SIBA_TGSHIGH); 2462 if (tmp & SIBA_TGSHIGH_DMA64) 2463 return (BWN_DMA_BIT_MASK(64)); 2464 base = bwn_dma_base(0, 0); 2465 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); 2466 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 2467 if (tmp & BWN_DMA32_TXADDREXT_MASK) 2468 return (BWN_DMA_BIT_MASK(32)); 2469 2470 return (BWN_DMA_BIT_MASK(30)); 2471} 2472 2473static int 2474bwn_dma_mask2type(uint64_t dmamask) 2475{ 2476 2477 if (dmamask == BWN_DMA_BIT_MASK(30)) 2478 return (BWN_DMA_30BIT); 2479 if (dmamask == BWN_DMA_BIT_MASK(32)) 2480 return (BWN_DMA_32BIT); 2481 if (dmamask == BWN_DMA_BIT_MASK(64)) 2482 return (BWN_DMA_64BIT); 2483 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2484 return (BWN_DMA_30BIT); 2485} 2486 2487static void 2488bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq) 2489{ 2490 struct bwn_pio_txpkt *tp; 2491 unsigned int i; 2492 2493 for (i = 0; i < N(tq->tq_pkts); i++) { 2494 tp = &(tq->tq_pkts[i]); 2495 if (tp->tp_m) { 2496 m_freem(tp->tp_m); 2497 tp->tp_m = NULL; 2498 } 2499 } 2500} 2501 2502static uint16_t 2503bwn_dma_base(int type, int controller_idx) 2504{ 2505 static const uint16_t map64[] = { 2506 BWN_DMA64_BASE0, 2507 BWN_DMA64_BASE1, 2508 BWN_DMA64_BASE2, 2509 BWN_DMA64_BASE3, 2510 BWN_DMA64_BASE4, 2511 BWN_DMA64_BASE5, 2512 }; 2513 static const uint16_t map32[] = { 2514 BWN_DMA32_BASE0, 2515 BWN_DMA32_BASE1, 2516 BWN_DMA32_BASE2, 2517 BWN_DMA32_BASE3, 2518 BWN_DMA32_BASE4, 2519 BWN_DMA32_BASE5, 2520 }; 2521 2522 if (type == BWN_DMA_64BIT) { 2523 KASSERT(controller_idx >= 0 && controller_idx < N(map64), 2524 ("%s:%d: fail", __func__, __LINE__)); 2525 return (map64[controller_idx]); 2526 } 2527 KASSERT(controller_idx >= 0 && controller_idx < N(map32), 2528 ("%s:%d: fail", __func__, __LINE__)); 2529 return (map32[controller_idx]); 2530} 2531 2532static void 2533bwn_dma_init(struct bwn_mac *mac) 2534{ 2535 struct bwn_dma *dma = &mac->mac_method.dma; 2536 2537 /* setup TX DMA channels. */ 2538 bwn_dma_setup(dma->wme[WME_AC_BK]); 2539 bwn_dma_setup(dma->wme[WME_AC_BE]); 2540 bwn_dma_setup(dma->wme[WME_AC_VI]); 2541 bwn_dma_setup(dma->wme[WME_AC_VO]); 2542 bwn_dma_setup(dma->mcast); 2543 /* setup RX DMA channel. */ 2544 bwn_dma_setup(dma->rx); 2545} 2546 2547static struct bwn_dma_ring * 2548bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, 2549 int for_tx, int type) 2550{ 2551 struct bwn_dma *dma = &mac->mac_method.dma; 2552 struct bwn_dma_ring *dr; 2553 struct bwn_dmadesc_generic *desc; 2554 struct bwn_dmadesc_meta *mt; 2555 struct bwn_softc *sc = mac->mac_sc; 2556 int error, i; 2557 2558 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO); 2559 if (dr == NULL) 2560 goto out; 2561 dr->dr_numslots = BWN_RXRING_SLOTS; 2562 if (for_tx) 2563 dr->dr_numslots = BWN_TXRING_SLOTS; 2564 2565 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta), 2566 M_DEVBUF, M_NOWAIT | M_ZERO); 2567 if (dr->dr_meta == NULL) 2568 goto fail0; 2569 2570 dr->dr_type = type; 2571 dr->dr_mac = mac; 2572 dr->dr_base = bwn_dma_base(type, controller_index); 2573 dr->dr_index = controller_index; 2574 if (type == BWN_DMA_64BIT) { 2575 dr->getdesc = bwn_dma_64_getdesc; 2576 dr->setdesc = bwn_dma_64_setdesc; 2577 dr->start_transfer = bwn_dma_64_start_transfer; 2578 dr->suspend = bwn_dma_64_suspend; 2579 dr->resume = bwn_dma_64_resume; 2580 dr->get_curslot = bwn_dma_64_get_curslot; 2581 dr->set_curslot = bwn_dma_64_set_curslot; 2582 } else { 2583 dr->getdesc = bwn_dma_32_getdesc; 2584 dr->setdesc = bwn_dma_32_setdesc; 2585 dr->start_transfer = bwn_dma_32_start_transfer; 2586 dr->suspend = bwn_dma_32_suspend; 2587 dr->resume = bwn_dma_32_resume; 2588 dr->get_curslot = bwn_dma_32_get_curslot; 2589 dr->set_curslot = bwn_dma_32_set_curslot; 2590 } 2591 if (for_tx) { 2592 dr->dr_tx = 1; 2593 dr->dr_curslot = -1; 2594 } else { 2595 if (dr->dr_index == 0) { 2596 dr->dr_rx_bufsize = BWN_DMA0_RX_BUFFERSIZE; 2597 dr->dr_frameoffset = BWN_DMA0_RX_FRAMEOFFSET; 2598 } else 2599 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2600 } 2601 2602 error = bwn_dma_allocringmemory(dr); 2603 if (error) 2604 goto fail2; 2605 2606 if (for_tx) { 2607 /* 2608 * Assumption: BWN_TXRING_SLOTS can be divided by 2609 * BWN_TX_SLOTS_PER_FRAME 2610 */ 2611 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0, 2612 ("%s:%d: fail", __func__, __LINE__)); 2613 2614 dr->dr_txhdr_cache = 2615 malloc((dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2616 BWN_HDRSIZE(mac), M_DEVBUF, M_NOWAIT | M_ZERO); 2617 KASSERT(dr->dr_txhdr_cache != NULL, 2618 ("%s:%d: fail", __func__, __LINE__)); 2619 2620 /* 2621 * Create TX ring DMA stuffs 2622 */ 2623 error = bus_dma_tag_create(dma->parent_dtag, 2624 BWN_ALIGN, 0, 2625 BUS_SPACE_MAXADDR, 2626 BUS_SPACE_MAXADDR, 2627 NULL, NULL, 2628 BWN_HDRSIZE(mac), 2629 1, 2630 BUS_SPACE_MAXSIZE_32BIT, 2631 0, 2632 NULL, NULL, 2633 &dr->dr_txring_dtag); 2634 if (error) { 2635 device_printf(sc->sc_dev, 2636 "can't create TX ring DMA tag: TODO frees\n"); 2637 goto fail1; 2638 } 2639 2640 for (i = 0; i < dr->dr_numslots; i += 2) { 2641 dr->getdesc(dr, i, &desc, &mt); 2642 2643 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER; 2644 mt->mt_m = NULL; 2645 mt->mt_ni = NULL; 2646 mt->mt_islast = 0; 2647 error = bus_dmamap_create(dr->dr_txring_dtag, 0, 2648 &mt->mt_dmap); 2649 if (error) { 2650 device_printf(sc->sc_dev, 2651 "can't create RX buf DMA map\n"); 2652 goto fail1; 2653 } 2654 2655 dr->getdesc(dr, i + 1, &desc, &mt); 2656 2657 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY; 2658 mt->mt_m = NULL; 2659 mt->mt_ni = NULL; 2660 mt->mt_islast = 1; 2661 error = bus_dmamap_create(dma->txbuf_dtag, 0, 2662 &mt->mt_dmap); 2663 if (error) { 2664 device_printf(sc->sc_dev, 2665 "can't create RX buf DMA map\n"); 2666 goto fail1; 2667 } 2668 } 2669 } else { 2670 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2671 &dr->dr_spare_dmap); 2672 if (error) { 2673 device_printf(sc->sc_dev, 2674 "can't create RX buf DMA map\n"); 2675 goto out; /* XXX wrong! */ 2676 } 2677 2678 for (i = 0; i < dr->dr_numslots; i++) { 2679 dr->getdesc(dr, i, &desc, &mt); 2680 2681 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2682 &mt->mt_dmap); 2683 if (error) { 2684 device_printf(sc->sc_dev, 2685 "can't create RX buf DMA map\n"); 2686 goto out; /* XXX wrong! */ 2687 } 2688 error = bwn_dma_newbuf(dr, desc, mt, 1); 2689 if (error) { 2690 device_printf(sc->sc_dev, 2691 "failed to allocate RX buf\n"); 2692 goto out; /* XXX wrong! */ 2693 } 2694 } 2695 2696 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 2697 BUS_DMASYNC_PREWRITE); 2698 2699 dr->dr_usedslot = dr->dr_numslots; 2700 } 2701 2702 out: 2703 return (dr); 2704 2705fail2: 2706 free(dr->dr_txhdr_cache, M_DEVBUF); 2707fail1: 2708 free(dr->dr_meta, M_DEVBUF); 2709fail0: 2710 free(dr, M_DEVBUF); 2711 return (NULL); 2712} 2713 2714static void 2715bwn_dma_ringfree(struct bwn_dma_ring **dr) 2716{ 2717 2718 if (dr == NULL) 2719 return; 2720 2721 bwn_dma_free_descbufs(*dr); 2722 bwn_dma_free_ringmemory(*dr); 2723 2724 free((*dr)->dr_txhdr_cache, M_DEVBUF); 2725 free((*dr)->dr_meta, M_DEVBUF); 2726 free(*dr, M_DEVBUF); 2727 2728 *dr = NULL; 2729} 2730 2731static void 2732bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot, 2733 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 2734{ 2735 struct bwn_dmadesc32 *desc; 2736 2737 *meta = &(dr->dr_meta[slot]); 2738 desc = dr->dr_ring_descbase; 2739 desc = &(desc[slot]); 2740 2741 *gdesc = (struct bwn_dmadesc_generic *)desc; 2742} 2743 2744static void 2745bwn_dma_32_setdesc(struct bwn_dma_ring *dr, 2746 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 2747 int start, int end, int irq) 2748{ 2749 struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase; 2750 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2751 uint32_t addr, addrext, ctl; 2752 int slot; 2753 2754 slot = (int)(&(desc->dma.dma32) - descbase); 2755 KASSERT(slot >= 0 && slot < dr->dr_numslots, 2756 ("%s:%d: fail", __func__, __LINE__)); 2757 2758 addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK); 2759 addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30; 2760 addr |= siba_dma_translation(sc->sc_dev); 2761 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT; 2762 if (slot == dr->dr_numslots - 1) 2763 ctl |= BWN_DMA32_DCTL_DTABLEEND; 2764 if (start) 2765 ctl |= BWN_DMA32_DCTL_FRAMESTART; 2766 if (end) 2767 ctl |= BWN_DMA32_DCTL_FRAMEEND; 2768 if (irq) 2769 ctl |= BWN_DMA32_DCTL_IRQ; 2770 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT) 2771 & BWN_DMA32_DCTL_ADDREXT_MASK; 2772 2773 desc->dma.dma32.control = htole32(ctl); 2774 desc->dma.dma32.address = htole32(addr); 2775} 2776 2777static void 2778bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot) 2779{ 2780 2781 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX, 2782 (uint32_t)(slot * sizeof(struct bwn_dmadesc32))); 2783} 2784 2785static void 2786bwn_dma_32_suspend(struct bwn_dma_ring *dr) 2787{ 2788 2789 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 2790 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND); 2791} 2792 2793static void 2794bwn_dma_32_resume(struct bwn_dma_ring *dr) 2795{ 2796 2797 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 2798 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND); 2799} 2800 2801static int 2802bwn_dma_32_get_curslot(struct bwn_dma_ring *dr) 2803{ 2804 uint32_t val; 2805 2806 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS); 2807 val &= BWN_DMA32_RXDPTR; 2808 2809 return (val / sizeof(struct bwn_dmadesc32)); 2810} 2811 2812static void 2813bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot) 2814{ 2815 2816 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, 2817 (uint32_t) (slot * sizeof(struct bwn_dmadesc32))); 2818} 2819 2820static void 2821bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot, 2822 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 2823{ 2824 struct bwn_dmadesc64 *desc; 2825 2826 *meta = &(dr->dr_meta[slot]); 2827 desc = dr->dr_ring_descbase; 2828 desc = &(desc[slot]); 2829 2830 *gdesc = (struct bwn_dmadesc_generic *)desc; 2831} 2832 2833static void 2834bwn_dma_64_setdesc(struct bwn_dma_ring *dr, 2835 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 2836 int start, int end, int irq) 2837{ 2838 struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase; 2839 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2840 int slot; 2841 uint32_t ctl0 = 0, ctl1 = 0; 2842 uint32_t addrlo, addrhi; 2843 uint32_t addrext; 2844 2845 slot = (int)(&(desc->dma.dma64) - descbase); 2846 KASSERT(slot >= 0 && slot < dr->dr_numslots, 2847 ("%s:%d: fail", __func__, __LINE__)); 2848 2849 addrlo = (uint32_t) (dmaaddr & 0xffffffff); 2850 addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK); 2851 addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 2852 30; 2853 addrhi |= (siba_dma_translation(sc->sc_dev) << 1); 2854 if (slot == dr->dr_numslots - 1) 2855 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND; 2856 if (start) 2857 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART; 2858 if (end) 2859 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND; 2860 if (irq) 2861 ctl0 |= BWN_DMA64_DCTL0_IRQ; 2862 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT; 2863 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT) 2864 & BWN_DMA64_DCTL1_ADDREXT_MASK; 2865 2866 desc->dma.dma64.control0 = htole32(ctl0); 2867 desc->dma.dma64.control1 = htole32(ctl1); 2868 desc->dma.dma64.address_low = htole32(addrlo); 2869 desc->dma.dma64.address_high = htole32(addrhi); 2870} 2871 2872static void 2873bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot) 2874{ 2875 2876 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX, 2877 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 2878} 2879 2880static void 2881bwn_dma_64_suspend(struct bwn_dma_ring *dr) 2882{ 2883 2884 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 2885 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND); 2886} 2887 2888static void 2889bwn_dma_64_resume(struct bwn_dma_ring *dr) 2890{ 2891 2892 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 2893 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND); 2894} 2895 2896static int 2897bwn_dma_64_get_curslot(struct bwn_dma_ring *dr) 2898{ 2899 uint32_t val; 2900 2901 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS); 2902 val &= BWN_DMA64_RXSTATDPTR; 2903 2904 return (val / sizeof(struct bwn_dmadesc64)); 2905} 2906 2907static void 2908bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot) 2909{ 2910 2911 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, 2912 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 2913} 2914 2915static int 2916bwn_dma_allocringmemory(struct bwn_dma_ring *dr) 2917{ 2918 struct bwn_mac *mac = dr->dr_mac; 2919 struct bwn_dma *dma = &mac->mac_method.dma; 2920 struct bwn_softc *sc = mac->mac_sc; 2921 int error; 2922 2923 error = bus_dma_tag_create(dma->parent_dtag, 2924 BWN_ALIGN, 0, 2925 BUS_SPACE_MAXADDR, 2926 BUS_SPACE_MAXADDR, 2927 NULL, NULL, 2928 BWN_DMA_RINGMEMSIZE, 2929 1, 2930 BUS_SPACE_MAXSIZE_32BIT, 2931 0, 2932 NULL, NULL, 2933 &dr->dr_ring_dtag); 2934 if (error) { 2935 device_printf(sc->sc_dev, 2936 "can't create TX ring DMA tag: TODO frees\n"); 2937 return (-1); 2938 } 2939 2940 error = bus_dmamem_alloc(dr->dr_ring_dtag, 2941 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO, 2942 &dr->dr_ring_dmap); 2943 if (error) { 2944 device_printf(sc->sc_dev, 2945 "can't allocate DMA mem: TODO frees\n"); 2946 return (-1); 2947 } 2948 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap, 2949 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE, 2950 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT); 2951 if (error) { 2952 device_printf(sc->sc_dev, 2953 "can't load DMA mem: TODO free\n"); 2954 return (-1); 2955 } 2956 2957 return (0); 2958} 2959 2960static void 2961bwn_dma_setup(struct bwn_dma_ring *dr) 2962{ 2963 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2964 uint64_t ring64; 2965 uint32_t addrext, ring32, value; 2966 uint32_t trans = siba_dma_translation(sc->sc_dev); 2967 2968 if (dr->dr_tx) { 2969 dr->dr_curslot = -1; 2970 2971 if (dr->dr_type == BWN_DMA_64BIT) { 2972 ring64 = (uint64_t)(dr->dr_ring_dmabase); 2973 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) 2974 >> 30; 2975 value = BWN_DMA64_TXENABLE; 2976 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT) 2977 & BWN_DMA64_TXADDREXT_MASK; 2978 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value); 2979 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 2980 (ring64 & 0xffffffff)); 2981 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 2982 ((ring64 >> 32) & 2983 ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1)); 2984 } else { 2985 ring32 = (uint32_t)(dr->dr_ring_dmabase); 2986 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; 2987 value = BWN_DMA32_TXENABLE; 2988 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT) 2989 & BWN_DMA32_TXADDREXT_MASK; 2990 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value); 2991 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 2992 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); 2993 } 2994 return; 2995 } 2996 2997 /* 2998 * set for RX 2999 */ 3000 dr->dr_usedslot = dr->dr_numslots; 3001 3002 if (dr->dr_type == BWN_DMA_64BIT) { 3003 ring64 = (uint64_t)(dr->dr_ring_dmabase); 3004 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30; 3005 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT); 3006 value |= BWN_DMA64_RXENABLE; 3007 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT) 3008 & BWN_DMA64_RXADDREXT_MASK; 3009 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value); 3010 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff)); 3011 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 3012 ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK) 3013 | (trans << 1)); 3014 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots * 3015 sizeof(struct bwn_dmadesc64)); 3016 } else { 3017 ring32 = (uint32_t)(dr->dr_ring_dmabase); 3018 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; 3019 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT); 3020 value |= BWN_DMA32_RXENABLE; 3021 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT) 3022 & BWN_DMA32_RXADDREXT_MASK; 3023 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value); 3024 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 3025 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); 3026 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots * 3027 sizeof(struct bwn_dmadesc32)); 3028 } 3029} 3030 3031static void 3032bwn_dma_free_ringmemory(struct bwn_dma_ring *dr) 3033{ 3034 3035 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap); 3036 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase, 3037 dr->dr_ring_dmap); 3038} 3039 3040static void 3041bwn_dma_cleanup(struct bwn_dma_ring *dr) 3042{ 3043 3044 if (dr->dr_tx) { 3045 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3046 if (dr->dr_type == BWN_DMA_64BIT) { 3047 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0); 3048 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0); 3049 } else 3050 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0); 3051 } else { 3052 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3053 if (dr->dr_type == BWN_DMA_64BIT) { 3054 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0); 3055 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0); 3056 } else 3057 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0); 3058 } 3059} 3060 3061static void 3062bwn_dma_free_descbufs(struct bwn_dma_ring *dr) 3063{ 3064 struct bwn_dmadesc_generic *desc; 3065 struct bwn_dmadesc_meta *meta; 3066 struct bwn_mac *mac = dr->dr_mac; 3067 struct bwn_dma *dma = &mac->mac_method.dma; 3068 struct bwn_softc *sc = mac->mac_sc; 3069 int i; 3070 3071 if (!dr->dr_usedslot) 3072 return; 3073 for (i = 0; i < dr->dr_numslots; i++) { 3074 dr->getdesc(dr, i, &desc, &meta); 3075 3076 if (meta->mt_m == NULL) { 3077 if (!dr->dr_tx) 3078 device_printf(sc->sc_dev, "%s: not TX?\n", 3079 __func__); 3080 continue; 3081 } 3082 if (dr->dr_tx) { 3083 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 3084 bus_dmamap_unload(dr->dr_txring_dtag, 3085 meta->mt_dmap); 3086 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 3087 bus_dmamap_unload(dma->txbuf_dtag, 3088 meta->mt_dmap); 3089 } else 3090 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 3091 bwn_dma_free_descbuf(dr, meta); 3092 } 3093} 3094 3095static int 3096bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base, 3097 int type) 3098{ 3099 struct bwn_softc *sc = mac->mac_sc; 3100 uint32_t value; 3101 int i; 3102 uint16_t offset; 3103 3104 for (i = 0; i < 10; i++) { 3105 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : 3106 BWN_DMA32_TXSTATUS; 3107 value = BWN_READ_4(mac, base + offset); 3108 if (type == BWN_DMA_64BIT) { 3109 value &= BWN_DMA64_TXSTAT; 3110 if (value == BWN_DMA64_TXSTAT_DISABLED || 3111 value == BWN_DMA64_TXSTAT_IDLEWAIT || 3112 value == BWN_DMA64_TXSTAT_STOPPED) 3113 break; 3114 } else { 3115 value &= BWN_DMA32_TXSTATE; 3116 if (value == BWN_DMA32_TXSTAT_DISABLED || 3117 value == BWN_DMA32_TXSTAT_IDLEWAIT || 3118 value == BWN_DMA32_TXSTAT_STOPPED) 3119 break; 3120 } 3121 DELAY(1000); 3122 } 3123 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL; 3124 BWN_WRITE_4(mac, base + offset, 0); 3125 for (i = 0; i < 10; i++) { 3126 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : 3127 BWN_DMA32_TXSTATUS; 3128 value = BWN_READ_4(mac, base + offset); 3129 if (type == BWN_DMA_64BIT) { 3130 value &= BWN_DMA64_TXSTAT; 3131 if (value == BWN_DMA64_TXSTAT_DISABLED) { 3132 i = -1; 3133 break; 3134 } 3135 } else { 3136 value &= BWN_DMA32_TXSTATE; 3137 if (value == BWN_DMA32_TXSTAT_DISABLED) { 3138 i = -1; 3139 break; 3140 } 3141 } 3142 DELAY(1000); 3143 } 3144 if (i != -1) { 3145 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3146 return (ENODEV); 3147 } 3148 DELAY(1000); 3149 3150 return (0); 3151} 3152 3153static int 3154bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base, 3155 int type) 3156{ 3157 struct bwn_softc *sc = mac->mac_sc; 3158 uint32_t value; 3159 int i; 3160 uint16_t offset; 3161 3162 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL; 3163 BWN_WRITE_4(mac, base + offset, 0); 3164 for (i = 0; i < 10; i++) { 3165 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS : 3166 BWN_DMA32_RXSTATUS; 3167 value = BWN_READ_4(mac, base + offset); 3168 if (type == BWN_DMA_64BIT) { 3169 value &= BWN_DMA64_RXSTAT; 3170 if (value == BWN_DMA64_RXSTAT_DISABLED) { 3171 i = -1; 3172 break; 3173 } 3174 } else { 3175 value &= BWN_DMA32_RXSTATE; 3176 if (value == BWN_DMA32_RXSTAT_DISABLED) { 3177 i = -1; 3178 break; 3179 } 3180 } 3181 DELAY(1000); 3182 } 3183 if (i != -1) { 3184 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3185 return (ENODEV); 3186 } 3187 3188 return (0); 3189} 3190 3191static void 3192bwn_dma_free_descbuf(struct bwn_dma_ring *dr, 3193 struct bwn_dmadesc_meta *meta) 3194{ 3195 3196 if (meta->mt_m != NULL) { 3197 m_freem(meta->mt_m); 3198 meta->mt_m = NULL; 3199 } 3200 if (meta->mt_ni != NULL) { 3201 ieee80211_free_node(meta->mt_ni); 3202 meta->mt_ni = NULL; 3203 } 3204} 3205 3206static void 3207bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3208{ 3209 struct bwn_rxhdr4 *rxhdr; 3210 unsigned char *frame; 3211 3212 rxhdr = mtod(m, struct bwn_rxhdr4 *); 3213 rxhdr->frame_len = 0; 3214 3215 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset + 3216 sizeof(struct bwn_plcp6) + 2, 3217 ("%s:%d: fail", __func__, __LINE__)); 3218 frame = mtod(m, char *) + dr->dr_frameoffset; 3219 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */); 3220} 3221 3222static uint8_t 3223bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3224{ 3225 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset; 3226 3227 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) 3228 == 0xff); 3229} 3230 3231static void 3232bwn_wme_init(struct bwn_mac *mac) 3233{ 3234 3235 bwn_wme_load(mac); 3236 3237 /* enable WME support. */ 3238 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF); 3239 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) | 3240 BWN_IFSCTL_USE_EDCF); 3241} 3242 3243static void 3244bwn_spu_setdelay(struct bwn_mac *mac, int idle) 3245{ 3246 struct bwn_softc *sc = mac->mac_sc; 3247 struct ieee80211com *ic = &sc->sc_ic; 3248 uint16_t delay; /* microsec */ 3249 3250 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050; 3251 if (ic->ic_opmode == IEEE80211_M_IBSS || idle) 3252 delay = 500; 3253 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8)) 3254 delay = max(delay, (uint16_t)2400); 3255 3256 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay); 3257} 3258 3259static void 3260bwn_bt_enable(struct bwn_mac *mac) 3261{ 3262 struct bwn_softc *sc = mac->mac_sc; 3263 uint64_t hf; 3264 3265 if (bwn_bluetooth == 0) 3266 return; 3267 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0) 3268 return; 3269 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode) 3270 return; 3271 3272 hf = bwn_hf_read(mac); 3273 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD) 3274 hf |= BWN_HF_BT_COEXISTALT; 3275 else 3276 hf |= BWN_HF_BT_COEXIST; 3277 bwn_hf_write(mac, hf); 3278} 3279 3280static void 3281bwn_set_macaddr(struct bwn_mac *mac) 3282{ 3283 3284 bwn_mac_write_bssid(mac); 3285 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF, 3286 mac->mac_sc->sc_ic.ic_macaddr); 3287} 3288 3289static void 3290bwn_clear_keys(struct bwn_mac *mac) 3291{ 3292 int i; 3293 3294 for (i = 0; i < mac->mac_max_nr_keys; i++) { 3295 KASSERT(i >= 0 && i < mac->mac_max_nr_keys, 3296 ("%s:%d: fail", __func__, __LINE__)); 3297 3298 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE, 3299 NULL, BWN_SEC_KEYSIZE, NULL); 3300 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) { 3301 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE, 3302 NULL, BWN_SEC_KEYSIZE, NULL); 3303 } 3304 mac->mac_key[i].keyconf = NULL; 3305 } 3306} 3307 3308static void 3309bwn_crypt_init(struct bwn_mac *mac) 3310{ 3311 struct bwn_softc *sc = mac->mac_sc; 3312 3313 mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20; 3314 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key), 3315 ("%s:%d: fail", __func__, __LINE__)); 3316 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP); 3317 mac->mac_ktp *= 2; 3318 if (siba_get_revid(sc->sc_dev) >= 5) 3319 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8); 3320 bwn_clear_keys(mac); 3321} 3322 3323static void 3324bwn_chip_exit(struct bwn_mac *mac) 3325{ 3326 struct bwn_softc *sc = mac->mac_sc; 3327 3328 bwn_phy_exit(mac); 3329 siba_gpio_set(sc->sc_dev, 0); 3330} 3331 3332static int 3333bwn_fw_fillinfo(struct bwn_mac *mac) 3334{ 3335 int error; 3336 3337 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT); 3338 if (error == 0) 3339 return (0); 3340 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE); 3341 if (error == 0) 3342 return (0); 3343 return (error); 3344} 3345 3346static int 3347bwn_gpio_init(struct bwn_mac *mac) 3348{ 3349 struct bwn_softc *sc = mac->mac_sc; 3350 uint32_t mask = 0x1f, set = 0xf, value; 3351 3352 BWN_WRITE_4(mac, BWN_MACCTL, 3353 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK); 3354 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3355 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f); 3356 3357 if (siba_get_chipid(sc->sc_dev) == 0x4301) { 3358 mask |= 0x0060; 3359 set |= 0x0060; 3360 } 3361 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) { 3362 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3363 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200); 3364 mask |= 0x0200; 3365 set |= 0x0200; 3366 } 3367 if (siba_get_revid(sc->sc_dev) >= 2) 3368 mask |= 0x0010; 3369 3370 value = siba_gpio_get(sc->sc_dev); 3371 if (value == -1) 3372 return (0); 3373 siba_gpio_set(sc->sc_dev, (value & mask) | set); 3374 3375 return (0); 3376} 3377 3378static int 3379bwn_fw_loadinitvals(struct bwn_mac *mac) 3380{ 3381#define GETFWOFFSET(fwp, offset) \ 3382 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset)) 3383 const size_t hdr_len = sizeof(struct bwn_fwhdr); 3384 const struct bwn_fwhdr *hdr; 3385 struct bwn_fw *fw = &mac->mac_fw; 3386 int error; 3387 3388 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data); 3389 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len), 3390 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len); 3391 if (error) 3392 return (error); 3393 if (fw->initvals_band.fw) { 3394 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data); 3395 error = bwn_fwinitvals_write(mac, 3396 GETFWOFFSET(fw->initvals_band, hdr_len), 3397 be32toh(hdr->size), 3398 fw->initvals_band.fw->datasize - hdr_len); 3399 } 3400 return (error); 3401#undef GETFWOFFSET 3402} 3403 3404static int 3405bwn_phy_init(struct bwn_mac *mac) 3406{ 3407 struct bwn_softc *sc = mac->mac_sc; 3408 int error; 3409 3410 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac); 3411 mac->mac_phy.rf_onoff(mac, 1); 3412 error = mac->mac_phy.init(mac); 3413 if (error) { 3414 device_printf(sc->sc_dev, "PHY init failed\n"); 3415 goto fail0; 3416 } 3417 error = bwn_switch_channel(mac, 3418 mac->mac_phy.get_default_chan(mac)); 3419 if (error) { 3420 device_printf(sc->sc_dev, 3421 "failed to switch default channel\n"); 3422 goto fail1; 3423 } 3424 return (0); 3425fail1: 3426 if (mac->mac_phy.exit) 3427 mac->mac_phy.exit(mac); 3428fail0: 3429 mac->mac_phy.rf_onoff(mac, 0); 3430 3431 return (error); 3432} 3433 3434static void 3435bwn_set_txantenna(struct bwn_mac *mac, int antenna) 3436{ 3437 uint16_t ant; 3438 uint16_t tmp; 3439 3440 ant = bwn_ant2phy(antenna); 3441 3442 /* For ACK/CTS */ 3443 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL); 3444 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3445 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp); 3446 /* For Probe Resposes */ 3447 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL); 3448 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3449 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp); 3450} 3451 3452static void 3453bwn_set_opmode(struct bwn_mac *mac) 3454{ 3455 struct bwn_softc *sc = mac->mac_sc; 3456 struct ieee80211com *ic = &sc->sc_ic; 3457 uint32_t ctl; 3458 uint16_t cfp_pretbtt; 3459 3460 ctl = BWN_READ_4(mac, BWN_MACCTL); 3461 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL | 3462 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS | 3463 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC); 3464 ctl |= BWN_MACCTL_STA; 3465 3466 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3467 ic->ic_opmode == IEEE80211_M_MBSS) 3468 ctl |= BWN_MACCTL_HOSTAP; 3469 else if (ic->ic_opmode == IEEE80211_M_IBSS) 3470 ctl &= ~BWN_MACCTL_STA; 3471 ctl |= sc->sc_filters; 3472 3473 if (siba_get_revid(sc->sc_dev) <= 4) 3474 ctl |= BWN_MACCTL_PROMISC; 3475 3476 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 3477 3478 cfp_pretbtt = 2; 3479 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) { 3480 if (siba_get_chipid(sc->sc_dev) == 0x4306 && 3481 siba_get_chiprev(sc->sc_dev) == 3) 3482 cfp_pretbtt = 100; 3483 else 3484 cfp_pretbtt = 50; 3485 } 3486 BWN_WRITE_2(mac, 0x612, cfp_pretbtt); 3487} 3488 3489static int 3490bwn_dma_gettype(struct bwn_mac *mac) 3491{ 3492 uint32_t tmp; 3493 uint16_t base; 3494 3495 tmp = BWN_READ_4(mac, SIBA_TGSHIGH); 3496 if (tmp & SIBA_TGSHIGH_DMA64) 3497 return (BWN_DMA_64BIT); 3498 base = bwn_dma_base(0, 0); 3499 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); 3500 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 3501 if (tmp & BWN_DMA32_TXADDREXT_MASK) 3502 return (BWN_DMA_32BIT); 3503 3504 return (BWN_DMA_30BIT); 3505} 3506 3507static void 3508bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 3509{ 3510 if (!error) { 3511 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 3512 *((bus_addr_t *)arg) = seg->ds_addr; 3513 } 3514} 3515 3516void 3517bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val) 3518{ 3519 uint32_t macctl; 3520 3521 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__)); 3522 3523 macctl = BWN_READ_4(mac, BWN_MACCTL); 3524 if (macctl & BWN_MACCTL_BIGENDIAN) 3525 printf("TODO: need swap\n"); 3526 3527 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset); 3528 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 3529 BWN_WRITE_4(mac, BWN_RAM_DATA, val); 3530} 3531 3532void 3533bwn_mac_suspend(struct bwn_mac *mac) 3534{ 3535 struct bwn_softc *sc = mac->mac_sc; 3536 int i; 3537 uint32_t tmp; 3538 3539 KASSERT(mac->mac_suspended >= 0, 3540 ("%s:%d: fail", __func__, __LINE__)); 3541 3542 if (mac->mac_suspended == 0) { 3543 bwn_psctl(mac, BWN_PS_AWAKE); 3544 BWN_WRITE_4(mac, BWN_MACCTL, 3545 BWN_READ_4(mac, BWN_MACCTL) 3546 & ~BWN_MACCTL_ON); 3547 BWN_READ_4(mac, BWN_MACCTL); 3548 for (i = 35; i; i--) { 3549 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3550 if (tmp & BWN_INTR_MAC_SUSPENDED) 3551 goto out; 3552 DELAY(10); 3553 } 3554 for (i = 40; i; i--) { 3555 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3556 if (tmp & BWN_INTR_MAC_SUSPENDED) 3557 goto out; 3558 DELAY(1000); 3559 } 3560 device_printf(sc->sc_dev, "MAC suspend failed\n"); 3561 } 3562out: 3563 mac->mac_suspended++; 3564} 3565 3566void 3567bwn_mac_enable(struct bwn_mac *mac) 3568{ 3569 struct bwn_softc *sc = mac->mac_sc; 3570 uint16_t state; 3571 3572 state = bwn_shm_read_2(mac, BWN_SHARED, 3573 BWN_SHARED_UCODESTAT); 3574 if (state != BWN_SHARED_UCODESTAT_SUSPEND && 3575 state != BWN_SHARED_UCODESTAT_SLEEP) 3576 device_printf(sc->sc_dev, "warn: firmware state (%d)\n", state); 3577 3578 mac->mac_suspended--; 3579 KASSERT(mac->mac_suspended >= 0, 3580 ("%s:%d: fail", __func__, __LINE__)); 3581 if (mac->mac_suspended == 0) { 3582 BWN_WRITE_4(mac, BWN_MACCTL, 3583 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON); 3584 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED); 3585 BWN_READ_4(mac, BWN_MACCTL); 3586 BWN_READ_4(mac, BWN_INTR_REASON); 3587 bwn_psctl(mac, 0); 3588 } 3589} 3590 3591void 3592bwn_psctl(struct bwn_mac *mac, uint32_t flags) 3593{ 3594 struct bwn_softc *sc = mac->mac_sc; 3595 int i; 3596 uint16_t ucstat; 3597 3598 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)), 3599 ("%s:%d: fail", __func__, __LINE__)); 3600 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)), 3601 ("%s:%d: fail", __func__, __LINE__)); 3602 3603 /* XXX forcibly awake and hwps-off */ 3604 3605 BWN_WRITE_4(mac, BWN_MACCTL, 3606 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) & 3607 ~BWN_MACCTL_HWPS); 3608 BWN_READ_4(mac, BWN_MACCTL); 3609 if (siba_get_revid(sc->sc_dev) >= 5) { 3610 for (i = 0; i < 100; i++) { 3611 ucstat = bwn_shm_read_2(mac, BWN_SHARED, 3612 BWN_SHARED_UCODESTAT); 3613 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP) 3614 break; 3615 DELAY(10); 3616 } 3617 } 3618} 3619 3620static int 3621bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type) 3622{ 3623 struct bwn_softc *sc = mac->mac_sc; 3624 struct bwn_fw *fw = &mac->mac_fw; 3625 const uint8_t rev = siba_get_revid(sc->sc_dev); 3626 const char *filename; 3627 uint32_t high; 3628 int error; 3629 3630 /* microcode */ 3631 if (rev >= 5 && rev <= 10) 3632 filename = "ucode5"; 3633 else if (rev >= 11 && rev <= 12) 3634 filename = "ucode11"; 3635 else if (rev == 13) 3636 filename = "ucode13"; 3637 else if (rev == 14) 3638 filename = "ucode14"; 3639 else if (rev >= 15) 3640 filename = "ucode15"; 3641 else { 3642 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev); 3643 bwn_release_firmware(mac); 3644 return (EOPNOTSUPP); 3645 } 3646 error = bwn_fw_get(mac, type, filename, &fw->ucode); 3647 if (error) { 3648 bwn_release_firmware(mac); 3649 return (error); 3650 } 3651 3652 /* PCM */ 3653 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__)); 3654 if (rev >= 5 && rev <= 10) { 3655 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm); 3656 if (error == ENOENT) 3657 fw->no_pcmfile = 1; 3658 else if (error) { 3659 bwn_release_firmware(mac); 3660 return (error); 3661 } 3662 } else if (rev < 11) { 3663 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev); 3664 return (EOPNOTSUPP); 3665 } 3666 3667 /* initvals */ 3668 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); 3669 switch (mac->mac_phy.type) { 3670 case BWN_PHYTYPE_A: 3671 if (rev < 5 || rev > 10) 3672 goto fail1; 3673 if (high & BWN_TGSHIGH_HAVE_2GHZ) 3674 filename = "a0g1initvals5"; 3675 else 3676 filename = "a0g0initvals5"; 3677 break; 3678 case BWN_PHYTYPE_G: 3679 if (rev >= 5 && rev <= 10) 3680 filename = "b0g0initvals5"; 3681 else if (rev >= 13) 3682 filename = "b0g0initvals13"; 3683 else 3684 goto fail1; 3685 break; 3686 case BWN_PHYTYPE_LP: 3687 if (rev == 13) 3688 filename = "lp0initvals13"; 3689 else if (rev == 14) 3690 filename = "lp0initvals14"; 3691 else if (rev >= 15) 3692 filename = "lp0initvals15"; 3693 else 3694 goto fail1; 3695 break; 3696 case BWN_PHYTYPE_N: 3697 if (rev >= 11 && rev <= 12) 3698 filename = "n0initvals11"; 3699 else 3700 goto fail1; 3701 break; 3702 default: 3703 goto fail1; 3704 } 3705 error = bwn_fw_get(mac, type, filename, &fw->initvals); 3706 if (error) { 3707 bwn_release_firmware(mac); 3708 return (error); 3709 } 3710 3711 /* bandswitch initvals */ 3712 switch (mac->mac_phy.type) { 3713 case BWN_PHYTYPE_A: 3714 if (rev >= 5 && rev <= 10) { 3715 if (high & BWN_TGSHIGH_HAVE_2GHZ) 3716 filename = "a0g1bsinitvals5"; 3717 else 3718 filename = "a0g0bsinitvals5"; 3719 } else if (rev >= 11) 3720 filename = NULL; 3721 else 3722 goto fail1; 3723 break; 3724 case BWN_PHYTYPE_G: 3725 if (rev >= 5 && rev <= 10) 3726 filename = "b0g0bsinitvals5"; 3727 else if (rev >= 11) 3728 filename = NULL; 3729 else 3730 goto fail1; 3731 break; 3732 case BWN_PHYTYPE_LP: 3733 if (rev == 13) 3734 filename = "lp0bsinitvals13"; 3735 else if (rev == 14) 3736 filename = "lp0bsinitvals14"; 3737 else if (rev >= 15) 3738 filename = "lp0bsinitvals15"; 3739 else 3740 goto fail1; 3741 break; 3742 case BWN_PHYTYPE_N: 3743 if (rev >= 11 && rev <= 12) 3744 filename = "n0bsinitvals11"; 3745 else 3746 goto fail1; 3747 break; 3748 default: 3749 goto fail1; 3750 } 3751 error = bwn_fw_get(mac, type, filename, &fw->initvals_band); 3752 if (error) { 3753 bwn_release_firmware(mac); 3754 return (error); 3755 } 3756 return (0); 3757fail1: 3758 device_printf(sc->sc_dev, "no INITVALS for rev %d\n", rev); 3759 bwn_release_firmware(mac); 3760 return (EOPNOTSUPP); 3761} 3762 3763static int 3764bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type, 3765 const char *name, struct bwn_fwfile *bfw) 3766{ 3767 const struct bwn_fwhdr *hdr; 3768 struct bwn_softc *sc = mac->mac_sc; 3769 const struct firmware *fw; 3770 char namebuf[64]; 3771 3772 if (name == NULL) { 3773 bwn_do_release_fw(bfw); 3774 return (0); 3775 } 3776 if (bfw->filename != NULL) { 3777 if (bfw->type == type && (strcmp(bfw->filename, name) == 0)) 3778 return (0); 3779 bwn_do_release_fw(bfw); 3780 } 3781 3782 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s", 3783 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "", 3784 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name); 3785 /* XXX Sleeping on "fwload" with the non-sleepable locks held */ 3786 fw = firmware_get(namebuf); 3787 if (fw == NULL) { 3788 device_printf(sc->sc_dev, "the fw file(%s) not found\n", 3789 namebuf); 3790 return (ENOENT); 3791 } 3792 if (fw->datasize < sizeof(struct bwn_fwhdr)) 3793 goto fail; 3794 hdr = (const struct bwn_fwhdr *)(fw->data); 3795 switch (hdr->type) { 3796 case BWN_FWTYPE_UCODE: 3797 case BWN_FWTYPE_PCM: 3798 if (be32toh(hdr->size) != 3799 (fw->datasize - sizeof(struct bwn_fwhdr))) 3800 goto fail; 3801 /* FALLTHROUGH */ 3802 case BWN_FWTYPE_IV: 3803 if (hdr->ver != 1) 3804 goto fail; 3805 break; 3806 default: 3807 goto fail; 3808 } 3809 bfw->filename = name; 3810 bfw->fw = fw; 3811 bfw->type = type; 3812 return (0); 3813fail: 3814 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf); 3815 if (fw != NULL) 3816 firmware_put(fw, FIRMWARE_UNLOAD); 3817 return (EPROTO); 3818} 3819 3820static void 3821bwn_release_firmware(struct bwn_mac *mac) 3822{ 3823 3824 bwn_do_release_fw(&mac->mac_fw.ucode); 3825 bwn_do_release_fw(&mac->mac_fw.pcm); 3826 bwn_do_release_fw(&mac->mac_fw.initvals); 3827 bwn_do_release_fw(&mac->mac_fw.initvals_band); 3828} 3829 3830static void 3831bwn_do_release_fw(struct bwn_fwfile *bfw) 3832{ 3833 3834 if (bfw->fw != NULL) 3835 firmware_put(bfw->fw, FIRMWARE_UNLOAD); 3836 bfw->fw = NULL; 3837 bfw->filename = NULL; 3838} 3839 3840static int 3841bwn_fw_loaducode(struct bwn_mac *mac) 3842{ 3843#define GETFWOFFSET(fwp, offset) \ 3844 ((const uint32_t *)((const char *)fwp.fw->data + offset)) 3845#define GETFWSIZE(fwp, offset) \ 3846 ((fwp.fw->datasize - offset) / sizeof(uint32_t)) 3847 struct bwn_softc *sc = mac->mac_sc; 3848 const uint32_t *data; 3849 unsigned int i; 3850 uint32_t ctl; 3851 uint16_t date, fwcaps, time; 3852 int error = 0; 3853 3854 ctl = BWN_READ_4(mac, BWN_MACCTL); 3855 ctl |= BWN_MACCTL_MCODE_JMP0; 3856 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__, 3857 __LINE__)); 3858 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 3859 for (i = 0; i < 64; i++) 3860 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0); 3861 for (i = 0; i < 4096; i += 2) 3862 bwn_shm_write_2(mac, BWN_SHARED, i, 0); 3863 3864 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 3865 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000); 3866 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 3867 i++) { 3868 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 3869 DELAY(10); 3870 } 3871 3872 if (mac->mac_fw.pcm.fw) { 3873 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr)); 3874 bwn_shm_ctlword(mac, BWN_HW, 0x01ea); 3875 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000); 3876 bwn_shm_ctlword(mac, BWN_HW, 0x01eb); 3877 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm, 3878 sizeof(struct bwn_fwhdr)); i++) { 3879 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 3880 DELAY(10); 3881 } 3882 } 3883 3884 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL); 3885 BWN_WRITE_4(mac, BWN_MACCTL, 3886 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) | 3887 BWN_MACCTL_MCODE_RUN); 3888 3889 for (i = 0; i < 21; i++) { 3890 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED) 3891 break; 3892 if (i >= 20) { 3893 device_printf(sc->sc_dev, "ucode timeout\n"); 3894 error = ENXIO; 3895 goto error; 3896 } 3897 DELAY(50000); 3898 } 3899 BWN_READ_4(mac, BWN_INTR_REASON); 3900 3901 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV); 3902 if (mac->mac_fw.rev <= 0x128) { 3903 device_printf(sc->sc_dev, "the firmware is too old\n"); 3904 error = EOPNOTSUPP; 3905 goto error; 3906 } 3907 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED, 3908 BWN_SHARED_UCODE_PATCH); 3909 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE); 3910 mac->mac_fw.opensource = (date == 0xffff); 3911 if (bwn_wme != 0) 3912 mac->mac_flags |= BWN_MAC_FLAG_WME; 3913 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO; 3914 3915 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME); 3916 if (mac->mac_fw.opensource == 0) { 3917 device_printf(sc->sc_dev, 3918 "firmware version (rev %u patch %u date %#x time %#x)\n", 3919 mac->mac_fw.rev, mac->mac_fw.patch, date, time); 3920 if (mac->mac_fw.no_pcmfile) 3921 device_printf(sc->sc_dev, 3922 "no HW crypto acceleration due to pcm5\n"); 3923 } else { 3924 mac->mac_fw.patch = time; 3925 fwcaps = bwn_fwcaps_read(mac); 3926 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) { 3927 device_printf(sc->sc_dev, 3928 "disabling HW crypto acceleration\n"); 3929 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO; 3930 } 3931 if (!(fwcaps & BWN_FWCAPS_WME)) { 3932 device_printf(sc->sc_dev, "disabling WME support\n"); 3933 mac->mac_flags &= ~BWN_MAC_FLAG_WME; 3934 } 3935 } 3936 3937 if (BWN_ISOLDFMT(mac)) 3938 device_printf(sc->sc_dev, "using old firmware image\n"); 3939 3940 return (0); 3941 3942error: 3943 BWN_WRITE_4(mac, BWN_MACCTL, 3944 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) | 3945 BWN_MACCTL_MCODE_JMP0); 3946 3947 return (error); 3948#undef GETFWSIZE 3949#undef GETFWOFFSET 3950} 3951 3952/* OpenFirmware only */ 3953static uint16_t 3954bwn_fwcaps_read(struct bwn_mac *mac) 3955{ 3956 3957 KASSERT(mac->mac_fw.opensource == 1, 3958 ("%s:%d: fail", __func__, __LINE__)); 3959 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS)); 3960} 3961 3962static int 3963bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals, 3964 size_t count, size_t array_size) 3965{ 3966#define GET_NEXTIV16(iv) \ 3967 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 3968 sizeof(uint16_t) + sizeof(uint16_t))) 3969#define GET_NEXTIV32(iv) \ 3970 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 3971 sizeof(uint16_t) + sizeof(uint32_t))) 3972 struct bwn_softc *sc = mac->mac_sc; 3973 const struct bwn_fwinitvals *iv; 3974 uint16_t offset; 3975 size_t i; 3976 uint8_t bit32; 3977 3978 KASSERT(sizeof(struct bwn_fwinitvals) == 6, 3979 ("%s:%d: fail", __func__, __LINE__)); 3980 iv = ivals; 3981 for (i = 0; i < count; i++) { 3982 if (array_size < sizeof(iv->offset_size)) 3983 goto fail; 3984 array_size -= sizeof(iv->offset_size); 3985 offset = be16toh(iv->offset_size); 3986 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0; 3987 offset &= BWN_FWINITVALS_OFFSET_MASK; 3988 if (offset >= 0x1000) 3989 goto fail; 3990 if (bit32) { 3991 if (array_size < sizeof(iv->data.d32)) 3992 goto fail; 3993 array_size -= sizeof(iv->data.d32); 3994 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32)); 3995 iv = GET_NEXTIV32(iv); 3996 } else { 3997 3998 if (array_size < sizeof(iv->data.d16)) 3999 goto fail; 4000 array_size -= sizeof(iv->data.d16); 4001 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16)); 4002 4003 iv = GET_NEXTIV16(iv); 4004 } 4005 } 4006 if (array_size != 0) 4007 goto fail; 4008 return (0); 4009fail: 4010 device_printf(sc->sc_dev, "initvals: invalid format\n"); 4011 return (EPROTO); 4012#undef GET_NEXTIV16 4013#undef GET_NEXTIV32 4014} 4015 4016int 4017bwn_switch_channel(struct bwn_mac *mac, int chan) 4018{ 4019 struct bwn_phy *phy = &(mac->mac_phy); 4020 struct bwn_softc *sc = mac->mac_sc; 4021 struct ieee80211com *ic = &sc->sc_ic; 4022 uint16_t channelcookie, savedcookie; 4023 int error; 4024 4025 if (chan == 0xffff) 4026 chan = phy->get_default_chan(mac); 4027 4028 channelcookie = chan; 4029 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4030 channelcookie |= 0x100; 4031 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN); 4032 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie); 4033 error = phy->switch_channel(mac, chan); 4034 if (error) 4035 goto fail; 4036 4037 mac->mac_phy.chan = chan; 4038 DELAY(8000); 4039 return (0); 4040fail: 4041 device_printf(sc->sc_dev, "failed to switch channel\n"); 4042 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie); 4043 return (error); 4044} 4045 4046static uint16_t 4047bwn_ant2phy(int antenna) 4048{ 4049 4050 switch (antenna) { 4051 case BWN_ANT0: 4052 return (BWN_TX_PHY_ANT0); 4053 case BWN_ANT1: 4054 return (BWN_TX_PHY_ANT1); 4055 case BWN_ANT2: 4056 return (BWN_TX_PHY_ANT2); 4057 case BWN_ANT3: 4058 return (BWN_TX_PHY_ANT3); 4059 case BWN_ANTAUTO: 4060 return (BWN_TX_PHY_ANT01AUTO); 4061 } 4062 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4063 return (0); 4064} 4065 4066static void 4067bwn_wme_load(struct bwn_mac *mac) 4068{ 4069 struct bwn_softc *sc = mac->mac_sc; 4070 int i; 4071 4072 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 4073 ("%s:%d: fail", __func__, __LINE__)); 4074 4075 bwn_mac_suspend(mac); 4076 for (i = 0; i < N(sc->sc_wmeParams); i++) 4077 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]), 4078 bwn_wme_shm_offsets[i]); 4079 bwn_mac_enable(mac); 4080} 4081 4082static void 4083bwn_wme_loadparams(struct bwn_mac *mac, 4084 const struct wmeParams *p, uint16_t shm_offset) 4085{ 4086#define SM(_v, _f) (((_v) << _f##_S) & _f) 4087 struct bwn_softc *sc = mac->mac_sc; 4088 uint16_t params[BWN_NR_WMEPARAMS]; 4089 int slot, tmp; 4090 unsigned int i; 4091 4092 slot = BWN_READ_2(mac, BWN_RNG) & 4093 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4094 4095 memset(¶ms, 0, sizeof(params)); 4096 4097 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d " 4098 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit, 4099 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn); 4100 4101 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32; 4102 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4103 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX); 4104 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4105 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn; 4106 params[BWN_WMEPARAM_BSLOTS] = slot; 4107 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn; 4108 4109 for (i = 0; i < N(params); i++) { 4110 if (i == BWN_WMEPARAM_STATUS) { 4111 tmp = bwn_shm_read_2(mac, BWN_SHARED, 4112 shm_offset + (i * 2)); 4113 tmp |= 0x100; 4114 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4115 tmp); 4116 } else { 4117 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4118 params[i]); 4119 } 4120 } 4121} 4122 4123static void 4124bwn_mac_write_bssid(struct bwn_mac *mac) 4125{ 4126 struct bwn_softc *sc = mac->mac_sc; 4127 uint32_t tmp; 4128 int i; 4129 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2]; 4130 4131 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid); 4132 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN); 4133 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid, 4134 IEEE80211_ADDR_LEN); 4135 4136 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) { 4137 tmp = (uint32_t) (mac_bssid[i + 0]); 4138 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8; 4139 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16; 4140 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24; 4141 bwn_ram_write(mac, 0x20 + i, tmp); 4142 } 4143} 4144 4145static void 4146bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset, 4147 const uint8_t *macaddr) 4148{ 4149 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 }; 4150 uint16_t data; 4151 4152 if (!mac) 4153 macaddr = zero; 4154 4155 offset |= 0x0020; 4156 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset); 4157 4158 data = macaddr[0]; 4159 data |= macaddr[1] << 8; 4160 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4161 data = macaddr[2]; 4162 data |= macaddr[3] << 8; 4163 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4164 data = macaddr[4]; 4165 data |= macaddr[5] << 8; 4166 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4167} 4168 4169static void 4170bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4171 const uint8_t *key, size_t key_len, const uint8_t *mac_addr) 4172{ 4173 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, }; 4174 uint8_t per_sta_keys_start = 8; 4175 4176 if (BWN_SEC_NEWAPI(mac)) 4177 per_sta_keys_start = 4; 4178 4179 KASSERT(index < mac->mac_max_nr_keys, 4180 ("%s:%d: fail", __func__, __LINE__)); 4181 KASSERT(key_len <= BWN_SEC_KEYSIZE, 4182 ("%s:%d: fail", __func__, __LINE__)); 4183 4184 if (index >= per_sta_keys_start) 4185 bwn_key_macwrite(mac, index, NULL); 4186 if (key) 4187 memcpy(buf, key, key_len); 4188 bwn_key_write(mac, index, algorithm, buf); 4189 if (index >= per_sta_keys_start) 4190 bwn_key_macwrite(mac, index, mac_addr); 4191 4192 mac->mac_key[index].algorithm = algorithm; 4193} 4194 4195static void 4196bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr) 4197{ 4198 struct bwn_softc *sc = mac->mac_sc; 4199 uint32_t addrtmp[2] = { 0, 0 }; 4200 uint8_t start = 8; 4201 4202 if (BWN_SEC_NEWAPI(mac)) 4203 start = 4; 4204 4205 KASSERT(index >= start, 4206 ("%s:%d: fail", __func__, __LINE__)); 4207 index -= start; 4208 4209 if (addr) { 4210 addrtmp[0] = addr[0]; 4211 addrtmp[0] |= ((uint32_t) (addr[1]) << 8); 4212 addrtmp[0] |= ((uint32_t) (addr[2]) << 16); 4213 addrtmp[0] |= ((uint32_t) (addr[3]) << 24); 4214 addrtmp[1] = addr[4]; 4215 addrtmp[1] |= ((uint32_t) (addr[5]) << 8); 4216 } 4217 4218 if (siba_get_revid(sc->sc_dev) >= 5) { 4219 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]); 4220 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]); 4221 } else { 4222 if (index >= 8) { 4223 bwn_shm_write_4(mac, BWN_SHARED, 4224 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]); 4225 bwn_shm_write_2(mac, BWN_SHARED, 4226 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]); 4227 } 4228 } 4229} 4230 4231static void 4232bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4233 const uint8_t *key) 4234{ 4235 unsigned int i; 4236 uint32_t offset; 4237 uint16_t kidx, value; 4238 4239 kidx = BWN_SEC_KEY2FW(mac, index); 4240 bwn_shm_write_2(mac, BWN_SHARED, 4241 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm); 4242 4243 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE); 4244 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) { 4245 value = key[i]; 4246 value |= (uint16_t)(key[i + 1]) << 8; 4247 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value); 4248 } 4249} 4250 4251static void 4252bwn_phy_exit(struct bwn_mac *mac) 4253{ 4254 4255 mac->mac_phy.rf_onoff(mac, 0); 4256 if (mac->mac_phy.exit != NULL) 4257 mac->mac_phy.exit(mac); 4258} 4259 4260static void 4261bwn_dma_free(struct bwn_mac *mac) 4262{ 4263 struct bwn_dma *dma; 4264 4265 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 4266 return; 4267 dma = &mac->mac_method.dma; 4268 4269 bwn_dma_ringfree(&dma->rx); 4270 bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 4271 bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 4272 bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 4273 bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 4274 bwn_dma_ringfree(&dma->mcast); 4275} 4276 4277static void 4278bwn_core_stop(struct bwn_mac *mac) 4279{ 4280 struct bwn_softc *sc = mac->mac_sc; 4281 4282 BWN_ASSERT_LOCKED(sc); 4283 4284 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 4285 return; 4286 4287 callout_stop(&sc->sc_rfswitch_ch); 4288 callout_stop(&sc->sc_task_ch); 4289 callout_stop(&sc->sc_watchdog_ch); 4290 sc->sc_watchdog_timer = 0; 4291 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4292 BWN_READ_4(mac, BWN_INTR_MASK); 4293 bwn_mac_suspend(mac); 4294 4295 mac->mac_status = BWN_MAC_STATUS_INITED; 4296} 4297 4298static int 4299bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan) 4300{ 4301 struct bwn_mac *up_dev = NULL; 4302 struct bwn_mac *down_dev; 4303 struct bwn_mac *mac; 4304 int err, status; 4305 uint8_t gmode; 4306 4307 BWN_ASSERT_LOCKED(sc); 4308 4309 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) { 4310 if (IEEE80211_IS_CHAN_2GHZ(chan) && 4311 mac->mac_phy.supports_2ghz) { 4312 up_dev = mac; 4313 gmode = 1; 4314 } else if (IEEE80211_IS_CHAN_5GHZ(chan) && 4315 mac->mac_phy.supports_5ghz) { 4316 up_dev = mac; 4317 gmode = 0; 4318 } else { 4319 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4320 return (EINVAL); 4321 } 4322 if (up_dev != NULL) 4323 break; 4324 } 4325 if (up_dev == NULL) { 4326 device_printf(sc->sc_dev, "Could not find a device\n"); 4327 return (ENODEV); 4328 } 4329 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode) 4330 return (0); 4331 4332 device_printf(sc->sc_dev, "switching to %s-GHz band\n", 4333 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4334 4335 down_dev = sc->sc_curmac; 4336 status = down_dev->mac_status; 4337 if (status >= BWN_MAC_STATUS_STARTED) 4338 bwn_core_stop(down_dev); 4339 if (status >= BWN_MAC_STATUS_INITED) 4340 bwn_core_exit(down_dev); 4341 4342 if (down_dev != up_dev) 4343 bwn_phy_reset(down_dev); 4344 4345 up_dev->mac_phy.gmode = gmode; 4346 if (status >= BWN_MAC_STATUS_INITED) { 4347 err = bwn_core_init(up_dev); 4348 if (err) { 4349 device_printf(sc->sc_dev, 4350 "fatal: failed to initialize for %s-GHz\n", 4351 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4352 goto fail; 4353 } 4354 } 4355 if (status >= BWN_MAC_STATUS_STARTED) 4356 bwn_core_start(up_dev); 4357 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__)); 4358 sc->sc_curmac = up_dev; 4359 4360 return (0); 4361fail: 4362 sc->sc_curmac = NULL; 4363 return (err); 4364} 4365 4366static void 4367bwn_rf_turnon(struct bwn_mac *mac) 4368{ 4369 4370 bwn_mac_suspend(mac); 4371 mac->mac_phy.rf_onoff(mac, 1); 4372 mac->mac_phy.rf_on = 1; 4373 bwn_mac_enable(mac); 4374} 4375 4376static void 4377bwn_rf_turnoff(struct bwn_mac *mac) 4378{ 4379 4380 bwn_mac_suspend(mac); 4381 mac->mac_phy.rf_onoff(mac, 0); 4382 mac->mac_phy.rf_on = 0; 4383 bwn_mac_enable(mac); 4384} 4385 4386static void 4387bwn_phy_reset(struct bwn_mac *mac) 4388{ 4389 struct bwn_softc *sc = mac->mac_sc; 4390 4391 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 4392 ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) | 4393 BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC); 4394 DELAY(1000); 4395 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 4396 (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC) | 4397 BWN_TGSLOW_PHYRESET); 4398 DELAY(1000); 4399} 4400 4401static int 4402bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4403{ 4404 struct bwn_vap *bvp = BWN_VAP(vap); 4405 struct ieee80211com *ic= vap->iv_ic; 4406 enum ieee80211_state ostate = vap->iv_state; 4407 struct bwn_softc *sc = ic->ic_softc; 4408 struct bwn_mac *mac = sc->sc_curmac; 4409 int error; 4410 4411 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4412 ieee80211_state_name[vap->iv_state], 4413 ieee80211_state_name[nstate]); 4414 4415 error = bvp->bv_newstate(vap, nstate, arg); 4416 if (error != 0) 4417 return (error); 4418 4419 BWN_LOCK(sc); 4420 4421 bwn_led_newstate(mac, nstate); 4422 4423 /* 4424 * Clear the BSSID when we stop a STA 4425 */ 4426 if (vap->iv_opmode == IEEE80211_M_STA) { 4427 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 4428 /* 4429 * Clear out the BSSID. If we reassociate to 4430 * the same AP, this will reinialize things 4431 * correctly... 4432 */ 4433 if (ic->ic_opmode == IEEE80211_M_STA && 4434 (sc->sc_flags & BWN_FLAG_INVALID) == 0) { 4435 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 4436 bwn_set_macaddr(mac); 4437 } 4438 } 4439 } 4440 4441 if (vap->iv_opmode == IEEE80211_M_MONITOR || 4442 vap->iv_opmode == IEEE80211_M_AHDEMO) { 4443 /* XXX nothing to do? */ 4444 } else if (nstate == IEEE80211_S_RUN) { 4445 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN); 4446 bwn_set_opmode(mac); 4447 bwn_set_pretbtt(mac); 4448 bwn_spu_setdelay(mac, 0); 4449 bwn_set_macaddr(mac); 4450 } 4451 4452 BWN_UNLOCK(sc); 4453 4454 return (error); 4455} 4456 4457static void 4458bwn_set_pretbtt(struct bwn_mac *mac) 4459{ 4460 struct bwn_softc *sc = mac->mac_sc; 4461 struct ieee80211com *ic = &sc->sc_ic; 4462 uint16_t pretbtt; 4463 4464 if (ic->ic_opmode == IEEE80211_M_IBSS) 4465 pretbtt = 2; 4466 else 4467 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250; 4468 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt); 4469 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt); 4470} 4471 4472static int 4473bwn_intr(void *arg) 4474{ 4475 struct bwn_mac *mac = arg; 4476 struct bwn_softc *sc = mac->mac_sc; 4477 uint32_t reason; 4478 4479 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 4480 (sc->sc_flags & BWN_FLAG_INVALID)) 4481 return (FILTER_STRAY); 4482 4483 reason = BWN_READ_4(mac, BWN_INTR_REASON); 4484 if (reason == 0xffffffff) /* shared IRQ */ 4485 return (FILTER_STRAY); 4486 reason &= mac->mac_intr_mask; 4487 if (reason == 0) 4488 return (FILTER_HANDLED); 4489 4490 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00; 4491 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00; 4492 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00; 4493 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00; 4494 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00; 4495 BWN_WRITE_4(mac, BWN_INTR_REASON, reason); 4496 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]); 4497 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]); 4498 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]); 4499 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]); 4500 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]); 4501 4502 /* Disable interrupts. */ 4503 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4504 4505 mac->mac_reason_intr = reason; 4506 4507 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); 4508 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 4509 4510 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask); 4511 return (FILTER_HANDLED); 4512} 4513 4514static void 4515bwn_intrtask(void *arg, int npending) 4516{ 4517 struct bwn_mac *mac = arg; 4518 struct bwn_softc *sc = mac->mac_sc; 4519 uint32_t merged = 0; 4520 int i, tx = 0, rx = 0; 4521 4522 BWN_LOCK(sc); 4523 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 4524 (sc->sc_flags & BWN_FLAG_INVALID)) { 4525 BWN_UNLOCK(sc); 4526 return; 4527 } 4528 4529 for (i = 0; i < N(mac->mac_reason); i++) 4530 merged |= mac->mac_reason[i]; 4531 4532 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR) 4533 device_printf(sc->sc_dev, "MAC trans error\n"); 4534 4535 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) { 4536 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__); 4537 mac->mac_phy.txerrors--; 4538 if (mac->mac_phy.txerrors == 0) { 4539 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 4540 bwn_restart(mac, "PHY TX errors"); 4541 } 4542 } 4543 4544 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) { 4545 if (merged & BWN_DMAINTR_FATALMASK) { 4546 device_printf(sc->sc_dev, 4547 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n", 4548 mac->mac_reason[0], mac->mac_reason[1], 4549 mac->mac_reason[2], mac->mac_reason[3], 4550 mac->mac_reason[4], mac->mac_reason[5]); 4551 bwn_restart(mac, "DMA error"); 4552 BWN_UNLOCK(sc); 4553 return; 4554 } 4555 if (merged & BWN_DMAINTR_NONFATALMASK) { 4556 device_printf(sc->sc_dev, 4557 "DMA error: %#x %#x %#x %#x %#x %#x\n", 4558 mac->mac_reason[0], mac->mac_reason[1], 4559 mac->mac_reason[2], mac->mac_reason[3], 4560 mac->mac_reason[4], mac->mac_reason[5]); 4561 } 4562 } 4563 4564 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG) 4565 bwn_intr_ucode_debug(mac); 4566 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI) 4567 bwn_intr_tbtt_indication(mac); 4568 if (mac->mac_reason_intr & BWN_INTR_ATIM_END) 4569 bwn_intr_atim_end(mac); 4570 if (mac->mac_reason_intr & BWN_INTR_BEACON) 4571 bwn_intr_beacon(mac); 4572 if (mac->mac_reason_intr & BWN_INTR_PMQ) 4573 bwn_intr_pmq(mac); 4574 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK) 4575 bwn_intr_noise(mac); 4576 4577 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 4578 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) { 4579 bwn_dma_rx(mac->mac_method.dma.rx); 4580 rx = 1; 4581 } 4582 } else 4583 rx = bwn_pio_rx(&mac->mac_method.pio.rx); 4584 4585 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4586 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4587 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4588 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4589 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4590 4591 if (mac->mac_reason_intr & BWN_INTR_TX_OK) { 4592 bwn_intr_txeof(mac); 4593 tx = 1; 4594 } 4595 4596 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 4597 4598 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 4599 int evt = BWN_LED_EVENT_NONE; 4600 4601 if (tx && rx) { 4602 if (sc->sc_rx_rate > sc->sc_tx_rate) 4603 evt = BWN_LED_EVENT_RX; 4604 else 4605 evt = BWN_LED_EVENT_TX; 4606 } else if (tx) { 4607 evt = BWN_LED_EVENT_TX; 4608 } else if (rx) { 4609 evt = BWN_LED_EVENT_RX; 4610 } else if (rx == 0) { 4611 evt = BWN_LED_EVENT_POLL; 4612 } 4613 4614 if (evt != BWN_LED_EVENT_NONE) 4615 bwn_led_event(mac, evt); 4616 } 4617 4618 if (mbufq_first(&sc->sc_snd) != NULL) 4619 bwn_start(sc); 4620 4621 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); 4622 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 4623 4624 BWN_UNLOCK(sc); 4625} 4626 4627static void 4628bwn_restart(struct bwn_mac *mac, const char *msg) 4629{ 4630 struct bwn_softc *sc = mac->mac_sc; 4631 struct ieee80211com *ic = &sc->sc_ic; 4632 4633 if (mac->mac_status < BWN_MAC_STATUS_INITED) 4634 return; 4635 4636 device_printf(sc->sc_dev, "HW reset: %s\n", msg); 4637 ieee80211_runtask(ic, &mac->mac_hwreset); 4638} 4639 4640static void 4641bwn_intr_ucode_debug(struct bwn_mac *mac) 4642{ 4643 struct bwn_softc *sc = mac->mac_sc; 4644 uint16_t reason; 4645 4646 if (mac->mac_fw.opensource == 0) 4647 return; 4648 4649 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG); 4650 switch (reason) { 4651 case BWN_DEBUGINTR_PANIC: 4652 bwn_handle_fwpanic(mac); 4653 break; 4654 case BWN_DEBUGINTR_DUMP_SHM: 4655 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n"); 4656 break; 4657 case BWN_DEBUGINTR_DUMP_REGS: 4658 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n"); 4659 break; 4660 case BWN_DEBUGINTR_MARKER: 4661 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n"); 4662 break; 4663 default: 4664 device_printf(sc->sc_dev, 4665 "ucode debug unknown reason: %#x\n", reason); 4666 } 4667 4668 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG, 4669 BWN_DEBUGINTR_ACK); 4670} 4671 4672static void 4673bwn_intr_tbtt_indication(struct bwn_mac *mac) 4674{ 4675 struct bwn_softc *sc = mac->mac_sc; 4676 struct ieee80211com *ic = &sc->sc_ic; 4677 4678 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 4679 bwn_psctl(mac, 0); 4680 if (ic->ic_opmode == IEEE80211_M_IBSS) 4681 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID; 4682} 4683 4684static void 4685bwn_intr_atim_end(struct bwn_mac *mac) 4686{ 4687 4688 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) { 4689 BWN_WRITE_4(mac, BWN_MACCMD, 4690 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID); 4691 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 4692 } 4693} 4694 4695static void 4696bwn_intr_beacon(struct bwn_mac *mac) 4697{ 4698 struct bwn_softc *sc = mac->mac_sc; 4699 struct ieee80211com *ic = &sc->sc_ic; 4700 uint32_t cmd, beacon0, beacon1; 4701 4702 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 4703 ic->ic_opmode == IEEE80211_M_MBSS) 4704 return; 4705 4706 mac->mac_intr_mask &= ~BWN_INTR_BEACON; 4707 4708 cmd = BWN_READ_4(mac, BWN_MACCMD); 4709 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID); 4710 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID); 4711 4712 if (beacon0 && beacon1) { 4713 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON); 4714 mac->mac_intr_mask |= BWN_INTR_BEACON; 4715 return; 4716 } 4717 4718 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) { 4719 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP; 4720 bwn_load_beacon0(mac); 4721 bwn_load_beacon1(mac); 4722 cmd = BWN_READ_4(mac, BWN_MACCMD); 4723 cmd |= BWN_MACCMD_BEACON0_VALID; 4724 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 4725 } else { 4726 if (!beacon0) { 4727 bwn_load_beacon0(mac); 4728 cmd = BWN_READ_4(mac, BWN_MACCMD); 4729 cmd |= BWN_MACCMD_BEACON0_VALID; 4730 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 4731 } else if (!beacon1) { 4732 bwn_load_beacon1(mac); 4733 cmd = BWN_READ_4(mac, BWN_MACCMD); 4734 cmd |= BWN_MACCMD_BEACON1_VALID; 4735 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 4736 } 4737 } 4738} 4739 4740static void 4741bwn_intr_pmq(struct bwn_mac *mac) 4742{ 4743 uint32_t tmp; 4744 4745 while (1) { 4746 tmp = BWN_READ_4(mac, BWN_PS_STATUS); 4747 if (!(tmp & 0x00000008)) 4748 break; 4749 } 4750 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002); 4751} 4752 4753static void 4754bwn_intr_noise(struct bwn_mac *mac) 4755{ 4756 struct bwn_phy_g *pg = &mac->mac_phy.phy_g; 4757 uint16_t tmp; 4758 uint8_t noise[4]; 4759 uint8_t i, j; 4760 int32_t average; 4761 4762 if (mac->mac_phy.type != BWN_PHYTYPE_G) 4763 return; 4764 4765 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__)); 4766 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac)); 4767 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f || 4768 noise[3] == 0x7f) 4769 goto new; 4770 4771 KASSERT(mac->mac_noise.noi_nsamples < 8, 4772 ("%s:%d: fail", __func__, __LINE__)); 4773 i = mac->mac_noise.noi_nsamples; 4774 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1); 4775 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1); 4776 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1); 4777 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1); 4778 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]]; 4779 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]]; 4780 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]]; 4781 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]]; 4782 mac->mac_noise.noi_nsamples++; 4783 if (mac->mac_noise.noi_nsamples == 8) { 4784 average = 0; 4785 for (i = 0; i < 8; i++) { 4786 for (j = 0; j < 4; j++) 4787 average += mac->mac_noise.noi_samples[i][j]; 4788 } 4789 average = (((average / 32) * 125) + 64) / 128; 4790 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f; 4791 if (tmp >= 8) 4792 average += 2; 4793 else 4794 average -= 25; 4795 average -= (tmp == 8) ? 72 : 48; 4796 4797 mac->mac_stats.link_noise = average; 4798 mac->mac_noise.noi_running = 0; 4799 return; 4800 } 4801new: 4802 bwn_noise_gensample(mac); 4803} 4804 4805static int 4806bwn_pio_rx(struct bwn_pio_rxqueue *prq) 4807{ 4808 struct bwn_mac *mac = prq->prq_mac; 4809 struct bwn_softc *sc = mac->mac_sc; 4810 unsigned int i; 4811 4812 BWN_ASSERT_LOCKED(sc); 4813 4814 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 4815 return (0); 4816 4817 for (i = 0; i < 5000; i++) { 4818 if (bwn_pio_rxeof(prq) == 0) 4819 break; 4820 } 4821 if (i >= 5000) 4822 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n"); 4823 return ((i > 0) ? 1 : 0); 4824} 4825 4826static void 4827bwn_dma_rx(struct bwn_dma_ring *dr) 4828{ 4829 int slot, curslot; 4830 4831 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 4832 curslot = dr->get_curslot(dr); 4833 KASSERT(curslot >= 0 && curslot < dr->dr_numslots, 4834 ("%s:%d: fail", __func__, __LINE__)); 4835 4836 slot = dr->dr_curslot; 4837 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot)) 4838 bwn_dma_rxeof(dr, &slot); 4839 4840 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 4841 BUS_DMASYNC_PREWRITE); 4842 4843 dr->set_curslot(dr, slot); 4844 dr->dr_curslot = slot; 4845} 4846 4847static void 4848bwn_intr_txeof(struct bwn_mac *mac) 4849{ 4850 struct bwn_txstatus stat; 4851 uint32_t stat0, stat1; 4852 uint16_t tmp; 4853 4854 BWN_ASSERT_LOCKED(mac->mac_sc); 4855 4856 while (1) { 4857 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0); 4858 if (!(stat0 & 0x00000001)) 4859 break; 4860 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1); 4861 4862 stat.cookie = (stat0 >> 16); 4863 stat.seq = (stat1 & 0x0000ffff); 4864 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16); 4865 tmp = (stat0 & 0x0000ffff); 4866 stat.framecnt = ((tmp & 0xf000) >> 12); 4867 stat.rtscnt = ((tmp & 0x0f00) >> 8); 4868 stat.sreason = ((tmp & 0x001c) >> 2); 4869 stat.pm = (tmp & 0x0080) ? 1 : 0; 4870 stat.im = (tmp & 0x0040) ? 1 : 0; 4871 stat.ampdu = (tmp & 0x0020) ? 1 : 0; 4872 stat.ack = (tmp & 0x0002) ? 1 : 0; 4873 4874 bwn_handle_txeof(mac, &stat); 4875 } 4876} 4877 4878static void 4879bwn_hwreset(void *arg, int npending) 4880{ 4881 struct bwn_mac *mac = arg; 4882 struct bwn_softc *sc = mac->mac_sc; 4883 int error = 0; 4884 int prev_status; 4885 4886 BWN_LOCK(sc); 4887 4888 prev_status = mac->mac_status; 4889 if (prev_status >= BWN_MAC_STATUS_STARTED) 4890 bwn_core_stop(mac); 4891 if (prev_status >= BWN_MAC_STATUS_INITED) 4892 bwn_core_exit(mac); 4893 4894 if (prev_status >= BWN_MAC_STATUS_INITED) { 4895 error = bwn_core_init(mac); 4896 if (error) 4897 goto out; 4898 } 4899 if (prev_status >= BWN_MAC_STATUS_STARTED) 4900 bwn_core_start(mac); 4901out: 4902 if (error) { 4903 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error); 4904 sc->sc_curmac = NULL; 4905 } 4906 BWN_UNLOCK(sc); 4907} 4908 4909static void 4910bwn_handle_fwpanic(struct bwn_mac *mac) 4911{ 4912 struct bwn_softc *sc = mac->mac_sc; 4913 uint16_t reason; 4914 4915 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG); 4916 device_printf(sc->sc_dev,"fw panic (%u)\n", reason); 4917 4918 if (reason == BWN_FWPANIC_RESTART) 4919 bwn_restart(mac, "ucode panic"); 4920} 4921 4922static void 4923bwn_load_beacon0(struct bwn_mac *mac) 4924{ 4925 4926 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4927} 4928 4929static void 4930bwn_load_beacon1(struct bwn_mac *mac) 4931{ 4932 4933 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4934} 4935 4936static uint32_t 4937bwn_jssi_read(struct bwn_mac *mac) 4938{ 4939 uint32_t val = 0; 4940 4941 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a); 4942 val <<= 16; 4943 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088); 4944 4945 return (val); 4946} 4947 4948static void 4949bwn_noise_gensample(struct bwn_mac *mac) 4950{ 4951 uint32_t jssi = 0x7f7f7f7f; 4952 4953 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff)); 4954 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16); 4955 BWN_WRITE_4(mac, BWN_MACCMD, 4956 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE); 4957} 4958 4959static int 4960bwn_dma_freeslot(struct bwn_dma_ring *dr) 4961{ 4962 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 4963 4964 return (dr->dr_numslots - dr->dr_usedslot); 4965} 4966 4967static int 4968bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot) 4969{ 4970 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 4971 4972 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1, 4973 ("%s:%d: fail", __func__, __LINE__)); 4974 if (slot == dr->dr_numslots - 1) 4975 return (0); 4976 return (slot + 1); 4977} 4978 4979static void 4980bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot) 4981{ 4982 struct bwn_mac *mac = dr->dr_mac; 4983 struct bwn_softc *sc = mac->mac_sc; 4984 struct bwn_dma *dma = &mac->mac_method.dma; 4985 struct bwn_dmadesc_generic *desc; 4986 struct bwn_dmadesc_meta *meta; 4987 struct bwn_rxhdr4 *rxhdr; 4988 struct mbuf *m; 4989 uint32_t macstat; 4990 int32_t tmp; 4991 int cnt = 0; 4992 uint16_t len; 4993 4994 dr->getdesc(dr, *slot, &desc, &meta); 4995 4996 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD); 4997 m = meta->mt_m; 4998 4999 if (bwn_dma_newbuf(dr, desc, meta, 0)) { 5000 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5001 return; 5002 } 5003 5004 rxhdr = mtod(m, struct bwn_rxhdr4 *); 5005 len = le16toh(rxhdr->frame_len); 5006 if (len <= 0) { 5007 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5008 return; 5009 } 5010 if (bwn_dma_check_redzone(dr, m)) { 5011 device_printf(sc->sc_dev, "redzone error.\n"); 5012 bwn_dma_set_redzone(dr, m); 5013 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5014 BUS_DMASYNC_PREWRITE); 5015 return; 5016 } 5017 if (len > dr->dr_rx_bufsize) { 5018 tmp = len; 5019 while (1) { 5020 dr->getdesc(dr, *slot, &desc, &meta); 5021 bwn_dma_set_redzone(dr, meta->mt_m); 5022 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5023 BUS_DMASYNC_PREWRITE); 5024 *slot = bwn_dma_nextslot(dr, *slot); 5025 cnt++; 5026 tmp -= dr->dr_rx_bufsize; 5027 if (tmp <= 0) 5028 break; 5029 } 5030 device_printf(sc->sc_dev, "too small buffer " 5031 "(len %u buffer %u dropped %d)\n", 5032 len, dr->dr_rx_bufsize, cnt); 5033 return; 5034 } 5035 macstat = le32toh(rxhdr->mac_status); 5036 if (macstat & BWN_RX_MAC_FCSERR) { 5037 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5038 device_printf(sc->sc_dev, "RX drop\n"); 5039 return; 5040 } 5041 } 5042 5043 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset; 5044 m_adj(m, dr->dr_frameoffset); 5045 5046 bwn_rxeof(dr->dr_mac, m, rxhdr); 5047} 5048 5049static void 5050bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) 5051{ 5052 struct bwn_dma_ring *dr; 5053 struct bwn_dmadesc_generic *desc; 5054 struct bwn_dmadesc_meta *meta; 5055 struct bwn_pio_txqueue *tq; 5056 struct bwn_pio_txpkt *tp = NULL; 5057 struct bwn_softc *sc = mac->mac_sc; 5058 struct bwn_stats *stats = &mac->mac_stats; 5059 struct ieee80211_node *ni; 5060 struct ieee80211vap *vap; 5061 int retrycnt = 0, slot; 5062 5063 BWN_ASSERT_LOCKED(mac->mac_sc); 5064 5065 if (status->im) 5066 device_printf(sc->sc_dev, "TODO: STATUS IM\n"); 5067 if (status->ampdu) 5068 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n"); 5069 if (status->rtscnt) { 5070 if (status->rtscnt == 0xf) 5071 stats->rtsfail++; 5072 else 5073 stats->rts++; 5074 } 5075 5076 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 5077 if (status->ack) { 5078 dr = bwn_dma_parse_cookie(mac, status, 5079 status->cookie, &slot); 5080 if (dr == NULL) { 5081 device_printf(sc->sc_dev, 5082 "failed to parse cookie\n"); 5083 return; 5084 } 5085 while (1) { 5086 dr->getdesc(dr, slot, &desc, &meta); 5087 if (meta->mt_islast) { 5088 ni = meta->mt_ni; 5089 vap = ni->ni_vap; 5090 ieee80211_ratectl_tx_complete(vap, ni, 5091 status->ack ? 5092 IEEE80211_RATECTL_TX_SUCCESS : 5093 IEEE80211_RATECTL_TX_FAILURE, 5094 &retrycnt, 0); 5095 break; 5096 } 5097 slot = bwn_dma_nextslot(dr, slot); 5098 } 5099 } 5100 bwn_dma_handle_txeof(mac, status); 5101 } else { 5102 if (status->ack) { 5103 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp); 5104 if (tq == NULL) { 5105 device_printf(sc->sc_dev, 5106 "failed to parse cookie\n"); 5107 return; 5108 } 5109 ni = tp->tp_ni; 5110 vap = ni->ni_vap; 5111 ieee80211_ratectl_tx_complete(vap, ni, 5112 status->ack ? 5113 IEEE80211_RATECTL_TX_SUCCESS : 5114 IEEE80211_RATECTL_TX_FAILURE, 5115 &retrycnt, 0); 5116 } 5117 bwn_pio_handle_txeof(mac, status); 5118 } 5119 5120 bwn_phy_txpower_check(mac, 0); 5121} 5122 5123static uint8_t 5124bwn_pio_rxeof(struct bwn_pio_rxqueue *prq) 5125{ 5126 struct bwn_mac *mac = prq->prq_mac; 5127 struct bwn_softc *sc = mac->mac_sc; 5128 struct bwn_rxhdr4 rxhdr; 5129 struct mbuf *m; 5130 uint32_t ctl32, macstat, v32; 5131 unsigned int i, padding; 5132 uint16_t ctl16, len, totlen, v16; 5133 unsigned char *mp; 5134 char *data; 5135 5136 memset(&rxhdr, 0, sizeof(rxhdr)); 5137 5138 if (prq->prq_rev >= 8) { 5139 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5140 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY)) 5141 return (0); 5142 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5143 BWN_PIO8_RXCTL_FRAMEREADY); 5144 for (i = 0; i < 10; i++) { 5145 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5146 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY) 5147 goto ready; 5148 DELAY(10); 5149 } 5150 } else { 5151 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5152 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY)) 5153 return (0); 5154 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, 5155 BWN_PIO_RXCTL_FRAMEREADY); 5156 for (i = 0; i < 10; i++) { 5157 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5158 if (ctl16 & BWN_PIO_RXCTL_DATAREADY) 5159 goto ready; 5160 DELAY(10); 5161 } 5162 } 5163 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 5164 return (1); 5165ready: 5166 if (prq->prq_rev >= 8) 5167 siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr), 5168 prq->prq_base + BWN_PIO8_RXDATA); 5169 else 5170 siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr), 5171 prq->prq_base + BWN_PIO_RXDATA); 5172 len = le16toh(rxhdr.frame_len); 5173 if (len > 0x700) { 5174 device_printf(sc->sc_dev, "%s: len is too big\n", __func__); 5175 goto error; 5176 } 5177 if (len == 0) { 5178 device_printf(sc->sc_dev, "%s: len is 0\n", __func__); 5179 goto error; 5180 } 5181 5182 macstat = le32toh(rxhdr.mac_status); 5183 if (macstat & BWN_RX_MAC_FCSERR) { 5184 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5185 device_printf(sc->sc_dev, "%s: FCS error", __func__); 5186 goto error; 5187 } 5188 } 5189 5190 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5191 totlen = len + padding; 5192 KASSERT(totlen <= MCLBYTES, ("too big..\n")); 5193 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5194 if (m == NULL) { 5195 device_printf(sc->sc_dev, "%s: out of memory", __func__); 5196 goto error; 5197 } 5198 mp = mtod(m, unsigned char *); 5199 if (prq->prq_rev >= 8) { 5200 siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3), 5201 prq->prq_base + BWN_PIO8_RXDATA); 5202 if (totlen & 3) { 5203 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA); 5204 data = &(mp[totlen - 1]); 5205 switch (totlen & 3) { 5206 case 3: 5207 *data = (v32 >> 16); 5208 data--; 5209 case 2: 5210 *data = (v32 >> 8); 5211 data--; 5212 case 1: 5213 *data = v32; 5214 } 5215 } 5216 } else { 5217 siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1), 5218 prq->prq_base + BWN_PIO_RXDATA); 5219 if (totlen & 1) { 5220 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA); 5221 mp[totlen - 1] = v16; 5222 } 5223 } 5224 5225 m->m_len = m->m_pkthdr.len = totlen; 5226 5227 bwn_rxeof(prq->prq_mac, m, &rxhdr); 5228 5229 return (1); 5230error: 5231 if (prq->prq_rev >= 8) 5232 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5233 BWN_PIO8_RXCTL_DATAREADY); 5234 else 5235 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY); 5236 return (1); 5237} 5238 5239static int 5240bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, 5241 struct bwn_dmadesc_meta *meta, int init) 5242{ 5243 struct bwn_mac *mac = dr->dr_mac; 5244 struct bwn_dma *dma = &mac->mac_method.dma; 5245 struct bwn_rxhdr4 *hdr; 5246 bus_dmamap_t map; 5247 bus_addr_t paddr; 5248 struct mbuf *m; 5249 int error; 5250 5251 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5252 if (m == NULL) { 5253 error = ENOBUFS; 5254 5255 /* 5256 * If the NIC is up and running, we need to: 5257 * - Clear RX buffer's header. 5258 * - Restore RX descriptor settings. 5259 */ 5260 if (init) 5261 return (error); 5262 else 5263 goto back; 5264 } 5265 m->m_len = m->m_pkthdr.len = MCLBYTES; 5266 5267 bwn_dma_set_redzone(dr, m); 5268 5269 /* 5270 * Try to load RX buf into temporary DMA map 5271 */ 5272 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m, 5273 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 5274 if (error) { 5275 m_freem(m); 5276 5277 /* 5278 * See the comment above 5279 */ 5280 if (init) 5281 return (error); 5282 else 5283 goto back; 5284 } 5285 5286 if (!init) 5287 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 5288 meta->mt_m = m; 5289 meta->mt_paddr = paddr; 5290 5291 /* 5292 * Swap RX buf's DMA map with the loaded temporary one 5293 */ 5294 map = meta->mt_dmap; 5295 meta->mt_dmap = dr->dr_spare_dmap; 5296 dr->dr_spare_dmap = map; 5297 5298back: 5299 /* 5300 * Clear RX buf header 5301 */ 5302 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *); 5303 bzero(hdr, sizeof(*hdr)); 5304 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5305 BUS_DMASYNC_PREWRITE); 5306 5307 /* 5308 * Setup RX buf descriptor 5309 */ 5310 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len - 5311 sizeof(*hdr), 0, 0, 0); 5312 return (error); 5313} 5314 5315static void 5316bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 5317 bus_size_t mapsz __unused, int error) 5318{ 5319 5320 if (!error) { 5321 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 5322 *((bus_addr_t *)arg) = seg->ds_addr; 5323 } 5324} 5325 5326static int 5327bwn_hwrate2ieeerate(int rate) 5328{ 5329 5330 switch (rate) { 5331 case BWN_CCK_RATE_1MB: 5332 return (2); 5333 case BWN_CCK_RATE_2MB: 5334 return (4); 5335 case BWN_CCK_RATE_5MB: 5336 return (11); 5337 case BWN_CCK_RATE_11MB: 5338 return (22); 5339 case BWN_OFDM_RATE_6MB: 5340 return (12); 5341 case BWN_OFDM_RATE_9MB: 5342 return (18); 5343 case BWN_OFDM_RATE_12MB: 5344 return (24); 5345 case BWN_OFDM_RATE_18MB: 5346 return (36); 5347 case BWN_OFDM_RATE_24MB: 5348 return (48); 5349 case BWN_OFDM_RATE_36MB: 5350 return (72); 5351 case BWN_OFDM_RATE_48MB: 5352 return (96); 5353 case BWN_OFDM_RATE_54MB: 5354 return (108); 5355 default: 5356 printf("Ooops\n"); 5357 return (0); 5358 } 5359} 5360 5361static void 5362bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) 5363{ 5364 const struct bwn_rxhdr4 *rxhdr = _rxhdr; 5365 struct bwn_plcp6 *plcp; 5366 struct bwn_softc *sc = mac->mac_sc; 5367 struct ieee80211_frame_min *wh; 5368 struct ieee80211_node *ni; 5369 struct ieee80211com *ic = &sc->sc_ic; 5370 uint32_t macstat; 5371 int padding, rate, rssi = 0, noise = 0, type; 5372 uint16_t phytype, phystat0, phystat3, chanstat; 5373 unsigned char *mp = mtod(m, unsigned char *); 5374 static int rx_mac_dec_rpt = 0; 5375 5376 BWN_ASSERT_LOCKED(sc); 5377 5378 phystat0 = le16toh(rxhdr->phy_status0); 5379 phystat3 = le16toh(rxhdr->phy_status3); 5380 macstat = le32toh(rxhdr->mac_status); 5381 chanstat = le16toh(rxhdr->channel); 5382 phytype = chanstat & BWN_RX_CHAN_PHYTYPE; 5383 5384 if (macstat & BWN_RX_MAC_FCSERR) 5385 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n"); 5386 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV)) 5387 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n"); 5388 if (macstat & BWN_RX_MAC_DECERR) 5389 goto drop; 5390 5391 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5392 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) { 5393 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 5394 m->m_pkthdr.len); 5395 goto drop; 5396 } 5397 plcp = (struct bwn_plcp6 *)(mp + padding); 5398 m_adj(m, sizeof(struct bwn_plcp6) + padding); 5399 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 5400 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 5401 m->m_pkthdr.len); 5402 goto drop; 5403 } 5404 wh = mtod(m, struct ieee80211_frame_min *); 5405 5406 if (macstat & BWN_RX_MAC_DEC && rx_mac_dec_rpt++ < 50) 5407 device_printf(sc->sc_dev, 5408 "RX decryption attempted (old %d keyidx %#x)\n", 5409 BWN_ISOLDFMT(mac), 5410 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT); 5411 5412 /* XXX calculating RSSI & noise & antenna */ 5413 5414 if (phystat0 & BWN_RX_PHYST0_OFDM) 5415 rate = bwn_plcp_get_ofdmrate(mac, plcp, 5416 phytype == BWN_PHYTYPE_A); 5417 else 5418 rate = bwn_plcp_get_cckrate(mac, plcp); 5419 if (rate == -1) { 5420 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP)) 5421 goto drop; 5422 } 5423 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate); 5424 5425 /* RX radio tap */ 5426 if (ieee80211_radiotap_active(ic)) 5427 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise); 5428 m_adj(m, -IEEE80211_CRC_LEN); 5429 5430 rssi = rxhdr->phy.abg.rssi; /* XXX incorrect RSSI calculation? */ 5431 noise = mac->mac_stats.link_noise; 5432 5433 BWN_UNLOCK(sc); 5434 5435 ni = ieee80211_find_rxnode(ic, wh); 5436 if (ni != NULL) { 5437 type = ieee80211_input(ni, m, rssi, noise); 5438 ieee80211_free_node(ni); 5439 } else 5440 type = ieee80211_input_all(ic, m, rssi, noise); 5441 5442 BWN_LOCK(sc); 5443 return; 5444drop: 5445 device_printf(sc->sc_dev, "%s: dropped\n", __func__); 5446} 5447 5448static void 5449bwn_dma_handle_txeof(struct bwn_mac *mac, 5450 const struct bwn_txstatus *status) 5451{ 5452 struct bwn_dma *dma = &mac->mac_method.dma; 5453 struct bwn_dma_ring *dr; 5454 struct bwn_dmadesc_generic *desc; 5455 struct bwn_dmadesc_meta *meta; 5456 struct bwn_softc *sc = mac->mac_sc; 5457 int slot; 5458 5459 BWN_ASSERT_LOCKED(sc); 5460 5461 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot); 5462 if (dr == NULL) { 5463 device_printf(sc->sc_dev, "failed to parse cookie\n"); 5464 return; 5465 } 5466 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 5467 5468 while (1) { 5469 KASSERT(slot >= 0 && slot < dr->dr_numslots, 5470 ("%s:%d: fail", __func__, __LINE__)); 5471 dr->getdesc(dr, slot, &desc, &meta); 5472 5473 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 5474 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap); 5475 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 5476 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap); 5477 5478 if (meta->mt_islast) { 5479 KASSERT(meta->mt_m != NULL, 5480 ("%s:%d: fail", __func__, __LINE__)); 5481 5482 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0); 5483 meta->mt_ni = NULL; 5484 meta->mt_m = NULL; 5485 } else 5486 KASSERT(meta->mt_m == NULL, 5487 ("%s:%d: fail", __func__, __LINE__)); 5488 5489 dr->dr_usedslot--; 5490 if (meta->mt_islast) 5491 break; 5492 slot = bwn_dma_nextslot(dr, slot); 5493 } 5494 sc->sc_watchdog_timer = 0; 5495 if (dr->dr_stop) { 5496 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME, 5497 ("%s:%d: fail", __func__, __LINE__)); 5498 dr->dr_stop = 0; 5499 } 5500} 5501 5502static void 5503bwn_pio_handle_txeof(struct bwn_mac *mac, 5504 const struct bwn_txstatus *status) 5505{ 5506 struct bwn_pio_txqueue *tq; 5507 struct bwn_pio_txpkt *tp = NULL; 5508 struct bwn_softc *sc = mac->mac_sc; 5509 5510 BWN_ASSERT_LOCKED(sc); 5511 5512 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp); 5513 if (tq == NULL) 5514 return; 5515 5516 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 5517 tq->tq_free++; 5518 5519 if (tp->tp_ni != NULL) { 5520 /* 5521 * Do any tx complete callback. Note this must 5522 * be done before releasing the node reference. 5523 */ 5524 if (tp->tp_m->m_flags & M_TXCB) 5525 ieee80211_process_callback(tp->tp_ni, tp->tp_m, 0); 5526 ieee80211_free_node(tp->tp_ni); 5527 tp->tp_ni = NULL; 5528 } 5529 m_freem(tp->tp_m); 5530 tp->tp_m = NULL; 5531 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 5532 5533 sc->sc_watchdog_timer = 0; 5534} 5535 5536static void 5537bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags) 5538{ 5539 struct bwn_softc *sc = mac->mac_sc; 5540 struct bwn_phy *phy = &mac->mac_phy; 5541 struct ieee80211com *ic = &sc->sc_ic; 5542 unsigned long now; 5543 int result; 5544 5545 BWN_GETTIME(now); 5546 5547 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime)) 5548 return; 5549 phy->nexttime = now + 2 * 1000; 5550 5551 if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM && 5552 siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306) 5553 return; 5554 5555 if (phy->recalc_txpwr != NULL) { 5556 result = phy->recalc_txpwr(mac, 5557 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0); 5558 if (result == BWN_TXPWR_RES_DONE) 5559 return; 5560 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST, 5561 ("%s: fail", __func__)); 5562 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__)); 5563 5564 ieee80211_runtask(ic, &mac->mac_txpower); 5565 } 5566} 5567 5568static uint16_t 5569bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset) 5570{ 5571 5572 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset)); 5573} 5574 5575static uint32_t 5576bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset) 5577{ 5578 5579 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset)); 5580} 5581 5582static void 5583bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value) 5584{ 5585 5586 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value); 5587} 5588 5589static void 5590bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value) 5591{ 5592 5593 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value); 5594} 5595 5596static int 5597bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate) 5598{ 5599 5600 switch (rate) { 5601 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 5602 case 12: 5603 return (BWN_OFDM_RATE_6MB); 5604 case 18: 5605 return (BWN_OFDM_RATE_9MB); 5606 case 24: 5607 return (BWN_OFDM_RATE_12MB); 5608 case 36: 5609 return (BWN_OFDM_RATE_18MB); 5610 case 48: 5611 return (BWN_OFDM_RATE_24MB); 5612 case 72: 5613 return (BWN_OFDM_RATE_36MB); 5614 case 96: 5615 return (BWN_OFDM_RATE_48MB); 5616 case 108: 5617 return (BWN_OFDM_RATE_54MB); 5618 /* CCK rates (NB: not IEEE std, device-specific) */ 5619 case 2: 5620 return (BWN_CCK_RATE_1MB); 5621 case 4: 5622 return (BWN_CCK_RATE_2MB); 5623 case 11: 5624 return (BWN_CCK_RATE_5MB); 5625 case 22: 5626 return (BWN_CCK_RATE_11MB); 5627 } 5628 5629 device_printf(sc->sc_dev, "unsupported rate %d\n", rate); 5630 return (BWN_CCK_RATE_1MB); 5631} 5632 5633static int 5634bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, 5635 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie) 5636{ 5637 const struct bwn_phy *phy = &mac->mac_phy; 5638 struct bwn_softc *sc = mac->mac_sc; 5639 struct ieee80211_frame *wh; 5640 struct ieee80211_frame *protwh; 5641 struct ieee80211_frame_cts *cts; 5642 struct ieee80211_frame_rts *rts; 5643 const struct ieee80211_txparam *tp; 5644 struct ieee80211vap *vap = ni->ni_vap; 5645 struct ieee80211com *ic = &sc->sc_ic; 5646 struct mbuf *mprot; 5647 unsigned int len; 5648 uint32_t macctl = 0; 5649 int protdur, rts_rate, rts_rate_fb, ismcast, isshort, rix, type; 5650 uint16_t phyctl = 0; 5651 uint8_t rate, rate_fb; 5652 5653 wh = mtod(m, struct ieee80211_frame *); 5654 memset(txhdr, 0, sizeof(*txhdr)); 5655 5656 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 5657 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 5658 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 5659 5660 /* 5661 * Find TX rate 5662 */ 5663 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 5664 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) 5665 rate = rate_fb = tp->mgmtrate; 5666 else if (ismcast) 5667 rate = rate_fb = tp->mcastrate; 5668 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 5669 rate = rate_fb = tp->ucastrate; 5670 else { 5671 rix = ieee80211_ratectl_rate(ni, NULL, 0); 5672 rate = ni->ni_txrate; 5673 5674 if (rix > 0) 5675 rate_fb = ni->ni_rates.rs_rates[rix - 1] & 5676 IEEE80211_RATE_VAL; 5677 else 5678 rate_fb = rate; 5679 } 5680 5681 sc->sc_tx_rate = rate; 5682 5683 rate = bwn_ieeerate2hwrate(sc, rate); 5684 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb); 5685 5686 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) : 5687 bwn_plcp_getcck(rate); 5688 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc)); 5689 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN); 5690 5691 if ((rate_fb == rate) || 5692 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) || 5693 (*(u_int16_t *)wh->i_dur == htole16(0))) 5694 txhdr->dur_fb = *(u_int16_t *)wh->i_dur; 5695 else 5696 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt, 5697 m->m_pkthdr.len, rate, isshort); 5698 5699 /* XXX TX encryption */ 5700 bwn_plcp_genhdr(BWN_ISOLDFMT(mac) ? 5701 (struct bwn_plcp4 *)(&txhdr->body.old.plcp) : 5702 (struct bwn_plcp4 *)(&txhdr->body.new.plcp), 5703 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 5704 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb), 5705 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb); 5706 5707 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM : 5708 BWN_TX_EFT_FB_CCK; 5709 txhdr->chan = phy->chan; 5710 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM : 5711 BWN_TX_PHY_ENC_CCK; 5712 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 5713 rate == BWN_CCK_RATE_11MB)) 5714 phyctl |= BWN_TX_PHY_SHORTPRMBL; 5715 5716 /* XXX TX antenna selection */ 5717 5718 switch (bwn_antenna_sanitize(mac, 0)) { 5719 case 0: 5720 phyctl |= BWN_TX_PHY_ANT01AUTO; 5721 break; 5722 case 1: 5723 phyctl |= BWN_TX_PHY_ANT0; 5724 break; 5725 case 2: 5726 phyctl |= BWN_TX_PHY_ANT1; 5727 break; 5728 case 3: 5729 phyctl |= BWN_TX_PHY_ANT2; 5730 break; 5731 case 4: 5732 phyctl |= BWN_TX_PHY_ANT3; 5733 break; 5734 default: 5735 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5736 } 5737 5738 if (!ismcast) 5739 macctl |= BWN_TX_MAC_ACK; 5740 5741 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU); 5742 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 5743 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 5744 macctl |= BWN_TX_MAC_LONGFRAME; 5745 5746 if (ic->ic_flags & IEEE80211_F_USEPROT) { 5747 /* XXX RTS rate is always 1MB??? */ 5748 rts_rate = BWN_CCK_RATE_1MB; 5749 rts_rate_fb = bwn_get_fbrate(rts_rate); 5750 5751 protdur = ieee80211_compute_duration(ic->ic_rt, 5752 m->m_pkthdr.len, rate, isshort) + 5753 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 5754 5755 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 5756 cts = (struct ieee80211_frame_cts *)(BWN_ISOLDFMT(mac) ? 5757 (txhdr->body.old.rts_frame) : 5758 (txhdr->body.new.rts_frame)); 5759 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, 5760 protdur); 5761 KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); 5762 bcopy(mtod(mprot, uint8_t *), (uint8_t *)cts, 5763 mprot->m_pkthdr.len); 5764 m_freem(mprot); 5765 macctl |= BWN_TX_MAC_SEND_CTSTOSELF; 5766 len = sizeof(struct ieee80211_frame_cts); 5767 } else { 5768 rts = (struct ieee80211_frame_rts *)(BWN_ISOLDFMT(mac) ? 5769 (txhdr->body.old.rts_frame) : 5770 (txhdr->body.new.rts_frame)); 5771 protdur += ieee80211_ack_duration(ic->ic_rt, rate, 5772 isshort); 5773 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, 5774 wh->i_addr2, protdur); 5775 KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); 5776 bcopy(mtod(mprot, uint8_t *), (uint8_t *)rts, 5777 mprot->m_pkthdr.len); 5778 m_freem(mprot); 5779 macctl |= BWN_TX_MAC_SEND_RTSCTS; 5780 len = sizeof(struct ieee80211_frame_rts); 5781 } 5782 len += IEEE80211_CRC_LEN; 5783 bwn_plcp_genhdr((struct bwn_plcp4 *)((BWN_ISOLDFMT(mac)) ? 5784 &txhdr->body.old.rts_plcp : 5785 &txhdr->body.new.rts_plcp), len, rts_rate); 5786 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len, 5787 rts_rate_fb); 5788 5789 protwh = (struct ieee80211_frame *)(BWN_ISOLDFMT(mac) ? 5790 (&txhdr->body.old.rts_frame) : 5791 (&txhdr->body.new.rts_frame)); 5792 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur; 5793 5794 if (BWN_ISOFDMRATE(rts_rate)) { 5795 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM; 5796 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate); 5797 } else { 5798 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK; 5799 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate); 5800 } 5801 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ? 5802 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK; 5803 } 5804 5805 if (BWN_ISOLDFMT(mac)) 5806 txhdr->body.old.cookie = htole16(cookie); 5807 else 5808 txhdr->body.new.cookie = htole16(cookie); 5809 5810 txhdr->macctl = htole32(macctl); 5811 txhdr->phyctl = htole16(phyctl); 5812 5813 /* 5814 * TX radio tap 5815 */ 5816 if (ieee80211_radiotap_active_vap(vap)) { 5817 sc->sc_tx_th.wt_flags = 0; 5818 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 5819 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 5820 if (isshort && 5821 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 5822 rate == BWN_CCK_RATE_11MB)) 5823 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5824 sc->sc_tx_th.wt_rate = rate; 5825 5826 ieee80211_radiotap_tx(vap, m); 5827 } 5828 5829 return (0); 5830} 5831 5832static void 5833bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets, 5834 const uint8_t rate) 5835{ 5836 uint32_t d, plen; 5837 uint8_t *raw = plcp->o.raw; 5838 5839 if (BWN_ISOFDMRATE(rate)) { 5840 d = bwn_plcp_getofdm(rate); 5841 KASSERT(!(octets & 0xf000), 5842 ("%s:%d: fail", __func__, __LINE__)); 5843 d |= (octets << 5); 5844 plcp->o.data = htole32(d); 5845 } else { 5846 plen = octets * 16 / rate; 5847 if ((octets * 16 % rate) > 0) { 5848 plen++; 5849 if ((rate == BWN_CCK_RATE_11MB) 5850 && ((octets * 8 % 11) < 4)) { 5851 raw[1] = 0x84; 5852 } else 5853 raw[1] = 0x04; 5854 } else 5855 raw[1] = 0x04; 5856 plcp->o.data |= htole32(plen << 16); 5857 raw[0] = bwn_plcp_getcck(rate); 5858 } 5859} 5860 5861static uint8_t 5862bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n) 5863{ 5864 struct bwn_softc *sc = mac->mac_sc; 5865 uint8_t mask; 5866 5867 if (n == 0) 5868 return (0); 5869 if (mac->mac_phy.gmode) 5870 mask = siba_sprom_get_ant_bg(sc->sc_dev); 5871 else 5872 mask = siba_sprom_get_ant_a(sc->sc_dev); 5873 if (!(mask & (1 << (n - 1)))) 5874 return (0); 5875 return (n); 5876} 5877 5878static uint8_t 5879bwn_get_fbrate(uint8_t bitrate) 5880{ 5881 switch (bitrate) { 5882 case BWN_CCK_RATE_1MB: 5883 return (BWN_CCK_RATE_1MB); 5884 case BWN_CCK_RATE_2MB: 5885 return (BWN_CCK_RATE_1MB); 5886 case BWN_CCK_RATE_5MB: 5887 return (BWN_CCK_RATE_2MB); 5888 case BWN_CCK_RATE_11MB: 5889 return (BWN_CCK_RATE_5MB); 5890 case BWN_OFDM_RATE_6MB: 5891 return (BWN_CCK_RATE_5MB); 5892 case BWN_OFDM_RATE_9MB: 5893 return (BWN_OFDM_RATE_6MB); 5894 case BWN_OFDM_RATE_12MB: 5895 return (BWN_OFDM_RATE_9MB); 5896 case BWN_OFDM_RATE_18MB: 5897 return (BWN_OFDM_RATE_12MB); 5898 case BWN_OFDM_RATE_24MB: 5899 return (BWN_OFDM_RATE_18MB); 5900 case BWN_OFDM_RATE_36MB: 5901 return (BWN_OFDM_RATE_24MB); 5902 case BWN_OFDM_RATE_48MB: 5903 return (BWN_OFDM_RATE_36MB); 5904 case BWN_OFDM_RATE_54MB: 5905 return (BWN_OFDM_RATE_48MB); 5906 } 5907 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5908 return (0); 5909} 5910 5911static uint32_t 5912bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 5913 uint32_t ctl, const void *_data, int len) 5914{ 5915 struct bwn_softc *sc = mac->mac_sc; 5916 uint32_t value = 0; 5917 const uint8_t *data = _data; 5918 5919 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 | 5920 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31; 5921 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 5922 5923 siba_write_multi_4(sc->sc_dev, data, (len & ~3), 5924 tq->tq_base + BWN_PIO8_TXDATA); 5925 if (len & 3) { 5926 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 | 5927 BWN_PIO8_TXCTL_24_31); 5928 data = &(data[len - 1]); 5929 switch (len & 3) { 5930 case 3: 5931 ctl |= BWN_PIO8_TXCTL_16_23; 5932 value |= (uint32_t)(*data) << 16; 5933 data--; 5934 case 2: 5935 ctl |= BWN_PIO8_TXCTL_8_15; 5936 value |= (uint32_t)(*data) << 8; 5937 data--; 5938 case 1: 5939 value |= (uint32_t)(*data); 5940 } 5941 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 5942 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value); 5943 } 5944 5945 return (ctl); 5946} 5947 5948static void 5949bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 5950 uint16_t offset, uint32_t value) 5951{ 5952 5953 BWN_WRITE_4(mac, tq->tq_base + offset, value); 5954} 5955 5956static uint16_t 5957bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 5958 uint16_t ctl, const void *_data, int len) 5959{ 5960 struct bwn_softc *sc = mac->mac_sc; 5961 const uint8_t *data = _data; 5962 5963 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 5964 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 5965 5966 siba_write_multi_2(sc->sc_dev, data, (len & ~1), 5967 tq->tq_base + BWN_PIO_TXDATA); 5968 if (len & 1) { 5969 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 5970 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 5971 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]); 5972 } 5973 5974 return (ctl); 5975} 5976 5977static uint16_t 5978bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 5979 uint16_t ctl, struct mbuf *m0) 5980{ 5981 int i, j = 0; 5982 uint16_t data = 0; 5983 const uint8_t *buf; 5984 struct mbuf *m = m0; 5985 5986 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 5987 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 5988 5989 for (; m != NULL; m = m->m_next) { 5990 buf = mtod(m, const uint8_t *); 5991 for (i = 0; i < m->m_len; i++) { 5992 if (!((j++) % 2)) 5993 data |= buf[i]; 5994 else { 5995 data |= (buf[i] << 8); 5996 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 5997 data = 0; 5998 } 5999 } 6000 } 6001 if (m0->m_pkthdr.len % 2) { 6002 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6003 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6004 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6005 } 6006 6007 return (ctl); 6008} 6009 6010static void 6011bwn_set_slot_time(struct bwn_mac *mac, uint16_t time) 6012{ 6013 6014 if (mac->mac_phy.type != BWN_PHYTYPE_G) 6015 return; 6016 BWN_WRITE_2(mac, 0x684, 510 + time); 6017 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time); 6018} 6019 6020static struct bwn_dma_ring * 6021bwn_dma_select(struct bwn_mac *mac, uint8_t prio) 6022{ 6023 6024 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 6025 return (mac->mac_method.dma.wme[WME_AC_BE]); 6026 6027 switch (prio) { 6028 case 3: 6029 return (mac->mac_method.dma.wme[WME_AC_VO]); 6030 case 2: 6031 return (mac->mac_method.dma.wme[WME_AC_VI]); 6032 case 0: 6033 return (mac->mac_method.dma.wme[WME_AC_BE]); 6034 case 1: 6035 return (mac->mac_method.dma.wme[WME_AC_BK]); 6036 } 6037 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6038 return (NULL); 6039} 6040 6041static int 6042bwn_dma_getslot(struct bwn_dma_ring *dr) 6043{ 6044 int slot; 6045 6046 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 6047 6048 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 6049 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__)); 6050 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__)); 6051 6052 slot = bwn_dma_nextslot(dr, dr->dr_curslot); 6053 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__)); 6054 dr->dr_curslot = slot; 6055 dr->dr_usedslot++; 6056 6057 return (slot); 6058} 6059 6060static struct bwn_pio_txqueue * 6061bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie, 6062 struct bwn_pio_txpkt **pack) 6063{ 6064 struct bwn_pio *pio = &mac->mac_method.pio; 6065 struct bwn_pio_txqueue *tq = NULL; 6066 unsigned int index; 6067 6068 switch (cookie & 0xf000) { 6069 case 0x1000: 6070 tq = &pio->wme[WME_AC_BK]; 6071 break; 6072 case 0x2000: 6073 tq = &pio->wme[WME_AC_BE]; 6074 break; 6075 case 0x3000: 6076 tq = &pio->wme[WME_AC_VI]; 6077 break; 6078 case 0x4000: 6079 tq = &pio->wme[WME_AC_VO]; 6080 break; 6081 case 0x5000: 6082 tq = &pio->mcast; 6083 break; 6084 } 6085 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__)); 6086 if (tq == NULL) 6087 return (NULL); 6088 index = (cookie & 0x0fff); 6089 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__)); 6090 if (index >= N(tq->tq_pkts)) 6091 return (NULL); 6092 *pack = &tq->tq_pkts[index]; 6093 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__)); 6094 return (tq); 6095} 6096 6097static void 6098bwn_txpwr(void *arg, int npending) 6099{ 6100 struct bwn_mac *mac = arg; 6101 struct bwn_softc *sc = mac->mac_sc; 6102 6103 BWN_LOCK(sc); 6104 if (mac && mac->mac_status >= BWN_MAC_STATUS_STARTED && 6105 mac->mac_phy.set_txpwr != NULL) 6106 mac->mac_phy.set_txpwr(mac); 6107 BWN_UNLOCK(sc); 6108} 6109 6110static void 6111bwn_task_15s(struct bwn_mac *mac) 6112{ 6113 uint16_t reg; 6114 6115 if (mac->mac_fw.opensource) { 6116 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG); 6117 if (reg) { 6118 bwn_restart(mac, "fw watchdog"); 6119 return; 6120 } 6121 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1); 6122 } 6123 if (mac->mac_phy.task_15s) 6124 mac->mac_phy.task_15s(mac); 6125 6126 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 6127} 6128 6129static void 6130bwn_task_30s(struct bwn_mac *mac) 6131{ 6132 6133 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running) 6134 return; 6135 mac->mac_noise.noi_running = 1; 6136 mac->mac_noise.noi_nsamples = 0; 6137 6138 bwn_noise_gensample(mac); 6139} 6140 6141static void 6142bwn_task_60s(struct bwn_mac *mac) 6143{ 6144 6145 if (mac->mac_phy.task_60s) 6146 mac->mac_phy.task_60s(mac); 6147 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME); 6148} 6149 6150static void 6151bwn_tasks(void *arg) 6152{ 6153 struct bwn_mac *mac = arg; 6154 struct bwn_softc *sc = mac->mac_sc; 6155 6156 BWN_ASSERT_LOCKED(sc); 6157 if (mac->mac_status != BWN_MAC_STATUS_STARTED) 6158 return; 6159 6160 if (mac->mac_task_state % 4 == 0) 6161 bwn_task_60s(mac); 6162 if (mac->mac_task_state % 2 == 0) 6163 bwn_task_30s(mac); 6164 bwn_task_15s(mac); 6165 6166 mac->mac_task_state++; 6167 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 6168} 6169 6170static int 6171bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a) 6172{ 6173 struct bwn_softc *sc = mac->mac_sc; 6174 6175 KASSERT(a == 0, ("not support APHY\n")); 6176 6177 switch (plcp->o.raw[0] & 0xf) { 6178 case 0xb: 6179 return (BWN_OFDM_RATE_6MB); 6180 case 0xf: 6181 return (BWN_OFDM_RATE_9MB); 6182 case 0xa: 6183 return (BWN_OFDM_RATE_12MB); 6184 case 0xe: 6185 return (BWN_OFDM_RATE_18MB); 6186 case 0x9: 6187 return (BWN_OFDM_RATE_24MB); 6188 case 0xd: 6189 return (BWN_OFDM_RATE_36MB); 6190 case 0x8: 6191 return (BWN_OFDM_RATE_48MB); 6192 case 0xc: 6193 return (BWN_OFDM_RATE_54MB); 6194 } 6195 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n", 6196 plcp->o.raw[0] & 0xf); 6197 return (-1); 6198} 6199 6200static int 6201bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp) 6202{ 6203 struct bwn_softc *sc = mac->mac_sc; 6204 6205 switch (plcp->o.raw[0]) { 6206 case 0x0a: 6207 return (BWN_CCK_RATE_1MB); 6208 case 0x14: 6209 return (BWN_CCK_RATE_2MB); 6210 case 0x37: 6211 return (BWN_CCK_RATE_5MB); 6212 case 0x6e: 6213 return (BWN_CCK_RATE_11MB); 6214 } 6215 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]); 6216 return (-1); 6217} 6218 6219static void 6220bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, 6221 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate, 6222 int rssi, int noise) 6223{ 6224 struct bwn_softc *sc = mac->mac_sc; 6225 const struct ieee80211_frame_min *wh; 6226 uint64_t tsf; 6227 uint16_t low_mactime_now; 6228 6229 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL) 6230 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6231 6232 wh = mtod(m, const struct ieee80211_frame_min *); 6233 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 6234 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 6235 6236 bwn_tsf_read(mac, &tsf); 6237 low_mactime_now = tsf; 6238 tsf = tsf & ~0xffffULL; 6239 tsf += le16toh(rxhdr->mac_time); 6240 if (low_mactime_now < le16toh(rxhdr->mac_time)) 6241 tsf -= 0x10000; 6242 6243 sc->sc_rx_th.wr_tsf = tsf; 6244 sc->sc_rx_th.wr_rate = rate; 6245 sc->sc_rx_th.wr_antsignal = rssi; 6246 sc->sc_rx_th.wr_antnoise = noise; 6247} 6248 6249static void 6250bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf) 6251{ 6252 uint32_t low, high; 6253 6254 KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3, 6255 ("%s:%d: fail", __func__, __LINE__)); 6256 6257 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW); 6258 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH); 6259 *tsf = high; 6260 *tsf <<= 32; 6261 *tsf |= low; 6262} 6263 6264static int 6265bwn_dma_attach(struct bwn_mac *mac) 6266{ 6267 struct bwn_dma *dma = &mac->mac_method.dma; 6268 struct bwn_softc *sc = mac->mac_sc; 6269 bus_addr_t lowaddr = 0; 6270 int error; 6271 6272 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) 6273 return (0); 6274 6275 KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__)); 6276 6277 mac->mac_flags |= BWN_MAC_FLAG_DMA; 6278 6279 dma->dmatype = bwn_dma_gettype(mac); 6280 if (dma->dmatype == BWN_DMA_30BIT) 6281 lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT; 6282 else if (dma->dmatype == BWN_DMA_32BIT) 6283 lowaddr = BUS_SPACE_MAXADDR_32BIT; 6284 else 6285 lowaddr = BUS_SPACE_MAXADDR; 6286 6287 /* 6288 * Create top level DMA tag 6289 */ 6290 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 6291 BWN_ALIGN, 0, /* alignment, bounds */ 6292 lowaddr, /* lowaddr */ 6293 BUS_SPACE_MAXADDR, /* highaddr */ 6294 NULL, NULL, /* filter, filterarg */ 6295 BUS_SPACE_MAXSIZE, /* maxsize */ 6296 BUS_SPACE_UNRESTRICTED, /* nsegments */ 6297 BUS_SPACE_MAXSIZE, /* maxsegsize */ 6298 0, /* flags */ 6299 NULL, NULL, /* lockfunc, lockarg */ 6300 &dma->parent_dtag); 6301 if (error) { 6302 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 6303 return (error); 6304 } 6305 6306 /* 6307 * Create TX/RX mbuf DMA tag 6308 */ 6309 error = bus_dma_tag_create(dma->parent_dtag, 6310 1, 6311 0, 6312 BUS_SPACE_MAXADDR, 6313 BUS_SPACE_MAXADDR, 6314 NULL, NULL, 6315 MCLBYTES, 6316 1, 6317 BUS_SPACE_MAXSIZE_32BIT, 6318 0, 6319 NULL, NULL, 6320 &dma->rxbuf_dtag); 6321 if (error) { 6322 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 6323 goto fail0; 6324 } 6325 error = bus_dma_tag_create(dma->parent_dtag, 6326 1, 6327 0, 6328 BUS_SPACE_MAXADDR, 6329 BUS_SPACE_MAXADDR, 6330 NULL, NULL, 6331 MCLBYTES, 6332 1, 6333 BUS_SPACE_MAXSIZE_32BIT, 6334 0, 6335 NULL, NULL, 6336 &dma->txbuf_dtag); 6337 if (error) { 6338 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 6339 goto fail1; 6340 } 6341 6342 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype); 6343 if (!dma->wme[WME_AC_BK]) 6344 goto fail2; 6345 6346 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype); 6347 if (!dma->wme[WME_AC_BE]) 6348 goto fail3; 6349 6350 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype); 6351 if (!dma->wme[WME_AC_VI]) 6352 goto fail4; 6353 6354 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype); 6355 if (!dma->wme[WME_AC_VO]) 6356 goto fail5; 6357 6358 dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype); 6359 if (!dma->mcast) 6360 goto fail6; 6361 dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype); 6362 if (!dma->rx) 6363 goto fail7; 6364 6365 return (error); 6366 6367fail7: bwn_dma_ringfree(&dma->mcast); 6368fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 6369fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 6370fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 6371fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 6372fail2: bus_dma_tag_destroy(dma->txbuf_dtag); 6373fail1: bus_dma_tag_destroy(dma->rxbuf_dtag); 6374fail0: bus_dma_tag_destroy(dma->parent_dtag); 6375 return (error); 6376} 6377 6378static struct bwn_dma_ring * 6379bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status, 6380 uint16_t cookie, int *slot) 6381{ 6382 struct bwn_dma *dma = &mac->mac_method.dma; 6383 struct bwn_dma_ring *dr; 6384 struct bwn_softc *sc = mac->mac_sc; 6385 6386 BWN_ASSERT_LOCKED(mac->mac_sc); 6387 6388 switch (cookie & 0xf000) { 6389 case 0x1000: 6390 dr = dma->wme[WME_AC_BK]; 6391 break; 6392 case 0x2000: 6393 dr = dma->wme[WME_AC_BE]; 6394 break; 6395 case 0x3000: 6396 dr = dma->wme[WME_AC_VI]; 6397 break; 6398 case 0x4000: 6399 dr = dma->wme[WME_AC_VO]; 6400 break; 6401 case 0x5000: 6402 dr = dma->mcast; 6403 break; 6404 default: 6405 dr = NULL; 6406 KASSERT(0 == 1, 6407 ("invalid cookie value %d", cookie & 0xf000)); 6408 } 6409 *slot = (cookie & 0x0fff); 6410 if (*slot < 0 || *slot >= dr->dr_numslots) { 6411 /* 6412 * XXX FIXME: sometimes H/W returns TX DONE events duplicately 6413 * that it occurs events which have same H/W sequence numbers. 6414 * When it's occurred just prints a WARNING msgs and ignores. 6415 */ 6416 KASSERT(status->seq == dma->lastseq, 6417 ("%s:%d: fail", __func__, __LINE__)); 6418 device_printf(sc->sc_dev, 6419 "out of slot ranges (0 < %d < %d)\n", *slot, 6420 dr->dr_numslots); 6421 return (NULL); 6422 } 6423 dma->lastseq = status->seq; 6424 return (dr); 6425} 6426 6427static void 6428bwn_dma_stop(struct bwn_mac *mac) 6429{ 6430 struct bwn_dma *dma; 6431 6432 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 6433 return; 6434 dma = &mac->mac_method.dma; 6435 6436 bwn_dma_ringstop(&dma->rx); 6437 bwn_dma_ringstop(&dma->wme[WME_AC_BK]); 6438 bwn_dma_ringstop(&dma->wme[WME_AC_BE]); 6439 bwn_dma_ringstop(&dma->wme[WME_AC_VI]); 6440 bwn_dma_ringstop(&dma->wme[WME_AC_VO]); 6441 bwn_dma_ringstop(&dma->mcast); 6442} 6443 6444static void 6445bwn_dma_ringstop(struct bwn_dma_ring **dr) 6446{ 6447 6448 if (dr == NULL) 6449 return; 6450 6451 bwn_dma_cleanup(*dr); 6452} 6453 6454static void 6455bwn_pio_stop(struct bwn_mac *mac) 6456{ 6457 struct bwn_pio *pio; 6458 6459 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 6460 return; 6461 pio = &mac->mac_method.pio; 6462 6463 bwn_destroy_queue_tx(&pio->mcast); 6464 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]); 6465 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]); 6466 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]); 6467 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]); 6468} 6469 6470static void 6471bwn_led_attach(struct bwn_mac *mac) 6472{ 6473 struct bwn_softc *sc = mac->mac_sc; 6474 const uint8_t *led_act = NULL; 6475 uint16_t val[BWN_LED_MAX]; 6476 int i; 6477 6478 sc->sc_led_idle = (2350 * hz) / 1000; 6479 sc->sc_led_blink = 1; 6480 6481 for (i = 0; i < N(bwn_vendor_led_act); ++i) { 6482 if (siba_get_pci_subvendor(sc->sc_dev) == 6483 bwn_vendor_led_act[i].vid) { 6484 led_act = bwn_vendor_led_act[i].led_act; 6485 break; 6486 } 6487 } 6488 if (led_act == NULL) 6489 led_act = bwn_default_led_act; 6490 6491 val[0] = siba_sprom_get_gpio0(sc->sc_dev); 6492 val[1] = siba_sprom_get_gpio1(sc->sc_dev); 6493 val[2] = siba_sprom_get_gpio2(sc->sc_dev); 6494 val[3] = siba_sprom_get_gpio3(sc->sc_dev); 6495 6496 for (i = 0; i < BWN_LED_MAX; ++i) { 6497 struct bwn_led *led = &sc->sc_leds[i]; 6498 6499 if (val[i] == 0xff) { 6500 led->led_act = led_act[i]; 6501 } else { 6502 if (val[i] & BWN_LED_ACT_LOW) 6503 led->led_flags |= BWN_LED_F_ACTLOW; 6504 led->led_act = val[i] & BWN_LED_ACT_MASK; 6505 } 6506 led->led_mask = (1 << i); 6507 6508 if (led->led_act == BWN_LED_ACT_BLINK_SLOW || 6509 led->led_act == BWN_LED_ACT_BLINK_POLL || 6510 led->led_act == BWN_LED_ACT_BLINK) { 6511 led->led_flags |= BWN_LED_F_BLINK; 6512 if (led->led_act == BWN_LED_ACT_BLINK_POLL) 6513 led->led_flags |= BWN_LED_F_POLLABLE; 6514 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW) 6515 led->led_flags |= BWN_LED_F_SLOW; 6516 6517 if (sc->sc_blink_led == NULL) { 6518 sc->sc_blink_led = led; 6519 if (led->led_flags & BWN_LED_F_SLOW) 6520 BWN_LED_SLOWDOWN(sc->sc_led_idle); 6521 } 6522 } 6523 6524 DPRINTF(sc, BWN_DEBUG_LED, 6525 "%dth led, act %d, lowact %d\n", i, 6526 led->led_act, led->led_flags & BWN_LED_F_ACTLOW); 6527 } 6528 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 6529} 6530 6531static __inline uint16_t 6532bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on) 6533{ 6534 6535 if (led->led_flags & BWN_LED_F_ACTLOW) 6536 on = !on; 6537 if (on) 6538 val |= led->led_mask; 6539 else 6540 val &= ~led->led_mask; 6541 return val; 6542} 6543 6544static void 6545bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate) 6546{ 6547 struct bwn_softc *sc = mac->mac_sc; 6548 struct ieee80211com *ic = &sc->sc_ic; 6549 uint16_t val; 6550 int i; 6551 6552 if (nstate == IEEE80211_S_INIT) { 6553 callout_stop(&sc->sc_led_blink_ch); 6554 sc->sc_led_blinking = 0; 6555 } 6556 6557 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) 6558 return; 6559 6560 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 6561 for (i = 0; i < BWN_LED_MAX; ++i) { 6562 struct bwn_led *led = &sc->sc_leds[i]; 6563 int on; 6564 6565 if (led->led_act == BWN_LED_ACT_UNKN || 6566 led->led_act == BWN_LED_ACT_NULL) 6567 continue; 6568 6569 if ((led->led_flags & BWN_LED_F_BLINK) && 6570 nstate != IEEE80211_S_INIT) 6571 continue; 6572 6573 switch (led->led_act) { 6574 case BWN_LED_ACT_ON: /* Always on */ 6575 on = 1; 6576 break; 6577 case BWN_LED_ACT_OFF: /* Always off */ 6578 case BWN_LED_ACT_5GHZ: /* TODO: 11A */ 6579 on = 0; 6580 break; 6581 default: 6582 on = 1; 6583 switch (nstate) { 6584 case IEEE80211_S_INIT: 6585 on = 0; 6586 break; 6587 case IEEE80211_S_RUN: 6588 if (led->led_act == BWN_LED_ACT_11G && 6589 ic->ic_curmode != IEEE80211_MODE_11G) 6590 on = 0; 6591 break; 6592 default: 6593 if (led->led_act == BWN_LED_ACT_ASSOC) 6594 on = 0; 6595 break; 6596 } 6597 break; 6598 } 6599 6600 val = bwn_led_onoff(led, val, on); 6601 } 6602 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 6603} 6604 6605static void 6606bwn_led_event(struct bwn_mac *mac, int event) 6607{ 6608 struct bwn_softc *sc = mac->mac_sc; 6609 struct bwn_led *led = sc->sc_blink_led; 6610 int rate; 6611 6612 if (event == BWN_LED_EVENT_POLL) { 6613 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0) 6614 return; 6615 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 6616 return; 6617 } 6618 6619 sc->sc_led_ticks = ticks; 6620 if (sc->sc_led_blinking) 6621 return; 6622 6623 switch (event) { 6624 case BWN_LED_EVENT_RX: 6625 rate = sc->sc_rx_rate; 6626 break; 6627 case BWN_LED_EVENT_TX: 6628 rate = sc->sc_tx_rate; 6629 break; 6630 case BWN_LED_EVENT_POLL: 6631 rate = 0; 6632 break; 6633 default: 6634 panic("unknown LED event %d\n", event); 6635 break; 6636 } 6637 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur, 6638 bwn_led_duration[rate].off_dur); 6639} 6640 6641static void 6642bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur) 6643{ 6644 struct bwn_softc *sc = mac->mac_sc; 6645 struct bwn_led *led = sc->sc_blink_led; 6646 uint16_t val; 6647 6648 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 6649 val = bwn_led_onoff(led, val, 1); 6650 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 6651 6652 if (led->led_flags & BWN_LED_F_SLOW) { 6653 BWN_LED_SLOWDOWN(on_dur); 6654 BWN_LED_SLOWDOWN(off_dur); 6655 } 6656 6657 sc->sc_led_blinking = 1; 6658 sc->sc_led_blink_offdur = off_dur; 6659 6660 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac); 6661} 6662 6663static void 6664bwn_led_blink_next(void *arg) 6665{ 6666 struct bwn_mac *mac = arg; 6667 struct bwn_softc *sc = mac->mac_sc; 6668 uint16_t val; 6669 6670 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 6671 val = bwn_led_onoff(sc->sc_blink_led, val, 0); 6672 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 6673 6674 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 6675 bwn_led_blink_end, mac); 6676} 6677 6678static void 6679bwn_led_blink_end(void *arg) 6680{ 6681 struct bwn_mac *mac = arg; 6682 struct bwn_softc *sc = mac->mac_sc; 6683 6684 sc->sc_led_blinking = 0; 6685} 6686 6687static int 6688bwn_suspend(device_t dev) 6689{ 6690 struct bwn_softc *sc = device_get_softc(dev); 6691 6692 BWN_LOCK(sc); 6693 bwn_stop(sc); 6694 BWN_UNLOCK(sc); 6695 return (0); 6696} 6697 6698static int 6699bwn_resume(device_t dev) 6700{ 6701 struct bwn_softc *sc = device_get_softc(dev); 6702 int error = EDOOFUS; 6703 6704 BWN_LOCK(sc); 6705 if (sc->sc_ic.ic_nrunning > 0) 6706 error = bwn_init(sc); 6707 BWN_UNLOCK(sc); 6708 if (error == 0) 6709 ieee80211_start_all(&sc->sc_ic); 6710 return (0); 6711} 6712 6713static void 6714bwn_rfswitch(void *arg) 6715{ 6716 struct bwn_softc *sc = arg; 6717 struct bwn_mac *mac = sc->sc_curmac; 6718 int cur = 0, prev = 0; 6719 6720 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED, 6721 ("%s: invalid MAC status %d", __func__, mac->mac_status)); 6722 6723 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP) { 6724 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI) 6725 & BWN_RF_HWENABLED_HI_MASK)) 6726 cur = 1; 6727 } else { 6728 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO) 6729 & BWN_RF_HWENABLED_LO_MASK) 6730 cur = 1; 6731 } 6732 6733 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON) 6734 prev = 1; 6735 6736 if (cur != prev) { 6737 if (cur) 6738 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 6739 else 6740 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON; 6741 6742 device_printf(sc->sc_dev, 6743 "status of RF switch is changed to %s\n", 6744 cur ? "ON" : "OFF"); 6745 if (cur != mac->mac_phy.rf_on) { 6746 if (cur) 6747 bwn_rf_turnon(mac); 6748 else 6749 bwn_rf_turnoff(mac); 6750 } 6751 } 6752 6753 callout_schedule(&sc->sc_rfswitch_ch, hz); 6754} 6755 6756static void 6757bwn_sysctl_node(struct bwn_softc *sc) 6758{ 6759 device_t dev = sc->sc_dev; 6760 struct bwn_mac *mac; 6761 struct bwn_stats *stats; 6762 6763 /* XXX assume that count of MAC is only 1. */ 6764 6765 if ((mac = sc->sc_curmac) == NULL) 6766 return; 6767 stats = &mac->mac_stats; 6768 6769 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 6770 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 6771 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level"); 6772 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 6773 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 6774 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS"); 6775 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 6776 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 6777 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send"); 6778 6779#ifdef BWN_DEBUG 6780 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 6781 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 6782 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 6783#endif 6784} 6785 6786static device_method_t bwn_methods[] = { 6787 /* Device interface */ 6788 DEVMETHOD(device_probe, bwn_probe), 6789 DEVMETHOD(device_attach, bwn_attach), 6790 DEVMETHOD(device_detach, bwn_detach), 6791 DEVMETHOD(device_suspend, bwn_suspend), 6792 DEVMETHOD(device_resume, bwn_resume), 6793 DEVMETHOD_END 6794}; 6795static driver_t bwn_driver = { 6796 "bwn", 6797 bwn_methods, 6798 sizeof(struct bwn_softc) 6799}; 6800static devclass_t bwn_devclass; 6801DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0); 6802MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1); 6803MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */ 6804MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */ 6805MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1); 6806