if_bwi.c revision 293339
1/* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/bwi/if_bwi.c 293339 2016-01-07 18:41:03Z avos $"); 39 40#include "opt_inet.h" 41#include "opt_bwi.h" 42#include "opt_wlan.h" 43 44#include <sys/param.h> 45#include <sys/endian.h> 46#include <sys/kernel.h> 47#include <sys/bus.h> 48#include <sys/malloc.h> 49#include <sys/proc.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54#include <sys/systm.h> 55#include <sys/taskqueue.h> 56 57#include <net/if.h> 58#include <net/if_var.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_arp.h> 63#include <net/ethernet.h> 64#include <net/if_llc.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_radiotap.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_phy.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <net/bpf.h> 73 74#ifdef INET 75#include <netinet/in.h> 76#include <netinet/if_ether.h> 77#endif 78 79#include <machine/bus.h> 80 81#include <dev/pci/pcivar.h> 82#include <dev/pci/pcireg.h> 83 84#include <dev/bwi/bitops.h> 85#include <dev/bwi/if_bwireg.h> 86#include <dev/bwi/if_bwivar.h> 87#include <dev/bwi/bwimac.h> 88#include <dev/bwi/bwirf.h> 89 90struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93}; 94 95struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98} __packed; 99 100static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104static void bwi_vap_delete(struct ieee80211vap *); 105static void bwi_init(struct bwi_softc *); 106static void bwi_parent(struct ieee80211com *); 107static int bwi_transmit(struct ieee80211com *, struct mbuf *); 108static void bwi_start_locked(struct bwi_softc *); 109static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111static void bwi_watchdog(void *); 112static void bwi_scan_start(struct ieee80211com *); 113static void bwi_set_channel(struct ieee80211com *); 114static void bwi_scan_end(struct ieee80211com *); 115static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 116static void bwi_updateslot(struct ieee80211com *); 117static int bwi_media_change(struct ifnet *); 118 119static void bwi_calibrate(void *); 120 121static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 122static int bwi_calc_noise(struct bwi_softc *); 123static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 124static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 125 struct bwi_rxbuf_hdr *, const void *, int, int, int); 126 127static void bwi_restart(void *, int); 128static void bwi_init_statechg(struct bwi_softc *, int); 129static void bwi_stop(struct bwi_softc *, int); 130static void bwi_stop_locked(struct bwi_softc *, int); 131static int bwi_newbuf(struct bwi_softc *, int, int); 132static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *); 134static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *, 136 const struct ieee80211_bpf_params *); 137 138static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 139 bus_addr_t, int, int); 140static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 141 142static int bwi_init_tx_ring32(struct bwi_softc *, int); 143static int bwi_init_rx_ring32(struct bwi_softc *); 144static int bwi_init_txstats32(struct bwi_softc *); 145static void bwi_free_tx_ring32(struct bwi_softc *, int); 146static void bwi_free_rx_ring32(struct bwi_softc *); 147static void bwi_free_txstats32(struct bwi_softc *); 148static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 149static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 150 int, bus_addr_t, int); 151static int bwi_rxeof32(struct bwi_softc *); 152static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 153static void bwi_txeof_status32(struct bwi_softc *); 154 155static int bwi_init_tx_ring64(struct bwi_softc *, int); 156static int bwi_init_rx_ring64(struct bwi_softc *); 157static int bwi_init_txstats64(struct bwi_softc *); 158static void bwi_free_tx_ring64(struct bwi_softc *, int); 159static void bwi_free_rx_ring64(struct bwi_softc *); 160static void bwi_free_txstats64(struct bwi_softc *); 161static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 162static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 163 int, bus_addr_t, int); 164static int bwi_rxeof64(struct bwi_softc *); 165static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 166static void bwi_txeof_status64(struct bwi_softc *); 167 168static int bwi_rxeof(struct bwi_softc *, int); 169static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 170static void bwi_txeof(struct bwi_softc *); 171static void bwi_txeof_status(struct bwi_softc *, int); 172static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 173static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 174 175static int bwi_dma_alloc(struct bwi_softc *); 176static void bwi_dma_free(struct bwi_softc *); 177static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 178 struct bwi_ring_data *, bus_size_t, 179 uint32_t); 180static int bwi_dma_mbuf_create(struct bwi_softc *); 181static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 182static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 183static void bwi_dma_txstats_free(struct bwi_softc *); 184static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 185static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 186 bus_size_t, int); 187 188static void bwi_power_on(struct bwi_softc *, int); 189static int bwi_power_off(struct bwi_softc *, int); 190static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 191static int bwi_set_clock_delay(struct bwi_softc *); 192static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 193static int bwi_get_pwron_delay(struct bwi_softc *sc); 194static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 195 const uint8_t *); 196static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 197 198static void bwi_get_card_flags(struct bwi_softc *); 199static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 200 201static int bwi_bus_attach(struct bwi_softc *); 202static int bwi_bbp_attach(struct bwi_softc *); 203static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 204static void bwi_bbp_power_off(struct bwi_softc *); 205 206static const char *bwi_regwin_name(const struct bwi_regwin *); 207static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 208static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 209static int bwi_regwin_select(struct bwi_softc *, int); 210 211static void bwi_led_attach(struct bwi_softc *); 212static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 213static void bwi_led_event(struct bwi_softc *, int); 214static void bwi_led_blink_start(struct bwi_softc *, int, int); 215static void bwi_led_blink_next(void *); 216static void bwi_led_blink_end(void *); 217 218static const struct { 219 uint16_t did_min; 220 uint16_t did_max; 221 uint16_t bbp_id; 222} bwi_bbpid_map[] = { 223 { 0x4301, 0x4301, 0x4301 }, 224 { 0x4305, 0x4307, 0x4307 }, 225 { 0x4402, 0x4403, 0x4402 }, 226 { 0x4610, 0x4615, 0x4610 }, 227 { 0x4710, 0x4715, 0x4710 }, 228 { 0x4720, 0x4725, 0x4309 } 229}; 230 231static const struct { 232 uint16_t bbp_id; 233 int nregwin; 234} bwi_regwin_count[] = { 235 { 0x4301, 5 }, 236 { 0x4306, 6 }, 237 { 0x4307, 5 }, 238 { 0x4310, 8 }, 239 { 0x4401, 3 }, 240 { 0x4402, 3 }, 241 { 0x4610, 9 }, 242 { 0x4704, 9 }, 243 { 0x4710, 9 }, 244 { 0x5365, 7 } 245}; 246 247#define CLKSRC(src) \ 248[BWI_CLKSRC_ ## src] = { \ 249 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 250 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 251} 252 253static const struct { 254 u_int freq_min; 255 u_int freq_max; 256} bwi_clkfreq[BWI_CLKSRC_MAX] = { 257 CLKSRC(LP_OSC), 258 CLKSRC(CS_OSC), 259 CLKSRC(PCI) 260}; 261 262#undef CLKSRC 263 264#define VENDOR_LED_ACT(vendor) \ 265{ \ 266 .vid = PCI_VENDOR_##vendor, \ 267 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 268} 269 270static const struct { 271#define PCI_VENDOR_COMPAQ 0x0e11 272#define PCI_VENDOR_LINKSYS 0x1737 273 uint16_t vid; 274 uint8_t led_act[BWI_LED_MAX]; 275} bwi_vendor_led_act[] = { 276 VENDOR_LED_ACT(COMPAQ), 277 VENDOR_LED_ACT(LINKSYS) 278#undef PCI_VENDOR_LINKSYS 279#undef PCI_VENDOR_COMPAQ 280}; 281 282static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 283 { BWI_VENDOR_LED_ACT_DEFAULT }; 284 285#undef VENDOR_LED_ACT 286 287static const struct { 288 int on_dur; 289 int off_dur; 290} bwi_led_duration[109] = { 291 [0] = { 400, 100 }, 292 [2] = { 150, 75 }, 293 [4] = { 90, 45 }, 294 [11] = { 66, 34 }, 295 [12] = { 53, 26 }, 296 [18] = { 42, 21 }, 297 [22] = { 35, 17 }, 298 [24] = { 32, 16 }, 299 [36] = { 21, 10 }, 300 [48] = { 16, 8 }, 301 [72] = { 11, 5 }, 302 [96] = { 9, 4 }, 303 [108] = { 7, 3 } 304}; 305 306#ifdef BWI_DEBUG 307#ifdef BWI_DEBUG_VERBOSE 308static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 309#else 310static uint32_t bwi_debug; 311#endif 312TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 313#endif /* BWI_DEBUG */ 314 315static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 316 317uint16_t 318bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 319{ 320 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 321} 322 323static __inline void 324bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 325 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 326 int tx) 327{ 328 struct bwi_desc32 *desc = &desc_array[desc_idx]; 329 uint32_t ctrl, addr, addr_hi, addr_lo; 330 331 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 332 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 333 334 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 335 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 336 337 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 338 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 339 if (desc_idx == ndesc - 1) 340 ctrl |= BWI_DESC32_C_EOR; 341 if (tx) { 342 /* XXX */ 343 ctrl |= BWI_DESC32_C_FRAME_START | 344 BWI_DESC32_C_FRAME_END | 345 BWI_DESC32_C_INTR; 346 } 347 348 desc->addr = htole32(addr); 349 desc->ctrl = htole32(ctrl); 350} 351 352int 353bwi_attach(struct bwi_softc *sc) 354{ 355 struct ieee80211com *ic = &sc->sc_ic; 356 device_t dev = sc->sc_dev; 357 struct bwi_mac *mac; 358 struct bwi_phy *phy; 359 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 360 int i, error; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 373 mbufq_init(&sc->sc_snd, ifqmaxlen); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_blink = 1; 381 sc->sc_txpwr_calib = 1; 382#ifdef BWI_DEBUG 383 sc->sc_debug = bwi_debug; 384#endif 385 bwi_power_on(sc, 1); 386 387 error = bwi_bbp_attach(sc); 388 if (error) 389 goto fail; 390 391 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 392 if (error) 393 goto fail; 394 395 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 396 error = bwi_set_clock_delay(sc); 397 if (error) 398 goto fail; 399 400 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 401 if (error) 402 goto fail; 403 404 error = bwi_get_pwron_delay(sc); 405 if (error) 406 goto fail; 407 } 408 409 error = bwi_bus_attach(sc); 410 if (error) 411 goto fail; 412 413 bwi_get_card_flags(sc); 414 415 bwi_led_attach(sc); 416 417 for (i = 0; i < sc->sc_nmac; ++i) { 418 struct bwi_regwin *old; 419 420 mac = &sc->sc_mac[i]; 421 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 422 if (error) 423 goto fail; 424 425 error = bwi_mac_lateattach(mac); 426 if (error) 427 goto fail; 428 429 error = bwi_regwin_switch(sc, old, NULL); 430 if (error) 431 goto fail; 432 } 433 434 /* 435 * XXX First MAC is known to exist 436 * TODO2 437 */ 438 mac = &sc->sc_mac[0]; 439 phy = &mac->mac_phy; 440 441 bwi_bbp_power_off(sc); 442 443 error = bwi_dma_alloc(sc); 444 if (error) 445 goto fail; 446 447 error = bwi_mac_fw_alloc(mac); 448 if (error) 449 goto fail; 450 451 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 452 453 /* 454 * Setup ratesets, phytype, channels and get MAC address 455 */ 456 memset(bands, 0, sizeof(bands)); 457 if (phy->phy_mode == IEEE80211_MODE_11B || 458 phy->phy_mode == IEEE80211_MODE_11G) { 459 setbit(bands, IEEE80211_MODE_11B); 460 if (phy->phy_mode == IEEE80211_MODE_11B) { 461 ic->ic_phytype = IEEE80211_T_DS; 462 } else { 463 ic->ic_phytype = IEEE80211_T_OFDM; 464 setbit(bands, IEEE80211_MODE_11G); 465 } 466 467 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 469 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 470 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 471 device_printf(dev, 472 "invalid MAC address: %6D\n", 473 ic->ic_macaddr, ":"); 474 } 475 } 476 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 477 /* TODO:11A */ 478 setbit(bands, IEEE80211_MODE_11A); 479 error = ENXIO; 480 goto fail; 481 } else { 482 panic("unknown phymode %d\n", phy->phy_mode); 483 } 484 485 /* Get locale */ 486 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 487 BWI_SPROM_CARD_INFO_LOCALE); 488 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 489 /* XXX use locale */ 490 ieee80211_init_channels(ic, NULL, bands); 491 492 ic->ic_softc = sc; 493 ic->ic_name = device_get_nameunit(dev); 494 ic->ic_caps = IEEE80211_C_STA | 495 IEEE80211_C_SHSLOT | 496 IEEE80211_C_SHPREAMBLE | 497 IEEE80211_C_WPA | 498 IEEE80211_C_BGSCAN | 499 IEEE80211_C_MONITOR; 500 ic->ic_opmode = IEEE80211_M_STA; 501 ieee80211_ifattach(ic); 502 503 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 504 505 /* override default methods */ 506 ic->ic_vap_create = bwi_vap_create; 507 ic->ic_vap_delete = bwi_vap_delete; 508 ic->ic_raw_xmit = bwi_raw_xmit; 509 ic->ic_updateslot = bwi_updateslot; 510 ic->ic_scan_start = bwi_scan_start; 511 ic->ic_scan_end = bwi_scan_end; 512 ic->ic_set_channel = bwi_set_channel; 513 ic->ic_transmit = bwi_transmit; 514 ic->ic_parent = bwi_parent; 515 516 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 517 518 ieee80211_radiotap_attach(ic, 519 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 520 BWI_TX_RADIOTAP_PRESENT, 521 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 522 BWI_RX_RADIOTAP_PRESENT); 523 524 /* 525 * Add sysctl nodes 526 */ 527 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 528 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 529 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 530 "Firmware version"); 531 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 533 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 534 "# ticks before LED enters idle state"); 535 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 537 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 538 "Allow LED to blink"); 539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 541 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 542 "Enable software TX power calibration"); 543#ifdef BWI_DEBUG 544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 547#endif 548 if (bootverbose) 549 ieee80211_announce(ic); 550 551 return (0); 552fail: 553 BWI_LOCK_DESTROY(sc); 554 return (error); 555} 556 557int 558bwi_detach(struct bwi_softc *sc) 559{ 560 struct ieee80211com *ic = &sc->sc_ic; 561 int i; 562 563 bwi_stop(sc, 1); 564 callout_drain(&sc->sc_led_blink_ch); 565 callout_drain(&sc->sc_calib_ch); 566 callout_drain(&sc->sc_watchdog_timer); 567 ieee80211_ifdetach(ic); 568 569 for (i = 0; i < sc->sc_nmac; ++i) 570 bwi_mac_detach(&sc->sc_mac[i]); 571 bwi_dma_free(sc); 572 taskqueue_free(sc->sc_tq); 573 mbufq_drain(&sc->sc_snd); 574 575 BWI_LOCK_DESTROY(sc); 576 577 return (0); 578} 579 580static struct ieee80211vap * 581bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 582 enum ieee80211_opmode opmode, int flags, 583 const uint8_t bssid[IEEE80211_ADDR_LEN], 584 const uint8_t mac[IEEE80211_ADDR_LEN]) 585{ 586 struct bwi_vap *bvp; 587 struct ieee80211vap *vap; 588 589 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 590 return NULL; 591 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 592 vap = &bvp->bv_vap; 593 /* enable s/w bmiss handling for sta mode */ 594 ieee80211_vap_setup(ic, vap, name, unit, opmode, 595 flags | IEEE80211_CLONE_NOBEACONS, bssid); 596 597 /* override default methods */ 598 bvp->bv_newstate = vap->iv_newstate; 599 vap->iv_newstate = bwi_newstate; 600#if 0 601 vap->iv_update_beacon = bwi_beacon_update; 602#endif 603 ieee80211_ratectl_init(vap); 604 605 /* complete setup */ 606 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status, 607 mac); 608 ic->ic_opmode = opmode; 609 return vap; 610} 611 612static void 613bwi_vap_delete(struct ieee80211vap *vap) 614{ 615 struct bwi_vap *bvp = BWI_VAP(vap); 616 617 ieee80211_ratectl_deinit(vap); 618 ieee80211_vap_detach(vap); 619 free(bvp, M_80211_VAP); 620} 621 622void 623bwi_suspend(struct bwi_softc *sc) 624{ 625 bwi_stop(sc, 1); 626} 627 628void 629bwi_resume(struct bwi_softc *sc) 630{ 631 632 if (sc->sc_ic.ic_nrunning > 0) 633 bwi_init(sc); 634} 635 636int 637bwi_shutdown(struct bwi_softc *sc) 638{ 639 bwi_stop(sc, 1); 640 return 0; 641} 642 643static void 644bwi_power_on(struct bwi_softc *sc, int with_pll) 645{ 646 uint32_t gpio_in, gpio_out, gpio_en; 647 uint16_t status; 648 649 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 650 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 651 goto back; 652 653 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 654 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 655 656 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 657 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 658 if (with_pll) { 659 /* Turn off PLL first */ 660 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 661 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 662 } 663 664 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 665 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 666 DELAY(1000); 667 668 if (with_pll) { 669 /* Turn on PLL */ 670 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 671 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 672 DELAY(5000); 673 } 674 675back: 676 /* Clear "Signaled Target Abort" */ 677 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 678 status &= ~PCIM_STATUS_STABORT; 679 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 680} 681 682static int 683bwi_power_off(struct bwi_softc *sc, int with_pll) 684{ 685 uint32_t gpio_out, gpio_en; 686 687 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 688 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 689 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 690 691 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 692 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 693 if (with_pll) { 694 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 695 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 696 } 697 698 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 699 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 700 return 0; 701} 702 703int 704bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 705 struct bwi_regwin **old_rw) 706{ 707 int error; 708 709 if (old_rw != NULL) 710 *old_rw = NULL; 711 712 if (!BWI_REGWIN_EXIST(rw)) 713 return EINVAL; 714 715 if (sc->sc_cur_regwin != rw) { 716 error = bwi_regwin_select(sc, rw->rw_id); 717 if (error) { 718 device_printf(sc->sc_dev, "can't select regwin %d\n", 719 rw->rw_id); 720 return error; 721 } 722 } 723 724 if (old_rw != NULL) 725 *old_rw = sc->sc_cur_regwin; 726 sc->sc_cur_regwin = rw; 727 return 0; 728} 729 730static int 731bwi_regwin_select(struct bwi_softc *sc, int id) 732{ 733 uint32_t win = BWI_PCIM_REGWIN(id); 734 int i; 735 736#define RETRY_MAX 50 737 for (i = 0; i < RETRY_MAX; ++i) { 738 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 739 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 740 return 0; 741 DELAY(10); 742 } 743#undef RETRY_MAX 744 745 return ENXIO; 746} 747 748static void 749bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 750{ 751 uint32_t val; 752 753 val = CSR_READ_4(sc, BWI_ID_HI); 754 *type = BWI_ID_HI_REGWIN_TYPE(val); 755 *rev = BWI_ID_HI_REGWIN_REV(val); 756 757 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 758 "vendor 0x%04x\n", *type, *rev, 759 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 760} 761 762static int 763bwi_bbp_attach(struct bwi_softc *sc) 764{ 765 uint16_t bbp_id, rw_type; 766 uint8_t rw_rev; 767 uint32_t info; 768 int error, nregwin, i; 769 770 /* 771 * Get 0th regwin information 772 * NOTE: 0th regwin should exist 773 */ 774 error = bwi_regwin_select(sc, 0); 775 if (error) { 776 device_printf(sc->sc_dev, "can't select regwin 0\n"); 777 return error; 778 } 779 bwi_regwin_info(sc, &rw_type, &rw_rev); 780 781 /* 782 * Find out BBP id 783 */ 784 bbp_id = 0; 785 info = 0; 786 if (rw_type == BWI_REGWIN_T_COM) { 787 info = CSR_READ_4(sc, BWI_INFO); 788 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 789 790 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 791 792 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 793 } else { 794 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 795 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 796 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 797 bbp_id = bwi_bbpid_map[i].bbp_id; 798 break; 799 } 800 } 801 if (bbp_id == 0) { 802 device_printf(sc->sc_dev, "no BBP id for device id " 803 "0x%04x\n", sc->sc_pci_did); 804 return ENXIO; 805 } 806 807 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 808 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 809 } 810 811 /* 812 * Find out number of regwins 813 */ 814 nregwin = 0; 815 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 816 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 817 } else { 818 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 819 if (bwi_regwin_count[i].bbp_id == bbp_id) { 820 nregwin = bwi_regwin_count[i].nregwin; 821 break; 822 } 823 } 824 if (nregwin == 0) { 825 device_printf(sc->sc_dev, "no number of win for " 826 "BBP id 0x%04x\n", bbp_id); 827 return ENXIO; 828 } 829 } 830 831 /* Record BBP id/rev for later using */ 832 sc->sc_bbp_id = bbp_id; 833 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 834 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 835 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 836 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 837 838 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 839 nregwin, sc->sc_cap); 840 841 /* 842 * Create rest of the regwins 843 */ 844 845 /* Don't re-create common regwin, if it is already created */ 846 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 847 848 for (; i < nregwin; ++i) { 849 /* 850 * Get regwin information 851 */ 852 error = bwi_regwin_select(sc, i); 853 if (error) { 854 device_printf(sc->sc_dev, 855 "can't select regwin %d\n", i); 856 return error; 857 } 858 bwi_regwin_info(sc, &rw_type, &rw_rev); 859 860 /* 861 * Try attach: 862 * 1) Bus (PCI/PCIE) regwin 863 * 2) MAC regwin 864 * Ignore rest types of regwin 865 */ 866 if (rw_type == BWI_REGWIN_T_BUSPCI || 867 rw_type == BWI_REGWIN_T_BUSPCIE) { 868 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 869 device_printf(sc->sc_dev, 870 "bus regwin already exists\n"); 871 } else { 872 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 873 rw_type, rw_rev); 874 } 875 } else if (rw_type == BWI_REGWIN_T_MAC) { 876 /* XXX ignore return value */ 877 bwi_mac_attach(sc, i, rw_rev); 878 } 879 } 880 881 /* At least one MAC shold exist */ 882 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 883 device_printf(sc->sc_dev, "no MAC was found\n"); 884 return ENXIO; 885 } 886 KASSERT(sc->sc_nmac > 0, ("no mac's")); 887 888 /* Bus regwin must exist */ 889 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 890 device_printf(sc->sc_dev, "no bus regwin was found\n"); 891 return ENXIO; 892 } 893 894 /* Start with first MAC */ 895 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 896 if (error) 897 return error; 898 899 return 0; 900} 901 902int 903bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 904{ 905 struct bwi_regwin *old, *bus; 906 uint32_t val; 907 int error; 908 909 bus = &sc->sc_bus_regwin; 910 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 911 912 /* 913 * Tell bus to generate requested interrupts 914 */ 915 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 916 /* 917 * NOTE: Read BWI_FLAGS from MAC regwin 918 */ 919 val = CSR_READ_4(sc, BWI_FLAGS); 920 921 error = bwi_regwin_switch(sc, bus, &old); 922 if (error) 923 return error; 924 925 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 926 } else { 927 uint32_t mac_mask; 928 929 mac_mask = 1 << mac->mac_id; 930 931 error = bwi_regwin_switch(sc, bus, &old); 932 if (error) 933 return error; 934 935 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 936 val |= mac_mask << 8; 937 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 938 } 939 940 if (sc->sc_flags & BWI_F_BUS_INITED) 941 goto back; 942 943 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 944 /* 945 * Enable prefetch and burst 946 */ 947 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 948 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 949 950 if (bus->rw_rev < 5) { 951 struct bwi_regwin *com = &sc->sc_com_regwin; 952 953 /* 954 * Configure timeouts for bus operation 955 */ 956 957 /* 958 * Set service timeout and request timeout 959 */ 960 CSR_SETBITS_4(sc, BWI_CONF_LO, 961 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 962 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 963 964 /* 965 * If there is common regwin, we switch to that regwin 966 * and switch back to bus regwin once we have done. 967 */ 968 if (BWI_REGWIN_EXIST(com)) { 969 error = bwi_regwin_switch(sc, com, NULL); 970 if (error) 971 return error; 972 } 973 974 /* Let bus know what we have changed */ 975 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 976 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 977 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 978 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 979 980 if (BWI_REGWIN_EXIST(com)) { 981 error = bwi_regwin_switch(sc, bus, NULL); 982 if (error) 983 return error; 984 } 985 } else if (bus->rw_rev >= 11) { 986 /* 987 * Enable memory read multiple 988 */ 989 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 990 } 991 } else { 992 /* TODO:PCIE */ 993 } 994 995 sc->sc_flags |= BWI_F_BUS_INITED; 996back: 997 return bwi_regwin_switch(sc, old, NULL); 998} 999 1000static void 1001bwi_get_card_flags(struct bwi_softc *sc) 1002{ 1003#define PCI_VENDOR_APPLE 0x106b 1004#define PCI_VENDOR_DELL 0x1028 1005 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1006 if (sc->sc_card_flags == 0xffff) 1007 sc->sc_card_flags = 0; 1008 1009 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1010 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1011 sc->sc_pci_revid == 0x74) 1012 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1013 1014 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1015 sc->sc_pci_subdid == 0x4e && /* XXX */ 1016 sc->sc_pci_revid > 0x40) 1017 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1018 1019 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1020#undef PCI_VENDOR_DELL 1021#undef PCI_VENDOR_APPLE 1022} 1023 1024static void 1025bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1026{ 1027 int i; 1028 1029 for (i = 0; i < 3; ++i) { 1030 *((uint16_t *)eaddr + i) = 1031 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1032 } 1033} 1034 1035static void 1036bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1037{ 1038 struct bwi_regwin *com; 1039 uint32_t val; 1040 u_int div; 1041 int src; 1042 1043 bzero(freq, sizeof(*freq)); 1044 com = &sc->sc_com_regwin; 1045 1046 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1047 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1048 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1049 1050 /* 1051 * Calculate clock frequency 1052 */ 1053 src = -1; 1054 div = 0; 1055 if (com->rw_rev < 6) { 1056 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1057 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1058 src = BWI_CLKSRC_PCI; 1059 div = 64; 1060 } else { 1061 src = BWI_CLKSRC_CS_OSC; 1062 div = 32; 1063 } 1064 } else if (com->rw_rev < 10) { 1065 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1066 1067 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1068 if (src == BWI_CLKSRC_LP_OSC) { 1069 div = 1; 1070 } else { 1071 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1072 1073 /* Unknown source */ 1074 if (src >= BWI_CLKSRC_MAX) 1075 src = BWI_CLKSRC_CS_OSC; 1076 } 1077 } else { 1078 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1079 1080 src = BWI_CLKSRC_CS_OSC; 1081 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1082 } 1083 1084 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1085 KASSERT(div != 0, ("div zero")); 1086 1087 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1088 src == BWI_CLKSRC_PCI ? "PCI" : 1089 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1090 1091 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1092 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1093 1094 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1095 freq->clkfreq_min, freq->clkfreq_max); 1096} 1097 1098static int 1099bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1100{ 1101 struct bwi_regwin *old, *com; 1102 uint32_t clk_ctrl, clk_src; 1103 int error, pwr_off = 0; 1104 1105 com = &sc->sc_com_regwin; 1106 if (!BWI_REGWIN_EXIST(com)) 1107 return 0; 1108 1109 if (com->rw_rev >= 10 || com->rw_rev < 6) 1110 return 0; 1111 1112 /* 1113 * For common regwin whose rev is [6, 10), the chip 1114 * must be capable to change clock mode. 1115 */ 1116 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1117 return 0; 1118 1119 error = bwi_regwin_switch(sc, com, &old); 1120 if (error) 1121 return error; 1122 1123 if (clk_mode == BWI_CLOCK_MODE_FAST) 1124 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1125 1126 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1127 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1128 1129 switch (clk_mode) { 1130 case BWI_CLOCK_MODE_FAST: 1131 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1132 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1133 break; 1134 case BWI_CLOCK_MODE_SLOW: 1135 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1136 break; 1137 case BWI_CLOCK_MODE_DYN: 1138 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1139 BWI_CLOCK_CTRL_IGNPLL | 1140 BWI_CLOCK_CTRL_NODYN); 1141 if (clk_src != BWI_CLKSRC_CS_OSC) { 1142 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1143 pwr_off = 1; 1144 } 1145 break; 1146 } 1147 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1148 1149 if (pwr_off) 1150 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1151 1152 return bwi_regwin_switch(sc, old, NULL); 1153} 1154 1155static int 1156bwi_set_clock_delay(struct bwi_softc *sc) 1157{ 1158 struct bwi_regwin *old, *com; 1159 int error; 1160 1161 com = &sc->sc_com_regwin; 1162 if (!BWI_REGWIN_EXIST(com)) 1163 return 0; 1164 1165 error = bwi_regwin_switch(sc, com, &old); 1166 if (error) 1167 return error; 1168 1169 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1170 if (sc->sc_bbp_rev == 0) 1171 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1172 else if (sc->sc_bbp_rev == 1) 1173 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1174 } 1175 1176 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1177 if (com->rw_rev >= 10) { 1178 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1179 } else { 1180 struct bwi_clock_freq freq; 1181 1182 bwi_get_clock_freq(sc, &freq); 1183 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1184 howmany(freq.clkfreq_max * 150, 1000000)); 1185 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1186 howmany(freq.clkfreq_max * 15, 1000000)); 1187 } 1188 } 1189 1190 return bwi_regwin_switch(sc, old, NULL); 1191} 1192 1193static void 1194bwi_init(struct bwi_softc *sc) 1195{ 1196 struct ieee80211com *ic = &sc->sc_ic; 1197 1198 BWI_LOCK(sc); 1199 bwi_init_statechg(sc, 1); 1200 BWI_UNLOCK(sc); 1201 1202 if (sc->sc_flags & BWI_F_RUNNING) 1203 ieee80211_start_all(ic); /* start all vap's */ 1204} 1205 1206static void 1207bwi_init_statechg(struct bwi_softc *sc, int statechg) 1208{ 1209 struct bwi_mac *mac; 1210 int error; 1211 1212 BWI_ASSERT_LOCKED(sc); 1213 1214 bwi_stop_locked(sc, statechg); 1215 1216 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1217 1218 /* TODO: 2 MAC */ 1219 1220 mac = &sc->sc_mac[0]; 1221 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1222 if (error) { 1223 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1224 __func__, error); 1225 goto bad; 1226 } 1227 error = bwi_mac_init(mac); 1228 if (error) { 1229 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1230 __func__, error); 1231 goto bad; 1232 } 1233 1234 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1235 1236 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1237 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1238 1239 bwi_mac_reset_hwkeys(mac); 1240 1241 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1242 int i; 1243 1244#define NRETRY 1000 1245 /* 1246 * Drain any possible pending TX status 1247 */ 1248 for (i = 0; i < NRETRY; ++i) { 1249 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1250 BWI_TXSTATUS0_VALID) == 0) 1251 break; 1252 CSR_READ_4(sc, BWI_TXSTATUS1); 1253 } 1254 if (i == NRETRY) 1255 device_printf(sc->sc_dev, 1256 "%s: can't drain TX status\n", __func__); 1257#undef NRETRY 1258 } 1259 1260 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1261 bwi_mac_updateslot(mac, 1); 1262 1263 /* Start MAC */ 1264 error = bwi_mac_start(mac); 1265 if (error) { 1266 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1267 __func__, error); 1268 goto bad; 1269 } 1270 1271 /* Clear stop flag before enabling interrupt */ 1272 sc->sc_flags &= ~BWI_F_STOP; 1273 sc->sc_flags |= BWI_F_RUNNING; 1274 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1275 1276 /* Enable intrs */ 1277 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1278 return; 1279bad: 1280 bwi_stop_locked(sc, 1); 1281} 1282 1283static void 1284bwi_parent(struct ieee80211com *ic) 1285{ 1286 struct bwi_softc *sc = ic->ic_softc; 1287 int startall = 0; 1288 1289 BWI_LOCK(sc); 1290 if (ic->ic_nrunning > 0) { 1291 struct bwi_mac *mac; 1292 int promisc = -1; 1293 1294 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1295 ("current regwin type %d", 1296 sc->sc_cur_regwin->rw_type)); 1297 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1298 1299 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1300 promisc = 1; 1301 sc->sc_flags |= BWI_F_PROMISC; 1302 } else if (ic->ic_promisc == 0 && 1303 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1304 promisc = 0; 1305 sc->sc_flags &= ~BWI_F_PROMISC; 1306 } 1307 1308 if (promisc >= 0) 1309 bwi_mac_set_promisc(mac, promisc); 1310 } 1311 if (ic->ic_nrunning > 0) { 1312 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1313 bwi_init_statechg(sc, 1); 1314 startall = 1; 1315 } 1316 } else if (sc->sc_flags & BWI_F_RUNNING) 1317 bwi_stop_locked(sc, 1); 1318 BWI_UNLOCK(sc); 1319 if (startall) 1320 ieee80211_start_all(ic); 1321} 1322 1323static int 1324bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1325{ 1326 struct bwi_softc *sc = ic->ic_softc; 1327 int error; 1328 1329 BWI_LOCK(sc); 1330 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1331 BWI_UNLOCK(sc); 1332 return (ENXIO); 1333 } 1334 error = mbufq_enqueue(&sc->sc_snd, m); 1335 if (error) { 1336 BWI_UNLOCK(sc); 1337 return (error); 1338 } 1339 bwi_start_locked(sc); 1340 BWI_UNLOCK(sc); 1341 return (0); 1342} 1343 1344static void 1345bwi_start_locked(struct bwi_softc *sc) 1346{ 1347 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1348 struct ieee80211_frame *wh; 1349 struct ieee80211_node *ni; 1350 struct mbuf *m; 1351 int trans, idx; 1352 1353 BWI_ASSERT_LOCKED(sc); 1354 1355 trans = 0; 1356 idx = tbd->tbd_idx; 1357 1358 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1359 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1360 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1361 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1362 wh = mtod(m, struct ieee80211_frame *); 1363 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1364 ieee80211_crypto_encap(ni, m) == NULL) { 1365 if_inc_counter(ni->ni_vap->iv_ifp, 1366 IFCOUNTER_OERRORS, 1); 1367 ieee80211_free_node(ni); 1368 m_freem(m); 1369 continue; 1370 } 1371 if (bwi_encap(sc, idx, m, ni) != 0) { 1372 /* 'm' is freed in bwi_encap() if we reach here */ 1373 if (ni != NULL) { 1374 if_inc_counter(ni->ni_vap->iv_ifp, 1375 IFCOUNTER_OERRORS, 1); 1376 ieee80211_free_node(ni); 1377 } else 1378 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1379 continue; 1380 } 1381 trans = 1; 1382 tbd->tbd_used++; 1383 idx = (idx + 1) % BWI_TX_NDESC; 1384 } 1385 1386 tbd->tbd_idx = idx; 1387 if (trans) 1388 sc->sc_tx_timer = 5; 1389} 1390 1391static int 1392bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1393 const struct ieee80211_bpf_params *params) 1394{ 1395 struct ieee80211com *ic = ni->ni_ic; 1396 struct bwi_softc *sc = ic->ic_softc; 1397 /* XXX wme? */ 1398 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1399 int idx, error; 1400 1401 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1402 m_freem(m); 1403 return ENETDOWN; 1404 } 1405 1406 BWI_LOCK(sc); 1407 idx = tbd->tbd_idx; 1408 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1409 if (params == NULL) { 1410 /* 1411 * Legacy path; interpret frame contents to decide 1412 * precisely how to send the frame. 1413 */ 1414 error = bwi_encap(sc, idx, m, ni); 1415 } else { 1416 /* 1417 * Caller supplied explicit parameters to use in 1418 * sending the frame. 1419 */ 1420 error = bwi_encap_raw(sc, idx, m, ni, params); 1421 } 1422 if (error == 0) { 1423 tbd->tbd_used++; 1424 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1425 sc->sc_tx_timer = 5; 1426 } 1427 BWI_UNLOCK(sc); 1428 return error; 1429} 1430 1431static void 1432bwi_watchdog(void *arg) 1433{ 1434 struct bwi_softc *sc; 1435 1436 sc = arg; 1437 BWI_ASSERT_LOCKED(sc); 1438 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1439 device_printf(sc->sc_dev, "watchdog timeout\n"); 1440 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1441 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1442 } 1443 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1444} 1445 1446static void 1447bwi_stop(struct bwi_softc *sc, int statechg) 1448{ 1449 BWI_LOCK(sc); 1450 bwi_stop_locked(sc, statechg); 1451 BWI_UNLOCK(sc); 1452} 1453 1454static void 1455bwi_stop_locked(struct bwi_softc *sc, int statechg) 1456{ 1457 struct bwi_mac *mac; 1458 int i, error, pwr_off = 0; 1459 1460 BWI_ASSERT_LOCKED(sc); 1461 1462 callout_stop(&sc->sc_calib_ch); 1463 callout_stop(&sc->sc_led_blink_ch); 1464 sc->sc_led_blinking = 0; 1465 sc->sc_flags |= BWI_F_STOP; 1466 1467 if (sc->sc_flags & BWI_F_RUNNING) { 1468 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1469 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1470 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1471 1472 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1473 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1474 bwi_mac_stop(mac); 1475 } 1476 1477 for (i = 0; i < sc->sc_nmac; ++i) { 1478 struct bwi_regwin *old_rw; 1479 1480 mac = &sc->sc_mac[i]; 1481 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1482 continue; 1483 1484 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1485 if (error) 1486 continue; 1487 1488 bwi_mac_shutdown(mac); 1489 pwr_off = 1; 1490 1491 bwi_regwin_switch(sc, old_rw, NULL); 1492 } 1493 1494 if (pwr_off) 1495 bwi_bbp_power_off(sc); 1496 1497 sc->sc_tx_timer = 0; 1498 callout_stop(&sc->sc_watchdog_timer); 1499 sc->sc_flags &= ~BWI_F_RUNNING; 1500} 1501 1502void 1503bwi_intr(void *xsc) 1504{ 1505 struct bwi_softc *sc = xsc; 1506 struct bwi_mac *mac; 1507 uint32_t intr_status; 1508 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1509 int i, txrx_error, tx = 0, rx_data = -1; 1510 1511 BWI_LOCK(sc); 1512 1513 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1514 (sc->sc_flags & BWI_F_STOP)) { 1515 BWI_UNLOCK(sc); 1516 return; 1517 } 1518 /* 1519 * Get interrupt status 1520 */ 1521 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1522 if (intr_status == 0xffffffff) { /* Not for us */ 1523 BWI_UNLOCK(sc); 1524 return; 1525 } 1526 1527 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1528 1529 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1530 if (intr_status == 0) { /* Nothing is interesting */ 1531 BWI_UNLOCK(sc); 1532 return; 1533 } 1534 1535 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1536 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1537 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1538 1539 txrx_error = 0; 1540 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1541 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1542 uint32_t mask; 1543 1544 if (BWI_TXRX_IS_RX(i)) 1545 mask = BWI_TXRX_RX_INTRS; 1546 else 1547 mask = BWI_TXRX_TX_INTRS; 1548 1549 txrx_intr_status[i] = 1550 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1551 1552 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1553 i, txrx_intr_status[i]); 1554 1555 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1556 device_printf(sc->sc_dev, 1557 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1558 __func__, i, txrx_intr_status[i]); 1559 txrx_error = 1; 1560 } 1561 } 1562 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1563 1564 /* 1565 * Acknowledge interrupt 1566 */ 1567 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1568 1569 for (i = 0; i < BWI_TXRX_NRING; ++i) 1570 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1571 1572 /* Disable all interrupts */ 1573 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1574 1575 /* 1576 * http://bcm-specs.sipsolutions.net/Interrupts 1577 * Says for this bit (0x800): 1578 * "Fatal Error 1579 * 1580 * We got this one while testing things when by accident the 1581 * template ram wasn't set to big endian when it should have 1582 * been after writing the initial values. It keeps on being 1583 * triggered, the only way to stop it seems to shut down the 1584 * chip." 1585 * 1586 * Suggesting that we should never get it and if we do we're not 1587 * feeding TX packets into the MAC correctly if we do... Apparently, 1588 * it is valid only on mac version 5 and higher, but I couldn't 1589 * find a reference for that... Since I see them from time to time 1590 * on my card, this suggests an error in the tx path still... 1591 */ 1592 if (intr_status & BWI_INTR_PHY_TXERR) { 1593 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1594 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1595 __func__); 1596 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1597 BWI_UNLOCK(sc); 1598 return; 1599 } 1600 } 1601 1602 if (txrx_error) { 1603 /* TODO: reset device */ 1604 } 1605 1606 if (intr_status & BWI_INTR_TBTT) 1607 bwi_mac_config_ps(mac); 1608 1609 if (intr_status & BWI_INTR_EO_ATIM) 1610 device_printf(sc->sc_dev, "EO_ATIM\n"); 1611 1612 if (intr_status & BWI_INTR_PMQ) { 1613 for (;;) { 1614 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1615 break; 1616 } 1617 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1618 } 1619 1620 if (intr_status & BWI_INTR_NOISE) 1621 device_printf(sc->sc_dev, "intr noise\n"); 1622 1623 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1624 rx_data = sc->sc_rxeof(sc); 1625 if (sc->sc_flags & BWI_F_STOP) { 1626 BWI_UNLOCK(sc); 1627 return; 1628 } 1629 } 1630 1631 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1632 sc->sc_txeof_status(sc); 1633 tx = 1; 1634 } 1635 1636 if (intr_status & BWI_INTR_TX_DONE) { 1637 bwi_txeof(sc); 1638 tx = 1; 1639 } 1640 1641 /* Re-enable interrupts */ 1642 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1643 1644 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1645 int evt = BWI_LED_EVENT_NONE; 1646 1647 if (tx && rx_data > 0) { 1648 if (sc->sc_rx_rate > sc->sc_tx_rate) 1649 evt = BWI_LED_EVENT_RX; 1650 else 1651 evt = BWI_LED_EVENT_TX; 1652 } else if (tx) { 1653 evt = BWI_LED_EVENT_TX; 1654 } else if (rx_data > 0) { 1655 evt = BWI_LED_EVENT_RX; 1656 } else if (rx_data == 0) { 1657 evt = BWI_LED_EVENT_POLL; 1658 } 1659 1660 if (evt != BWI_LED_EVENT_NONE) 1661 bwi_led_event(sc, evt); 1662 } 1663 1664 BWI_UNLOCK(sc); 1665} 1666 1667static void 1668bwi_scan_start(struct ieee80211com *ic) 1669{ 1670 struct bwi_softc *sc = ic->ic_softc; 1671 1672 BWI_LOCK(sc); 1673 /* Enable MAC beacon promiscuity */ 1674 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1675 BWI_UNLOCK(sc); 1676} 1677 1678static void 1679bwi_set_channel(struct ieee80211com *ic) 1680{ 1681 struct bwi_softc *sc = ic->ic_softc; 1682 struct ieee80211_channel *c = ic->ic_curchan; 1683 struct bwi_mac *mac; 1684 1685 BWI_LOCK(sc); 1686 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1687 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1688 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1689 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1690 1691 sc->sc_rates = ieee80211_get_ratetable(c); 1692 1693 /* 1694 * Setup radio tap channel freq and flags 1695 */ 1696 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1697 htole16(c->ic_freq); 1698 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1699 htole16(c->ic_flags & 0xffff); 1700 1701 BWI_UNLOCK(sc); 1702} 1703 1704static void 1705bwi_scan_end(struct ieee80211com *ic) 1706{ 1707 struct bwi_softc *sc = ic->ic_softc; 1708 1709 BWI_LOCK(sc); 1710 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1711 BWI_UNLOCK(sc); 1712} 1713 1714static int 1715bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1716{ 1717 struct bwi_vap *bvp = BWI_VAP(vap); 1718 struct ieee80211com *ic= vap->iv_ic; 1719 struct bwi_softc *sc = ic->ic_softc; 1720 enum ieee80211_state ostate = vap->iv_state; 1721 struct bwi_mac *mac; 1722 int error; 1723 1724 BWI_LOCK(sc); 1725 1726 callout_stop(&sc->sc_calib_ch); 1727 1728 if (nstate == IEEE80211_S_INIT) 1729 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1730 1731 bwi_led_newstate(sc, nstate); 1732 1733 error = bvp->bv_newstate(vap, nstate, arg); 1734 if (error != 0) 1735 goto back; 1736 1737 /* 1738 * Clear the BSSID when we stop a STA 1739 */ 1740 if (vap->iv_opmode == IEEE80211_M_STA) { 1741 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1742 /* 1743 * Clear out the BSSID. If we reassociate to 1744 * the same AP, this will reinialize things 1745 * correctly... 1746 */ 1747 if (ic->ic_opmode == IEEE80211_M_STA && 1748 !(sc->sc_flags & BWI_F_STOP)) 1749 bwi_set_bssid(sc, bwi_zero_addr); 1750 } 1751 } 1752 1753 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1754 /* Nothing to do */ 1755 } else if (nstate == IEEE80211_S_RUN) { 1756 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1757 1758 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1759 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1760 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1761 1762 /* Initial TX power calibration */ 1763 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1764#ifdef notyet 1765 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1766#else 1767 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1768#endif 1769 1770 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1771 } 1772back: 1773 BWI_UNLOCK(sc); 1774 1775 return error; 1776} 1777 1778static int 1779bwi_media_change(struct ifnet *ifp) 1780{ 1781 int error = ieee80211_media_change(ifp); 1782 /* NB: only the fixed rate can change and that doesn't need a reset */ 1783 return (error == ENETRESET ? 0 : error); 1784} 1785 1786static int 1787bwi_dma_alloc(struct bwi_softc *sc) 1788{ 1789 int error, i, has_txstats; 1790 bus_addr_t lowaddr = 0; 1791 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1792 uint32_t txrx_ctrl_step = 0; 1793 1794 has_txstats = 0; 1795 for (i = 0; i < sc->sc_nmac; ++i) { 1796 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1797 has_txstats = 1; 1798 break; 1799 } 1800 } 1801 1802 switch (sc->sc_bus_space) { 1803 case BWI_BUS_SPACE_30BIT: 1804 case BWI_BUS_SPACE_32BIT: 1805 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1806 lowaddr = BWI_BUS_SPACE_MAXADDR; 1807 else 1808 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1809 desc_sz = sizeof(struct bwi_desc32); 1810 txrx_ctrl_step = 0x20; 1811 1812 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1813 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1814 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1815 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1816 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1817 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1818 sc->sc_rxeof = bwi_rxeof32; 1819 sc->sc_start_tx = bwi_start_tx32; 1820 if (has_txstats) { 1821 sc->sc_init_txstats = bwi_init_txstats32; 1822 sc->sc_free_txstats = bwi_free_txstats32; 1823 sc->sc_txeof_status = bwi_txeof_status32; 1824 } 1825 break; 1826 1827 case BWI_BUS_SPACE_64BIT: 1828 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1829 desc_sz = sizeof(struct bwi_desc64); 1830 txrx_ctrl_step = 0x40; 1831 1832 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1833 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1834 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1835 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1836 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1837 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1838 sc->sc_rxeof = bwi_rxeof64; 1839 sc->sc_start_tx = bwi_start_tx64; 1840 if (has_txstats) { 1841 sc->sc_init_txstats = bwi_init_txstats64; 1842 sc->sc_free_txstats = bwi_free_txstats64; 1843 sc->sc_txeof_status = bwi_txeof_status64; 1844 } 1845 break; 1846 } 1847 1848 KASSERT(lowaddr != 0, ("lowaddr zero")); 1849 KASSERT(desc_sz != 0, ("desc_sz zero")); 1850 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1851 1852 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1853 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1854 1855 /* 1856 * Create top level DMA tag 1857 */ 1858 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1859 BWI_ALIGN, 0, /* alignment, bounds */ 1860 lowaddr, /* lowaddr */ 1861 BUS_SPACE_MAXADDR, /* highaddr */ 1862 NULL, NULL, /* filter, filterarg */ 1863 BUS_SPACE_MAXSIZE, /* maxsize */ 1864 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1865 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1866 0, /* flags */ 1867 NULL, NULL, /* lockfunc, lockarg */ 1868 &sc->sc_parent_dtag); 1869 if (error) { 1870 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1871 return error; 1872 } 1873 1874#define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1875 1876 /* 1877 * Create TX ring DMA stuffs 1878 */ 1879 error = bus_dma_tag_create(sc->sc_parent_dtag, 1880 BWI_RING_ALIGN, 0, 1881 BUS_SPACE_MAXADDR, 1882 BUS_SPACE_MAXADDR, 1883 NULL, NULL, 1884 tx_ring_sz, 1885 1, 1886 tx_ring_sz, 1887 0, 1888 NULL, NULL, 1889 &sc->sc_txring_dtag); 1890 if (error) { 1891 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1892 return error; 1893 } 1894 1895 for (i = 0; i < BWI_TX_NRING; ++i) { 1896 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1897 &sc->sc_tx_rdata[i], tx_ring_sz, 1898 TXRX_CTRL(i)); 1899 if (error) { 1900 device_printf(sc->sc_dev, "%dth TX ring " 1901 "DMA alloc failed\n", i); 1902 return error; 1903 } 1904 } 1905 1906 /* 1907 * Create RX ring DMA stuffs 1908 */ 1909 error = bus_dma_tag_create(sc->sc_parent_dtag, 1910 BWI_RING_ALIGN, 0, 1911 BUS_SPACE_MAXADDR, 1912 BUS_SPACE_MAXADDR, 1913 NULL, NULL, 1914 rx_ring_sz, 1915 1, 1916 rx_ring_sz, 1917 0, 1918 NULL, NULL, 1919 &sc->sc_rxring_dtag); 1920 if (error) { 1921 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1922 return error; 1923 } 1924 1925 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1926 rx_ring_sz, TXRX_CTRL(0)); 1927 if (error) { 1928 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1929 return error; 1930 } 1931 1932 if (has_txstats) { 1933 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1934 if (error) { 1935 device_printf(sc->sc_dev, 1936 "TX stats DMA alloc failed\n"); 1937 return error; 1938 } 1939 } 1940 1941#undef TXRX_CTRL 1942 1943 return bwi_dma_mbuf_create(sc); 1944} 1945 1946static void 1947bwi_dma_free(struct bwi_softc *sc) 1948{ 1949 if (sc->sc_txring_dtag != NULL) { 1950 int i; 1951 1952 for (i = 0; i < BWI_TX_NRING; ++i) { 1953 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1954 1955 if (rd->rdata_desc != NULL) { 1956 bus_dmamap_unload(sc->sc_txring_dtag, 1957 rd->rdata_dmap); 1958 bus_dmamem_free(sc->sc_txring_dtag, 1959 rd->rdata_desc, 1960 rd->rdata_dmap); 1961 } 1962 } 1963 bus_dma_tag_destroy(sc->sc_txring_dtag); 1964 } 1965 1966 if (sc->sc_rxring_dtag != NULL) { 1967 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 1968 1969 if (rd->rdata_desc != NULL) { 1970 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 1971 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 1972 rd->rdata_dmap); 1973 } 1974 bus_dma_tag_destroy(sc->sc_rxring_dtag); 1975 } 1976 1977 bwi_dma_txstats_free(sc); 1978 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 1979 1980 if (sc->sc_parent_dtag != NULL) 1981 bus_dma_tag_destroy(sc->sc_parent_dtag); 1982} 1983 1984static int 1985bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 1986 struct bwi_ring_data *rd, bus_size_t size, 1987 uint32_t txrx_ctrl) 1988{ 1989 int error; 1990 1991 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 1992 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1993 &rd->rdata_dmap); 1994 if (error) { 1995 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 1996 return error; 1997 } 1998 1999 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2000 bwi_dma_ring_addr, &rd->rdata_paddr, 2001 BUS_DMA_NOWAIT); 2002 if (error) { 2003 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2004 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2005 rd->rdata_desc = NULL; 2006 return error; 2007 } 2008 2009 rd->rdata_txrx_ctrl = txrx_ctrl; 2010 return 0; 2011} 2012 2013static int 2014bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2015 bus_size_t desc_sz) 2016{ 2017 struct bwi_txstats_data *st; 2018 bus_size_t dma_size; 2019 int error; 2020 2021 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2022 if (st == NULL) { 2023 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2024 return ENOMEM; 2025 } 2026 sc->sc_txstats = st; 2027 2028 /* 2029 * Create TX stats descriptor DMA stuffs 2030 */ 2031 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2032 2033 error = bus_dma_tag_create(sc->sc_parent_dtag, 2034 BWI_RING_ALIGN, 2035 0, 2036 BUS_SPACE_MAXADDR, 2037 BUS_SPACE_MAXADDR, 2038 NULL, NULL, 2039 dma_size, 2040 1, 2041 dma_size, 2042 0, 2043 NULL, NULL, 2044 &st->stats_ring_dtag); 2045 if (error) { 2046 device_printf(sc->sc_dev, "can't create txstats ring " 2047 "DMA tag\n"); 2048 return error; 2049 } 2050 2051 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2052 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2053 &st->stats_ring_dmap); 2054 if (error) { 2055 device_printf(sc->sc_dev, "can't allocate txstats ring " 2056 "DMA mem\n"); 2057 bus_dma_tag_destroy(st->stats_ring_dtag); 2058 st->stats_ring_dtag = NULL; 2059 return error; 2060 } 2061 2062 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2063 st->stats_ring, dma_size, 2064 bwi_dma_ring_addr, &st->stats_ring_paddr, 2065 BUS_DMA_NOWAIT); 2066 if (error) { 2067 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2068 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2069 st->stats_ring_dmap); 2070 bus_dma_tag_destroy(st->stats_ring_dtag); 2071 st->stats_ring_dtag = NULL; 2072 return error; 2073 } 2074 2075 /* 2076 * Create TX stats DMA stuffs 2077 */ 2078 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2079 BWI_ALIGN); 2080 2081 error = bus_dma_tag_create(sc->sc_parent_dtag, 2082 BWI_ALIGN, 2083 0, 2084 BUS_SPACE_MAXADDR, 2085 BUS_SPACE_MAXADDR, 2086 NULL, NULL, 2087 dma_size, 2088 1, 2089 dma_size, 2090 0, 2091 NULL, NULL, 2092 &st->stats_dtag); 2093 if (error) { 2094 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2095 return error; 2096 } 2097 2098 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2099 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2100 &st->stats_dmap); 2101 if (error) { 2102 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2103 bus_dma_tag_destroy(st->stats_dtag); 2104 st->stats_dtag = NULL; 2105 return error; 2106 } 2107 2108 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2109 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2110 BUS_DMA_NOWAIT); 2111 if (error) { 2112 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2113 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2114 bus_dma_tag_destroy(st->stats_dtag); 2115 st->stats_dtag = NULL; 2116 return error; 2117 } 2118 2119 st->stats_ctrl_base = ctrl_base; 2120 return 0; 2121} 2122 2123static void 2124bwi_dma_txstats_free(struct bwi_softc *sc) 2125{ 2126 struct bwi_txstats_data *st; 2127 2128 if (sc->sc_txstats == NULL) 2129 return; 2130 st = sc->sc_txstats; 2131 2132 if (st->stats_ring_dtag != NULL) { 2133 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2134 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2135 st->stats_ring_dmap); 2136 bus_dma_tag_destroy(st->stats_ring_dtag); 2137 } 2138 2139 if (st->stats_dtag != NULL) { 2140 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2141 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2142 bus_dma_tag_destroy(st->stats_dtag); 2143 } 2144 2145 free(st, M_DEVBUF); 2146} 2147 2148static void 2149bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2150{ 2151 KASSERT(nseg == 1, ("too many segments\n")); 2152 *((bus_addr_t *)arg) = seg->ds_addr; 2153} 2154 2155static int 2156bwi_dma_mbuf_create(struct bwi_softc *sc) 2157{ 2158 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2159 int i, j, k, ntx, error; 2160 2161 /* 2162 * Create TX/RX mbuf DMA tag 2163 */ 2164 error = bus_dma_tag_create(sc->sc_parent_dtag, 2165 1, 2166 0, 2167 BUS_SPACE_MAXADDR, 2168 BUS_SPACE_MAXADDR, 2169 NULL, NULL, 2170 MCLBYTES, 2171 1, 2172 MCLBYTES, 2173 BUS_DMA_ALLOCNOW, 2174 NULL, NULL, 2175 &sc->sc_buf_dtag); 2176 if (error) { 2177 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2178 return error; 2179 } 2180 2181 ntx = 0; 2182 2183 /* 2184 * Create TX mbuf DMA map 2185 */ 2186 for (i = 0; i < BWI_TX_NRING; ++i) { 2187 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2188 2189 for (j = 0; j < BWI_TX_NDESC; ++j) { 2190 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2191 &tbd->tbd_buf[j].tb_dmap); 2192 if (error) { 2193 device_printf(sc->sc_dev, "can't create " 2194 "%dth tbd, %dth DMA map\n", i, j); 2195 2196 ntx = i; 2197 for (k = 0; k < j; ++k) { 2198 bus_dmamap_destroy(sc->sc_buf_dtag, 2199 tbd->tbd_buf[k].tb_dmap); 2200 } 2201 goto fail; 2202 } 2203 } 2204 } 2205 ntx = BWI_TX_NRING; 2206 2207 /* 2208 * Create RX mbuf DMA map and a spare DMA map 2209 */ 2210 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2211 &rbd->rbd_tmp_dmap); 2212 if (error) { 2213 device_printf(sc->sc_dev, 2214 "can't create spare RX buf DMA map\n"); 2215 goto fail; 2216 } 2217 2218 for (j = 0; j < BWI_RX_NDESC; ++j) { 2219 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2220 &rbd->rbd_buf[j].rb_dmap); 2221 if (error) { 2222 device_printf(sc->sc_dev, "can't create %dth " 2223 "RX buf DMA map\n", j); 2224 2225 for (k = 0; k < j; ++k) { 2226 bus_dmamap_destroy(sc->sc_buf_dtag, 2227 rbd->rbd_buf[j].rb_dmap); 2228 } 2229 bus_dmamap_destroy(sc->sc_buf_dtag, 2230 rbd->rbd_tmp_dmap); 2231 goto fail; 2232 } 2233 } 2234 2235 return 0; 2236fail: 2237 bwi_dma_mbuf_destroy(sc, ntx, 0); 2238 return error; 2239} 2240 2241static void 2242bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2243{ 2244 int i, j; 2245 2246 if (sc->sc_buf_dtag == NULL) 2247 return; 2248 2249 for (i = 0; i < ntx; ++i) { 2250 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2251 2252 for (j = 0; j < BWI_TX_NDESC; ++j) { 2253 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2254 2255 if (tb->tb_mbuf != NULL) { 2256 bus_dmamap_unload(sc->sc_buf_dtag, 2257 tb->tb_dmap); 2258 m_freem(tb->tb_mbuf); 2259 } 2260 if (tb->tb_ni != NULL) 2261 ieee80211_free_node(tb->tb_ni); 2262 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2263 } 2264 } 2265 2266 if (nrx) { 2267 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2268 2269 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2270 for (j = 0; j < BWI_RX_NDESC; ++j) { 2271 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2272 2273 if (rb->rb_mbuf != NULL) { 2274 bus_dmamap_unload(sc->sc_buf_dtag, 2275 rb->rb_dmap); 2276 m_freem(rb->rb_mbuf); 2277 } 2278 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2279 } 2280 } 2281 2282 bus_dma_tag_destroy(sc->sc_buf_dtag); 2283 sc->sc_buf_dtag = NULL; 2284} 2285 2286static void 2287bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2288{ 2289 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2290} 2291 2292static void 2293bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2294{ 2295 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2296} 2297 2298static int 2299bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2300{ 2301 struct bwi_ring_data *rd; 2302 struct bwi_txbuf_data *tbd; 2303 uint32_t val, addr_hi, addr_lo; 2304 2305 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2306 rd = &sc->sc_tx_rdata[ring_idx]; 2307 tbd = &sc->sc_tx_bdata[ring_idx]; 2308 2309 tbd->tbd_idx = 0; 2310 tbd->tbd_used = 0; 2311 2312 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2313 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2314 BUS_DMASYNC_PREWRITE); 2315 2316 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2317 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2318 2319 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2320 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2321 BWI_TXRX32_RINGINFO_FUNC_MASK); 2322 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2323 2324 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2325 BWI_TXRX32_CTRL_ENABLE; 2326 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2327 2328 return 0; 2329} 2330 2331static void 2332bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2333 bus_addr_t paddr, int hdr_size, int ndesc) 2334{ 2335 uint32_t val, addr_hi, addr_lo; 2336 2337 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2338 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2339 2340 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2341 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2342 BWI_TXRX32_RINGINFO_FUNC_MASK); 2343 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2344 2345 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2346 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2347 BWI_TXRX32_CTRL_ENABLE; 2348 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2349 2350 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2351 (ndesc - 1) * sizeof(struct bwi_desc32)); 2352} 2353 2354static int 2355bwi_init_rx_ring32(struct bwi_softc *sc) 2356{ 2357 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2358 int i, error; 2359 2360 sc->sc_rx_bdata.rbd_idx = 0; 2361 2362 for (i = 0; i < BWI_RX_NDESC; ++i) { 2363 error = bwi_newbuf(sc, i, 1); 2364 if (error) { 2365 device_printf(sc->sc_dev, 2366 "can't allocate %dth RX buffer\n", i); 2367 return error; 2368 } 2369 } 2370 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2371 BUS_DMASYNC_PREWRITE); 2372 2373 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2374 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2375 return 0; 2376} 2377 2378static int 2379bwi_init_txstats32(struct bwi_softc *sc) 2380{ 2381 struct bwi_txstats_data *st = sc->sc_txstats; 2382 bus_addr_t stats_paddr; 2383 int i; 2384 2385 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2386 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2387 2388 st->stats_idx = 0; 2389 2390 stats_paddr = st->stats_paddr; 2391 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2392 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2393 stats_paddr, sizeof(struct bwi_txstats), 0); 2394 stats_paddr += sizeof(struct bwi_txstats); 2395 } 2396 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2397 BUS_DMASYNC_PREWRITE); 2398 2399 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2400 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2401 return 0; 2402} 2403 2404static void 2405bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2406 int buf_len) 2407{ 2408 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2409 2410 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2411 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2412 paddr, buf_len, 0); 2413} 2414 2415static void 2416bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2417 int buf_idx, bus_addr_t paddr, int buf_len) 2418{ 2419 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2420 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2421 paddr, buf_len, 1); 2422} 2423 2424static int 2425bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2426{ 2427 /* TODO:64 */ 2428 return EOPNOTSUPP; 2429} 2430 2431static int 2432bwi_init_rx_ring64(struct bwi_softc *sc) 2433{ 2434 /* TODO:64 */ 2435 return EOPNOTSUPP; 2436} 2437 2438static int 2439bwi_init_txstats64(struct bwi_softc *sc) 2440{ 2441 /* TODO:64 */ 2442 return EOPNOTSUPP; 2443} 2444 2445static void 2446bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2447 int buf_len) 2448{ 2449 /* TODO:64 */ 2450} 2451 2452static void 2453bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2454 int buf_idx, bus_addr_t paddr, int buf_len) 2455{ 2456 /* TODO:64 */ 2457} 2458 2459static void 2460bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2461 bus_size_t mapsz __unused, int error) 2462{ 2463 if (!error) { 2464 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2465 *((bus_addr_t *)arg) = seg->ds_addr; 2466 } 2467} 2468 2469static int 2470bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2471{ 2472 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2473 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2474 struct bwi_rxbuf_hdr *hdr; 2475 bus_dmamap_t map; 2476 bus_addr_t paddr; 2477 struct mbuf *m; 2478 int error; 2479 2480 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2481 2482 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2483 if (m == NULL) { 2484 error = ENOBUFS; 2485 2486 /* 2487 * If the NIC is up and running, we need to: 2488 * - Clear RX buffer's header. 2489 * - Restore RX descriptor settings. 2490 */ 2491 if (init) 2492 return error; 2493 else 2494 goto back; 2495 } 2496 m->m_len = m->m_pkthdr.len = MCLBYTES; 2497 2498 /* 2499 * Try to load RX buf into temporary DMA map 2500 */ 2501 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2502 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2503 if (error) { 2504 m_freem(m); 2505 2506 /* 2507 * See the comment above 2508 */ 2509 if (init) 2510 return error; 2511 else 2512 goto back; 2513 } 2514 2515 if (!init) 2516 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2517 rxbuf->rb_mbuf = m; 2518 rxbuf->rb_paddr = paddr; 2519 2520 /* 2521 * Swap RX buf's DMA map with the loaded temporary one 2522 */ 2523 map = rxbuf->rb_dmap; 2524 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2525 rbd->rbd_tmp_dmap = map; 2526 2527back: 2528 /* 2529 * Clear RX buf header 2530 */ 2531 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2532 bzero(hdr, sizeof(*hdr)); 2533 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2534 2535 /* 2536 * Setup RX buf descriptor 2537 */ 2538 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2539 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2540 return error; 2541} 2542 2543static void 2544bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2545 const uint8_t *addr) 2546{ 2547 int i; 2548 2549 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2550 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2551 2552 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2553 uint16_t addr_val; 2554 2555 addr_val = (uint16_t)addr[i * 2] | 2556 (((uint16_t)addr[(i * 2) + 1]) << 8); 2557 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2558 } 2559} 2560 2561static int 2562bwi_rxeof(struct bwi_softc *sc, int end_idx) 2563{ 2564 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2565 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2566 struct ieee80211com *ic = &sc->sc_ic; 2567 int idx, rx_data = 0; 2568 2569 idx = rbd->rbd_idx; 2570 while (idx != end_idx) { 2571 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2572 struct bwi_rxbuf_hdr *hdr; 2573 struct ieee80211_frame_min *wh; 2574 struct ieee80211_node *ni; 2575 struct mbuf *m; 2576 uint32_t plcp; 2577 uint16_t flags2; 2578 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2579 2580 m = rb->rb_mbuf; 2581 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2582 BUS_DMASYNC_POSTREAD); 2583 2584 if (bwi_newbuf(sc, idx, 0)) { 2585 counter_u64_add(ic->ic_ierrors, 1); 2586 goto next; 2587 } 2588 2589 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2590 flags2 = le16toh(hdr->rxh_flags2); 2591 2592 hdr_extra = 0; 2593 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2594 hdr_extra = 2; 2595 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2596 2597 buflen = le16toh(hdr->rxh_buflen); 2598 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2599 device_printf(sc->sc_dev, 2600 "%s: zero length data, hdr_extra %d\n", 2601 __func__, hdr_extra); 2602 counter_u64_add(ic->ic_ierrors, 1); 2603 m_freem(m); 2604 goto next; 2605 } 2606 2607 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2608 rssi = bwi_calc_rssi(sc, hdr); 2609 noise = bwi_calc_noise(sc); 2610 2611 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2612 m_adj(m, sizeof(*hdr) + wh_ofs); 2613 2614 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2615 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2616 else 2617 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2618 2619 /* RX radio tap */ 2620 if (ieee80211_radiotap_active(ic)) 2621 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2622 2623 m_adj(m, -IEEE80211_CRC_LEN); 2624 2625 BWI_UNLOCK(sc); 2626 2627 wh = mtod(m, struct ieee80211_frame_min *); 2628 ni = ieee80211_find_rxnode(ic, wh); 2629 if (ni != NULL) { 2630 type = ieee80211_input(ni, m, rssi - noise, noise); 2631 ieee80211_free_node(ni); 2632 } else 2633 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2634 if (type == IEEE80211_FC0_TYPE_DATA) { 2635 rx_data = 1; 2636 sc->sc_rx_rate = rate; 2637 } 2638 2639 BWI_LOCK(sc); 2640next: 2641 idx = (idx + 1) % BWI_RX_NDESC; 2642 2643 if (sc->sc_flags & BWI_F_STOP) { 2644 /* 2645 * Take the fast lane, don't do 2646 * any damage to softc 2647 */ 2648 return -1; 2649 } 2650 } 2651 2652 rbd->rbd_idx = idx; 2653 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2654 BUS_DMASYNC_PREWRITE); 2655 2656 return rx_data; 2657} 2658 2659static int 2660bwi_rxeof32(struct bwi_softc *sc) 2661{ 2662 uint32_t val, rx_ctrl; 2663 int end_idx, rx_data; 2664 2665 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2666 2667 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2668 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2669 sizeof(struct bwi_desc32); 2670 2671 rx_data = bwi_rxeof(sc, end_idx); 2672 if (rx_data >= 0) { 2673 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2674 end_idx * sizeof(struct bwi_desc32)); 2675 } 2676 return rx_data; 2677} 2678 2679static int 2680bwi_rxeof64(struct bwi_softc *sc) 2681{ 2682 /* TODO:64 */ 2683 return 0; 2684} 2685 2686static void 2687bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2688{ 2689 int i; 2690 2691 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2692 2693#define NRETRY 10 2694 2695 for (i = 0; i < NRETRY; ++i) { 2696 uint32_t status; 2697 2698 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2699 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2700 BWI_RX32_STATUS_STATE_DISABLED) 2701 break; 2702 2703 DELAY(1000); 2704 } 2705 if (i == NRETRY) 2706 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2707 2708#undef NRETRY 2709 2710 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2711} 2712 2713static void 2714bwi_free_txstats32(struct bwi_softc *sc) 2715{ 2716 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2717} 2718 2719static void 2720bwi_free_rx_ring32(struct bwi_softc *sc) 2721{ 2722 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2723 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2724 int i; 2725 2726 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2727 2728 for (i = 0; i < BWI_RX_NDESC; ++i) { 2729 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2730 2731 if (rb->rb_mbuf != NULL) { 2732 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2733 m_freem(rb->rb_mbuf); 2734 rb->rb_mbuf = NULL; 2735 } 2736 } 2737} 2738 2739static void 2740bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2741{ 2742 struct bwi_ring_data *rd; 2743 struct bwi_txbuf_data *tbd; 2744 uint32_t state, val; 2745 int i; 2746 2747 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2748 rd = &sc->sc_tx_rdata[ring_idx]; 2749 tbd = &sc->sc_tx_bdata[ring_idx]; 2750 2751#define NRETRY 10 2752 2753 for (i = 0; i < NRETRY; ++i) { 2754 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2755 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2756 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2757 state == BWI_TX32_STATUS_STATE_IDLE || 2758 state == BWI_TX32_STATUS_STATE_STOPPED) 2759 break; 2760 2761 DELAY(1000); 2762 } 2763 if (i == NRETRY) { 2764 device_printf(sc->sc_dev, 2765 "%s: wait for TX ring(%d) stable timed out\n", 2766 __func__, ring_idx); 2767 } 2768 2769 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2770 for (i = 0; i < NRETRY; ++i) { 2771 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2772 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2773 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2774 break; 2775 2776 DELAY(1000); 2777 } 2778 if (i == NRETRY) 2779 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2780 __func__, ring_idx); 2781 2782#undef NRETRY 2783 2784 DELAY(1000); 2785 2786 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2787 2788 for (i = 0; i < BWI_TX_NDESC; ++i) { 2789 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2790 2791 if (tb->tb_mbuf != NULL) { 2792 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2793 m_freem(tb->tb_mbuf); 2794 tb->tb_mbuf = NULL; 2795 } 2796 if (tb->tb_ni != NULL) { 2797 ieee80211_free_node(tb->tb_ni); 2798 tb->tb_ni = NULL; 2799 } 2800 } 2801} 2802 2803static void 2804bwi_free_txstats64(struct bwi_softc *sc) 2805{ 2806 /* TODO:64 */ 2807} 2808 2809static void 2810bwi_free_rx_ring64(struct bwi_softc *sc) 2811{ 2812 /* TODO:64 */ 2813} 2814 2815static void 2816bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2817{ 2818 /* TODO:64 */ 2819} 2820 2821/* XXX does not belong here */ 2822#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2823#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2824 2825static __inline void 2826bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2827{ 2828 uint32_t plcp; 2829 2830 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2831 IEEE80211_OFDM_PLCP_RATE_MASK) | 2832 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2833 *plcp0 = htole32(plcp); 2834} 2835 2836static __inline void 2837bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2838 uint8_t rate) 2839{ 2840 int len, service, pkt_bitlen; 2841 2842 pkt_bitlen = pkt_len * NBBY; 2843 len = howmany(pkt_bitlen * 2, rate); 2844 2845 service = IEEE80211_PLCP_SERVICE_LOCKED; 2846 if (rate == (11 * 2)) { 2847 int pkt_bitlen1; 2848 2849 /* 2850 * PLCP service field needs to be adjusted, 2851 * if TX rate is 11Mbytes/s 2852 */ 2853 pkt_bitlen1 = len * 11; 2854 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2855 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2856 } 2857 2858 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2859 plcp->i_service = service; 2860 plcp->i_length = htole16(len); 2861 /* NOTE: do NOT touch i_crc */ 2862} 2863 2864static __inline void 2865bwi_plcp_header(const struct ieee80211_rate_table *rt, 2866 void *plcp, int pkt_len, uint8_t rate) 2867{ 2868 enum ieee80211_phytype modtype; 2869 2870 /* 2871 * Assume caller has zeroed 'plcp' 2872 */ 2873 modtype = ieee80211_rate2phytype(rt, rate); 2874 if (modtype == IEEE80211_T_OFDM) 2875 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2876 else if (modtype == IEEE80211_T_DS) 2877 bwi_ds_plcp_header(plcp, pkt_len, rate); 2878 else 2879 panic("unsupport modulation type %u\n", modtype); 2880} 2881 2882static int 2883bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2884 struct ieee80211_node *ni) 2885{ 2886 struct ieee80211vap *vap = ni->ni_vap; 2887 struct ieee80211com *ic = &sc->sc_ic; 2888 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2889 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2890 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2891 struct bwi_mac *mac; 2892 struct bwi_txbuf_hdr *hdr; 2893 struct ieee80211_frame *wh; 2894 const struct ieee80211_txparam *tp; 2895 uint8_t rate, rate_fb; 2896 uint32_t mac_ctrl; 2897 uint16_t phy_ctrl; 2898 bus_addr_t paddr; 2899 int type, ismcast, pkt_len, error, rix; 2900#if 0 2901 const uint8_t *p; 2902 int i; 2903#endif 2904 2905 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2906 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2907 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2908 2909 wh = mtod(m, struct ieee80211_frame *); 2910 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2911 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2912 2913 /* Get 802.11 frame len before prepending TX header */ 2914 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2915 2916 /* 2917 * Find TX rate 2918 */ 2919 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2920 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2921 rate = rate_fb = tp->mgmtrate; 2922 } else if (ismcast) { 2923 rate = rate_fb = tp->mcastrate; 2924 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2925 rate = rate_fb = tp->ucastrate; 2926 } else { 2927 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2928 rate = ni->ni_txrate; 2929 2930 if (rix > 0) { 2931 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2932 IEEE80211_RATE_VAL; 2933 } else { 2934 rate_fb = rate; 2935 } 2936 } 2937 tb->tb_rate[0] = rate; 2938 tb->tb_rate[1] = rate_fb; 2939 sc->sc_tx_rate = rate; 2940 2941 /* 2942 * TX radio tap 2943 */ 2944 if (ieee80211_radiotap_active_vap(vap)) { 2945 sc->sc_tx_th.wt_flags = 0; 2946 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2947 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2948 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2949 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2950 rate != (1 * 2)) { 2951 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2952 } 2953 sc->sc_tx_th.wt_rate = rate; 2954 2955 ieee80211_radiotap_tx(vap, m); 2956 } 2957 2958 /* 2959 * Setup the embedded TX header 2960 */ 2961 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2962 if (m == NULL) { 2963 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2964 __func__); 2965 return ENOBUFS; 2966 } 2967 hdr = mtod(m, struct bwi_txbuf_hdr *); 2968 2969 bzero(hdr, sizeof(*hdr)); 2970 2971 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 2972 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 2973 2974 if (!ismcast) { 2975 uint16_t dur; 2976 2977 dur = ieee80211_ack_duration(sc->sc_rates, rate, 2978 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 2979 2980 hdr->txh_fb_duration = htole16(dur); 2981 } 2982 2983 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 2984 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 2985 2986 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 2987 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 2988 2989 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 2990 BWI_TXH_PHY_C_ANTMODE_MASK); 2991 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 2992 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 2993 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 2994 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 2995 2996 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 2997 if (!ismcast) 2998 mac_ctrl |= BWI_TXH_MAC_C_ACK; 2999 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3000 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3001 3002 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3003 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3004 3005 /* Catch any further usage */ 3006 hdr = NULL; 3007 wh = NULL; 3008 3009 /* DMA load */ 3010 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3011 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3012 if (error && error != EFBIG) { 3013 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3014 __func__, error); 3015 goto back; 3016 } 3017 3018 if (error) { /* error == EFBIG */ 3019 struct mbuf *m_new; 3020 3021 m_new = m_defrag(m, M_NOWAIT); 3022 if (m_new == NULL) { 3023 device_printf(sc->sc_dev, 3024 "%s: can't defrag TX buffer\n", __func__); 3025 error = ENOBUFS; 3026 goto back; 3027 } else { 3028 m = m_new; 3029 } 3030 3031 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3032 bwi_dma_buf_addr, &paddr, 3033 BUS_DMA_NOWAIT); 3034 if (error) { 3035 device_printf(sc->sc_dev, 3036 "%s: can't load TX buffer (2) %d\n", 3037 __func__, error); 3038 goto back; 3039 } 3040 } 3041 error = 0; 3042 3043 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3044 3045 tb->tb_mbuf = m; 3046 tb->tb_ni = ni; 3047 3048#if 0 3049 p = mtod(m, const uint8_t *); 3050 for (i = 0; i < m->m_pkthdr.len; ++i) { 3051 if (i != 0 && i % 8 == 0) 3052 printf("\n"); 3053 printf("%02x ", p[i]); 3054 } 3055 printf("\n"); 3056#endif 3057 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3058 idx, pkt_len, m->m_pkthdr.len); 3059 3060 /* Setup TX descriptor */ 3061 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3062 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3063 BUS_DMASYNC_PREWRITE); 3064 3065 /* Kick start */ 3066 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3067 3068back: 3069 if (error) 3070 m_freem(m); 3071 return error; 3072} 3073 3074static int 3075bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3076 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3077{ 3078 struct ieee80211vap *vap = ni->ni_vap; 3079 struct ieee80211com *ic = ni->ni_ic; 3080 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3081 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3082 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3083 struct bwi_mac *mac; 3084 struct bwi_txbuf_hdr *hdr; 3085 struct ieee80211_frame *wh; 3086 uint8_t rate, rate_fb; 3087 uint32_t mac_ctrl; 3088 uint16_t phy_ctrl; 3089 bus_addr_t paddr; 3090 int ismcast, pkt_len, error; 3091 3092 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3093 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3094 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3095 3096 wh = mtod(m, struct ieee80211_frame *); 3097 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3098 3099 /* Get 802.11 frame len before prepending TX header */ 3100 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3101 3102 /* 3103 * Find TX rate 3104 */ 3105 rate = params->ibp_rate0; 3106 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3107 /* XXX fall back to mcast/mgmt rate? */ 3108 m_freem(m); 3109 return EINVAL; 3110 } 3111 if (params->ibp_try1 != 0) { 3112 rate_fb = params->ibp_rate1; 3113 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3114 /* XXX fall back to rate0? */ 3115 m_freem(m); 3116 return EINVAL; 3117 } 3118 } else 3119 rate_fb = rate; 3120 tb->tb_rate[0] = rate; 3121 tb->tb_rate[1] = rate_fb; 3122 sc->sc_tx_rate = rate; 3123 3124 /* 3125 * TX radio tap 3126 */ 3127 if (ieee80211_radiotap_active_vap(vap)) { 3128 sc->sc_tx_th.wt_flags = 0; 3129 /* XXX IEEE80211_BPF_CRYPTO */ 3130 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3131 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3132 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3133 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3134 sc->sc_tx_th.wt_rate = rate; 3135 3136 ieee80211_radiotap_tx(vap, m); 3137 } 3138 3139 /* 3140 * Setup the embedded TX header 3141 */ 3142 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3143 if (m == NULL) { 3144 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3145 __func__); 3146 return ENOBUFS; 3147 } 3148 hdr = mtod(m, struct bwi_txbuf_hdr *); 3149 3150 bzero(hdr, sizeof(*hdr)); 3151 3152 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3153 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3154 3155 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3156 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3157 uint16_t dur; 3158 3159 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3160 3161 hdr->txh_fb_duration = htole16(dur); 3162 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3163 } 3164 3165 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3166 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3167 3168 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3169 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3170 3171 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3172 BWI_TXH_PHY_C_ANTMODE_MASK); 3173 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3174 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3175 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3176 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3177 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3178 3179 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3180 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3181 3182 /* Catch any further usage */ 3183 hdr = NULL; 3184 wh = NULL; 3185 3186 /* DMA load */ 3187 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3188 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3189 if (error != 0) { 3190 struct mbuf *m_new; 3191 3192 if (error != EFBIG) { 3193 device_printf(sc->sc_dev, 3194 "%s: can't load TX buffer (1) %d\n", 3195 __func__, error); 3196 goto back; 3197 } 3198 m_new = m_defrag(m, M_NOWAIT); 3199 if (m_new == NULL) { 3200 device_printf(sc->sc_dev, 3201 "%s: can't defrag TX buffer\n", __func__); 3202 error = ENOBUFS; 3203 goto back; 3204 } 3205 m = m_new; 3206 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3207 bwi_dma_buf_addr, &paddr, 3208 BUS_DMA_NOWAIT); 3209 if (error) { 3210 device_printf(sc->sc_dev, 3211 "%s: can't load TX buffer (2) %d\n", 3212 __func__, error); 3213 goto back; 3214 } 3215 } 3216 3217 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3218 3219 tb->tb_mbuf = m; 3220 tb->tb_ni = ni; 3221 3222 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3223 idx, pkt_len, m->m_pkthdr.len); 3224 3225 /* Setup TX descriptor */ 3226 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3227 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3228 BUS_DMASYNC_PREWRITE); 3229 3230 /* Kick start */ 3231 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3232back: 3233 if (error) 3234 m_freem(m); 3235 return error; 3236} 3237 3238static void 3239bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3240{ 3241 idx = (idx + 1) % BWI_TX_NDESC; 3242 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3243 idx * sizeof(struct bwi_desc32)); 3244} 3245 3246static void 3247bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3248{ 3249 /* TODO:64 */ 3250} 3251 3252static void 3253bwi_txeof_status32(struct bwi_softc *sc) 3254{ 3255 uint32_t val, ctrl_base; 3256 int end_idx; 3257 3258 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3259 3260 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3261 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3262 sizeof(struct bwi_desc32); 3263 3264 bwi_txeof_status(sc, end_idx); 3265 3266 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3267 end_idx * sizeof(struct bwi_desc32)); 3268 3269 bwi_start_locked(sc); 3270} 3271 3272static void 3273bwi_txeof_status64(struct bwi_softc *sc) 3274{ 3275 /* TODO:64 */ 3276} 3277 3278static void 3279_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3280{ 3281 struct bwi_txbuf_data *tbd; 3282 struct bwi_txbuf *tb; 3283 int ring_idx, buf_idx; 3284 struct ieee80211_node *ni; 3285 struct ieee80211vap *vap; 3286 3287 if (tx_id == 0) { 3288 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3289 return; 3290 } 3291 3292 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3293 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3294 3295 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3296 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3297 3298 tbd = &sc->sc_tx_bdata[ring_idx]; 3299 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3300 tbd->tbd_used--; 3301 3302 tb = &tbd->tbd_buf[buf_idx]; 3303 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3304 "acked %d, data_txcnt %d, ni %p\n", 3305 buf_idx, acked, data_txcnt, tb->tb_ni); 3306 3307 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3308 3309 if ((ni = tb->tb_ni) != NULL) { 3310 const struct bwi_txbuf_hdr *hdr = 3311 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3312 vap = ni->ni_vap; 3313 3314 /* NB: update rate control only for unicast frames */ 3315 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3316 /* 3317 * Feed back 'acked and data_txcnt'. Note that the 3318 * generic AMRR code only understands one tx rate 3319 * and the estimator doesn't handle real retry counts 3320 * well so to avoid over-aggressive downshifting we 3321 * treat any number of retries as "1". 3322 */ 3323 ieee80211_ratectl_tx_complete(vap, ni, 3324 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3325 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3326 } 3327 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3328 tb->tb_ni = NULL; 3329 } else 3330 m_freem(tb->tb_mbuf); 3331 tb->tb_mbuf = NULL; 3332 3333 if (tbd->tbd_used == 0) 3334 sc->sc_tx_timer = 0; 3335} 3336 3337static void 3338bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3339{ 3340 struct bwi_txstats_data *st = sc->sc_txstats; 3341 int idx; 3342 3343 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3344 3345 idx = st->stats_idx; 3346 while (idx != end_idx) { 3347 const struct bwi_txstats *stats = &st->stats[idx]; 3348 3349 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3350 int data_txcnt; 3351 3352 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3353 BWI_TXS_TXCNT_DATA); 3354 _bwi_txeof(sc, le16toh(stats->txs_id), 3355 stats->txs_flags & BWI_TXS_F_ACKED, 3356 data_txcnt); 3357 } 3358 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3359 } 3360 st->stats_idx = idx; 3361} 3362 3363static void 3364bwi_txeof(struct bwi_softc *sc) 3365{ 3366 3367 for (;;) { 3368 uint32_t tx_status0, tx_status1; 3369 uint16_t tx_id; 3370 int data_txcnt; 3371 3372 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3373 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3374 break; 3375 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3376 3377 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3378 data_txcnt = __SHIFTOUT(tx_status0, 3379 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3380 3381 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3382 continue; 3383 3384 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3385 data_txcnt); 3386 } 3387 3388 bwi_start_locked(sc); 3389} 3390 3391static int 3392bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3393{ 3394 bwi_power_on(sc, 1); 3395 return bwi_set_clock_mode(sc, clk_mode); 3396} 3397 3398static void 3399bwi_bbp_power_off(struct bwi_softc *sc) 3400{ 3401 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3402 bwi_power_off(sc, 1); 3403} 3404 3405static int 3406bwi_get_pwron_delay(struct bwi_softc *sc) 3407{ 3408 struct bwi_regwin *com, *old; 3409 struct bwi_clock_freq freq; 3410 uint32_t val; 3411 int error; 3412 3413 com = &sc->sc_com_regwin; 3414 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3415 3416 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3417 return 0; 3418 3419 error = bwi_regwin_switch(sc, com, &old); 3420 if (error) 3421 return error; 3422 3423 bwi_get_clock_freq(sc, &freq); 3424 3425 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3426 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3427 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3428 3429 return bwi_regwin_switch(sc, old, NULL); 3430} 3431 3432static int 3433bwi_bus_attach(struct bwi_softc *sc) 3434{ 3435 struct bwi_regwin *bus, *old; 3436 int error; 3437 3438 bus = &sc->sc_bus_regwin; 3439 3440 error = bwi_regwin_switch(sc, bus, &old); 3441 if (error) 3442 return error; 3443 3444 if (!bwi_regwin_is_enabled(sc, bus)) 3445 bwi_regwin_enable(sc, bus, 0); 3446 3447 /* Disable interripts */ 3448 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3449 3450 return bwi_regwin_switch(sc, old, NULL); 3451} 3452 3453static const char * 3454bwi_regwin_name(const struct bwi_regwin *rw) 3455{ 3456 switch (rw->rw_type) { 3457 case BWI_REGWIN_T_COM: 3458 return "COM"; 3459 case BWI_REGWIN_T_BUSPCI: 3460 return "PCI"; 3461 case BWI_REGWIN_T_MAC: 3462 return "MAC"; 3463 case BWI_REGWIN_T_BUSPCIE: 3464 return "PCIE"; 3465 } 3466 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3467 return NULL; 3468} 3469 3470static uint32_t 3471bwi_regwin_disable_bits(struct bwi_softc *sc) 3472{ 3473 uint32_t busrev; 3474 3475 /* XXX cache this */ 3476 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3477 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3478 "bus rev %u\n", busrev); 3479 3480 if (busrev == BWI_BUSREV_0) 3481 return BWI_STATE_LO_DISABLE1; 3482 else if (busrev == BWI_BUSREV_1) 3483 return BWI_STATE_LO_DISABLE2; 3484 else 3485 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3486} 3487 3488int 3489bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3490{ 3491 uint32_t val, disable_bits; 3492 3493 disable_bits = bwi_regwin_disable_bits(sc); 3494 val = CSR_READ_4(sc, BWI_STATE_LO); 3495 3496 if ((val & (BWI_STATE_LO_CLOCK | 3497 BWI_STATE_LO_RESET | 3498 disable_bits)) == BWI_STATE_LO_CLOCK) { 3499 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3500 bwi_regwin_name(rw)); 3501 return 1; 3502 } else { 3503 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3504 bwi_regwin_name(rw)); 3505 return 0; 3506 } 3507} 3508 3509void 3510bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3511{ 3512 uint32_t state_lo, disable_bits; 3513 int i; 3514 3515 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3516 3517 /* 3518 * If current regwin is in 'reset' state, it was already disabled. 3519 */ 3520 if (state_lo & BWI_STATE_LO_RESET) { 3521 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3522 "%s was already disabled\n", bwi_regwin_name(rw)); 3523 return; 3524 } 3525 3526 disable_bits = bwi_regwin_disable_bits(sc); 3527 3528 /* 3529 * Disable normal clock 3530 */ 3531 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3532 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3533 3534 /* 3535 * Wait until normal clock is disabled 3536 */ 3537#define NRETRY 1000 3538 for (i = 0; i < NRETRY; ++i) { 3539 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3540 if (state_lo & disable_bits) 3541 break; 3542 DELAY(10); 3543 } 3544 if (i == NRETRY) { 3545 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3546 bwi_regwin_name(rw)); 3547 } 3548 3549 for (i = 0; i < NRETRY; ++i) { 3550 uint32_t state_hi; 3551 3552 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3553 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3554 break; 3555 DELAY(10); 3556 } 3557 if (i == NRETRY) { 3558 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3559 bwi_regwin_name(rw)); 3560 } 3561#undef NRETRY 3562 3563 /* 3564 * Reset and disable regwin with gated clock 3565 */ 3566 state_lo = BWI_STATE_LO_RESET | disable_bits | 3567 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3568 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3569 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3570 3571 /* Flush pending bus write */ 3572 CSR_READ_4(sc, BWI_STATE_LO); 3573 DELAY(1); 3574 3575 /* Reset and disable regwin */ 3576 state_lo = BWI_STATE_LO_RESET | disable_bits | 3577 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3578 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3579 3580 /* Flush pending bus write */ 3581 CSR_READ_4(sc, BWI_STATE_LO); 3582 DELAY(1); 3583} 3584 3585void 3586bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3587{ 3588 uint32_t state_lo, state_hi, imstate; 3589 3590 bwi_regwin_disable(sc, rw, flags); 3591 3592 /* Reset regwin with gated clock */ 3593 state_lo = BWI_STATE_LO_RESET | 3594 BWI_STATE_LO_CLOCK | 3595 BWI_STATE_LO_GATED_CLOCK | 3596 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3597 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3598 3599 /* Flush pending bus write */ 3600 CSR_READ_4(sc, BWI_STATE_LO); 3601 DELAY(1); 3602 3603 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3604 if (state_hi & BWI_STATE_HI_SERROR) 3605 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3606 3607 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3608 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3609 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3610 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3611 } 3612 3613 /* Enable regwin with gated clock */ 3614 state_lo = BWI_STATE_LO_CLOCK | 3615 BWI_STATE_LO_GATED_CLOCK | 3616 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3617 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3618 3619 /* Flush pending bus write */ 3620 CSR_READ_4(sc, BWI_STATE_LO); 3621 DELAY(1); 3622 3623 /* Enable regwin with normal clock */ 3624 state_lo = BWI_STATE_LO_CLOCK | 3625 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3626 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3627 3628 /* Flush pending bus write */ 3629 CSR_READ_4(sc, BWI_STATE_LO); 3630 DELAY(1); 3631} 3632 3633static void 3634bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3635{ 3636 struct bwi_mac *mac; 3637 struct bwi_myaddr_bssid buf; 3638 const uint8_t *p; 3639 uint32_t val; 3640 int n, i; 3641 3642 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3643 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3644 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3645 3646 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3647 3648 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3649 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3650 3651 n = sizeof(buf) / sizeof(val); 3652 p = (const uint8_t *)&buf; 3653 for (i = 0; i < n; ++i) { 3654 int j; 3655 3656 val = 0; 3657 for (j = 0; j < sizeof(val); ++j) 3658 val |= ((uint32_t)(*p++)) << (j * 8); 3659 3660 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3661 } 3662} 3663 3664static void 3665bwi_updateslot(struct ieee80211com *ic) 3666{ 3667 struct bwi_softc *sc = ic->ic_softc; 3668 struct bwi_mac *mac; 3669 3670 BWI_LOCK(sc); 3671 if (sc->sc_flags & BWI_F_RUNNING) { 3672 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3673 3674 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3675 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3676 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3677 3678 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3679 } 3680 BWI_UNLOCK(sc); 3681} 3682 3683static void 3684bwi_calibrate(void *xsc) 3685{ 3686 struct bwi_softc *sc = xsc; 3687 struct bwi_mac *mac; 3688 3689 BWI_ASSERT_LOCKED(sc); 3690 3691 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3692 ("opmode %d", sc->sc_ic.ic_opmode)); 3693 3694 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3695 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3696 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3697 3698 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3699 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3700 3701 /* XXX 15 seconds */ 3702 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3703} 3704 3705static int 3706bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3707{ 3708 struct bwi_mac *mac; 3709 3710 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3711 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3712 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3713 3714 return bwi_rf_calc_rssi(mac, hdr); 3715} 3716 3717static int 3718bwi_calc_noise(struct bwi_softc *sc) 3719{ 3720 struct bwi_mac *mac; 3721 3722 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3723 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3724 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3725 3726 return bwi_rf_calc_noise(mac); 3727} 3728 3729static __inline uint8_t 3730bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3731{ 3732 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3733 return (ieee80211_plcp2rate(plcp, type)); 3734} 3735 3736static void 3737bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3738 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3739{ 3740 const struct ieee80211_frame_min *wh; 3741 3742 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3743 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3744 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3745 3746 wh = mtod(m, const struct ieee80211_frame_min *); 3747 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3748 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3749 3750 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3751 sc->sc_rx_th.wr_rate = rate; 3752 sc->sc_rx_th.wr_antsignal = rssi; 3753 sc->sc_rx_th.wr_antnoise = noise; 3754} 3755 3756static void 3757bwi_led_attach(struct bwi_softc *sc) 3758{ 3759 const uint8_t *led_act = NULL; 3760 uint16_t gpio, val[BWI_LED_MAX]; 3761 int i; 3762 3763 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3764 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3765 led_act = bwi_vendor_led_act[i].led_act; 3766 break; 3767 } 3768 } 3769 if (led_act == NULL) 3770 led_act = bwi_default_led_act; 3771 3772 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3773 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3774 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3775 3776 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3777 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3778 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3779 3780 for (i = 0; i < BWI_LED_MAX; ++i) { 3781 struct bwi_led *led = &sc->sc_leds[i]; 3782 3783 if (val[i] == 0xff) { 3784 led->l_act = led_act[i]; 3785 } else { 3786 if (val[i] & BWI_LED_ACT_LOW) 3787 led->l_flags |= BWI_LED_F_ACTLOW; 3788 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3789 } 3790 led->l_mask = (1 << i); 3791 3792 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3793 led->l_act == BWI_LED_ACT_BLINK_POLL || 3794 led->l_act == BWI_LED_ACT_BLINK) { 3795 led->l_flags |= BWI_LED_F_BLINK; 3796 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3797 led->l_flags |= BWI_LED_F_POLLABLE; 3798 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3799 led->l_flags |= BWI_LED_F_SLOW; 3800 3801 if (sc->sc_blink_led == NULL) { 3802 sc->sc_blink_led = led; 3803 if (led->l_flags & BWI_LED_F_SLOW) 3804 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3805 } 3806 } 3807 3808 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3809 "%dth led, act %d, lowact %d\n", i, 3810 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3811 } 3812 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3813} 3814 3815static __inline uint16_t 3816bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3817{ 3818 if (led->l_flags & BWI_LED_F_ACTLOW) 3819 on = !on; 3820 if (on) 3821 val |= led->l_mask; 3822 else 3823 val &= ~led->l_mask; 3824 return val; 3825} 3826 3827static void 3828bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3829{ 3830 struct ieee80211com *ic = &sc->sc_ic; 3831 uint16_t val; 3832 int i; 3833 3834 if (nstate == IEEE80211_S_INIT) { 3835 callout_stop(&sc->sc_led_blink_ch); 3836 sc->sc_led_blinking = 0; 3837 } 3838 3839 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3840 return; 3841 3842 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3843 for (i = 0; i < BWI_LED_MAX; ++i) { 3844 struct bwi_led *led = &sc->sc_leds[i]; 3845 int on; 3846 3847 if (led->l_act == BWI_LED_ACT_UNKN || 3848 led->l_act == BWI_LED_ACT_NULL) 3849 continue; 3850 3851 if ((led->l_flags & BWI_LED_F_BLINK) && 3852 nstate != IEEE80211_S_INIT) 3853 continue; 3854 3855 switch (led->l_act) { 3856 case BWI_LED_ACT_ON: /* Always on */ 3857 on = 1; 3858 break; 3859 case BWI_LED_ACT_OFF: /* Always off */ 3860 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3861 on = 0; 3862 break; 3863 default: 3864 on = 1; 3865 switch (nstate) { 3866 case IEEE80211_S_INIT: 3867 on = 0; 3868 break; 3869 case IEEE80211_S_RUN: 3870 if (led->l_act == BWI_LED_ACT_11G && 3871 ic->ic_curmode != IEEE80211_MODE_11G) 3872 on = 0; 3873 break; 3874 default: 3875 if (led->l_act == BWI_LED_ACT_ASSOC) 3876 on = 0; 3877 break; 3878 } 3879 break; 3880 } 3881 3882 val = bwi_led_onoff(led, val, on); 3883 } 3884 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3885} 3886static void 3887bwi_led_event(struct bwi_softc *sc, int event) 3888{ 3889 struct bwi_led *led = sc->sc_blink_led; 3890 int rate; 3891 3892 if (event == BWI_LED_EVENT_POLL) { 3893 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3894 return; 3895 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3896 return; 3897 } 3898 3899 sc->sc_led_ticks = ticks; 3900 if (sc->sc_led_blinking) 3901 return; 3902 3903 switch (event) { 3904 case BWI_LED_EVENT_RX: 3905 rate = sc->sc_rx_rate; 3906 break; 3907 case BWI_LED_EVENT_TX: 3908 rate = sc->sc_tx_rate; 3909 break; 3910 case BWI_LED_EVENT_POLL: 3911 rate = 0; 3912 break; 3913 default: 3914 panic("unknown LED event %d\n", event); 3915 break; 3916 } 3917 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3918 bwi_led_duration[rate].off_dur); 3919} 3920 3921static void 3922bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3923{ 3924 struct bwi_led *led = sc->sc_blink_led; 3925 uint16_t val; 3926 3927 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3928 val = bwi_led_onoff(led, val, 1); 3929 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3930 3931 if (led->l_flags & BWI_LED_F_SLOW) { 3932 BWI_LED_SLOWDOWN(on_dur); 3933 BWI_LED_SLOWDOWN(off_dur); 3934 } 3935 3936 sc->sc_led_blinking = 1; 3937 sc->sc_led_blink_offdur = off_dur; 3938 3939 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3940} 3941 3942static void 3943bwi_led_blink_next(void *xsc) 3944{ 3945 struct bwi_softc *sc = xsc; 3946 uint16_t val; 3947 3948 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3949 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3950 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3951 3952 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3953 bwi_led_blink_end, sc); 3954} 3955 3956static void 3957bwi_led_blink_end(void *xsc) 3958{ 3959 struct bwi_softc *sc = xsc; 3960 sc->sc_led_blinking = 0; 3961} 3962 3963static void 3964bwi_restart(void *xsc, int pending) 3965{ 3966 struct bwi_softc *sc = xsc; 3967 3968 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 3969 BWI_LOCK(sc); 3970 bwi_init_statechg(sc, 0); 3971#if 0 3972 bwi_start_locked(sc); 3973#endif 3974 BWI_UNLOCK(sc); 3975} 3976