if_bwi.c revision 287197
1/* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/bwi/if_bwi.c 287197 2015-08-27 08:56:39Z glebius $"); 39 40#include "opt_inet.h" 41#include "opt_bwi.h" 42#include "opt_wlan.h" 43 44#include <sys/param.h> 45#include <sys/endian.h> 46#include <sys/kernel.h> 47#include <sys/bus.h> 48#include <sys/malloc.h> 49#include <sys/proc.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54#include <sys/systm.h> 55#include <sys/taskqueue.h> 56 57#include <net/if.h> 58#include <net/if_var.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_arp.h> 63#include <net/ethernet.h> 64#include <net/if_llc.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_radiotap.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_phy.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <net/bpf.h> 73 74#ifdef INET 75#include <netinet/in.h> 76#include <netinet/if_ether.h> 77#endif 78 79#include <machine/bus.h> 80 81#include <dev/pci/pcivar.h> 82#include <dev/pci/pcireg.h> 83 84#include <dev/bwi/bitops.h> 85#include <dev/bwi/if_bwireg.h> 86#include <dev/bwi/if_bwivar.h> 87#include <dev/bwi/bwimac.h> 88#include <dev/bwi/bwirf.h> 89 90struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93}; 94 95struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98} __packed; 99 100static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104static void bwi_vap_delete(struct ieee80211vap *); 105static void bwi_init(struct bwi_softc *); 106static void bwi_parent(struct ieee80211com *); 107static int bwi_transmit(struct ieee80211com *, struct mbuf *); 108static void bwi_start_locked(struct bwi_softc *); 109static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111static void bwi_watchdog(void *); 112static void bwi_scan_start(struct ieee80211com *); 113static void bwi_set_channel(struct ieee80211com *); 114static void bwi_scan_end(struct ieee80211com *); 115static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 116static void bwi_updateslot(struct ieee80211com *); 117static int bwi_media_change(struct ifnet *); 118 119static void bwi_calibrate(void *); 120 121static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 122static int bwi_calc_noise(struct bwi_softc *); 123static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 124static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 125 struct bwi_rxbuf_hdr *, const void *, int, int, int); 126 127static void bwi_restart(void *, int); 128static void bwi_init_statechg(struct bwi_softc *, int); 129static void bwi_stop(struct bwi_softc *, int); 130static void bwi_stop_locked(struct bwi_softc *, int); 131static int bwi_newbuf(struct bwi_softc *, int, int); 132static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *); 134static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *, 136 const struct ieee80211_bpf_params *); 137 138static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 139 bus_addr_t, int, int); 140static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 141 142static int bwi_init_tx_ring32(struct bwi_softc *, int); 143static int bwi_init_rx_ring32(struct bwi_softc *); 144static int bwi_init_txstats32(struct bwi_softc *); 145static void bwi_free_tx_ring32(struct bwi_softc *, int); 146static void bwi_free_rx_ring32(struct bwi_softc *); 147static void bwi_free_txstats32(struct bwi_softc *); 148static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 149static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 150 int, bus_addr_t, int); 151static int bwi_rxeof32(struct bwi_softc *); 152static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 153static void bwi_txeof_status32(struct bwi_softc *); 154 155static int bwi_init_tx_ring64(struct bwi_softc *, int); 156static int bwi_init_rx_ring64(struct bwi_softc *); 157static int bwi_init_txstats64(struct bwi_softc *); 158static void bwi_free_tx_ring64(struct bwi_softc *, int); 159static void bwi_free_rx_ring64(struct bwi_softc *); 160static void bwi_free_txstats64(struct bwi_softc *); 161static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 162static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 163 int, bus_addr_t, int); 164static int bwi_rxeof64(struct bwi_softc *); 165static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 166static void bwi_txeof_status64(struct bwi_softc *); 167 168static int bwi_rxeof(struct bwi_softc *, int); 169static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 170static void bwi_txeof(struct bwi_softc *); 171static void bwi_txeof_status(struct bwi_softc *, int); 172static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 173static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 174 175static int bwi_dma_alloc(struct bwi_softc *); 176static void bwi_dma_free(struct bwi_softc *); 177static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 178 struct bwi_ring_data *, bus_size_t, 179 uint32_t); 180static int bwi_dma_mbuf_create(struct bwi_softc *); 181static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 182static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 183static void bwi_dma_txstats_free(struct bwi_softc *); 184static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 185static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 186 bus_size_t, int); 187 188static void bwi_power_on(struct bwi_softc *, int); 189static int bwi_power_off(struct bwi_softc *, int); 190static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 191static int bwi_set_clock_delay(struct bwi_softc *); 192static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 193static int bwi_get_pwron_delay(struct bwi_softc *sc); 194static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 195 const uint8_t *); 196static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 197 198static void bwi_get_card_flags(struct bwi_softc *); 199static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 200 201static int bwi_bus_attach(struct bwi_softc *); 202static int bwi_bbp_attach(struct bwi_softc *); 203static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 204static void bwi_bbp_power_off(struct bwi_softc *); 205 206static const char *bwi_regwin_name(const struct bwi_regwin *); 207static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 208static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 209static int bwi_regwin_select(struct bwi_softc *, int); 210 211static void bwi_led_attach(struct bwi_softc *); 212static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 213static void bwi_led_event(struct bwi_softc *, int); 214static void bwi_led_blink_start(struct bwi_softc *, int, int); 215static void bwi_led_blink_next(void *); 216static void bwi_led_blink_end(void *); 217 218static const struct { 219 uint16_t did_min; 220 uint16_t did_max; 221 uint16_t bbp_id; 222} bwi_bbpid_map[] = { 223 { 0x4301, 0x4301, 0x4301 }, 224 { 0x4305, 0x4307, 0x4307 }, 225 { 0x4402, 0x4403, 0x4402 }, 226 { 0x4610, 0x4615, 0x4610 }, 227 { 0x4710, 0x4715, 0x4710 }, 228 { 0x4720, 0x4725, 0x4309 } 229}; 230 231static const struct { 232 uint16_t bbp_id; 233 int nregwin; 234} bwi_regwin_count[] = { 235 { 0x4301, 5 }, 236 { 0x4306, 6 }, 237 { 0x4307, 5 }, 238 { 0x4310, 8 }, 239 { 0x4401, 3 }, 240 { 0x4402, 3 }, 241 { 0x4610, 9 }, 242 { 0x4704, 9 }, 243 { 0x4710, 9 }, 244 { 0x5365, 7 } 245}; 246 247#define CLKSRC(src) \ 248[BWI_CLKSRC_ ## src] = { \ 249 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 250 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 251} 252 253static const struct { 254 u_int freq_min; 255 u_int freq_max; 256} bwi_clkfreq[BWI_CLKSRC_MAX] = { 257 CLKSRC(LP_OSC), 258 CLKSRC(CS_OSC), 259 CLKSRC(PCI) 260}; 261 262#undef CLKSRC 263 264#define VENDOR_LED_ACT(vendor) \ 265{ \ 266 .vid = PCI_VENDOR_##vendor, \ 267 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 268} 269 270static const struct { 271#define PCI_VENDOR_COMPAQ 0x0e11 272#define PCI_VENDOR_LINKSYS 0x1737 273 uint16_t vid; 274 uint8_t led_act[BWI_LED_MAX]; 275} bwi_vendor_led_act[] = { 276 VENDOR_LED_ACT(COMPAQ), 277 VENDOR_LED_ACT(LINKSYS) 278#undef PCI_VENDOR_LINKSYS 279#undef PCI_VENDOR_COMPAQ 280}; 281 282static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 283 { BWI_VENDOR_LED_ACT_DEFAULT }; 284 285#undef VENDOR_LED_ACT 286 287static const struct { 288 int on_dur; 289 int off_dur; 290} bwi_led_duration[109] = { 291 [0] = { 400, 100 }, 292 [2] = { 150, 75 }, 293 [4] = { 90, 45 }, 294 [11] = { 66, 34 }, 295 [12] = { 53, 26 }, 296 [18] = { 42, 21 }, 297 [22] = { 35, 17 }, 298 [24] = { 32, 16 }, 299 [36] = { 21, 10 }, 300 [48] = { 16, 8 }, 301 [72] = { 11, 5 }, 302 [96] = { 9, 4 }, 303 [108] = { 7, 3 } 304}; 305 306#ifdef BWI_DEBUG 307#ifdef BWI_DEBUG_VERBOSE 308static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 309#else 310static uint32_t bwi_debug; 311#endif 312TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 313#endif /* BWI_DEBUG */ 314 315static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 316 317uint16_t 318bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 319{ 320 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 321} 322 323static __inline void 324bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 325 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 326 int tx) 327{ 328 struct bwi_desc32 *desc = &desc_array[desc_idx]; 329 uint32_t ctrl, addr, addr_hi, addr_lo; 330 331 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 332 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 333 334 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 335 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 336 337 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 338 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 339 if (desc_idx == ndesc - 1) 340 ctrl |= BWI_DESC32_C_EOR; 341 if (tx) { 342 /* XXX */ 343 ctrl |= BWI_DESC32_C_FRAME_START | 344 BWI_DESC32_C_FRAME_END | 345 BWI_DESC32_C_INTR; 346 } 347 348 desc->addr = htole32(addr); 349 desc->ctrl = htole32(ctrl); 350} 351 352int 353bwi_attach(struct bwi_softc *sc) 354{ 355 struct ieee80211com *ic = &sc->sc_ic; 356 device_t dev = sc->sc_dev; 357 struct bwi_mac *mac; 358 struct bwi_phy *phy; 359 int i, error; 360 uint8_t bands; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 373 mbufq_init(&sc->sc_snd, ifqmaxlen); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_blink = 1; 381 sc->sc_txpwr_calib = 1; 382#ifdef BWI_DEBUG 383 sc->sc_debug = bwi_debug; 384#endif 385 bwi_power_on(sc, 1); 386 387 error = bwi_bbp_attach(sc); 388 if (error) 389 goto fail; 390 391 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 392 if (error) 393 goto fail; 394 395 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 396 error = bwi_set_clock_delay(sc); 397 if (error) 398 goto fail; 399 400 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 401 if (error) 402 goto fail; 403 404 error = bwi_get_pwron_delay(sc); 405 if (error) 406 goto fail; 407 } 408 409 error = bwi_bus_attach(sc); 410 if (error) 411 goto fail; 412 413 bwi_get_card_flags(sc); 414 415 bwi_led_attach(sc); 416 417 for (i = 0; i < sc->sc_nmac; ++i) { 418 struct bwi_regwin *old; 419 420 mac = &sc->sc_mac[i]; 421 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 422 if (error) 423 goto fail; 424 425 error = bwi_mac_lateattach(mac); 426 if (error) 427 goto fail; 428 429 error = bwi_regwin_switch(sc, old, NULL); 430 if (error) 431 goto fail; 432 } 433 434 /* 435 * XXX First MAC is known to exist 436 * TODO2 437 */ 438 mac = &sc->sc_mac[0]; 439 phy = &mac->mac_phy; 440 441 bwi_bbp_power_off(sc); 442 443 error = bwi_dma_alloc(sc); 444 if (error) 445 goto fail; 446 447 error = bwi_mac_fw_alloc(mac); 448 if (error) 449 goto fail; 450 451 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 452 453 /* 454 * Setup ratesets, phytype, channels and get MAC address 455 */ 456 bands = 0; 457 if (phy->phy_mode == IEEE80211_MODE_11B || 458 phy->phy_mode == IEEE80211_MODE_11G) { 459 setbit(&bands, IEEE80211_MODE_11B); 460 if (phy->phy_mode == IEEE80211_MODE_11B) { 461 ic->ic_phytype = IEEE80211_T_DS; 462 } else { 463 ic->ic_phytype = IEEE80211_T_OFDM; 464 setbit(&bands, IEEE80211_MODE_11G); 465 } 466 467 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 469 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 470 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 471 device_printf(dev, 472 "invalid MAC address: %6D\n", 473 ic->ic_macaddr, ":"); 474 } 475 } 476 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 477 /* TODO:11A */ 478 setbit(&bands, IEEE80211_MODE_11A); 479 error = ENXIO; 480 goto fail; 481 } else { 482 panic("unknown phymode %d\n", phy->phy_mode); 483 } 484 485 /* Get locale */ 486 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 487 BWI_SPROM_CARD_INFO_LOCALE); 488 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 489 /* XXX use locale */ 490 ieee80211_init_channels(ic, NULL, &bands); 491 492 ic->ic_softc = sc; 493 ic->ic_name = device_get_nameunit(dev); 494 ic->ic_caps = IEEE80211_C_STA | 495 IEEE80211_C_SHSLOT | 496 IEEE80211_C_SHPREAMBLE | 497 IEEE80211_C_WPA | 498 IEEE80211_C_BGSCAN | 499 IEEE80211_C_MONITOR; 500 ic->ic_opmode = IEEE80211_M_STA; 501 ieee80211_ifattach(ic); 502 503 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 504 505 /* override default methods */ 506 ic->ic_vap_create = bwi_vap_create; 507 ic->ic_vap_delete = bwi_vap_delete; 508 ic->ic_raw_xmit = bwi_raw_xmit; 509 ic->ic_updateslot = bwi_updateslot; 510 ic->ic_scan_start = bwi_scan_start; 511 ic->ic_scan_end = bwi_scan_end; 512 ic->ic_set_channel = bwi_set_channel; 513 ic->ic_transmit = bwi_transmit; 514 ic->ic_parent = bwi_parent; 515 516 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 517 518 ieee80211_radiotap_attach(ic, 519 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 520 BWI_TX_RADIOTAP_PRESENT, 521 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 522 BWI_RX_RADIOTAP_PRESENT); 523 524 /* 525 * Add sysctl nodes 526 */ 527 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 528 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 529 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 530 "Firmware version"); 531 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 533 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 534 "# ticks before LED enters idle state"); 535 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 537 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 538 "Allow LED to blink"); 539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 541 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 542 "Enable software TX power calibration"); 543#ifdef BWI_DEBUG 544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 547#endif 548 if (bootverbose) 549 ieee80211_announce(ic); 550 551 return (0); 552fail: 553 BWI_LOCK_DESTROY(sc); 554 return (error); 555} 556 557int 558bwi_detach(struct bwi_softc *sc) 559{ 560 struct ieee80211com *ic = &sc->sc_ic; 561 int i; 562 563 bwi_stop(sc, 1); 564 callout_drain(&sc->sc_led_blink_ch); 565 callout_drain(&sc->sc_calib_ch); 566 callout_drain(&sc->sc_watchdog_timer); 567 ieee80211_ifdetach(ic); 568 569 for (i = 0; i < sc->sc_nmac; ++i) 570 bwi_mac_detach(&sc->sc_mac[i]); 571 bwi_dma_free(sc); 572 taskqueue_free(sc->sc_tq); 573 mbufq_drain(&sc->sc_snd); 574 575 BWI_LOCK_DESTROY(sc); 576 577 return (0); 578} 579 580static struct ieee80211vap * 581bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 582 enum ieee80211_opmode opmode, int flags, 583 const uint8_t bssid[IEEE80211_ADDR_LEN], 584 const uint8_t mac[IEEE80211_ADDR_LEN]) 585{ 586 struct bwi_vap *bvp; 587 struct ieee80211vap *vap; 588 589 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 590 return NULL; 591 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 592 vap = &bvp->bv_vap; 593 /* enable s/w bmiss handling for sta mode */ 594 ieee80211_vap_setup(ic, vap, name, unit, opmode, 595 flags | IEEE80211_CLONE_NOBEACONS, bssid); 596 597 /* override default methods */ 598 bvp->bv_newstate = vap->iv_newstate; 599 vap->iv_newstate = bwi_newstate; 600#if 0 601 vap->iv_update_beacon = bwi_beacon_update; 602#endif 603 ieee80211_ratectl_init(vap); 604 605 /* complete setup */ 606 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status, 607 mac); 608 ic->ic_opmode = opmode; 609 return vap; 610} 611 612static void 613bwi_vap_delete(struct ieee80211vap *vap) 614{ 615 struct bwi_vap *bvp = BWI_VAP(vap); 616 617 ieee80211_ratectl_deinit(vap); 618 ieee80211_vap_detach(vap); 619 free(bvp, M_80211_VAP); 620} 621 622void 623bwi_suspend(struct bwi_softc *sc) 624{ 625 bwi_stop(sc, 1); 626} 627 628void 629bwi_resume(struct bwi_softc *sc) 630{ 631 632 if (sc->sc_ic.ic_nrunning > 0) 633 bwi_init(sc); 634} 635 636int 637bwi_shutdown(struct bwi_softc *sc) 638{ 639 bwi_stop(sc, 1); 640 return 0; 641} 642 643static void 644bwi_power_on(struct bwi_softc *sc, int with_pll) 645{ 646 uint32_t gpio_in, gpio_out, gpio_en; 647 uint16_t status; 648 649 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 650 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 651 goto back; 652 653 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 654 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 655 656 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 657 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 658 if (with_pll) { 659 /* Turn off PLL first */ 660 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 661 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 662 } 663 664 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 665 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 666 DELAY(1000); 667 668 if (with_pll) { 669 /* Turn on PLL */ 670 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 671 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 672 DELAY(5000); 673 } 674 675back: 676 /* Clear "Signaled Target Abort" */ 677 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 678 status &= ~PCIM_STATUS_STABORT; 679 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 680} 681 682static int 683bwi_power_off(struct bwi_softc *sc, int with_pll) 684{ 685 uint32_t gpio_out, gpio_en; 686 687 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 688 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 689 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 690 691 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 692 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 693 if (with_pll) { 694 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 695 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 696 } 697 698 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 699 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 700 return 0; 701} 702 703int 704bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 705 struct bwi_regwin **old_rw) 706{ 707 int error; 708 709 if (old_rw != NULL) 710 *old_rw = NULL; 711 712 if (!BWI_REGWIN_EXIST(rw)) 713 return EINVAL; 714 715 if (sc->sc_cur_regwin != rw) { 716 error = bwi_regwin_select(sc, rw->rw_id); 717 if (error) { 718 device_printf(sc->sc_dev, "can't select regwin %d\n", 719 rw->rw_id); 720 return error; 721 } 722 } 723 724 if (old_rw != NULL) 725 *old_rw = sc->sc_cur_regwin; 726 sc->sc_cur_regwin = rw; 727 return 0; 728} 729 730static int 731bwi_regwin_select(struct bwi_softc *sc, int id) 732{ 733 uint32_t win = BWI_PCIM_REGWIN(id); 734 int i; 735 736#define RETRY_MAX 50 737 for (i = 0; i < RETRY_MAX; ++i) { 738 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 739 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 740 return 0; 741 DELAY(10); 742 } 743#undef RETRY_MAX 744 745 return ENXIO; 746} 747 748static void 749bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 750{ 751 uint32_t val; 752 753 val = CSR_READ_4(sc, BWI_ID_HI); 754 *type = BWI_ID_HI_REGWIN_TYPE(val); 755 *rev = BWI_ID_HI_REGWIN_REV(val); 756 757 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 758 "vendor 0x%04x\n", *type, *rev, 759 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 760} 761 762static int 763bwi_bbp_attach(struct bwi_softc *sc) 764{ 765#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 766 uint16_t bbp_id, rw_type; 767 uint8_t rw_rev; 768 uint32_t info; 769 int error, nregwin, i; 770 771 /* 772 * Get 0th regwin information 773 * NOTE: 0th regwin should exist 774 */ 775 error = bwi_regwin_select(sc, 0); 776 if (error) { 777 device_printf(sc->sc_dev, "can't select regwin 0\n"); 778 return error; 779 } 780 bwi_regwin_info(sc, &rw_type, &rw_rev); 781 782 /* 783 * Find out BBP id 784 */ 785 bbp_id = 0; 786 info = 0; 787 if (rw_type == BWI_REGWIN_T_COM) { 788 info = CSR_READ_4(sc, BWI_INFO); 789 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 790 791 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 792 793 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 794 } else { 795 for (i = 0; i < N(bwi_bbpid_map); ++i) { 796 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 797 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 798 bbp_id = bwi_bbpid_map[i].bbp_id; 799 break; 800 } 801 } 802 if (bbp_id == 0) { 803 device_printf(sc->sc_dev, "no BBP id for device id " 804 "0x%04x\n", sc->sc_pci_did); 805 return ENXIO; 806 } 807 808 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 809 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 810 } 811 812 /* 813 * Find out number of regwins 814 */ 815 nregwin = 0; 816 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 817 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 818 } else { 819 for (i = 0; i < N(bwi_regwin_count); ++i) { 820 if (bwi_regwin_count[i].bbp_id == bbp_id) { 821 nregwin = bwi_regwin_count[i].nregwin; 822 break; 823 } 824 } 825 if (nregwin == 0) { 826 device_printf(sc->sc_dev, "no number of win for " 827 "BBP id 0x%04x\n", bbp_id); 828 return ENXIO; 829 } 830 } 831 832 /* Record BBP id/rev for later using */ 833 sc->sc_bbp_id = bbp_id; 834 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 835 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 836 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 837 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 838 839 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 840 nregwin, sc->sc_cap); 841 842 /* 843 * Create rest of the regwins 844 */ 845 846 /* Don't re-create common regwin, if it is already created */ 847 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 848 849 for (; i < nregwin; ++i) { 850 /* 851 * Get regwin information 852 */ 853 error = bwi_regwin_select(sc, i); 854 if (error) { 855 device_printf(sc->sc_dev, 856 "can't select regwin %d\n", i); 857 return error; 858 } 859 bwi_regwin_info(sc, &rw_type, &rw_rev); 860 861 /* 862 * Try attach: 863 * 1) Bus (PCI/PCIE) regwin 864 * 2) MAC regwin 865 * Ignore rest types of regwin 866 */ 867 if (rw_type == BWI_REGWIN_T_BUSPCI || 868 rw_type == BWI_REGWIN_T_BUSPCIE) { 869 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 870 device_printf(sc->sc_dev, 871 "bus regwin already exists\n"); 872 } else { 873 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 874 rw_type, rw_rev); 875 } 876 } else if (rw_type == BWI_REGWIN_T_MAC) { 877 /* XXX ignore return value */ 878 bwi_mac_attach(sc, i, rw_rev); 879 } 880 } 881 882 /* At least one MAC shold exist */ 883 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 884 device_printf(sc->sc_dev, "no MAC was found\n"); 885 return ENXIO; 886 } 887 KASSERT(sc->sc_nmac > 0, ("no mac's")); 888 889 /* Bus regwin must exist */ 890 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 891 device_printf(sc->sc_dev, "no bus regwin was found\n"); 892 return ENXIO; 893 } 894 895 /* Start with first MAC */ 896 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 897 if (error) 898 return error; 899 900 return 0; 901#undef N 902} 903 904int 905bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 906{ 907 struct bwi_regwin *old, *bus; 908 uint32_t val; 909 int error; 910 911 bus = &sc->sc_bus_regwin; 912 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 913 914 /* 915 * Tell bus to generate requested interrupts 916 */ 917 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 918 /* 919 * NOTE: Read BWI_FLAGS from MAC regwin 920 */ 921 val = CSR_READ_4(sc, BWI_FLAGS); 922 923 error = bwi_regwin_switch(sc, bus, &old); 924 if (error) 925 return error; 926 927 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 928 } else { 929 uint32_t mac_mask; 930 931 mac_mask = 1 << mac->mac_id; 932 933 error = bwi_regwin_switch(sc, bus, &old); 934 if (error) 935 return error; 936 937 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 938 val |= mac_mask << 8; 939 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 940 } 941 942 if (sc->sc_flags & BWI_F_BUS_INITED) 943 goto back; 944 945 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 946 /* 947 * Enable prefetch and burst 948 */ 949 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 950 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 951 952 if (bus->rw_rev < 5) { 953 struct bwi_regwin *com = &sc->sc_com_regwin; 954 955 /* 956 * Configure timeouts for bus operation 957 */ 958 959 /* 960 * Set service timeout and request timeout 961 */ 962 CSR_SETBITS_4(sc, BWI_CONF_LO, 963 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 964 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 965 966 /* 967 * If there is common regwin, we switch to that regwin 968 * and switch back to bus regwin once we have done. 969 */ 970 if (BWI_REGWIN_EXIST(com)) { 971 error = bwi_regwin_switch(sc, com, NULL); 972 if (error) 973 return error; 974 } 975 976 /* Let bus know what we have changed */ 977 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 978 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 979 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 980 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 981 982 if (BWI_REGWIN_EXIST(com)) { 983 error = bwi_regwin_switch(sc, bus, NULL); 984 if (error) 985 return error; 986 } 987 } else if (bus->rw_rev >= 11) { 988 /* 989 * Enable memory read multiple 990 */ 991 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 992 } 993 } else { 994 /* TODO:PCIE */ 995 } 996 997 sc->sc_flags |= BWI_F_BUS_INITED; 998back: 999 return bwi_regwin_switch(sc, old, NULL); 1000} 1001 1002static void 1003bwi_get_card_flags(struct bwi_softc *sc) 1004{ 1005#define PCI_VENDOR_APPLE 0x106b 1006#define PCI_VENDOR_DELL 0x1028 1007 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1008 if (sc->sc_card_flags == 0xffff) 1009 sc->sc_card_flags = 0; 1010 1011 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1012 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1013 sc->sc_pci_revid == 0x74) 1014 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1015 1016 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1017 sc->sc_pci_subdid == 0x4e && /* XXX */ 1018 sc->sc_pci_revid > 0x40) 1019 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1020 1021 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1022#undef PCI_VENDOR_DELL 1023#undef PCI_VENDOR_APPLE 1024} 1025 1026static void 1027bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1028{ 1029 int i; 1030 1031 for (i = 0; i < 3; ++i) { 1032 *((uint16_t *)eaddr + i) = 1033 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1034 } 1035} 1036 1037static void 1038bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1039{ 1040 struct bwi_regwin *com; 1041 uint32_t val; 1042 u_int div; 1043 int src; 1044 1045 bzero(freq, sizeof(*freq)); 1046 com = &sc->sc_com_regwin; 1047 1048 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1049 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1050 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1051 1052 /* 1053 * Calculate clock frequency 1054 */ 1055 src = -1; 1056 div = 0; 1057 if (com->rw_rev < 6) { 1058 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1059 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1060 src = BWI_CLKSRC_PCI; 1061 div = 64; 1062 } else { 1063 src = BWI_CLKSRC_CS_OSC; 1064 div = 32; 1065 } 1066 } else if (com->rw_rev < 10) { 1067 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1068 1069 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1070 if (src == BWI_CLKSRC_LP_OSC) { 1071 div = 1; 1072 } else { 1073 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1074 1075 /* Unknown source */ 1076 if (src >= BWI_CLKSRC_MAX) 1077 src = BWI_CLKSRC_CS_OSC; 1078 } 1079 } else { 1080 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1081 1082 src = BWI_CLKSRC_CS_OSC; 1083 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1084 } 1085 1086 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1087 KASSERT(div != 0, ("div zero")); 1088 1089 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1090 src == BWI_CLKSRC_PCI ? "PCI" : 1091 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1092 1093 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1094 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1095 1096 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1097 freq->clkfreq_min, freq->clkfreq_max); 1098} 1099 1100static int 1101bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1102{ 1103 struct bwi_regwin *old, *com; 1104 uint32_t clk_ctrl, clk_src; 1105 int error, pwr_off = 0; 1106 1107 com = &sc->sc_com_regwin; 1108 if (!BWI_REGWIN_EXIST(com)) 1109 return 0; 1110 1111 if (com->rw_rev >= 10 || com->rw_rev < 6) 1112 return 0; 1113 1114 /* 1115 * For common regwin whose rev is [6, 10), the chip 1116 * must be capable to change clock mode. 1117 */ 1118 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1119 return 0; 1120 1121 error = bwi_regwin_switch(sc, com, &old); 1122 if (error) 1123 return error; 1124 1125 if (clk_mode == BWI_CLOCK_MODE_FAST) 1126 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1127 1128 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1129 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1130 1131 switch (clk_mode) { 1132 case BWI_CLOCK_MODE_FAST: 1133 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1134 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1135 break; 1136 case BWI_CLOCK_MODE_SLOW: 1137 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1138 break; 1139 case BWI_CLOCK_MODE_DYN: 1140 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1141 BWI_CLOCK_CTRL_IGNPLL | 1142 BWI_CLOCK_CTRL_NODYN); 1143 if (clk_src != BWI_CLKSRC_CS_OSC) { 1144 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1145 pwr_off = 1; 1146 } 1147 break; 1148 } 1149 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1150 1151 if (pwr_off) 1152 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1153 1154 return bwi_regwin_switch(sc, old, NULL); 1155} 1156 1157static int 1158bwi_set_clock_delay(struct bwi_softc *sc) 1159{ 1160 struct bwi_regwin *old, *com; 1161 int error; 1162 1163 com = &sc->sc_com_regwin; 1164 if (!BWI_REGWIN_EXIST(com)) 1165 return 0; 1166 1167 error = bwi_regwin_switch(sc, com, &old); 1168 if (error) 1169 return error; 1170 1171 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1172 if (sc->sc_bbp_rev == 0) 1173 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1174 else if (sc->sc_bbp_rev == 1) 1175 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1176 } 1177 1178 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1179 if (com->rw_rev >= 10) { 1180 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1181 } else { 1182 struct bwi_clock_freq freq; 1183 1184 bwi_get_clock_freq(sc, &freq); 1185 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1186 howmany(freq.clkfreq_max * 150, 1000000)); 1187 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1188 howmany(freq.clkfreq_max * 15, 1000000)); 1189 } 1190 } 1191 1192 return bwi_regwin_switch(sc, old, NULL); 1193} 1194 1195static void 1196bwi_init(struct bwi_softc *sc) 1197{ 1198 struct ieee80211com *ic = &sc->sc_ic; 1199 1200 BWI_LOCK(sc); 1201 bwi_init_statechg(sc, 1); 1202 BWI_UNLOCK(sc); 1203 1204 if (sc->sc_flags & BWI_F_RUNNING) 1205 ieee80211_start_all(ic); /* start all vap's */ 1206} 1207 1208static void 1209bwi_init_statechg(struct bwi_softc *sc, int statechg) 1210{ 1211 struct bwi_mac *mac; 1212 int error; 1213 1214 BWI_ASSERT_LOCKED(sc); 1215 1216 bwi_stop_locked(sc, statechg); 1217 1218 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1219 1220 /* TODO: 2 MAC */ 1221 1222 mac = &sc->sc_mac[0]; 1223 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1224 if (error) { 1225 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1226 __func__, error); 1227 goto bad; 1228 } 1229 error = bwi_mac_init(mac); 1230 if (error) { 1231 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1232 __func__, error); 1233 goto bad; 1234 } 1235 1236 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1237 1238 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1239 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1240 1241 bwi_mac_reset_hwkeys(mac); 1242 1243 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1244 int i; 1245 1246#define NRETRY 1000 1247 /* 1248 * Drain any possible pending TX status 1249 */ 1250 for (i = 0; i < NRETRY; ++i) { 1251 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1252 BWI_TXSTATUS0_VALID) == 0) 1253 break; 1254 CSR_READ_4(sc, BWI_TXSTATUS1); 1255 } 1256 if (i == NRETRY) 1257 device_printf(sc->sc_dev, 1258 "%s: can't drain TX status\n", __func__); 1259#undef NRETRY 1260 } 1261 1262 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1263 bwi_mac_updateslot(mac, 1); 1264 1265 /* Start MAC */ 1266 error = bwi_mac_start(mac); 1267 if (error) { 1268 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1269 __func__, error); 1270 goto bad; 1271 } 1272 1273 /* Clear stop flag before enabling interrupt */ 1274 sc->sc_flags &= ~BWI_F_STOP; 1275 sc->sc_flags |= BWI_F_RUNNING; 1276 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1277 1278 /* Enable intrs */ 1279 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1280 return; 1281bad: 1282 bwi_stop_locked(sc, 1); 1283} 1284 1285static void 1286bwi_parent(struct ieee80211com *ic) 1287{ 1288 struct bwi_softc *sc = ic->ic_softc; 1289 int startall = 0; 1290 1291 BWI_LOCK(sc); 1292 if (ic->ic_nrunning > 0) { 1293 struct bwi_mac *mac; 1294 int promisc = -1; 1295 1296 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1297 ("current regwin type %d", 1298 sc->sc_cur_regwin->rw_type)); 1299 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1300 1301 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1302 promisc = 1; 1303 sc->sc_flags |= BWI_F_PROMISC; 1304 } else if (ic->ic_promisc == 0 && 1305 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1306 promisc = 0; 1307 sc->sc_flags &= ~BWI_F_PROMISC; 1308 } 1309 1310 if (promisc >= 0) 1311 bwi_mac_set_promisc(mac, promisc); 1312 } 1313 if (ic->ic_nrunning > 0) { 1314 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1315 bwi_init_statechg(sc, 1); 1316 startall = 1; 1317 } 1318 } else if (sc->sc_flags & BWI_F_RUNNING) 1319 bwi_stop_locked(sc, 1); 1320 BWI_UNLOCK(sc); 1321 if (startall) 1322 ieee80211_start_all(ic); 1323} 1324 1325static int 1326bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1327{ 1328 struct bwi_softc *sc = ic->ic_softc; 1329 int error; 1330 1331 BWI_LOCK(sc); 1332 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1333 BWI_UNLOCK(sc); 1334 return (ENXIO); 1335 } 1336 error = mbufq_enqueue(&sc->sc_snd, m); 1337 if (error) { 1338 BWI_UNLOCK(sc); 1339 return (error); 1340 } 1341 bwi_start_locked(sc); 1342 BWI_UNLOCK(sc); 1343 return (0); 1344} 1345 1346static void 1347bwi_start_locked(struct bwi_softc *sc) 1348{ 1349 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1350 struct ieee80211_frame *wh; 1351 struct ieee80211_node *ni; 1352 struct mbuf *m; 1353 int trans, idx; 1354 1355 BWI_ASSERT_LOCKED(sc); 1356 1357 trans = 0; 1358 idx = tbd->tbd_idx; 1359 1360 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1361 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1362 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1363 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1364 wh = mtod(m, struct ieee80211_frame *); 1365 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1366 ieee80211_crypto_encap(ni, m) == NULL) { 1367 if_inc_counter(ni->ni_vap->iv_ifp, 1368 IFCOUNTER_OERRORS, 1); 1369 ieee80211_free_node(ni); 1370 m_freem(m); 1371 continue; 1372 } 1373 if (bwi_encap(sc, idx, m, ni) != 0) { 1374 /* 'm' is freed in bwi_encap() if we reach here */ 1375 if (ni != NULL) { 1376 if_inc_counter(ni->ni_vap->iv_ifp, 1377 IFCOUNTER_OERRORS, 1); 1378 ieee80211_free_node(ni); 1379 } else 1380 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1381 continue; 1382 } 1383 trans = 1; 1384 tbd->tbd_used++; 1385 idx = (idx + 1) % BWI_TX_NDESC; 1386 } 1387 1388 tbd->tbd_idx = idx; 1389 if (trans) 1390 sc->sc_tx_timer = 5; 1391} 1392 1393static int 1394bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1395 const struct ieee80211_bpf_params *params) 1396{ 1397 struct ieee80211com *ic = ni->ni_ic; 1398 struct bwi_softc *sc = ic->ic_softc; 1399 /* XXX wme? */ 1400 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1401 int idx, error; 1402 1403 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1404 ieee80211_free_node(ni); 1405 m_freem(m); 1406 return ENETDOWN; 1407 } 1408 1409 BWI_LOCK(sc); 1410 idx = tbd->tbd_idx; 1411 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1412 if (params == NULL) { 1413 /* 1414 * Legacy path; interpret frame contents to decide 1415 * precisely how to send the frame. 1416 */ 1417 error = bwi_encap(sc, idx, m, ni); 1418 } else { 1419 /* 1420 * Caller supplied explicit parameters to use in 1421 * sending the frame. 1422 */ 1423 error = bwi_encap_raw(sc, idx, m, ni, params); 1424 } 1425 if (error == 0) { 1426 tbd->tbd_used++; 1427 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1428 sc->sc_tx_timer = 5; 1429 } else 1430 /* NB: m is reclaimed on encap failure */ 1431 ieee80211_free_node(ni); 1432 BWI_UNLOCK(sc); 1433 return error; 1434} 1435 1436static void 1437bwi_watchdog(void *arg) 1438{ 1439 struct bwi_softc *sc; 1440 1441 sc = arg; 1442 BWI_ASSERT_LOCKED(sc); 1443 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1444 device_printf(sc->sc_dev, "watchdog timeout\n"); 1445 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1446 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1447 } 1448 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1449} 1450 1451static void 1452bwi_stop(struct bwi_softc *sc, int statechg) 1453{ 1454 BWI_LOCK(sc); 1455 bwi_stop_locked(sc, statechg); 1456 BWI_UNLOCK(sc); 1457} 1458 1459static void 1460bwi_stop_locked(struct bwi_softc *sc, int statechg) 1461{ 1462 struct bwi_mac *mac; 1463 int i, error, pwr_off = 0; 1464 1465 BWI_ASSERT_LOCKED(sc); 1466 1467 callout_stop(&sc->sc_calib_ch); 1468 callout_stop(&sc->sc_led_blink_ch); 1469 sc->sc_led_blinking = 0; 1470 sc->sc_flags |= BWI_F_STOP; 1471 1472 if (sc->sc_flags & BWI_F_RUNNING) { 1473 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1474 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1475 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1476 1477 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1478 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1479 bwi_mac_stop(mac); 1480 } 1481 1482 for (i = 0; i < sc->sc_nmac; ++i) { 1483 struct bwi_regwin *old_rw; 1484 1485 mac = &sc->sc_mac[i]; 1486 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1487 continue; 1488 1489 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1490 if (error) 1491 continue; 1492 1493 bwi_mac_shutdown(mac); 1494 pwr_off = 1; 1495 1496 bwi_regwin_switch(sc, old_rw, NULL); 1497 } 1498 1499 if (pwr_off) 1500 bwi_bbp_power_off(sc); 1501 1502 sc->sc_tx_timer = 0; 1503 callout_stop(&sc->sc_watchdog_timer); 1504 sc->sc_flags &= ~BWI_F_RUNNING; 1505} 1506 1507void 1508bwi_intr(void *xsc) 1509{ 1510 struct bwi_softc *sc = xsc; 1511 struct bwi_mac *mac; 1512 uint32_t intr_status; 1513 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1514 int i, txrx_error, tx = 0, rx_data = -1; 1515 1516 BWI_LOCK(sc); 1517 1518 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1519 (sc->sc_flags & BWI_F_STOP)) { 1520 BWI_UNLOCK(sc); 1521 return; 1522 } 1523 /* 1524 * Get interrupt status 1525 */ 1526 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1527 if (intr_status == 0xffffffff) { /* Not for us */ 1528 BWI_UNLOCK(sc); 1529 return; 1530 } 1531 1532 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1533 1534 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1535 if (intr_status == 0) { /* Nothing is interesting */ 1536 BWI_UNLOCK(sc); 1537 return; 1538 } 1539 1540 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1541 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1542 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1543 1544 txrx_error = 0; 1545 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1546 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1547 uint32_t mask; 1548 1549 if (BWI_TXRX_IS_RX(i)) 1550 mask = BWI_TXRX_RX_INTRS; 1551 else 1552 mask = BWI_TXRX_TX_INTRS; 1553 1554 txrx_intr_status[i] = 1555 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1556 1557 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1558 i, txrx_intr_status[i]); 1559 1560 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1561 device_printf(sc->sc_dev, 1562 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1563 __func__, i, txrx_intr_status[i]); 1564 txrx_error = 1; 1565 } 1566 } 1567 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1568 1569 /* 1570 * Acknowledge interrupt 1571 */ 1572 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1573 1574 for (i = 0; i < BWI_TXRX_NRING; ++i) 1575 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1576 1577 /* Disable all interrupts */ 1578 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1579 1580 /* 1581 * http://bcm-specs.sipsolutions.net/Interrupts 1582 * Says for this bit (0x800): 1583 * "Fatal Error 1584 * 1585 * We got this one while testing things when by accident the 1586 * template ram wasn't set to big endian when it should have 1587 * been after writing the initial values. It keeps on being 1588 * triggered, the only way to stop it seems to shut down the 1589 * chip." 1590 * 1591 * Suggesting that we should never get it and if we do we're not 1592 * feeding TX packets into the MAC correctly if we do... Apparently, 1593 * it is valid only on mac version 5 and higher, but I couldn't 1594 * find a reference for that... Since I see them from time to time 1595 * on my card, this suggests an error in the tx path still... 1596 */ 1597 if (intr_status & BWI_INTR_PHY_TXERR) { 1598 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1599 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1600 __func__); 1601 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1602 BWI_UNLOCK(sc); 1603 return; 1604 } 1605 } 1606 1607 if (txrx_error) { 1608 /* TODO: reset device */ 1609 } 1610 1611 if (intr_status & BWI_INTR_TBTT) 1612 bwi_mac_config_ps(mac); 1613 1614 if (intr_status & BWI_INTR_EO_ATIM) 1615 device_printf(sc->sc_dev, "EO_ATIM\n"); 1616 1617 if (intr_status & BWI_INTR_PMQ) { 1618 for (;;) { 1619 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1620 break; 1621 } 1622 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1623 } 1624 1625 if (intr_status & BWI_INTR_NOISE) 1626 device_printf(sc->sc_dev, "intr noise\n"); 1627 1628 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1629 rx_data = sc->sc_rxeof(sc); 1630 if (sc->sc_flags & BWI_F_STOP) { 1631 BWI_UNLOCK(sc); 1632 return; 1633 } 1634 } 1635 1636 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1637 sc->sc_txeof_status(sc); 1638 tx = 1; 1639 } 1640 1641 if (intr_status & BWI_INTR_TX_DONE) { 1642 bwi_txeof(sc); 1643 tx = 1; 1644 } 1645 1646 /* Re-enable interrupts */ 1647 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1648 1649 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1650 int evt = BWI_LED_EVENT_NONE; 1651 1652 if (tx && rx_data > 0) { 1653 if (sc->sc_rx_rate > sc->sc_tx_rate) 1654 evt = BWI_LED_EVENT_RX; 1655 else 1656 evt = BWI_LED_EVENT_TX; 1657 } else if (tx) { 1658 evt = BWI_LED_EVENT_TX; 1659 } else if (rx_data > 0) { 1660 evt = BWI_LED_EVENT_RX; 1661 } else if (rx_data == 0) { 1662 evt = BWI_LED_EVENT_POLL; 1663 } 1664 1665 if (evt != BWI_LED_EVENT_NONE) 1666 bwi_led_event(sc, evt); 1667 } 1668 1669 BWI_UNLOCK(sc); 1670} 1671 1672static void 1673bwi_scan_start(struct ieee80211com *ic) 1674{ 1675 struct bwi_softc *sc = ic->ic_softc; 1676 1677 BWI_LOCK(sc); 1678 /* Enable MAC beacon promiscuity */ 1679 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1680 BWI_UNLOCK(sc); 1681} 1682 1683static void 1684bwi_set_channel(struct ieee80211com *ic) 1685{ 1686 struct bwi_softc *sc = ic->ic_softc; 1687 struct ieee80211_channel *c = ic->ic_curchan; 1688 struct bwi_mac *mac; 1689 1690 BWI_LOCK(sc); 1691 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1692 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1693 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1694 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1695 1696 sc->sc_rates = ieee80211_get_ratetable(c); 1697 1698 /* 1699 * Setup radio tap channel freq and flags 1700 */ 1701 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1702 htole16(c->ic_freq); 1703 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1704 htole16(c->ic_flags & 0xffff); 1705 1706 BWI_UNLOCK(sc); 1707} 1708 1709static void 1710bwi_scan_end(struct ieee80211com *ic) 1711{ 1712 struct bwi_softc *sc = ic->ic_softc; 1713 1714 BWI_LOCK(sc); 1715 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1716 BWI_UNLOCK(sc); 1717} 1718 1719static int 1720bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1721{ 1722 struct bwi_vap *bvp = BWI_VAP(vap); 1723 struct ieee80211com *ic= vap->iv_ic; 1724 struct bwi_softc *sc = ic->ic_softc; 1725 enum ieee80211_state ostate = vap->iv_state; 1726 struct bwi_mac *mac; 1727 int error; 1728 1729 BWI_LOCK(sc); 1730 1731 callout_stop(&sc->sc_calib_ch); 1732 1733 if (nstate == IEEE80211_S_INIT) 1734 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1735 1736 bwi_led_newstate(sc, nstate); 1737 1738 error = bvp->bv_newstate(vap, nstate, arg); 1739 if (error != 0) 1740 goto back; 1741 1742 /* 1743 * Clear the BSSID when we stop a STA 1744 */ 1745 if (vap->iv_opmode == IEEE80211_M_STA) { 1746 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1747 /* 1748 * Clear out the BSSID. If we reassociate to 1749 * the same AP, this will reinialize things 1750 * correctly... 1751 */ 1752 if (ic->ic_opmode == IEEE80211_M_STA && 1753 !(sc->sc_flags & BWI_F_STOP)) 1754 bwi_set_bssid(sc, bwi_zero_addr); 1755 } 1756 } 1757 1758 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1759 /* Nothing to do */ 1760 } else if (nstate == IEEE80211_S_RUN) { 1761 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1762 1763 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1764 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1765 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1766 1767 /* Initial TX power calibration */ 1768 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1769#ifdef notyet 1770 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1771#else 1772 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1773#endif 1774 1775 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1776 } 1777back: 1778 BWI_UNLOCK(sc); 1779 1780 return error; 1781} 1782 1783static int 1784bwi_media_change(struct ifnet *ifp) 1785{ 1786 int error = ieee80211_media_change(ifp); 1787 /* NB: only the fixed rate can change and that doesn't need a reset */ 1788 return (error == ENETRESET ? 0 : error); 1789} 1790 1791static int 1792bwi_dma_alloc(struct bwi_softc *sc) 1793{ 1794 int error, i, has_txstats; 1795 bus_addr_t lowaddr = 0; 1796 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1797 uint32_t txrx_ctrl_step = 0; 1798 1799 has_txstats = 0; 1800 for (i = 0; i < sc->sc_nmac; ++i) { 1801 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1802 has_txstats = 1; 1803 break; 1804 } 1805 } 1806 1807 switch (sc->sc_bus_space) { 1808 case BWI_BUS_SPACE_30BIT: 1809 case BWI_BUS_SPACE_32BIT: 1810 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1811 lowaddr = BWI_BUS_SPACE_MAXADDR; 1812 else 1813 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1814 desc_sz = sizeof(struct bwi_desc32); 1815 txrx_ctrl_step = 0x20; 1816 1817 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1818 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1819 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1820 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1821 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1822 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1823 sc->sc_rxeof = bwi_rxeof32; 1824 sc->sc_start_tx = bwi_start_tx32; 1825 if (has_txstats) { 1826 sc->sc_init_txstats = bwi_init_txstats32; 1827 sc->sc_free_txstats = bwi_free_txstats32; 1828 sc->sc_txeof_status = bwi_txeof_status32; 1829 } 1830 break; 1831 1832 case BWI_BUS_SPACE_64BIT: 1833 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1834 desc_sz = sizeof(struct bwi_desc64); 1835 txrx_ctrl_step = 0x40; 1836 1837 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1838 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1839 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1840 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1841 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1842 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1843 sc->sc_rxeof = bwi_rxeof64; 1844 sc->sc_start_tx = bwi_start_tx64; 1845 if (has_txstats) { 1846 sc->sc_init_txstats = bwi_init_txstats64; 1847 sc->sc_free_txstats = bwi_free_txstats64; 1848 sc->sc_txeof_status = bwi_txeof_status64; 1849 } 1850 break; 1851 } 1852 1853 KASSERT(lowaddr != 0, ("lowaddr zero")); 1854 KASSERT(desc_sz != 0, ("desc_sz zero")); 1855 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1856 1857 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1858 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1859 1860 /* 1861 * Create top level DMA tag 1862 */ 1863 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1864 BWI_ALIGN, 0, /* alignment, bounds */ 1865 lowaddr, /* lowaddr */ 1866 BUS_SPACE_MAXADDR, /* highaddr */ 1867 NULL, NULL, /* filter, filterarg */ 1868 BUS_SPACE_MAXSIZE, /* maxsize */ 1869 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1870 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1871 0, /* flags */ 1872 NULL, NULL, /* lockfunc, lockarg */ 1873 &sc->sc_parent_dtag); 1874 if (error) { 1875 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1876 return error; 1877 } 1878 1879#define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1880 1881 /* 1882 * Create TX ring DMA stuffs 1883 */ 1884 error = bus_dma_tag_create(sc->sc_parent_dtag, 1885 BWI_RING_ALIGN, 0, 1886 BUS_SPACE_MAXADDR, 1887 BUS_SPACE_MAXADDR, 1888 NULL, NULL, 1889 tx_ring_sz, 1890 1, 1891 tx_ring_sz, 1892 0, 1893 NULL, NULL, 1894 &sc->sc_txring_dtag); 1895 if (error) { 1896 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1897 return error; 1898 } 1899 1900 for (i = 0; i < BWI_TX_NRING; ++i) { 1901 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1902 &sc->sc_tx_rdata[i], tx_ring_sz, 1903 TXRX_CTRL(i)); 1904 if (error) { 1905 device_printf(sc->sc_dev, "%dth TX ring " 1906 "DMA alloc failed\n", i); 1907 return error; 1908 } 1909 } 1910 1911 /* 1912 * Create RX ring DMA stuffs 1913 */ 1914 error = bus_dma_tag_create(sc->sc_parent_dtag, 1915 BWI_RING_ALIGN, 0, 1916 BUS_SPACE_MAXADDR, 1917 BUS_SPACE_MAXADDR, 1918 NULL, NULL, 1919 rx_ring_sz, 1920 1, 1921 rx_ring_sz, 1922 0, 1923 NULL, NULL, 1924 &sc->sc_rxring_dtag); 1925 if (error) { 1926 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1927 return error; 1928 } 1929 1930 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1931 rx_ring_sz, TXRX_CTRL(0)); 1932 if (error) { 1933 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1934 return error; 1935 } 1936 1937 if (has_txstats) { 1938 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1939 if (error) { 1940 device_printf(sc->sc_dev, 1941 "TX stats DMA alloc failed\n"); 1942 return error; 1943 } 1944 } 1945 1946#undef TXRX_CTRL 1947 1948 return bwi_dma_mbuf_create(sc); 1949} 1950 1951static void 1952bwi_dma_free(struct bwi_softc *sc) 1953{ 1954 if (sc->sc_txring_dtag != NULL) { 1955 int i; 1956 1957 for (i = 0; i < BWI_TX_NRING; ++i) { 1958 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1959 1960 if (rd->rdata_desc != NULL) { 1961 bus_dmamap_unload(sc->sc_txring_dtag, 1962 rd->rdata_dmap); 1963 bus_dmamem_free(sc->sc_txring_dtag, 1964 rd->rdata_desc, 1965 rd->rdata_dmap); 1966 } 1967 } 1968 bus_dma_tag_destroy(sc->sc_txring_dtag); 1969 } 1970 1971 if (sc->sc_rxring_dtag != NULL) { 1972 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 1973 1974 if (rd->rdata_desc != NULL) { 1975 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 1976 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 1977 rd->rdata_dmap); 1978 } 1979 bus_dma_tag_destroy(sc->sc_rxring_dtag); 1980 } 1981 1982 bwi_dma_txstats_free(sc); 1983 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 1984 1985 if (sc->sc_parent_dtag != NULL) 1986 bus_dma_tag_destroy(sc->sc_parent_dtag); 1987} 1988 1989static int 1990bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 1991 struct bwi_ring_data *rd, bus_size_t size, 1992 uint32_t txrx_ctrl) 1993{ 1994 int error; 1995 1996 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 1997 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1998 &rd->rdata_dmap); 1999 if (error) { 2000 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2001 return error; 2002 } 2003 2004 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2005 bwi_dma_ring_addr, &rd->rdata_paddr, 2006 BUS_DMA_NOWAIT); 2007 if (error) { 2008 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2009 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2010 rd->rdata_desc = NULL; 2011 return error; 2012 } 2013 2014 rd->rdata_txrx_ctrl = txrx_ctrl; 2015 return 0; 2016} 2017 2018static int 2019bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2020 bus_size_t desc_sz) 2021{ 2022 struct bwi_txstats_data *st; 2023 bus_size_t dma_size; 2024 int error; 2025 2026 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2027 if (st == NULL) { 2028 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2029 return ENOMEM; 2030 } 2031 sc->sc_txstats = st; 2032 2033 /* 2034 * Create TX stats descriptor DMA stuffs 2035 */ 2036 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2037 2038 error = bus_dma_tag_create(sc->sc_parent_dtag, 2039 BWI_RING_ALIGN, 2040 0, 2041 BUS_SPACE_MAXADDR, 2042 BUS_SPACE_MAXADDR, 2043 NULL, NULL, 2044 dma_size, 2045 1, 2046 dma_size, 2047 0, 2048 NULL, NULL, 2049 &st->stats_ring_dtag); 2050 if (error) { 2051 device_printf(sc->sc_dev, "can't create txstats ring " 2052 "DMA tag\n"); 2053 return error; 2054 } 2055 2056 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2057 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2058 &st->stats_ring_dmap); 2059 if (error) { 2060 device_printf(sc->sc_dev, "can't allocate txstats ring " 2061 "DMA mem\n"); 2062 bus_dma_tag_destroy(st->stats_ring_dtag); 2063 st->stats_ring_dtag = NULL; 2064 return error; 2065 } 2066 2067 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2068 st->stats_ring, dma_size, 2069 bwi_dma_ring_addr, &st->stats_ring_paddr, 2070 BUS_DMA_NOWAIT); 2071 if (error) { 2072 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2073 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2074 st->stats_ring_dmap); 2075 bus_dma_tag_destroy(st->stats_ring_dtag); 2076 st->stats_ring_dtag = NULL; 2077 return error; 2078 } 2079 2080 /* 2081 * Create TX stats DMA stuffs 2082 */ 2083 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2084 BWI_ALIGN); 2085 2086 error = bus_dma_tag_create(sc->sc_parent_dtag, 2087 BWI_ALIGN, 2088 0, 2089 BUS_SPACE_MAXADDR, 2090 BUS_SPACE_MAXADDR, 2091 NULL, NULL, 2092 dma_size, 2093 1, 2094 dma_size, 2095 0, 2096 NULL, NULL, 2097 &st->stats_dtag); 2098 if (error) { 2099 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2100 return error; 2101 } 2102 2103 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2104 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2105 &st->stats_dmap); 2106 if (error) { 2107 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2108 bus_dma_tag_destroy(st->stats_dtag); 2109 st->stats_dtag = NULL; 2110 return error; 2111 } 2112 2113 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2114 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2115 BUS_DMA_NOWAIT); 2116 if (error) { 2117 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2118 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2119 bus_dma_tag_destroy(st->stats_dtag); 2120 st->stats_dtag = NULL; 2121 return error; 2122 } 2123 2124 st->stats_ctrl_base = ctrl_base; 2125 return 0; 2126} 2127 2128static void 2129bwi_dma_txstats_free(struct bwi_softc *sc) 2130{ 2131 struct bwi_txstats_data *st; 2132 2133 if (sc->sc_txstats == NULL) 2134 return; 2135 st = sc->sc_txstats; 2136 2137 if (st->stats_ring_dtag != NULL) { 2138 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2139 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2140 st->stats_ring_dmap); 2141 bus_dma_tag_destroy(st->stats_ring_dtag); 2142 } 2143 2144 if (st->stats_dtag != NULL) { 2145 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2146 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2147 bus_dma_tag_destroy(st->stats_dtag); 2148 } 2149 2150 free(st, M_DEVBUF); 2151} 2152 2153static void 2154bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2155{ 2156 KASSERT(nseg == 1, ("too many segments\n")); 2157 *((bus_addr_t *)arg) = seg->ds_addr; 2158} 2159 2160static int 2161bwi_dma_mbuf_create(struct bwi_softc *sc) 2162{ 2163 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2164 int i, j, k, ntx, error; 2165 2166 /* 2167 * Create TX/RX mbuf DMA tag 2168 */ 2169 error = bus_dma_tag_create(sc->sc_parent_dtag, 2170 1, 2171 0, 2172 BUS_SPACE_MAXADDR, 2173 BUS_SPACE_MAXADDR, 2174 NULL, NULL, 2175 MCLBYTES, 2176 1, 2177 MCLBYTES, 2178 BUS_DMA_ALLOCNOW, 2179 NULL, NULL, 2180 &sc->sc_buf_dtag); 2181 if (error) { 2182 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2183 return error; 2184 } 2185 2186 ntx = 0; 2187 2188 /* 2189 * Create TX mbuf DMA map 2190 */ 2191 for (i = 0; i < BWI_TX_NRING; ++i) { 2192 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2193 2194 for (j = 0; j < BWI_TX_NDESC; ++j) { 2195 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2196 &tbd->tbd_buf[j].tb_dmap); 2197 if (error) { 2198 device_printf(sc->sc_dev, "can't create " 2199 "%dth tbd, %dth DMA map\n", i, j); 2200 2201 ntx = i; 2202 for (k = 0; k < j; ++k) { 2203 bus_dmamap_destroy(sc->sc_buf_dtag, 2204 tbd->tbd_buf[k].tb_dmap); 2205 } 2206 goto fail; 2207 } 2208 } 2209 } 2210 ntx = BWI_TX_NRING; 2211 2212 /* 2213 * Create RX mbuf DMA map and a spare DMA map 2214 */ 2215 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2216 &rbd->rbd_tmp_dmap); 2217 if (error) { 2218 device_printf(sc->sc_dev, 2219 "can't create spare RX buf DMA map\n"); 2220 goto fail; 2221 } 2222 2223 for (j = 0; j < BWI_RX_NDESC; ++j) { 2224 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2225 &rbd->rbd_buf[j].rb_dmap); 2226 if (error) { 2227 device_printf(sc->sc_dev, "can't create %dth " 2228 "RX buf DMA map\n", j); 2229 2230 for (k = 0; k < j; ++k) { 2231 bus_dmamap_destroy(sc->sc_buf_dtag, 2232 rbd->rbd_buf[j].rb_dmap); 2233 } 2234 bus_dmamap_destroy(sc->sc_buf_dtag, 2235 rbd->rbd_tmp_dmap); 2236 goto fail; 2237 } 2238 } 2239 2240 return 0; 2241fail: 2242 bwi_dma_mbuf_destroy(sc, ntx, 0); 2243 return error; 2244} 2245 2246static void 2247bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2248{ 2249 int i, j; 2250 2251 if (sc->sc_buf_dtag == NULL) 2252 return; 2253 2254 for (i = 0; i < ntx; ++i) { 2255 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2256 2257 for (j = 0; j < BWI_TX_NDESC; ++j) { 2258 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2259 2260 if (tb->tb_mbuf != NULL) { 2261 bus_dmamap_unload(sc->sc_buf_dtag, 2262 tb->tb_dmap); 2263 m_freem(tb->tb_mbuf); 2264 } 2265 if (tb->tb_ni != NULL) 2266 ieee80211_free_node(tb->tb_ni); 2267 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2268 } 2269 } 2270 2271 if (nrx) { 2272 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2273 2274 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2275 for (j = 0; j < BWI_RX_NDESC; ++j) { 2276 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2277 2278 if (rb->rb_mbuf != NULL) { 2279 bus_dmamap_unload(sc->sc_buf_dtag, 2280 rb->rb_dmap); 2281 m_freem(rb->rb_mbuf); 2282 } 2283 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2284 } 2285 } 2286 2287 bus_dma_tag_destroy(sc->sc_buf_dtag); 2288 sc->sc_buf_dtag = NULL; 2289} 2290 2291static void 2292bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2293{ 2294 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2295} 2296 2297static void 2298bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2299{ 2300 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2301} 2302 2303static int 2304bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2305{ 2306 struct bwi_ring_data *rd; 2307 struct bwi_txbuf_data *tbd; 2308 uint32_t val, addr_hi, addr_lo; 2309 2310 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2311 rd = &sc->sc_tx_rdata[ring_idx]; 2312 tbd = &sc->sc_tx_bdata[ring_idx]; 2313 2314 tbd->tbd_idx = 0; 2315 tbd->tbd_used = 0; 2316 2317 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2318 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2319 BUS_DMASYNC_PREWRITE); 2320 2321 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2322 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2323 2324 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2325 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2326 BWI_TXRX32_RINGINFO_FUNC_MASK); 2327 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2328 2329 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2330 BWI_TXRX32_CTRL_ENABLE; 2331 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2332 2333 return 0; 2334} 2335 2336static void 2337bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2338 bus_addr_t paddr, int hdr_size, int ndesc) 2339{ 2340 uint32_t val, addr_hi, addr_lo; 2341 2342 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2343 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2344 2345 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2346 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2347 BWI_TXRX32_RINGINFO_FUNC_MASK); 2348 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2349 2350 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2351 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2352 BWI_TXRX32_CTRL_ENABLE; 2353 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2354 2355 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2356 (ndesc - 1) * sizeof(struct bwi_desc32)); 2357} 2358 2359static int 2360bwi_init_rx_ring32(struct bwi_softc *sc) 2361{ 2362 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2363 int i, error; 2364 2365 sc->sc_rx_bdata.rbd_idx = 0; 2366 2367 for (i = 0; i < BWI_RX_NDESC; ++i) { 2368 error = bwi_newbuf(sc, i, 1); 2369 if (error) { 2370 device_printf(sc->sc_dev, 2371 "can't allocate %dth RX buffer\n", i); 2372 return error; 2373 } 2374 } 2375 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2376 BUS_DMASYNC_PREWRITE); 2377 2378 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2379 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2380 return 0; 2381} 2382 2383static int 2384bwi_init_txstats32(struct bwi_softc *sc) 2385{ 2386 struct bwi_txstats_data *st = sc->sc_txstats; 2387 bus_addr_t stats_paddr; 2388 int i; 2389 2390 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2391 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2392 2393 st->stats_idx = 0; 2394 2395 stats_paddr = st->stats_paddr; 2396 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2397 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2398 stats_paddr, sizeof(struct bwi_txstats), 0); 2399 stats_paddr += sizeof(struct bwi_txstats); 2400 } 2401 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2402 BUS_DMASYNC_PREWRITE); 2403 2404 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2405 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2406 return 0; 2407} 2408 2409static void 2410bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2411 int buf_len) 2412{ 2413 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2414 2415 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2416 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2417 paddr, buf_len, 0); 2418} 2419 2420static void 2421bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2422 int buf_idx, bus_addr_t paddr, int buf_len) 2423{ 2424 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2425 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2426 paddr, buf_len, 1); 2427} 2428 2429static int 2430bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2431{ 2432 /* TODO:64 */ 2433 return EOPNOTSUPP; 2434} 2435 2436static int 2437bwi_init_rx_ring64(struct bwi_softc *sc) 2438{ 2439 /* TODO:64 */ 2440 return EOPNOTSUPP; 2441} 2442 2443static int 2444bwi_init_txstats64(struct bwi_softc *sc) 2445{ 2446 /* TODO:64 */ 2447 return EOPNOTSUPP; 2448} 2449 2450static void 2451bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2452 int buf_len) 2453{ 2454 /* TODO:64 */ 2455} 2456 2457static void 2458bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2459 int buf_idx, bus_addr_t paddr, int buf_len) 2460{ 2461 /* TODO:64 */ 2462} 2463 2464static void 2465bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2466 bus_size_t mapsz __unused, int error) 2467{ 2468 if (!error) { 2469 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2470 *((bus_addr_t *)arg) = seg->ds_addr; 2471 } 2472} 2473 2474static int 2475bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2476{ 2477 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2478 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2479 struct bwi_rxbuf_hdr *hdr; 2480 bus_dmamap_t map; 2481 bus_addr_t paddr; 2482 struct mbuf *m; 2483 int error; 2484 2485 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2486 2487 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2488 if (m == NULL) { 2489 error = ENOBUFS; 2490 2491 /* 2492 * If the NIC is up and running, we need to: 2493 * - Clear RX buffer's header. 2494 * - Restore RX descriptor settings. 2495 */ 2496 if (init) 2497 return error; 2498 else 2499 goto back; 2500 } 2501 m->m_len = m->m_pkthdr.len = MCLBYTES; 2502 2503 /* 2504 * Try to load RX buf into temporary DMA map 2505 */ 2506 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2507 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2508 if (error) { 2509 m_freem(m); 2510 2511 /* 2512 * See the comment above 2513 */ 2514 if (init) 2515 return error; 2516 else 2517 goto back; 2518 } 2519 2520 if (!init) 2521 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2522 rxbuf->rb_mbuf = m; 2523 rxbuf->rb_paddr = paddr; 2524 2525 /* 2526 * Swap RX buf's DMA map with the loaded temporary one 2527 */ 2528 map = rxbuf->rb_dmap; 2529 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2530 rbd->rbd_tmp_dmap = map; 2531 2532back: 2533 /* 2534 * Clear RX buf header 2535 */ 2536 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2537 bzero(hdr, sizeof(*hdr)); 2538 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2539 2540 /* 2541 * Setup RX buf descriptor 2542 */ 2543 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2544 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2545 return error; 2546} 2547 2548static void 2549bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2550 const uint8_t *addr) 2551{ 2552 int i; 2553 2554 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2555 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2556 2557 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2558 uint16_t addr_val; 2559 2560 addr_val = (uint16_t)addr[i * 2] | 2561 (((uint16_t)addr[(i * 2) + 1]) << 8); 2562 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2563 } 2564} 2565 2566static int 2567bwi_rxeof(struct bwi_softc *sc, int end_idx) 2568{ 2569 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2570 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2571 struct ieee80211com *ic = &sc->sc_ic; 2572 int idx, rx_data = 0; 2573 2574 idx = rbd->rbd_idx; 2575 while (idx != end_idx) { 2576 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2577 struct bwi_rxbuf_hdr *hdr; 2578 struct ieee80211_frame_min *wh; 2579 struct ieee80211_node *ni; 2580 struct mbuf *m; 2581 uint32_t plcp; 2582 uint16_t flags2; 2583 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2584 2585 m = rb->rb_mbuf; 2586 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2587 BUS_DMASYNC_POSTREAD); 2588 2589 if (bwi_newbuf(sc, idx, 0)) { 2590 counter_u64_add(ic->ic_ierrors, 1); 2591 goto next; 2592 } 2593 2594 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2595 flags2 = le16toh(hdr->rxh_flags2); 2596 2597 hdr_extra = 0; 2598 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2599 hdr_extra = 2; 2600 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2601 2602 buflen = le16toh(hdr->rxh_buflen); 2603 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2604 device_printf(sc->sc_dev, 2605 "%s: zero length data, hdr_extra %d\n", 2606 __func__, hdr_extra); 2607 counter_u64_add(ic->ic_ierrors, 1); 2608 m_freem(m); 2609 goto next; 2610 } 2611 2612 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2613 rssi = bwi_calc_rssi(sc, hdr); 2614 noise = bwi_calc_noise(sc); 2615 2616 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2617 m_adj(m, sizeof(*hdr) + wh_ofs); 2618 2619 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2620 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2621 else 2622 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2623 2624 /* RX radio tap */ 2625 if (ieee80211_radiotap_active(ic)) 2626 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2627 2628 m_adj(m, -IEEE80211_CRC_LEN); 2629 2630 BWI_UNLOCK(sc); 2631 2632 wh = mtod(m, struct ieee80211_frame_min *); 2633 ni = ieee80211_find_rxnode(ic, wh); 2634 if (ni != NULL) { 2635 type = ieee80211_input(ni, m, rssi - noise, noise); 2636 ieee80211_free_node(ni); 2637 } else 2638 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2639 if (type == IEEE80211_FC0_TYPE_DATA) { 2640 rx_data = 1; 2641 sc->sc_rx_rate = rate; 2642 } 2643 2644 BWI_LOCK(sc); 2645next: 2646 idx = (idx + 1) % BWI_RX_NDESC; 2647 2648 if (sc->sc_flags & BWI_F_STOP) { 2649 /* 2650 * Take the fast lane, don't do 2651 * any damage to softc 2652 */ 2653 return -1; 2654 } 2655 } 2656 2657 rbd->rbd_idx = idx; 2658 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2659 BUS_DMASYNC_PREWRITE); 2660 2661 return rx_data; 2662} 2663 2664static int 2665bwi_rxeof32(struct bwi_softc *sc) 2666{ 2667 uint32_t val, rx_ctrl; 2668 int end_idx, rx_data; 2669 2670 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2671 2672 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2673 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2674 sizeof(struct bwi_desc32); 2675 2676 rx_data = bwi_rxeof(sc, end_idx); 2677 if (rx_data >= 0) { 2678 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2679 end_idx * sizeof(struct bwi_desc32)); 2680 } 2681 return rx_data; 2682} 2683 2684static int 2685bwi_rxeof64(struct bwi_softc *sc) 2686{ 2687 /* TODO:64 */ 2688 return 0; 2689} 2690 2691static void 2692bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2693{ 2694 int i; 2695 2696 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2697 2698#define NRETRY 10 2699 2700 for (i = 0; i < NRETRY; ++i) { 2701 uint32_t status; 2702 2703 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2704 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2705 BWI_RX32_STATUS_STATE_DISABLED) 2706 break; 2707 2708 DELAY(1000); 2709 } 2710 if (i == NRETRY) 2711 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2712 2713#undef NRETRY 2714 2715 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2716} 2717 2718static void 2719bwi_free_txstats32(struct bwi_softc *sc) 2720{ 2721 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2722} 2723 2724static void 2725bwi_free_rx_ring32(struct bwi_softc *sc) 2726{ 2727 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2728 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2729 int i; 2730 2731 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2732 2733 for (i = 0; i < BWI_RX_NDESC; ++i) { 2734 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2735 2736 if (rb->rb_mbuf != NULL) { 2737 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2738 m_freem(rb->rb_mbuf); 2739 rb->rb_mbuf = NULL; 2740 } 2741 } 2742} 2743 2744static void 2745bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2746{ 2747 struct bwi_ring_data *rd; 2748 struct bwi_txbuf_data *tbd; 2749 uint32_t state, val; 2750 int i; 2751 2752 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2753 rd = &sc->sc_tx_rdata[ring_idx]; 2754 tbd = &sc->sc_tx_bdata[ring_idx]; 2755 2756#define NRETRY 10 2757 2758 for (i = 0; i < NRETRY; ++i) { 2759 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2760 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2761 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2762 state == BWI_TX32_STATUS_STATE_IDLE || 2763 state == BWI_TX32_STATUS_STATE_STOPPED) 2764 break; 2765 2766 DELAY(1000); 2767 } 2768 if (i == NRETRY) { 2769 device_printf(sc->sc_dev, 2770 "%s: wait for TX ring(%d) stable timed out\n", 2771 __func__, ring_idx); 2772 } 2773 2774 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2775 for (i = 0; i < NRETRY; ++i) { 2776 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2777 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2778 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2779 break; 2780 2781 DELAY(1000); 2782 } 2783 if (i == NRETRY) 2784 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2785 __func__, ring_idx); 2786 2787#undef NRETRY 2788 2789 DELAY(1000); 2790 2791 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2792 2793 for (i = 0; i < BWI_TX_NDESC; ++i) { 2794 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2795 2796 if (tb->tb_mbuf != NULL) { 2797 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2798 m_freem(tb->tb_mbuf); 2799 tb->tb_mbuf = NULL; 2800 } 2801 if (tb->tb_ni != NULL) { 2802 ieee80211_free_node(tb->tb_ni); 2803 tb->tb_ni = NULL; 2804 } 2805 } 2806} 2807 2808static void 2809bwi_free_txstats64(struct bwi_softc *sc) 2810{ 2811 /* TODO:64 */ 2812} 2813 2814static void 2815bwi_free_rx_ring64(struct bwi_softc *sc) 2816{ 2817 /* TODO:64 */ 2818} 2819 2820static void 2821bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2822{ 2823 /* TODO:64 */ 2824} 2825 2826/* XXX does not belong here */ 2827#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2828#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2829 2830static __inline void 2831bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2832{ 2833 uint32_t plcp; 2834 2835 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2836 IEEE80211_OFDM_PLCP_RATE_MASK) | 2837 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2838 *plcp0 = htole32(plcp); 2839} 2840 2841static __inline void 2842bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2843 uint8_t rate) 2844{ 2845 int len, service, pkt_bitlen; 2846 2847 pkt_bitlen = pkt_len * NBBY; 2848 len = howmany(pkt_bitlen * 2, rate); 2849 2850 service = IEEE80211_PLCP_SERVICE_LOCKED; 2851 if (rate == (11 * 2)) { 2852 int pkt_bitlen1; 2853 2854 /* 2855 * PLCP service field needs to be adjusted, 2856 * if TX rate is 11Mbytes/s 2857 */ 2858 pkt_bitlen1 = len * 11; 2859 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2860 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2861 } 2862 2863 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2864 plcp->i_service = service; 2865 plcp->i_length = htole16(len); 2866 /* NOTE: do NOT touch i_crc */ 2867} 2868 2869static __inline void 2870bwi_plcp_header(const struct ieee80211_rate_table *rt, 2871 void *plcp, int pkt_len, uint8_t rate) 2872{ 2873 enum ieee80211_phytype modtype; 2874 2875 /* 2876 * Assume caller has zeroed 'plcp' 2877 */ 2878 modtype = ieee80211_rate2phytype(rt, rate); 2879 if (modtype == IEEE80211_T_OFDM) 2880 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2881 else if (modtype == IEEE80211_T_DS) 2882 bwi_ds_plcp_header(plcp, pkt_len, rate); 2883 else 2884 panic("unsupport modulation type %u\n", modtype); 2885} 2886 2887static int 2888bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2889 struct ieee80211_node *ni) 2890{ 2891 struct ieee80211vap *vap = ni->ni_vap; 2892 struct ieee80211com *ic = &sc->sc_ic; 2893 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2894 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2895 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2896 struct bwi_mac *mac; 2897 struct bwi_txbuf_hdr *hdr; 2898 struct ieee80211_frame *wh; 2899 const struct ieee80211_txparam *tp; 2900 uint8_t rate, rate_fb; 2901 uint32_t mac_ctrl; 2902 uint16_t phy_ctrl; 2903 bus_addr_t paddr; 2904 int type, ismcast, pkt_len, error, rix; 2905#if 0 2906 const uint8_t *p; 2907 int i; 2908#endif 2909 2910 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2911 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2912 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2913 2914 wh = mtod(m, struct ieee80211_frame *); 2915 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2916 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2917 2918 /* Get 802.11 frame len before prepending TX header */ 2919 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2920 2921 /* 2922 * Find TX rate 2923 */ 2924 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2925 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2926 rate = rate_fb = tp->mgmtrate; 2927 } else if (ismcast) { 2928 rate = rate_fb = tp->mcastrate; 2929 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2930 rate = rate_fb = tp->ucastrate; 2931 } else { 2932 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2933 rate = ni->ni_txrate; 2934 2935 if (rix > 0) { 2936 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2937 IEEE80211_RATE_VAL; 2938 } else { 2939 rate_fb = rate; 2940 } 2941 } 2942 tb->tb_rate[0] = rate; 2943 tb->tb_rate[1] = rate_fb; 2944 sc->sc_tx_rate = rate; 2945 2946 /* 2947 * TX radio tap 2948 */ 2949 if (ieee80211_radiotap_active_vap(vap)) { 2950 sc->sc_tx_th.wt_flags = 0; 2951 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2952 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2953 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2954 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2955 rate != (1 * 2)) { 2956 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2957 } 2958 sc->sc_tx_th.wt_rate = rate; 2959 2960 ieee80211_radiotap_tx(vap, m); 2961 } 2962 2963 /* 2964 * Setup the embedded TX header 2965 */ 2966 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2967 if (m == NULL) { 2968 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2969 __func__); 2970 return ENOBUFS; 2971 } 2972 hdr = mtod(m, struct bwi_txbuf_hdr *); 2973 2974 bzero(hdr, sizeof(*hdr)); 2975 2976 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 2977 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 2978 2979 if (!ismcast) { 2980 uint16_t dur; 2981 2982 dur = ieee80211_ack_duration(sc->sc_rates, rate, 2983 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 2984 2985 hdr->txh_fb_duration = htole16(dur); 2986 } 2987 2988 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 2989 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 2990 2991 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 2992 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 2993 2994 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 2995 BWI_TXH_PHY_C_ANTMODE_MASK); 2996 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 2997 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 2998 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 2999 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3000 3001 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3002 if (!ismcast) 3003 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3004 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3005 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3006 3007 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3008 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3009 3010 /* Catch any further usage */ 3011 hdr = NULL; 3012 wh = NULL; 3013 3014 /* DMA load */ 3015 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3016 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3017 if (error && error != EFBIG) { 3018 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3019 __func__, error); 3020 goto back; 3021 } 3022 3023 if (error) { /* error == EFBIG */ 3024 struct mbuf *m_new; 3025 3026 m_new = m_defrag(m, M_NOWAIT); 3027 if (m_new == NULL) { 3028 device_printf(sc->sc_dev, 3029 "%s: can't defrag TX buffer\n", __func__); 3030 error = ENOBUFS; 3031 goto back; 3032 } else { 3033 m = m_new; 3034 } 3035 3036 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3037 bwi_dma_buf_addr, &paddr, 3038 BUS_DMA_NOWAIT); 3039 if (error) { 3040 device_printf(sc->sc_dev, 3041 "%s: can't load TX buffer (2) %d\n", 3042 __func__, error); 3043 goto back; 3044 } 3045 } 3046 error = 0; 3047 3048 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3049 3050 tb->tb_mbuf = m; 3051 tb->tb_ni = ni; 3052 3053#if 0 3054 p = mtod(m, const uint8_t *); 3055 for (i = 0; i < m->m_pkthdr.len; ++i) { 3056 if (i != 0 && i % 8 == 0) 3057 printf("\n"); 3058 printf("%02x ", p[i]); 3059 } 3060 printf("\n"); 3061#endif 3062 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3063 idx, pkt_len, m->m_pkthdr.len); 3064 3065 /* Setup TX descriptor */ 3066 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3067 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3068 BUS_DMASYNC_PREWRITE); 3069 3070 /* Kick start */ 3071 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3072 3073back: 3074 if (error) 3075 m_freem(m); 3076 return error; 3077} 3078 3079static int 3080bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3081 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3082{ 3083 struct ieee80211vap *vap = ni->ni_vap; 3084 struct ieee80211com *ic = ni->ni_ic; 3085 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3086 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3087 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3088 struct bwi_mac *mac; 3089 struct bwi_txbuf_hdr *hdr; 3090 struct ieee80211_frame *wh; 3091 uint8_t rate, rate_fb; 3092 uint32_t mac_ctrl; 3093 uint16_t phy_ctrl; 3094 bus_addr_t paddr; 3095 int ismcast, pkt_len, error; 3096 3097 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3098 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3099 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3100 3101 wh = mtod(m, struct ieee80211_frame *); 3102 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3103 3104 /* Get 802.11 frame len before prepending TX header */ 3105 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3106 3107 /* 3108 * Find TX rate 3109 */ 3110 rate = params->ibp_rate0; 3111 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3112 /* XXX fall back to mcast/mgmt rate? */ 3113 m_freem(m); 3114 return EINVAL; 3115 } 3116 if (params->ibp_try1 != 0) { 3117 rate_fb = params->ibp_rate1; 3118 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3119 /* XXX fall back to rate0? */ 3120 m_freem(m); 3121 return EINVAL; 3122 } 3123 } else 3124 rate_fb = rate; 3125 tb->tb_rate[0] = rate; 3126 tb->tb_rate[1] = rate_fb; 3127 sc->sc_tx_rate = rate; 3128 3129 /* 3130 * TX radio tap 3131 */ 3132 if (ieee80211_radiotap_active_vap(vap)) { 3133 sc->sc_tx_th.wt_flags = 0; 3134 /* XXX IEEE80211_BPF_CRYPTO */ 3135 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3136 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3137 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3138 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3139 sc->sc_tx_th.wt_rate = rate; 3140 3141 ieee80211_radiotap_tx(vap, m); 3142 } 3143 3144 /* 3145 * Setup the embedded TX header 3146 */ 3147 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3148 if (m == NULL) { 3149 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3150 __func__); 3151 return ENOBUFS; 3152 } 3153 hdr = mtod(m, struct bwi_txbuf_hdr *); 3154 3155 bzero(hdr, sizeof(*hdr)); 3156 3157 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3158 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3159 3160 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3161 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3162 uint16_t dur; 3163 3164 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3165 3166 hdr->txh_fb_duration = htole16(dur); 3167 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3168 } 3169 3170 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3171 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3172 3173 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3174 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3175 3176 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3177 BWI_TXH_PHY_C_ANTMODE_MASK); 3178 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3179 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3180 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3181 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3182 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3183 3184 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3185 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3186 3187 /* Catch any further usage */ 3188 hdr = NULL; 3189 wh = NULL; 3190 3191 /* DMA load */ 3192 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3193 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3194 if (error != 0) { 3195 struct mbuf *m_new; 3196 3197 if (error != EFBIG) { 3198 device_printf(sc->sc_dev, 3199 "%s: can't load TX buffer (1) %d\n", 3200 __func__, error); 3201 goto back; 3202 } 3203 m_new = m_defrag(m, M_NOWAIT); 3204 if (m_new == NULL) { 3205 device_printf(sc->sc_dev, 3206 "%s: can't defrag TX buffer\n", __func__); 3207 error = ENOBUFS; 3208 goto back; 3209 } 3210 m = m_new; 3211 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3212 bwi_dma_buf_addr, &paddr, 3213 BUS_DMA_NOWAIT); 3214 if (error) { 3215 device_printf(sc->sc_dev, 3216 "%s: can't load TX buffer (2) %d\n", 3217 __func__, error); 3218 goto back; 3219 } 3220 } 3221 3222 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3223 3224 tb->tb_mbuf = m; 3225 tb->tb_ni = ni; 3226 3227 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3228 idx, pkt_len, m->m_pkthdr.len); 3229 3230 /* Setup TX descriptor */ 3231 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3232 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3233 BUS_DMASYNC_PREWRITE); 3234 3235 /* Kick start */ 3236 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3237back: 3238 if (error) 3239 m_freem(m); 3240 return error; 3241} 3242 3243static void 3244bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3245{ 3246 idx = (idx + 1) % BWI_TX_NDESC; 3247 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3248 idx * sizeof(struct bwi_desc32)); 3249} 3250 3251static void 3252bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3253{ 3254 /* TODO:64 */ 3255} 3256 3257static void 3258bwi_txeof_status32(struct bwi_softc *sc) 3259{ 3260 uint32_t val, ctrl_base; 3261 int end_idx; 3262 3263 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3264 3265 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3266 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3267 sizeof(struct bwi_desc32); 3268 3269 bwi_txeof_status(sc, end_idx); 3270 3271 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3272 end_idx * sizeof(struct bwi_desc32)); 3273 3274 bwi_start_locked(sc); 3275} 3276 3277static void 3278bwi_txeof_status64(struct bwi_softc *sc) 3279{ 3280 /* TODO:64 */ 3281} 3282 3283static void 3284_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3285{ 3286 struct bwi_txbuf_data *tbd; 3287 struct bwi_txbuf *tb; 3288 int ring_idx, buf_idx; 3289 struct ieee80211_node *ni; 3290 struct ieee80211vap *vap; 3291 3292 if (tx_id == 0) { 3293 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3294 return; 3295 } 3296 3297 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3298 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3299 3300 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3301 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3302 3303 tbd = &sc->sc_tx_bdata[ring_idx]; 3304 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3305 tbd->tbd_used--; 3306 3307 tb = &tbd->tbd_buf[buf_idx]; 3308 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3309 "acked %d, data_txcnt %d, ni %p\n", 3310 buf_idx, acked, data_txcnt, tb->tb_ni); 3311 3312 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3313 3314 if ((ni = tb->tb_ni) != NULL) { 3315 const struct bwi_txbuf_hdr *hdr = 3316 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3317 vap = ni->ni_vap; 3318 3319 /* NB: update rate control only for unicast frames */ 3320 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3321 /* 3322 * Feed back 'acked and data_txcnt'. Note that the 3323 * generic AMRR code only understands one tx rate 3324 * and the estimator doesn't handle real retry counts 3325 * well so to avoid over-aggressive downshifting we 3326 * treat any number of retries as "1". 3327 */ 3328 ieee80211_ratectl_tx_complete(vap, ni, 3329 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3330 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3331 } 3332 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3333 tb->tb_ni = NULL; 3334 } else 3335 m_freem(tb->tb_mbuf); 3336 tb->tb_mbuf = NULL; 3337 3338 if (tbd->tbd_used == 0) 3339 sc->sc_tx_timer = 0; 3340} 3341 3342static void 3343bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3344{ 3345 struct bwi_txstats_data *st = sc->sc_txstats; 3346 int idx; 3347 3348 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3349 3350 idx = st->stats_idx; 3351 while (idx != end_idx) { 3352 const struct bwi_txstats *stats = &st->stats[idx]; 3353 3354 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3355 int data_txcnt; 3356 3357 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3358 BWI_TXS_TXCNT_DATA); 3359 _bwi_txeof(sc, le16toh(stats->txs_id), 3360 stats->txs_flags & BWI_TXS_F_ACKED, 3361 data_txcnt); 3362 } 3363 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3364 } 3365 st->stats_idx = idx; 3366} 3367 3368static void 3369bwi_txeof(struct bwi_softc *sc) 3370{ 3371 3372 for (;;) { 3373 uint32_t tx_status0, tx_status1; 3374 uint16_t tx_id; 3375 int data_txcnt; 3376 3377 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3378 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3379 break; 3380 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3381 3382 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3383 data_txcnt = __SHIFTOUT(tx_status0, 3384 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3385 3386 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3387 continue; 3388 3389 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3390 data_txcnt); 3391 } 3392 3393 bwi_start_locked(sc); 3394} 3395 3396static int 3397bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3398{ 3399 bwi_power_on(sc, 1); 3400 return bwi_set_clock_mode(sc, clk_mode); 3401} 3402 3403static void 3404bwi_bbp_power_off(struct bwi_softc *sc) 3405{ 3406 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3407 bwi_power_off(sc, 1); 3408} 3409 3410static int 3411bwi_get_pwron_delay(struct bwi_softc *sc) 3412{ 3413 struct bwi_regwin *com, *old; 3414 struct bwi_clock_freq freq; 3415 uint32_t val; 3416 int error; 3417 3418 com = &sc->sc_com_regwin; 3419 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3420 3421 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3422 return 0; 3423 3424 error = bwi_regwin_switch(sc, com, &old); 3425 if (error) 3426 return error; 3427 3428 bwi_get_clock_freq(sc, &freq); 3429 3430 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3431 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3432 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3433 3434 return bwi_regwin_switch(sc, old, NULL); 3435} 3436 3437static int 3438bwi_bus_attach(struct bwi_softc *sc) 3439{ 3440 struct bwi_regwin *bus, *old; 3441 int error; 3442 3443 bus = &sc->sc_bus_regwin; 3444 3445 error = bwi_regwin_switch(sc, bus, &old); 3446 if (error) 3447 return error; 3448 3449 if (!bwi_regwin_is_enabled(sc, bus)) 3450 bwi_regwin_enable(sc, bus, 0); 3451 3452 /* Disable interripts */ 3453 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3454 3455 return bwi_regwin_switch(sc, old, NULL); 3456} 3457 3458static const char * 3459bwi_regwin_name(const struct bwi_regwin *rw) 3460{ 3461 switch (rw->rw_type) { 3462 case BWI_REGWIN_T_COM: 3463 return "COM"; 3464 case BWI_REGWIN_T_BUSPCI: 3465 return "PCI"; 3466 case BWI_REGWIN_T_MAC: 3467 return "MAC"; 3468 case BWI_REGWIN_T_BUSPCIE: 3469 return "PCIE"; 3470 } 3471 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3472 return NULL; 3473} 3474 3475static uint32_t 3476bwi_regwin_disable_bits(struct bwi_softc *sc) 3477{ 3478 uint32_t busrev; 3479 3480 /* XXX cache this */ 3481 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3482 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3483 "bus rev %u\n", busrev); 3484 3485 if (busrev == BWI_BUSREV_0) 3486 return BWI_STATE_LO_DISABLE1; 3487 else if (busrev == BWI_BUSREV_1) 3488 return BWI_STATE_LO_DISABLE2; 3489 else 3490 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3491} 3492 3493int 3494bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3495{ 3496 uint32_t val, disable_bits; 3497 3498 disable_bits = bwi_regwin_disable_bits(sc); 3499 val = CSR_READ_4(sc, BWI_STATE_LO); 3500 3501 if ((val & (BWI_STATE_LO_CLOCK | 3502 BWI_STATE_LO_RESET | 3503 disable_bits)) == BWI_STATE_LO_CLOCK) { 3504 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3505 bwi_regwin_name(rw)); 3506 return 1; 3507 } else { 3508 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3509 bwi_regwin_name(rw)); 3510 return 0; 3511 } 3512} 3513 3514void 3515bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3516{ 3517 uint32_t state_lo, disable_bits; 3518 int i; 3519 3520 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3521 3522 /* 3523 * If current regwin is in 'reset' state, it was already disabled. 3524 */ 3525 if (state_lo & BWI_STATE_LO_RESET) { 3526 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3527 "%s was already disabled\n", bwi_regwin_name(rw)); 3528 return; 3529 } 3530 3531 disable_bits = bwi_regwin_disable_bits(sc); 3532 3533 /* 3534 * Disable normal clock 3535 */ 3536 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3537 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3538 3539 /* 3540 * Wait until normal clock is disabled 3541 */ 3542#define NRETRY 1000 3543 for (i = 0; i < NRETRY; ++i) { 3544 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3545 if (state_lo & disable_bits) 3546 break; 3547 DELAY(10); 3548 } 3549 if (i == NRETRY) { 3550 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3551 bwi_regwin_name(rw)); 3552 } 3553 3554 for (i = 0; i < NRETRY; ++i) { 3555 uint32_t state_hi; 3556 3557 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3558 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3559 break; 3560 DELAY(10); 3561 } 3562 if (i == NRETRY) { 3563 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3564 bwi_regwin_name(rw)); 3565 } 3566#undef NRETRY 3567 3568 /* 3569 * Reset and disable regwin with gated clock 3570 */ 3571 state_lo = BWI_STATE_LO_RESET | disable_bits | 3572 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3573 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3574 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3575 3576 /* Flush pending bus write */ 3577 CSR_READ_4(sc, BWI_STATE_LO); 3578 DELAY(1); 3579 3580 /* Reset and disable regwin */ 3581 state_lo = BWI_STATE_LO_RESET | disable_bits | 3582 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3583 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3584 3585 /* Flush pending bus write */ 3586 CSR_READ_4(sc, BWI_STATE_LO); 3587 DELAY(1); 3588} 3589 3590void 3591bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3592{ 3593 uint32_t state_lo, state_hi, imstate; 3594 3595 bwi_regwin_disable(sc, rw, flags); 3596 3597 /* Reset regwin with gated clock */ 3598 state_lo = BWI_STATE_LO_RESET | 3599 BWI_STATE_LO_CLOCK | 3600 BWI_STATE_LO_GATED_CLOCK | 3601 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3602 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3603 3604 /* Flush pending bus write */ 3605 CSR_READ_4(sc, BWI_STATE_LO); 3606 DELAY(1); 3607 3608 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3609 if (state_hi & BWI_STATE_HI_SERROR) 3610 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3611 3612 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3613 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3614 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3615 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3616 } 3617 3618 /* Enable regwin with gated clock */ 3619 state_lo = BWI_STATE_LO_CLOCK | 3620 BWI_STATE_LO_GATED_CLOCK | 3621 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3622 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3623 3624 /* Flush pending bus write */ 3625 CSR_READ_4(sc, BWI_STATE_LO); 3626 DELAY(1); 3627 3628 /* Enable regwin with normal clock */ 3629 state_lo = BWI_STATE_LO_CLOCK | 3630 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3631 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3632 3633 /* Flush pending bus write */ 3634 CSR_READ_4(sc, BWI_STATE_LO); 3635 DELAY(1); 3636} 3637 3638static void 3639bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3640{ 3641 struct bwi_mac *mac; 3642 struct bwi_myaddr_bssid buf; 3643 const uint8_t *p; 3644 uint32_t val; 3645 int n, i; 3646 3647 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3648 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3649 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3650 3651 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3652 3653 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3654 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3655 3656 n = sizeof(buf) / sizeof(val); 3657 p = (const uint8_t *)&buf; 3658 for (i = 0; i < n; ++i) { 3659 int j; 3660 3661 val = 0; 3662 for (j = 0; j < sizeof(val); ++j) 3663 val |= ((uint32_t)(*p++)) << (j * 8); 3664 3665 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3666 } 3667} 3668 3669static void 3670bwi_updateslot(struct ieee80211com *ic) 3671{ 3672 struct bwi_softc *sc = ic->ic_softc; 3673 struct bwi_mac *mac; 3674 3675 BWI_LOCK(sc); 3676 if (sc->sc_flags & BWI_F_RUNNING) { 3677 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3678 3679 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3680 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3681 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3682 3683 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3684 } 3685 BWI_UNLOCK(sc); 3686} 3687 3688static void 3689bwi_calibrate(void *xsc) 3690{ 3691 struct bwi_softc *sc = xsc; 3692 struct bwi_mac *mac; 3693 3694 BWI_ASSERT_LOCKED(sc); 3695 3696 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3697 ("opmode %d", sc->sc_ic.ic_opmode)); 3698 3699 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3700 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3701 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3702 3703 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3704 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3705 3706 /* XXX 15 seconds */ 3707 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3708} 3709 3710static int 3711bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3712{ 3713 struct bwi_mac *mac; 3714 3715 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3716 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3717 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3718 3719 return bwi_rf_calc_rssi(mac, hdr); 3720} 3721 3722static int 3723bwi_calc_noise(struct bwi_softc *sc) 3724{ 3725 struct bwi_mac *mac; 3726 3727 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3728 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3729 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3730 3731 return bwi_rf_calc_noise(mac); 3732} 3733 3734static __inline uint8_t 3735bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3736{ 3737 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3738 return (ieee80211_plcp2rate(plcp, type)); 3739} 3740 3741static void 3742bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3743 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3744{ 3745 const struct ieee80211_frame_min *wh; 3746 3747 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3748 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3749 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3750 3751 wh = mtod(m, const struct ieee80211_frame_min *); 3752 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3753 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3754 3755 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3756 sc->sc_rx_th.wr_rate = rate; 3757 sc->sc_rx_th.wr_antsignal = rssi; 3758 sc->sc_rx_th.wr_antnoise = noise; 3759} 3760 3761static void 3762bwi_led_attach(struct bwi_softc *sc) 3763{ 3764 const uint8_t *led_act = NULL; 3765 uint16_t gpio, val[BWI_LED_MAX]; 3766 int i; 3767 3768#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3769 3770 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3771 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3772 led_act = bwi_vendor_led_act[i].led_act; 3773 break; 3774 } 3775 } 3776 if (led_act == NULL) 3777 led_act = bwi_default_led_act; 3778 3779#undef N 3780 3781 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3782 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3783 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3784 3785 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3786 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3787 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3788 3789 for (i = 0; i < BWI_LED_MAX; ++i) { 3790 struct bwi_led *led = &sc->sc_leds[i]; 3791 3792 if (val[i] == 0xff) { 3793 led->l_act = led_act[i]; 3794 } else { 3795 if (val[i] & BWI_LED_ACT_LOW) 3796 led->l_flags |= BWI_LED_F_ACTLOW; 3797 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3798 } 3799 led->l_mask = (1 << i); 3800 3801 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3802 led->l_act == BWI_LED_ACT_BLINK_POLL || 3803 led->l_act == BWI_LED_ACT_BLINK) { 3804 led->l_flags |= BWI_LED_F_BLINK; 3805 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3806 led->l_flags |= BWI_LED_F_POLLABLE; 3807 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3808 led->l_flags |= BWI_LED_F_SLOW; 3809 3810 if (sc->sc_blink_led == NULL) { 3811 sc->sc_blink_led = led; 3812 if (led->l_flags & BWI_LED_F_SLOW) 3813 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3814 } 3815 } 3816 3817 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3818 "%dth led, act %d, lowact %d\n", i, 3819 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3820 } 3821 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3822} 3823 3824static __inline uint16_t 3825bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3826{ 3827 if (led->l_flags & BWI_LED_F_ACTLOW) 3828 on = !on; 3829 if (on) 3830 val |= led->l_mask; 3831 else 3832 val &= ~led->l_mask; 3833 return val; 3834} 3835 3836static void 3837bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3838{ 3839 struct ieee80211com *ic = &sc->sc_ic; 3840 uint16_t val; 3841 int i; 3842 3843 if (nstate == IEEE80211_S_INIT) { 3844 callout_stop(&sc->sc_led_blink_ch); 3845 sc->sc_led_blinking = 0; 3846 } 3847 3848 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3849 return; 3850 3851 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3852 for (i = 0; i < BWI_LED_MAX; ++i) { 3853 struct bwi_led *led = &sc->sc_leds[i]; 3854 int on; 3855 3856 if (led->l_act == BWI_LED_ACT_UNKN || 3857 led->l_act == BWI_LED_ACT_NULL) 3858 continue; 3859 3860 if ((led->l_flags & BWI_LED_F_BLINK) && 3861 nstate != IEEE80211_S_INIT) 3862 continue; 3863 3864 switch (led->l_act) { 3865 case BWI_LED_ACT_ON: /* Always on */ 3866 on = 1; 3867 break; 3868 case BWI_LED_ACT_OFF: /* Always off */ 3869 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3870 on = 0; 3871 break; 3872 default: 3873 on = 1; 3874 switch (nstate) { 3875 case IEEE80211_S_INIT: 3876 on = 0; 3877 break; 3878 case IEEE80211_S_RUN: 3879 if (led->l_act == BWI_LED_ACT_11G && 3880 ic->ic_curmode != IEEE80211_MODE_11G) 3881 on = 0; 3882 break; 3883 default: 3884 if (led->l_act == BWI_LED_ACT_ASSOC) 3885 on = 0; 3886 break; 3887 } 3888 break; 3889 } 3890 3891 val = bwi_led_onoff(led, val, on); 3892 } 3893 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3894} 3895static void 3896bwi_led_event(struct bwi_softc *sc, int event) 3897{ 3898 struct bwi_led *led = sc->sc_blink_led; 3899 int rate; 3900 3901 if (event == BWI_LED_EVENT_POLL) { 3902 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3903 return; 3904 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3905 return; 3906 } 3907 3908 sc->sc_led_ticks = ticks; 3909 if (sc->sc_led_blinking) 3910 return; 3911 3912 switch (event) { 3913 case BWI_LED_EVENT_RX: 3914 rate = sc->sc_rx_rate; 3915 break; 3916 case BWI_LED_EVENT_TX: 3917 rate = sc->sc_tx_rate; 3918 break; 3919 case BWI_LED_EVENT_POLL: 3920 rate = 0; 3921 break; 3922 default: 3923 panic("unknown LED event %d\n", event); 3924 break; 3925 } 3926 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3927 bwi_led_duration[rate].off_dur); 3928} 3929 3930static void 3931bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3932{ 3933 struct bwi_led *led = sc->sc_blink_led; 3934 uint16_t val; 3935 3936 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3937 val = bwi_led_onoff(led, val, 1); 3938 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3939 3940 if (led->l_flags & BWI_LED_F_SLOW) { 3941 BWI_LED_SLOWDOWN(on_dur); 3942 BWI_LED_SLOWDOWN(off_dur); 3943 } 3944 3945 sc->sc_led_blinking = 1; 3946 sc->sc_led_blink_offdur = off_dur; 3947 3948 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3949} 3950 3951static void 3952bwi_led_blink_next(void *xsc) 3953{ 3954 struct bwi_softc *sc = xsc; 3955 uint16_t val; 3956 3957 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3958 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3959 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3960 3961 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3962 bwi_led_blink_end, sc); 3963} 3964 3965static void 3966bwi_led_blink_end(void *xsc) 3967{ 3968 struct bwi_softc *sc = xsc; 3969 sc->sc_led_blinking = 0; 3970} 3971 3972static void 3973bwi_restart(void *xsc, int pending) 3974{ 3975 struct bwi_softc *sc = xsc; 3976 3977 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 3978 BWI_LOCK(sc); 3979 bwi_init_statechg(sc, 0); 3980#if 0 3981 bwi_start_locked(sc); 3982#endif 3983 BWI_UNLOCK(sc); 3984} 3985