if_bwi.c revision 283643
1/* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/bwi/if_bwi.c 283643 2015-05-28 08:00:11Z scottl $"); 39 40#include "opt_inet.h" 41#include "opt_bwi.h" 42#include "opt_wlan.h" 43 44#include <sys/param.h> 45#include <sys/endian.h> 46#include <sys/kernel.h> 47#include <sys/bus.h> 48#include <sys/malloc.h> 49#include <sys/proc.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54#include <sys/systm.h> 55#include <sys/taskqueue.h> 56 57#include <net/if.h> 58#include <net/if_var.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_arp.h> 63#include <net/ethernet.h> 64#include <net/if_llc.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_radiotap.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_phy.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <net/bpf.h> 73 74#ifdef INET 75#include <netinet/in.h> 76#include <netinet/if_ether.h> 77#endif 78 79#include <machine/bus.h> 80 81#include <dev/pci/pcivar.h> 82#include <dev/pci/pcireg.h> 83 84#include <dev/bwi/bitops.h> 85#include <dev/bwi/if_bwireg.h> 86#include <dev/bwi/if_bwivar.h> 87#include <dev/bwi/bwimac.h> 88#include <dev/bwi/bwirf.h> 89 90struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93}; 94 95struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98} __packed; 99 100static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104static void bwi_vap_delete(struct ieee80211vap *); 105static void bwi_init(void *); 106static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 107static void bwi_start(struct ifnet *); 108static void bwi_start_locked(struct ifnet *); 109static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111static void bwi_watchdog(void *); 112static void bwi_scan_start(struct ieee80211com *); 113static void bwi_set_channel(struct ieee80211com *); 114static void bwi_scan_end(struct ieee80211com *); 115static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 116static void bwi_updateslot(struct ieee80211com *); 117static int bwi_media_change(struct ifnet *); 118 119static void bwi_calibrate(void *); 120 121static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 122static int bwi_calc_noise(struct bwi_softc *); 123static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 124static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 125 struct bwi_rxbuf_hdr *, const void *, int, int, int); 126 127static void bwi_restart(void *, int); 128static void bwi_init_statechg(struct bwi_softc *, int); 129static void bwi_stop(struct bwi_softc *, int); 130static void bwi_stop_locked(struct bwi_softc *, int); 131static int bwi_newbuf(struct bwi_softc *, int, int); 132static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *); 134static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *, 136 const struct ieee80211_bpf_params *); 137 138static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 139 bus_addr_t, int, int); 140static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 141 142static int bwi_init_tx_ring32(struct bwi_softc *, int); 143static int bwi_init_rx_ring32(struct bwi_softc *); 144static int bwi_init_txstats32(struct bwi_softc *); 145static void bwi_free_tx_ring32(struct bwi_softc *, int); 146static void bwi_free_rx_ring32(struct bwi_softc *); 147static void bwi_free_txstats32(struct bwi_softc *); 148static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 149static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 150 int, bus_addr_t, int); 151static int bwi_rxeof32(struct bwi_softc *); 152static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 153static void bwi_txeof_status32(struct bwi_softc *); 154 155static int bwi_init_tx_ring64(struct bwi_softc *, int); 156static int bwi_init_rx_ring64(struct bwi_softc *); 157static int bwi_init_txstats64(struct bwi_softc *); 158static void bwi_free_tx_ring64(struct bwi_softc *, int); 159static void bwi_free_rx_ring64(struct bwi_softc *); 160static void bwi_free_txstats64(struct bwi_softc *); 161static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 162static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 163 int, bus_addr_t, int); 164static int bwi_rxeof64(struct bwi_softc *); 165static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 166static void bwi_txeof_status64(struct bwi_softc *); 167 168static int bwi_rxeof(struct bwi_softc *, int); 169static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 170static void bwi_txeof(struct bwi_softc *); 171static void bwi_txeof_status(struct bwi_softc *, int); 172static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 173static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 174 175static int bwi_dma_alloc(struct bwi_softc *); 176static void bwi_dma_free(struct bwi_softc *); 177static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 178 struct bwi_ring_data *, bus_size_t, 179 uint32_t); 180static int bwi_dma_mbuf_create(struct bwi_softc *); 181static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 182static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 183static void bwi_dma_txstats_free(struct bwi_softc *); 184static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 185static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 186 bus_size_t, int); 187 188static void bwi_power_on(struct bwi_softc *, int); 189static int bwi_power_off(struct bwi_softc *, int); 190static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 191static int bwi_set_clock_delay(struct bwi_softc *); 192static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 193static int bwi_get_pwron_delay(struct bwi_softc *sc); 194static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 195 const uint8_t *); 196static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 197 198static void bwi_get_card_flags(struct bwi_softc *); 199static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 200 201static int bwi_bus_attach(struct bwi_softc *); 202static int bwi_bbp_attach(struct bwi_softc *); 203static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 204static void bwi_bbp_power_off(struct bwi_softc *); 205 206static const char *bwi_regwin_name(const struct bwi_regwin *); 207static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 208static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 209static int bwi_regwin_select(struct bwi_softc *, int); 210 211static void bwi_led_attach(struct bwi_softc *); 212static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 213static void bwi_led_event(struct bwi_softc *, int); 214static void bwi_led_blink_start(struct bwi_softc *, int, int); 215static void bwi_led_blink_next(void *); 216static void bwi_led_blink_end(void *); 217 218static const struct { 219 uint16_t did_min; 220 uint16_t did_max; 221 uint16_t bbp_id; 222} bwi_bbpid_map[] = { 223 { 0x4301, 0x4301, 0x4301 }, 224 { 0x4305, 0x4307, 0x4307 }, 225 { 0x4402, 0x4403, 0x4402 }, 226 { 0x4610, 0x4615, 0x4610 }, 227 { 0x4710, 0x4715, 0x4710 }, 228 { 0x4720, 0x4725, 0x4309 } 229}; 230 231static const struct { 232 uint16_t bbp_id; 233 int nregwin; 234} bwi_regwin_count[] = { 235 { 0x4301, 5 }, 236 { 0x4306, 6 }, 237 { 0x4307, 5 }, 238 { 0x4310, 8 }, 239 { 0x4401, 3 }, 240 { 0x4402, 3 }, 241 { 0x4610, 9 }, 242 { 0x4704, 9 }, 243 { 0x4710, 9 }, 244 { 0x5365, 7 } 245}; 246 247#define CLKSRC(src) \ 248[BWI_CLKSRC_ ## src] = { \ 249 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 250 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 251} 252 253static const struct { 254 u_int freq_min; 255 u_int freq_max; 256} bwi_clkfreq[BWI_CLKSRC_MAX] = { 257 CLKSRC(LP_OSC), 258 CLKSRC(CS_OSC), 259 CLKSRC(PCI) 260}; 261 262#undef CLKSRC 263 264#define VENDOR_LED_ACT(vendor) \ 265{ \ 266 .vid = PCI_VENDOR_##vendor, \ 267 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 268} 269 270static const struct { 271#define PCI_VENDOR_COMPAQ 0x0e11 272#define PCI_VENDOR_LINKSYS 0x1737 273 uint16_t vid; 274 uint8_t led_act[BWI_LED_MAX]; 275} bwi_vendor_led_act[] = { 276 VENDOR_LED_ACT(COMPAQ), 277 VENDOR_LED_ACT(LINKSYS) 278#undef PCI_VENDOR_LINKSYS 279#undef PCI_VENDOR_COMPAQ 280}; 281 282static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 283 { BWI_VENDOR_LED_ACT_DEFAULT }; 284 285#undef VENDOR_LED_ACT 286 287static const struct { 288 int on_dur; 289 int off_dur; 290} bwi_led_duration[109] = { 291 [0] = { 400, 100 }, 292 [2] = { 150, 75 }, 293 [4] = { 90, 45 }, 294 [11] = { 66, 34 }, 295 [12] = { 53, 26 }, 296 [18] = { 42, 21 }, 297 [22] = { 35, 17 }, 298 [24] = { 32, 16 }, 299 [36] = { 21, 10 }, 300 [48] = { 16, 8 }, 301 [72] = { 11, 5 }, 302 [96] = { 9, 4 }, 303 [108] = { 7, 3 } 304}; 305 306#ifdef BWI_DEBUG 307#ifdef BWI_DEBUG_VERBOSE 308static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 309#else 310static uint32_t bwi_debug; 311#endif 312TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 313#endif /* BWI_DEBUG */ 314 315static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 316 317uint16_t 318bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 319{ 320 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 321} 322 323static __inline void 324bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 325 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 326 int tx) 327{ 328 struct bwi_desc32 *desc = &desc_array[desc_idx]; 329 uint32_t ctrl, addr, addr_hi, addr_lo; 330 331 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 332 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 333 334 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 335 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 336 337 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 338 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 339 if (desc_idx == ndesc - 1) 340 ctrl |= BWI_DESC32_C_EOR; 341 if (tx) { 342 /* XXX */ 343 ctrl |= BWI_DESC32_C_FRAME_START | 344 BWI_DESC32_C_FRAME_END | 345 BWI_DESC32_C_INTR; 346 } 347 348 desc->addr = htole32(addr); 349 desc->ctrl = htole32(ctrl); 350} 351 352int 353bwi_attach(struct bwi_softc *sc) 354{ 355 struct ieee80211com *ic; 356 device_t dev = sc->sc_dev; 357 struct ifnet *ifp; 358 struct bwi_mac *mac; 359 struct bwi_phy *phy; 360 int i, error; 361 uint8_t bands; 362 uint8_t macaddr[IEEE80211_ADDR_LEN]; 363 364 BWI_LOCK_INIT(sc); 365 366 /* 367 * Initialize taskq and various tasks 368 */ 369 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 370 taskqueue_thread_enqueue, &sc->sc_tq); 371 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 372 device_get_nameunit(dev)); 373 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 374 375 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 376 377 /* 378 * Initialize sysctl variables 379 */ 380 sc->sc_fw_version = BWI_FW_VERSION3; 381 sc->sc_led_idle = (2350 * hz) / 1000; 382 sc->sc_led_blink = 1; 383 sc->sc_txpwr_calib = 1; 384#ifdef BWI_DEBUG 385 sc->sc_debug = bwi_debug; 386#endif 387 bwi_power_on(sc, 1); 388 389 error = bwi_bbp_attach(sc); 390 if (error) 391 goto fail; 392 393 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 394 if (error) 395 goto fail; 396 397 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 398 error = bwi_set_clock_delay(sc); 399 if (error) 400 goto fail; 401 402 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 403 if (error) 404 goto fail; 405 406 error = bwi_get_pwron_delay(sc); 407 if (error) 408 goto fail; 409 } 410 411 error = bwi_bus_attach(sc); 412 if (error) 413 goto fail; 414 415 bwi_get_card_flags(sc); 416 417 bwi_led_attach(sc); 418 419 for (i = 0; i < sc->sc_nmac; ++i) { 420 struct bwi_regwin *old; 421 422 mac = &sc->sc_mac[i]; 423 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 424 if (error) 425 goto fail; 426 427 error = bwi_mac_lateattach(mac); 428 if (error) 429 goto fail; 430 431 error = bwi_regwin_switch(sc, old, NULL); 432 if (error) 433 goto fail; 434 } 435 436 /* 437 * XXX First MAC is known to exist 438 * TODO2 439 */ 440 mac = &sc->sc_mac[0]; 441 phy = &mac->mac_phy; 442 443 bwi_bbp_power_off(sc); 444 445 error = bwi_dma_alloc(sc); 446 if (error) 447 goto fail; 448 449 error = bwi_mac_fw_alloc(mac); 450 if (error) 451 goto fail; 452 453 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 454 if (ifp == NULL) { 455 device_printf(dev, "can not if_alloc()\n"); 456 error = ENOSPC; 457 goto fail; 458 } 459 ic = ifp->if_l2com; 460 461 /* set these up early for if_printf use */ 462 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 463 464 ifp->if_softc = sc; 465 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 466 ifp->if_init = bwi_init; 467 ifp->if_ioctl = bwi_ioctl; 468 ifp->if_start = bwi_start; 469 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 470 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 471 IFQ_SET_READY(&ifp->if_snd); 472 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 473 474 /* 475 * Setup ratesets, phytype, channels and get MAC address 476 */ 477 bands = 0; 478 if (phy->phy_mode == IEEE80211_MODE_11B || 479 phy->phy_mode == IEEE80211_MODE_11G) { 480 setbit(&bands, IEEE80211_MODE_11B); 481 if (phy->phy_mode == IEEE80211_MODE_11B) { 482 ic->ic_phytype = IEEE80211_T_DS; 483 } else { 484 ic->ic_phytype = IEEE80211_T_OFDM; 485 setbit(&bands, IEEE80211_MODE_11G); 486 } 487 488 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 489 if (IEEE80211_IS_MULTICAST(macaddr)) { 490 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 491 if (IEEE80211_IS_MULTICAST(macaddr)) { 492 device_printf(dev, 493 "invalid MAC address: %6D\n", 494 macaddr, ":"); 495 } 496 } 497 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 498 /* TODO:11A */ 499 setbit(&bands, IEEE80211_MODE_11A); 500 error = ENXIO; 501 goto fail; 502 } else { 503 panic("unknown phymode %d\n", phy->phy_mode); 504 } 505 506 /* Get locale */ 507 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 508 BWI_SPROM_CARD_INFO_LOCALE); 509 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 510 /* XXX use locale */ 511 ieee80211_init_channels(ic, NULL, &bands); 512 513 ic->ic_ifp = ifp; 514 ic->ic_softc = sc; 515 ic->ic_name = device_get_nameunit(dev); 516 ic->ic_caps = IEEE80211_C_STA | 517 IEEE80211_C_SHSLOT | 518 IEEE80211_C_SHPREAMBLE | 519 IEEE80211_C_WPA | 520 IEEE80211_C_BGSCAN | 521 IEEE80211_C_MONITOR; 522 ic->ic_opmode = IEEE80211_M_STA; 523 ieee80211_ifattach(ic, macaddr); 524 525 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 526 527 /* override default methods */ 528 ic->ic_vap_create = bwi_vap_create; 529 ic->ic_vap_delete = bwi_vap_delete; 530 ic->ic_raw_xmit = bwi_raw_xmit; 531 ic->ic_updateslot = bwi_updateslot; 532 ic->ic_scan_start = bwi_scan_start; 533 ic->ic_scan_end = bwi_scan_end; 534 ic->ic_set_channel = bwi_set_channel; 535 536 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 537 538 ieee80211_radiotap_attach(ic, 539 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 540 BWI_TX_RADIOTAP_PRESENT, 541 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 542 BWI_RX_RADIOTAP_PRESENT); 543 544 /* 545 * Add sysctl nodes 546 */ 547 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 549 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 550 "Firmware version"); 551 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 552 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 553 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 554 "# ticks before LED enters idle state"); 555 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 556 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 557 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 558 "Allow LED to blink"); 559 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 560 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 561 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 562 "Enable software TX power calibration"); 563#ifdef BWI_DEBUG 564 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 565 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 566 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 567#endif 568 if (bootverbose) 569 ieee80211_announce(ic); 570 571 return (0); 572fail: 573 BWI_LOCK_DESTROY(sc); 574 return (error); 575} 576 577int 578bwi_detach(struct bwi_softc *sc) 579{ 580 struct ifnet *ifp = sc->sc_ifp; 581 struct ieee80211com *ic = ifp->if_l2com; 582 int i; 583 584 bwi_stop(sc, 1); 585 callout_drain(&sc->sc_led_blink_ch); 586 callout_drain(&sc->sc_calib_ch); 587 callout_drain(&sc->sc_watchdog_timer); 588 ieee80211_ifdetach(ic); 589 590 for (i = 0; i < sc->sc_nmac; ++i) 591 bwi_mac_detach(&sc->sc_mac[i]); 592 bwi_dma_free(sc); 593 if_free(ifp); 594 taskqueue_free(sc->sc_tq); 595 596 BWI_LOCK_DESTROY(sc); 597 598 return (0); 599} 600 601static struct ieee80211vap * 602bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 603 enum ieee80211_opmode opmode, int flags, 604 const uint8_t bssid[IEEE80211_ADDR_LEN], 605 const uint8_t mac[IEEE80211_ADDR_LEN]) 606{ 607 struct bwi_vap *bvp; 608 struct ieee80211vap *vap; 609 610 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 611 return NULL; 612 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 613 M_80211_VAP, M_WAITOK | M_ZERO); 614 if (bvp == NULL) 615 return NULL; 616 vap = &bvp->bv_vap; 617 /* enable s/w bmiss handling for sta mode */ 618 ieee80211_vap_setup(ic, vap, name, unit, opmode, 619 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 620 621 /* override default methods */ 622 bvp->bv_newstate = vap->iv_newstate; 623 vap->iv_newstate = bwi_newstate; 624#if 0 625 vap->iv_update_beacon = bwi_beacon_update; 626#endif 627 ieee80211_ratectl_init(vap); 628 629 /* complete setup */ 630 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 631 ic->ic_opmode = opmode; 632 return vap; 633} 634 635static void 636bwi_vap_delete(struct ieee80211vap *vap) 637{ 638 struct bwi_vap *bvp = BWI_VAP(vap); 639 640 ieee80211_ratectl_deinit(vap); 641 ieee80211_vap_detach(vap); 642 free(bvp, M_80211_VAP); 643} 644 645void 646bwi_suspend(struct bwi_softc *sc) 647{ 648 bwi_stop(sc, 1); 649} 650 651void 652bwi_resume(struct bwi_softc *sc) 653{ 654 struct ifnet *ifp = sc->sc_ifp; 655 656 if (ifp->if_flags & IFF_UP) 657 bwi_init(sc); 658} 659 660int 661bwi_shutdown(struct bwi_softc *sc) 662{ 663 bwi_stop(sc, 1); 664 return 0; 665} 666 667static void 668bwi_power_on(struct bwi_softc *sc, int with_pll) 669{ 670 uint32_t gpio_in, gpio_out, gpio_en; 671 uint16_t status; 672 673 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 674 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 675 goto back; 676 677 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 678 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 679 680 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 681 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 682 if (with_pll) { 683 /* Turn off PLL first */ 684 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 685 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 686 } 687 688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 689 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 690 DELAY(1000); 691 692 if (with_pll) { 693 /* Turn on PLL */ 694 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 695 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 696 DELAY(5000); 697 } 698 699back: 700 /* Clear "Signaled Target Abort" */ 701 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 702 status &= ~PCIM_STATUS_STABORT; 703 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 704} 705 706static int 707bwi_power_off(struct bwi_softc *sc, int with_pll) 708{ 709 uint32_t gpio_out, gpio_en; 710 711 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 712 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 713 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 714 715 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 716 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 717 if (with_pll) { 718 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 719 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 720 } 721 722 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 723 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 724 return 0; 725} 726 727int 728bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 729 struct bwi_regwin **old_rw) 730{ 731 int error; 732 733 if (old_rw != NULL) 734 *old_rw = NULL; 735 736 if (!BWI_REGWIN_EXIST(rw)) 737 return EINVAL; 738 739 if (sc->sc_cur_regwin != rw) { 740 error = bwi_regwin_select(sc, rw->rw_id); 741 if (error) { 742 device_printf(sc->sc_dev, "can't select regwin %d\n", 743 rw->rw_id); 744 return error; 745 } 746 } 747 748 if (old_rw != NULL) 749 *old_rw = sc->sc_cur_regwin; 750 sc->sc_cur_regwin = rw; 751 return 0; 752} 753 754static int 755bwi_regwin_select(struct bwi_softc *sc, int id) 756{ 757 uint32_t win = BWI_PCIM_REGWIN(id); 758 int i; 759 760#define RETRY_MAX 50 761 for (i = 0; i < RETRY_MAX; ++i) { 762 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 763 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 764 return 0; 765 DELAY(10); 766 } 767#undef RETRY_MAX 768 769 return ENXIO; 770} 771 772static void 773bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 774{ 775 uint32_t val; 776 777 val = CSR_READ_4(sc, BWI_ID_HI); 778 *type = BWI_ID_HI_REGWIN_TYPE(val); 779 *rev = BWI_ID_HI_REGWIN_REV(val); 780 781 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 782 "vendor 0x%04x\n", *type, *rev, 783 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 784} 785 786static int 787bwi_bbp_attach(struct bwi_softc *sc) 788{ 789#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 790 uint16_t bbp_id, rw_type; 791 uint8_t rw_rev; 792 uint32_t info; 793 int error, nregwin, i; 794 795 /* 796 * Get 0th regwin information 797 * NOTE: 0th regwin should exist 798 */ 799 error = bwi_regwin_select(sc, 0); 800 if (error) { 801 device_printf(sc->sc_dev, "can't select regwin 0\n"); 802 return error; 803 } 804 bwi_regwin_info(sc, &rw_type, &rw_rev); 805 806 /* 807 * Find out BBP id 808 */ 809 bbp_id = 0; 810 info = 0; 811 if (rw_type == BWI_REGWIN_T_COM) { 812 info = CSR_READ_4(sc, BWI_INFO); 813 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 814 815 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 816 817 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 818 } else { 819 for (i = 0; i < N(bwi_bbpid_map); ++i) { 820 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 821 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 822 bbp_id = bwi_bbpid_map[i].bbp_id; 823 break; 824 } 825 } 826 if (bbp_id == 0) { 827 device_printf(sc->sc_dev, "no BBP id for device id " 828 "0x%04x\n", sc->sc_pci_did); 829 return ENXIO; 830 } 831 832 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 833 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 834 } 835 836 /* 837 * Find out number of regwins 838 */ 839 nregwin = 0; 840 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 841 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 842 } else { 843 for (i = 0; i < N(bwi_regwin_count); ++i) { 844 if (bwi_regwin_count[i].bbp_id == bbp_id) { 845 nregwin = bwi_regwin_count[i].nregwin; 846 break; 847 } 848 } 849 if (nregwin == 0) { 850 device_printf(sc->sc_dev, "no number of win for " 851 "BBP id 0x%04x\n", bbp_id); 852 return ENXIO; 853 } 854 } 855 856 /* Record BBP id/rev for later using */ 857 sc->sc_bbp_id = bbp_id; 858 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 859 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 860 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 861 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 862 863 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 864 nregwin, sc->sc_cap); 865 866 /* 867 * Create rest of the regwins 868 */ 869 870 /* Don't re-create common regwin, if it is already created */ 871 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 872 873 for (; i < nregwin; ++i) { 874 /* 875 * Get regwin information 876 */ 877 error = bwi_regwin_select(sc, i); 878 if (error) { 879 device_printf(sc->sc_dev, 880 "can't select regwin %d\n", i); 881 return error; 882 } 883 bwi_regwin_info(sc, &rw_type, &rw_rev); 884 885 /* 886 * Try attach: 887 * 1) Bus (PCI/PCIE) regwin 888 * 2) MAC regwin 889 * Ignore rest types of regwin 890 */ 891 if (rw_type == BWI_REGWIN_T_BUSPCI || 892 rw_type == BWI_REGWIN_T_BUSPCIE) { 893 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 894 device_printf(sc->sc_dev, 895 "bus regwin already exists\n"); 896 } else { 897 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 898 rw_type, rw_rev); 899 } 900 } else if (rw_type == BWI_REGWIN_T_MAC) { 901 /* XXX ignore return value */ 902 bwi_mac_attach(sc, i, rw_rev); 903 } 904 } 905 906 /* At least one MAC shold exist */ 907 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 908 device_printf(sc->sc_dev, "no MAC was found\n"); 909 return ENXIO; 910 } 911 KASSERT(sc->sc_nmac > 0, ("no mac's")); 912 913 /* Bus regwin must exist */ 914 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 915 device_printf(sc->sc_dev, "no bus regwin was found\n"); 916 return ENXIO; 917 } 918 919 /* Start with first MAC */ 920 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 921 if (error) 922 return error; 923 924 return 0; 925#undef N 926} 927 928int 929bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 930{ 931 struct bwi_regwin *old, *bus; 932 uint32_t val; 933 int error; 934 935 bus = &sc->sc_bus_regwin; 936 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 937 938 /* 939 * Tell bus to generate requested interrupts 940 */ 941 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 942 /* 943 * NOTE: Read BWI_FLAGS from MAC regwin 944 */ 945 val = CSR_READ_4(sc, BWI_FLAGS); 946 947 error = bwi_regwin_switch(sc, bus, &old); 948 if (error) 949 return error; 950 951 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 952 } else { 953 uint32_t mac_mask; 954 955 mac_mask = 1 << mac->mac_id; 956 957 error = bwi_regwin_switch(sc, bus, &old); 958 if (error) 959 return error; 960 961 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 962 val |= mac_mask << 8; 963 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 964 } 965 966 if (sc->sc_flags & BWI_F_BUS_INITED) 967 goto back; 968 969 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 970 /* 971 * Enable prefetch and burst 972 */ 973 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 974 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 975 976 if (bus->rw_rev < 5) { 977 struct bwi_regwin *com = &sc->sc_com_regwin; 978 979 /* 980 * Configure timeouts for bus operation 981 */ 982 983 /* 984 * Set service timeout and request timeout 985 */ 986 CSR_SETBITS_4(sc, BWI_CONF_LO, 987 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 988 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 989 990 /* 991 * If there is common regwin, we switch to that regwin 992 * and switch back to bus regwin once we have done. 993 */ 994 if (BWI_REGWIN_EXIST(com)) { 995 error = bwi_regwin_switch(sc, com, NULL); 996 if (error) 997 return error; 998 } 999 1000 /* Let bus know what we have changed */ 1001 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 1002 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 1003 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 1004 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 1005 1006 if (BWI_REGWIN_EXIST(com)) { 1007 error = bwi_regwin_switch(sc, bus, NULL); 1008 if (error) 1009 return error; 1010 } 1011 } else if (bus->rw_rev >= 11) { 1012 /* 1013 * Enable memory read multiple 1014 */ 1015 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1016 } 1017 } else { 1018 /* TODO:PCIE */ 1019 } 1020 1021 sc->sc_flags |= BWI_F_BUS_INITED; 1022back: 1023 return bwi_regwin_switch(sc, old, NULL); 1024} 1025 1026static void 1027bwi_get_card_flags(struct bwi_softc *sc) 1028{ 1029#define PCI_VENDOR_APPLE 0x106b 1030#define PCI_VENDOR_DELL 0x1028 1031 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1032 if (sc->sc_card_flags == 0xffff) 1033 sc->sc_card_flags = 0; 1034 1035 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1036 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1037 sc->sc_pci_revid == 0x74) 1038 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1039 1040 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1041 sc->sc_pci_subdid == 0x4e && /* XXX */ 1042 sc->sc_pci_revid > 0x40) 1043 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1044 1045 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1046#undef PCI_VENDOR_DELL 1047#undef PCI_VENDOR_APPLE 1048} 1049 1050static void 1051bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1052{ 1053 int i; 1054 1055 for (i = 0; i < 3; ++i) { 1056 *((uint16_t *)eaddr + i) = 1057 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1058 } 1059} 1060 1061static void 1062bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1063{ 1064 struct bwi_regwin *com; 1065 uint32_t val; 1066 u_int div; 1067 int src; 1068 1069 bzero(freq, sizeof(*freq)); 1070 com = &sc->sc_com_regwin; 1071 1072 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1073 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1074 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1075 1076 /* 1077 * Calculate clock frequency 1078 */ 1079 src = -1; 1080 div = 0; 1081 if (com->rw_rev < 6) { 1082 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1083 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1084 src = BWI_CLKSRC_PCI; 1085 div = 64; 1086 } else { 1087 src = BWI_CLKSRC_CS_OSC; 1088 div = 32; 1089 } 1090 } else if (com->rw_rev < 10) { 1091 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1092 1093 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1094 if (src == BWI_CLKSRC_LP_OSC) { 1095 div = 1; 1096 } else { 1097 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1098 1099 /* Unknown source */ 1100 if (src >= BWI_CLKSRC_MAX) 1101 src = BWI_CLKSRC_CS_OSC; 1102 } 1103 } else { 1104 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1105 1106 src = BWI_CLKSRC_CS_OSC; 1107 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1108 } 1109 1110 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1111 KASSERT(div != 0, ("div zero")); 1112 1113 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1114 src == BWI_CLKSRC_PCI ? "PCI" : 1115 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1116 1117 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1118 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1119 1120 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1121 freq->clkfreq_min, freq->clkfreq_max); 1122} 1123 1124static int 1125bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1126{ 1127 struct bwi_regwin *old, *com; 1128 uint32_t clk_ctrl, clk_src; 1129 int error, pwr_off = 0; 1130 1131 com = &sc->sc_com_regwin; 1132 if (!BWI_REGWIN_EXIST(com)) 1133 return 0; 1134 1135 if (com->rw_rev >= 10 || com->rw_rev < 6) 1136 return 0; 1137 1138 /* 1139 * For common regwin whose rev is [6, 10), the chip 1140 * must be capable to change clock mode. 1141 */ 1142 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1143 return 0; 1144 1145 error = bwi_regwin_switch(sc, com, &old); 1146 if (error) 1147 return error; 1148 1149 if (clk_mode == BWI_CLOCK_MODE_FAST) 1150 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1151 1152 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1153 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1154 1155 switch (clk_mode) { 1156 case BWI_CLOCK_MODE_FAST: 1157 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1158 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1159 break; 1160 case BWI_CLOCK_MODE_SLOW: 1161 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1162 break; 1163 case BWI_CLOCK_MODE_DYN: 1164 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1165 BWI_CLOCK_CTRL_IGNPLL | 1166 BWI_CLOCK_CTRL_NODYN); 1167 if (clk_src != BWI_CLKSRC_CS_OSC) { 1168 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1169 pwr_off = 1; 1170 } 1171 break; 1172 } 1173 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1174 1175 if (pwr_off) 1176 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1177 1178 return bwi_regwin_switch(sc, old, NULL); 1179} 1180 1181static int 1182bwi_set_clock_delay(struct bwi_softc *sc) 1183{ 1184 struct bwi_regwin *old, *com; 1185 int error; 1186 1187 com = &sc->sc_com_regwin; 1188 if (!BWI_REGWIN_EXIST(com)) 1189 return 0; 1190 1191 error = bwi_regwin_switch(sc, com, &old); 1192 if (error) 1193 return error; 1194 1195 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1196 if (sc->sc_bbp_rev == 0) 1197 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1198 else if (sc->sc_bbp_rev == 1) 1199 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1200 } 1201 1202 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1203 if (com->rw_rev >= 10) { 1204 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1205 } else { 1206 struct bwi_clock_freq freq; 1207 1208 bwi_get_clock_freq(sc, &freq); 1209 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1210 howmany(freq.clkfreq_max * 150, 1000000)); 1211 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1212 howmany(freq.clkfreq_max * 15, 1000000)); 1213 } 1214 } 1215 1216 return bwi_regwin_switch(sc, old, NULL); 1217} 1218 1219static void 1220bwi_init(void *xsc) 1221{ 1222 struct bwi_softc *sc = xsc; 1223 struct ifnet *ifp = sc->sc_ifp; 1224 struct ieee80211com *ic = ifp->if_l2com; 1225 1226 BWI_LOCK(sc); 1227 bwi_init_statechg(sc, 1); 1228 BWI_UNLOCK(sc); 1229 1230 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1231 ieee80211_start_all(ic); /* start all vap's */ 1232} 1233 1234static void 1235bwi_init_statechg(struct bwi_softc *sc, int statechg) 1236{ 1237 struct ifnet *ifp = sc->sc_ifp; 1238 struct bwi_mac *mac; 1239 int error; 1240 1241 bwi_stop_locked(sc, statechg); 1242 1243 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1244 1245 /* TODO: 2 MAC */ 1246 1247 mac = &sc->sc_mac[0]; 1248 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1249 if (error) { 1250 if_printf(ifp, "%s: error %d on regwin switch\n", 1251 __func__, error); 1252 goto bad; 1253 } 1254 error = bwi_mac_init(mac); 1255 if (error) { 1256 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1257 goto bad; 1258 } 1259 1260 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1261 1262 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1263 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1264 1265 bwi_mac_reset_hwkeys(mac); 1266 1267 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1268 int i; 1269 1270#define NRETRY 1000 1271 /* 1272 * Drain any possible pending TX status 1273 */ 1274 for (i = 0; i < NRETRY; ++i) { 1275 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1276 BWI_TXSTATUS0_VALID) == 0) 1277 break; 1278 CSR_READ_4(sc, BWI_TXSTATUS1); 1279 } 1280 if (i == NRETRY) 1281 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1282#undef NRETRY 1283 } 1284 1285 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1286 bwi_mac_updateslot(mac, 1); 1287 1288 /* Start MAC */ 1289 error = bwi_mac_start(mac); 1290 if (error) { 1291 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1292 goto bad; 1293 } 1294 1295 /* Clear stop flag before enabling interrupt */ 1296 sc->sc_flags &= ~BWI_F_STOP; 1297 1298 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1299 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1300 1301 /* Enable intrs */ 1302 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1303 return; 1304bad: 1305 bwi_stop_locked(sc, 1); 1306} 1307 1308static int 1309bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1310{ 1311#define IS_RUNNING(ifp) \ 1312 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1313 struct bwi_softc *sc = ifp->if_softc; 1314 struct ieee80211com *ic = ifp->if_l2com; 1315 struct ifreq *ifr = (struct ifreq *) data; 1316 int error = 0, startall = 0; 1317 1318 switch (cmd) { 1319 case SIOCSIFFLAGS: 1320 BWI_LOCK(sc); 1321 if (IS_RUNNING(ifp)) { 1322 struct bwi_mac *mac; 1323 int promisc = -1; 1324 1325 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1326 ("current regwin type %d", 1327 sc->sc_cur_regwin->rw_type)); 1328 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1329 1330 if ((ifp->if_flags & IFF_PROMISC) && 1331 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1332 promisc = 1; 1333 sc->sc_flags |= BWI_F_PROMISC; 1334 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1335 (sc->sc_flags & BWI_F_PROMISC)) { 1336 promisc = 0; 1337 sc->sc_flags &= ~BWI_F_PROMISC; 1338 } 1339 1340 if (promisc >= 0) 1341 bwi_mac_set_promisc(mac, promisc); 1342 } 1343 1344 if (ifp->if_flags & IFF_UP) { 1345 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1346 bwi_init_statechg(sc, 1); 1347 startall = 1; 1348 } 1349 } else { 1350 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1351 bwi_stop_locked(sc, 1); 1352 } 1353 BWI_UNLOCK(sc); 1354 if (startall) 1355 ieee80211_start_all(ic); 1356 break; 1357 case SIOCGIFMEDIA: 1358 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1359 break; 1360 case SIOCGIFADDR: 1361 error = ether_ioctl(ifp, cmd, data); 1362 break; 1363 default: 1364 error = EINVAL; 1365 break; 1366 } 1367 return error; 1368#undef IS_RUNNING 1369} 1370 1371static void 1372bwi_start(struct ifnet *ifp) 1373{ 1374 struct bwi_softc *sc = ifp->if_softc; 1375 1376 BWI_LOCK(sc); 1377 bwi_start_locked(ifp); 1378 BWI_UNLOCK(sc); 1379} 1380 1381static void 1382bwi_start_locked(struct ifnet *ifp) 1383{ 1384 struct bwi_softc *sc = ifp->if_softc; 1385 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1386 struct ieee80211_frame *wh; 1387 struct ieee80211_node *ni; 1388 struct ieee80211_key *k; 1389 struct mbuf *m; 1390 int trans, idx; 1391 1392 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1393 return; 1394 1395 trans = 0; 1396 idx = tbd->tbd_idx; 1397 1398 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1399 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1400 if (m == NULL) 1401 break; 1402 1403 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1404 wh = mtod(m, struct ieee80211_frame *); 1405 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1406 k = ieee80211_crypto_encap(ni, m); 1407 if (k == NULL) { 1408 ieee80211_free_node(ni); 1409 m_freem(m); 1410 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1411 continue; 1412 } 1413 } 1414 wh = NULL; /* Catch any invalid use */ 1415 1416 if (bwi_encap(sc, idx, m, ni) != 0) { 1417 /* 'm' is freed in bwi_encap() if we reach here */ 1418 if (ni != NULL) 1419 ieee80211_free_node(ni); 1420 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1421 continue; 1422 } 1423 1424 trans = 1; 1425 tbd->tbd_used++; 1426 idx = (idx + 1) % BWI_TX_NDESC; 1427 1428 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1429 1430 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1431 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1432 break; 1433 } 1434 } 1435 tbd->tbd_idx = idx; 1436 1437 if (trans) 1438 sc->sc_tx_timer = 5; 1439} 1440 1441static int 1442bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1443 const struct ieee80211_bpf_params *params) 1444{ 1445 struct ieee80211com *ic = ni->ni_ic; 1446 struct ifnet *ifp = ic->ic_ifp; 1447 struct bwi_softc *sc = ifp->if_softc; 1448 /* XXX wme? */ 1449 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1450 int idx, error; 1451 1452 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1453 ieee80211_free_node(ni); 1454 m_freem(m); 1455 return ENETDOWN; 1456 } 1457 1458 BWI_LOCK(sc); 1459 idx = tbd->tbd_idx; 1460 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1461 if (params == NULL) { 1462 /* 1463 * Legacy path; interpret frame contents to decide 1464 * precisely how to send the frame. 1465 */ 1466 error = bwi_encap(sc, idx, m, ni); 1467 } else { 1468 /* 1469 * Caller supplied explicit parameters to use in 1470 * sending the frame. 1471 */ 1472 error = bwi_encap_raw(sc, idx, m, ni, params); 1473 } 1474 if (error == 0) { 1475 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1476 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1477 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1478 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1479 sc->sc_tx_timer = 5; 1480 } else { 1481 /* NB: m is reclaimed on encap failure */ 1482 ieee80211_free_node(ni); 1483 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1484 } 1485 BWI_UNLOCK(sc); 1486 return error; 1487} 1488 1489static void 1490bwi_watchdog(void *arg) 1491{ 1492 struct bwi_softc *sc; 1493 struct ifnet *ifp; 1494 1495 sc = arg; 1496 ifp = sc->sc_ifp; 1497 BWI_ASSERT_LOCKED(sc); 1498 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1499 if_printf(ifp, "watchdog timeout\n"); 1500 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1501 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1502 } 1503 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1504} 1505 1506static void 1507bwi_stop(struct bwi_softc *sc, int statechg) 1508{ 1509 BWI_LOCK(sc); 1510 bwi_stop_locked(sc, statechg); 1511 BWI_UNLOCK(sc); 1512} 1513 1514static void 1515bwi_stop_locked(struct bwi_softc *sc, int statechg) 1516{ 1517 struct ifnet *ifp = sc->sc_ifp; 1518 struct bwi_mac *mac; 1519 int i, error, pwr_off = 0; 1520 1521 BWI_ASSERT_LOCKED(sc); 1522 1523 callout_stop(&sc->sc_calib_ch); 1524 callout_stop(&sc->sc_led_blink_ch); 1525 sc->sc_led_blinking = 0; 1526 sc->sc_flags |= BWI_F_STOP; 1527 1528 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1529 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1530 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1531 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1532 1533 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1534 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1535 bwi_mac_stop(mac); 1536 } 1537 1538 for (i = 0; i < sc->sc_nmac; ++i) { 1539 struct bwi_regwin *old_rw; 1540 1541 mac = &sc->sc_mac[i]; 1542 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1543 continue; 1544 1545 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1546 if (error) 1547 continue; 1548 1549 bwi_mac_shutdown(mac); 1550 pwr_off = 1; 1551 1552 bwi_regwin_switch(sc, old_rw, NULL); 1553 } 1554 1555 if (pwr_off) 1556 bwi_bbp_power_off(sc); 1557 1558 sc->sc_tx_timer = 0; 1559 callout_stop(&sc->sc_watchdog_timer); 1560 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1561} 1562 1563void 1564bwi_intr(void *xsc) 1565{ 1566 struct bwi_softc *sc = xsc; 1567 struct ifnet *ifp = sc->sc_ifp; 1568 struct bwi_mac *mac; 1569 uint32_t intr_status; 1570 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1571 int i, txrx_error, tx = 0, rx_data = -1; 1572 1573 BWI_LOCK(sc); 1574 1575 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1576 (sc->sc_flags & BWI_F_STOP)) { 1577 BWI_UNLOCK(sc); 1578 return; 1579 } 1580 /* 1581 * Get interrupt status 1582 */ 1583 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1584 if (intr_status == 0xffffffff) { /* Not for us */ 1585 BWI_UNLOCK(sc); 1586 return; 1587 } 1588 1589 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1590 1591 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1592 if (intr_status == 0) { /* Nothing is interesting */ 1593 BWI_UNLOCK(sc); 1594 return; 1595 } 1596 1597 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1598 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1599 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1600 1601 txrx_error = 0; 1602 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1603 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1604 uint32_t mask; 1605 1606 if (BWI_TXRX_IS_RX(i)) 1607 mask = BWI_TXRX_RX_INTRS; 1608 else 1609 mask = BWI_TXRX_TX_INTRS; 1610 1611 txrx_intr_status[i] = 1612 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1613 1614 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1615 i, txrx_intr_status[i]); 1616 1617 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1618 if_printf(ifp, 1619 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1620 __func__, i, txrx_intr_status[i]); 1621 txrx_error = 1; 1622 } 1623 } 1624 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1625 1626 /* 1627 * Acknowledge interrupt 1628 */ 1629 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1630 1631 for (i = 0; i < BWI_TXRX_NRING; ++i) 1632 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1633 1634 /* Disable all interrupts */ 1635 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1636 1637 /* 1638 * http://bcm-specs.sipsolutions.net/Interrupts 1639 * Says for this bit (0x800): 1640 * "Fatal Error 1641 * 1642 * We got this one while testing things when by accident the 1643 * template ram wasn't set to big endian when it should have 1644 * been after writing the initial values. It keeps on being 1645 * triggered, the only way to stop it seems to shut down the 1646 * chip." 1647 * 1648 * Suggesting that we should never get it and if we do we're not 1649 * feeding TX packets into the MAC correctly if we do... Apparently, 1650 * it is valid only on mac version 5 and higher, but I couldn't 1651 * find a reference for that... Since I see them from time to time 1652 * on my card, this suggests an error in the tx path still... 1653 */ 1654 if (intr_status & BWI_INTR_PHY_TXERR) { 1655 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1656 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1657 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1658 BWI_UNLOCK(sc); 1659 return; 1660 } 1661 } 1662 1663 if (txrx_error) { 1664 /* TODO: reset device */ 1665 } 1666 1667 if (intr_status & BWI_INTR_TBTT) 1668 bwi_mac_config_ps(mac); 1669 1670 if (intr_status & BWI_INTR_EO_ATIM) 1671 if_printf(ifp, "EO_ATIM\n"); 1672 1673 if (intr_status & BWI_INTR_PMQ) { 1674 for (;;) { 1675 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1676 break; 1677 } 1678 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1679 } 1680 1681 if (intr_status & BWI_INTR_NOISE) 1682 if_printf(ifp, "intr noise\n"); 1683 1684 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1685 rx_data = sc->sc_rxeof(sc); 1686 if (sc->sc_flags & BWI_F_STOP) { 1687 BWI_UNLOCK(sc); 1688 return; 1689 } 1690 } 1691 1692 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1693 sc->sc_txeof_status(sc); 1694 tx = 1; 1695 } 1696 1697 if (intr_status & BWI_INTR_TX_DONE) { 1698 bwi_txeof(sc); 1699 tx = 1; 1700 } 1701 1702 /* Re-enable interrupts */ 1703 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1704 1705 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1706 int evt = BWI_LED_EVENT_NONE; 1707 1708 if (tx && rx_data > 0) { 1709 if (sc->sc_rx_rate > sc->sc_tx_rate) 1710 evt = BWI_LED_EVENT_RX; 1711 else 1712 evt = BWI_LED_EVENT_TX; 1713 } else if (tx) { 1714 evt = BWI_LED_EVENT_TX; 1715 } else if (rx_data > 0) { 1716 evt = BWI_LED_EVENT_RX; 1717 } else if (rx_data == 0) { 1718 evt = BWI_LED_EVENT_POLL; 1719 } 1720 1721 if (evt != BWI_LED_EVENT_NONE) 1722 bwi_led_event(sc, evt); 1723 } 1724 1725 BWI_UNLOCK(sc); 1726} 1727 1728static void 1729bwi_scan_start(struct ieee80211com *ic) 1730{ 1731 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1732 1733 BWI_LOCK(sc); 1734 /* Enable MAC beacon promiscuity */ 1735 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1736 BWI_UNLOCK(sc); 1737} 1738 1739static void 1740bwi_set_channel(struct ieee80211com *ic) 1741{ 1742 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1743 struct ieee80211_channel *c = ic->ic_curchan; 1744 struct bwi_mac *mac; 1745 1746 BWI_LOCK(sc); 1747 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1748 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1749 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1750 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1751 1752 sc->sc_rates = ieee80211_get_ratetable(c); 1753 1754 /* 1755 * Setup radio tap channel freq and flags 1756 */ 1757 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1758 htole16(c->ic_freq); 1759 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1760 htole16(c->ic_flags & 0xffff); 1761 1762 BWI_UNLOCK(sc); 1763} 1764 1765static void 1766bwi_scan_end(struct ieee80211com *ic) 1767{ 1768 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1769 1770 BWI_LOCK(sc); 1771 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1772 BWI_UNLOCK(sc); 1773} 1774 1775static int 1776bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1777{ 1778 struct bwi_vap *bvp = BWI_VAP(vap); 1779 struct ieee80211com *ic= vap->iv_ic; 1780 struct ifnet *ifp = ic->ic_ifp; 1781 enum ieee80211_state ostate = vap->iv_state; 1782 struct bwi_softc *sc = ifp->if_softc; 1783 struct bwi_mac *mac; 1784 int error; 1785 1786 BWI_LOCK(sc); 1787 1788 callout_stop(&sc->sc_calib_ch); 1789 1790 if (nstate == IEEE80211_S_INIT) 1791 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1792 1793 bwi_led_newstate(sc, nstate); 1794 1795 error = bvp->bv_newstate(vap, nstate, arg); 1796 if (error != 0) 1797 goto back; 1798 1799 /* 1800 * Clear the BSSID when we stop a STA 1801 */ 1802 if (vap->iv_opmode == IEEE80211_M_STA) { 1803 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1804 /* 1805 * Clear out the BSSID. If we reassociate to 1806 * the same AP, this will reinialize things 1807 * correctly... 1808 */ 1809 if (ic->ic_opmode == IEEE80211_M_STA && 1810 !(sc->sc_flags & BWI_F_STOP)) 1811 bwi_set_bssid(sc, bwi_zero_addr); 1812 } 1813 } 1814 1815 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1816 /* Nothing to do */ 1817 } else if (nstate == IEEE80211_S_RUN) { 1818 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1819 1820 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1821 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1822 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1823 1824 /* Initial TX power calibration */ 1825 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1826#ifdef notyet 1827 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1828#else 1829 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1830#endif 1831 1832 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1833 } 1834back: 1835 BWI_UNLOCK(sc); 1836 1837 return error; 1838} 1839 1840static int 1841bwi_media_change(struct ifnet *ifp) 1842{ 1843 int error = ieee80211_media_change(ifp); 1844 /* NB: only the fixed rate can change and that doesn't need a reset */ 1845 return (error == ENETRESET ? 0 : error); 1846} 1847 1848static int 1849bwi_dma_alloc(struct bwi_softc *sc) 1850{ 1851 int error, i, has_txstats; 1852 bus_addr_t lowaddr = 0; 1853 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1854 uint32_t txrx_ctrl_step = 0; 1855 1856 has_txstats = 0; 1857 for (i = 0; i < sc->sc_nmac; ++i) { 1858 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1859 has_txstats = 1; 1860 break; 1861 } 1862 } 1863 1864 switch (sc->sc_bus_space) { 1865 case BWI_BUS_SPACE_30BIT: 1866 case BWI_BUS_SPACE_32BIT: 1867 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1868 lowaddr = BWI_BUS_SPACE_MAXADDR; 1869 else 1870 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1871 desc_sz = sizeof(struct bwi_desc32); 1872 txrx_ctrl_step = 0x20; 1873 1874 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1875 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1876 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1877 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1878 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1879 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1880 sc->sc_rxeof = bwi_rxeof32; 1881 sc->sc_start_tx = bwi_start_tx32; 1882 if (has_txstats) { 1883 sc->sc_init_txstats = bwi_init_txstats32; 1884 sc->sc_free_txstats = bwi_free_txstats32; 1885 sc->sc_txeof_status = bwi_txeof_status32; 1886 } 1887 break; 1888 1889 case BWI_BUS_SPACE_64BIT: 1890 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1891 desc_sz = sizeof(struct bwi_desc64); 1892 txrx_ctrl_step = 0x40; 1893 1894 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1895 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1896 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1897 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1898 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1899 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1900 sc->sc_rxeof = bwi_rxeof64; 1901 sc->sc_start_tx = bwi_start_tx64; 1902 if (has_txstats) { 1903 sc->sc_init_txstats = bwi_init_txstats64; 1904 sc->sc_free_txstats = bwi_free_txstats64; 1905 sc->sc_txeof_status = bwi_txeof_status64; 1906 } 1907 break; 1908 } 1909 1910 KASSERT(lowaddr != 0, ("lowaddr zero")); 1911 KASSERT(desc_sz != 0, ("desc_sz zero")); 1912 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1913 1914 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1915 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1916 1917 /* 1918 * Create top level DMA tag 1919 */ 1920 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1921 BWI_ALIGN, 0, /* alignment, bounds */ 1922 lowaddr, /* lowaddr */ 1923 BUS_SPACE_MAXADDR, /* highaddr */ 1924 NULL, NULL, /* filter, filterarg */ 1925 BUS_SPACE_MAXSIZE, /* maxsize */ 1926 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1927 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1928 0, /* flags */ 1929 NULL, NULL, /* lockfunc, lockarg */ 1930 &sc->sc_parent_dtag); 1931 if (error) { 1932 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1933 return error; 1934 } 1935 1936#define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1937 1938 /* 1939 * Create TX ring DMA stuffs 1940 */ 1941 error = bus_dma_tag_create(sc->sc_parent_dtag, 1942 BWI_RING_ALIGN, 0, 1943 BUS_SPACE_MAXADDR, 1944 BUS_SPACE_MAXADDR, 1945 NULL, NULL, 1946 tx_ring_sz, 1947 1, 1948 tx_ring_sz, 1949 0, 1950 NULL, NULL, 1951 &sc->sc_txring_dtag); 1952 if (error) { 1953 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1954 return error; 1955 } 1956 1957 for (i = 0; i < BWI_TX_NRING; ++i) { 1958 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1959 &sc->sc_tx_rdata[i], tx_ring_sz, 1960 TXRX_CTRL(i)); 1961 if (error) { 1962 device_printf(sc->sc_dev, "%dth TX ring " 1963 "DMA alloc failed\n", i); 1964 return error; 1965 } 1966 } 1967 1968 /* 1969 * Create RX ring DMA stuffs 1970 */ 1971 error = bus_dma_tag_create(sc->sc_parent_dtag, 1972 BWI_RING_ALIGN, 0, 1973 BUS_SPACE_MAXADDR, 1974 BUS_SPACE_MAXADDR, 1975 NULL, NULL, 1976 rx_ring_sz, 1977 1, 1978 rx_ring_sz, 1979 0, 1980 NULL, NULL, 1981 &sc->sc_rxring_dtag); 1982 if (error) { 1983 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1984 return error; 1985 } 1986 1987 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1988 rx_ring_sz, TXRX_CTRL(0)); 1989 if (error) { 1990 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1991 return error; 1992 } 1993 1994 if (has_txstats) { 1995 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1996 if (error) { 1997 device_printf(sc->sc_dev, 1998 "TX stats DMA alloc failed\n"); 1999 return error; 2000 } 2001 } 2002 2003#undef TXRX_CTRL 2004 2005 return bwi_dma_mbuf_create(sc); 2006} 2007 2008static void 2009bwi_dma_free(struct bwi_softc *sc) 2010{ 2011 if (sc->sc_txring_dtag != NULL) { 2012 int i; 2013 2014 for (i = 0; i < BWI_TX_NRING; ++i) { 2015 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2016 2017 if (rd->rdata_desc != NULL) { 2018 bus_dmamap_unload(sc->sc_txring_dtag, 2019 rd->rdata_dmap); 2020 bus_dmamem_free(sc->sc_txring_dtag, 2021 rd->rdata_desc, 2022 rd->rdata_dmap); 2023 } 2024 } 2025 bus_dma_tag_destroy(sc->sc_txring_dtag); 2026 } 2027 2028 if (sc->sc_rxring_dtag != NULL) { 2029 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2030 2031 if (rd->rdata_desc != NULL) { 2032 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2033 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2034 rd->rdata_dmap); 2035 } 2036 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2037 } 2038 2039 bwi_dma_txstats_free(sc); 2040 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2041 2042 if (sc->sc_parent_dtag != NULL) 2043 bus_dma_tag_destroy(sc->sc_parent_dtag); 2044} 2045 2046static int 2047bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2048 struct bwi_ring_data *rd, bus_size_t size, 2049 uint32_t txrx_ctrl) 2050{ 2051 int error; 2052 2053 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2054 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2055 &rd->rdata_dmap); 2056 if (error) { 2057 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2058 return error; 2059 } 2060 2061 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2062 bwi_dma_ring_addr, &rd->rdata_paddr, 2063 BUS_DMA_NOWAIT); 2064 if (error) { 2065 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2066 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2067 rd->rdata_desc = NULL; 2068 return error; 2069 } 2070 2071 rd->rdata_txrx_ctrl = txrx_ctrl; 2072 return 0; 2073} 2074 2075static int 2076bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2077 bus_size_t desc_sz) 2078{ 2079 struct bwi_txstats_data *st; 2080 bus_size_t dma_size; 2081 int error; 2082 2083 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2084 if (st == NULL) { 2085 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2086 return ENOMEM; 2087 } 2088 sc->sc_txstats = st; 2089 2090 /* 2091 * Create TX stats descriptor DMA stuffs 2092 */ 2093 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2094 2095 error = bus_dma_tag_create(sc->sc_parent_dtag, 2096 BWI_RING_ALIGN, 2097 0, 2098 BUS_SPACE_MAXADDR, 2099 BUS_SPACE_MAXADDR, 2100 NULL, NULL, 2101 dma_size, 2102 1, 2103 dma_size, 2104 0, 2105 NULL, NULL, 2106 &st->stats_ring_dtag); 2107 if (error) { 2108 device_printf(sc->sc_dev, "can't create txstats ring " 2109 "DMA tag\n"); 2110 return error; 2111 } 2112 2113 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2114 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2115 &st->stats_ring_dmap); 2116 if (error) { 2117 device_printf(sc->sc_dev, "can't allocate txstats ring " 2118 "DMA mem\n"); 2119 bus_dma_tag_destroy(st->stats_ring_dtag); 2120 st->stats_ring_dtag = NULL; 2121 return error; 2122 } 2123 2124 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2125 st->stats_ring, dma_size, 2126 bwi_dma_ring_addr, &st->stats_ring_paddr, 2127 BUS_DMA_NOWAIT); 2128 if (error) { 2129 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2130 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2131 st->stats_ring_dmap); 2132 bus_dma_tag_destroy(st->stats_ring_dtag); 2133 st->stats_ring_dtag = NULL; 2134 return error; 2135 } 2136 2137 /* 2138 * Create TX stats DMA stuffs 2139 */ 2140 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2141 BWI_ALIGN); 2142 2143 error = bus_dma_tag_create(sc->sc_parent_dtag, 2144 BWI_ALIGN, 2145 0, 2146 BUS_SPACE_MAXADDR, 2147 BUS_SPACE_MAXADDR, 2148 NULL, NULL, 2149 dma_size, 2150 1, 2151 dma_size, 2152 0, 2153 NULL, NULL, 2154 &st->stats_dtag); 2155 if (error) { 2156 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2157 return error; 2158 } 2159 2160 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2161 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2162 &st->stats_dmap); 2163 if (error) { 2164 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2165 bus_dma_tag_destroy(st->stats_dtag); 2166 st->stats_dtag = NULL; 2167 return error; 2168 } 2169 2170 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2171 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2172 BUS_DMA_NOWAIT); 2173 if (error) { 2174 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2175 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2176 bus_dma_tag_destroy(st->stats_dtag); 2177 st->stats_dtag = NULL; 2178 return error; 2179 } 2180 2181 st->stats_ctrl_base = ctrl_base; 2182 return 0; 2183} 2184 2185static void 2186bwi_dma_txstats_free(struct bwi_softc *sc) 2187{ 2188 struct bwi_txstats_data *st; 2189 2190 if (sc->sc_txstats == NULL) 2191 return; 2192 st = sc->sc_txstats; 2193 2194 if (st->stats_ring_dtag != NULL) { 2195 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2196 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2197 st->stats_ring_dmap); 2198 bus_dma_tag_destroy(st->stats_ring_dtag); 2199 } 2200 2201 if (st->stats_dtag != NULL) { 2202 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2203 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2204 bus_dma_tag_destroy(st->stats_dtag); 2205 } 2206 2207 free(st, M_DEVBUF); 2208} 2209 2210static void 2211bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2212{ 2213 KASSERT(nseg == 1, ("too many segments\n")); 2214 *((bus_addr_t *)arg) = seg->ds_addr; 2215} 2216 2217static int 2218bwi_dma_mbuf_create(struct bwi_softc *sc) 2219{ 2220 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2221 int i, j, k, ntx, error; 2222 2223 /* 2224 * Create TX/RX mbuf DMA tag 2225 */ 2226 error = bus_dma_tag_create(sc->sc_parent_dtag, 2227 1, 2228 0, 2229 BUS_SPACE_MAXADDR, 2230 BUS_SPACE_MAXADDR, 2231 NULL, NULL, 2232 MCLBYTES, 2233 1, 2234 MCLBYTES, 2235 BUS_DMA_ALLOCNOW, 2236 NULL, NULL, 2237 &sc->sc_buf_dtag); 2238 if (error) { 2239 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2240 return error; 2241 } 2242 2243 ntx = 0; 2244 2245 /* 2246 * Create TX mbuf DMA map 2247 */ 2248 for (i = 0; i < BWI_TX_NRING; ++i) { 2249 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2250 2251 for (j = 0; j < BWI_TX_NDESC; ++j) { 2252 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2253 &tbd->tbd_buf[j].tb_dmap); 2254 if (error) { 2255 device_printf(sc->sc_dev, "can't create " 2256 "%dth tbd, %dth DMA map\n", i, j); 2257 2258 ntx = i; 2259 for (k = 0; k < j; ++k) { 2260 bus_dmamap_destroy(sc->sc_buf_dtag, 2261 tbd->tbd_buf[k].tb_dmap); 2262 } 2263 goto fail; 2264 } 2265 } 2266 } 2267 ntx = BWI_TX_NRING; 2268 2269 /* 2270 * Create RX mbuf DMA map and a spare DMA map 2271 */ 2272 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2273 &rbd->rbd_tmp_dmap); 2274 if (error) { 2275 device_printf(sc->sc_dev, 2276 "can't create spare RX buf DMA map\n"); 2277 goto fail; 2278 } 2279 2280 for (j = 0; j < BWI_RX_NDESC; ++j) { 2281 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2282 &rbd->rbd_buf[j].rb_dmap); 2283 if (error) { 2284 device_printf(sc->sc_dev, "can't create %dth " 2285 "RX buf DMA map\n", j); 2286 2287 for (k = 0; k < j; ++k) { 2288 bus_dmamap_destroy(sc->sc_buf_dtag, 2289 rbd->rbd_buf[j].rb_dmap); 2290 } 2291 bus_dmamap_destroy(sc->sc_buf_dtag, 2292 rbd->rbd_tmp_dmap); 2293 goto fail; 2294 } 2295 } 2296 2297 return 0; 2298fail: 2299 bwi_dma_mbuf_destroy(sc, ntx, 0); 2300 return error; 2301} 2302 2303static void 2304bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2305{ 2306 int i, j; 2307 2308 if (sc->sc_buf_dtag == NULL) 2309 return; 2310 2311 for (i = 0; i < ntx; ++i) { 2312 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2313 2314 for (j = 0; j < BWI_TX_NDESC; ++j) { 2315 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2316 2317 if (tb->tb_mbuf != NULL) { 2318 bus_dmamap_unload(sc->sc_buf_dtag, 2319 tb->tb_dmap); 2320 m_freem(tb->tb_mbuf); 2321 } 2322 if (tb->tb_ni != NULL) 2323 ieee80211_free_node(tb->tb_ni); 2324 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2325 } 2326 } 2327 2328 if (nrx) { 2329 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2330 2331 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2332 for (j = 0; j < BWI_RX_NDESC; ++j) { 2333 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2334 2335 if (rb->rb_mbuf != NULL) { 2336 bus_dmamap_unload(sc->sc_buf_dtag, 2337 rb->rb_dmap); 2338 m_freem(rb->rb_mbuf); 2339 } 2340 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2341 } 2342 } 2343 2344 bus_dma_tag_destroy(sc->sc_buf_dtag); 2345 sc->sc_buf_dtag = NULL; 2346} 2347 2348static void 2349bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2350{ 2351 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2352} 2353 2354static void 2355bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2356{ 2357 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2358} 2359 2360static int 2361bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2362{ 2363 struct bwi_ring_data *rd; 2364 struct bwi_txbuf_data *tbd; 2365 uint32_t val, addr_hi, addr_lo; 2366 2367 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2368 rd = &sc->sc_tx_rdata[ring_idx]; 2369 tbd = &sc->sc_tx_bdata[ring_idx]; 2370 2371 tbd->tbd_idx = 0; 2372 tbd->tbd_used = 0; 2373 2374 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2375 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2376 BUS_DMASYNC_PREWRITE); 2377 2378 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2379 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2380 2381 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2382 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2383 BWI_TXRX32_RINGINFO_FUNC_MASK); 2384 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2385 2386 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2387 BWI_TXRX32_CTRL_ENABLE; 2388 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2389 2390 return 0; 2391} 2392 2393static void 2394bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2395 bus_addr_t paddr, int hdr_size, int ndesc) 2396{ 2397 uint32_t val, addr_hi, addr_lo; 2398 2399 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2400 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2401 2402 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2403 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2404 BWI_TXRX32_RINGINFO_FUNC_MASK); 2405 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2406 2407 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2408 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2409 BWI_TXRX32_CTRL_ENABLE; 2410 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2411 2412 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2413 (ndesc - 1) * sizeof(struct bwi_desc32)); 2414} 2415 2416static int 2417bwi_init_rx_ring32(struct bwi_softc *sc) 2418{ 2419 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2420 int i, error; 2421 2422 sc->sc_rx_bdata.rbd_idx = 0; 2423 2424 for (i = 0; i < BWI_RX_NDESC; ++i) { 2425 error = bwi_newbuf(sc, i, 1); 2426 if (error) { 2427 device_printf(sc->sc_dev, 2428 "can't allocate %dth RX buffer\n", i); 2429 return error; 2430 } 2431 } 2432 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2433 BUS_DMASYNC_PREWRITE); 2434 2435 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2436 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2437 return 0; 2438} 2439 2440static int 2441bwi_init_txstats32(struct bwi_softc *sc) 2442{ 2443 struct bwi_txstats_data *st = sc->sc_txstats; 2444 bus_addr_t stats_paddr; 2445 int i; 2446 2447 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2448 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2449 2450 st->stats_idx = 0; 2451 2452 stats_paddr = st->stats_paddr; 2453 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2454 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2455 stats_paddr, sizeof(struct bwi_txstats), 0); 2456 stats_paddr += sizeof(struct bwi_txstats); 2457 } 2458 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2459 BUS_DMASYNC_PREWRITE); 2460 2461 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2462 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2463 return 0; 2464} 2465 2466static void 2467bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2468 int buf_len) 2469{ 2470 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2471 2472 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2473 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2474 paddr, buf_len, 0); 2475} 2476 2477static void 2478bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2479 int buf_idx, bus_addr_t paddr, int buf_len) 2480{ 2481 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2482 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2483 paddr, buf_len, 1); 2484} 2485 2486static int 2487bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2488{ 2489 /* TODO:64 */ 2490 return EOPNOTSUPP; 2491} 2492 2493static int 2494bwi_init_rx_ring64(struct bwi_softc *sc) 2495{ 2496 /* TODO:64 */ 2497 return EOPNOTSUPP; 2498} 2499 2500static int 2501bwi_init_txstats64(struct bwi_softc *sc) 2502{ 2503 /* TODO:64 */ 2504 return EOPNOTSUPP; 2505} 2506 2507static void 2508bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2509 int buf_len) 2510{ 2511 /* TODO:64 */ 2512} 2513 2514static void 2515bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2516 int buf_idx, bus_addr_t paddr, int buf_len) 2517{ 2518 /* TODO:64 */ 2519} 2520 2521static void 2522bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2523 bus_size_t mapsz __unused, int error) 2524{ 2525 if (!error) { 2526 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2527 *((bus_addr_t *)arg) = seg->ds_addr; 2528 } 2529} 2530 2531static int 2532bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2533{ 2534 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2535 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2536 struct bwi_rxbuf_hdr *hdr; 2537 bus_dmamap_t map; 2538 bus_addr_t paddr; 2539 struct mbuf *m; 2540 int error; 2541 2542 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2543 2544 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2545 if (m == NULL) { 2546 error = ENOBUFS; 2547 2548 /* 2549 * If the NIC is up and running, we need to: 2550 * - Clear RX buffer's header. 2551 * - Restore RX descriptor settings. 2552 */ 2553 if (init) 2554 return error; 2555 else 2556 goto back; 2557 } 2558 m->m_len = m->m_pkthdr.len = MCLBYTES; 2559 2560 /* 2561 * Try to load RX buf into temporary DMA map 2562 */ 2563 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2564 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2565 if (error) { 2566 m_freem(m); 2567 2568 /* 2569 * See the comment above 2570 */ 2571 if (init) 2572 return error; 2573 else 2574 goto back; 2575 } 2576 2577 if (!init) 2578 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2579 rxbuf->rb_mbuf = m; 2580 rxbuf->rb_paddr = paddr; 2581 2582 /* 2583 * Swap RX buf's DMA map with the loaded temporary one 2584 */ 2585 map = rxbuf->rb_dmap; 2586 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2587 rbd->rbd_tmp_dmap = map; 2588 2589back: 2590 /* 2591 * Clear RX buf header 2592 */ 2593 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2594 bzero(hdr, sizeof(*hdr)); 2595 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2596 2597 /* 2598 * Setup RX buf descriptor 2599 */ 2600 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2601 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2602 return error; 2603} 2604 2605static void 2606bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2607 const uint8_t *addr) 2608{ 2609 int i; 2610 2611 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2612 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2613 2614 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2615 uint16_t addr_val; 2616 2617 addr_val = (uint16_t)addr[i * 2] | 2618 (((uint16_t)addr[(i * 2) + 1]) << 8); 2619 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2620 } 2621} 2622 2623static int 2624bwi_rxeof(struct bwi_softc *sc, int end_idx) 2625{ 2626 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2627 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2628 struct ifnet *ifp = sc->sc_ifp; 2629 struct ieee80211com *ic = ifp->if_l2com; 2630 int idx, rx_data = 0; 2631 2632 idx = rbd->rbd_idx; 2633 while (idx != end_idx) { 2634 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2635 struct bwi_rxbuf_hdr *hdr; 2636 struct ieee80211_frame_min *wh; 2637 struct ieee80211_node *ni; 2638 struct mbuf *m; 2639 uint32_t plcp; 2640 uint16_t flags2; 2641 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2642 2643 m = rb->rb_mbuf; 2644 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2645 BUS_DMASYNC_POSTREAD); 2646 2647 if (bwi_newbuf(sc, idx, 0)) { 2648 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2649 goto next; 2650 } 2651 2652 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2653 flags2 = le16toh(hdr->rxh_flags2); 2654 2655 hdr_extra = 0; 2656 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2657 hdr_extra = 2; 2658 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2659 2660 buflen = le16toh(hdr->rxh_buflen); 2661 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2662 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2663 __func__, hdr_extra); 2664 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2665 m_freem(m); 2666 goto next; 2667 } 2668 2669 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2670 rssi = bwi_calc_rssi(sc, hdr); 2671 noise = bwi_calc_noise(sc); 2672 2673 m->m_pkthdr.rcvif = ifp; 2674 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2675 m_adj(m, sizeof(*hdr) + wh_ofs); 2676 2677 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2678 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2679 else 2680 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2681 2682 /* RX radio tap */ 2683 if (ieee80211_radiotap_active(ic)) 2684 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2685 2686 m_adj(m, -IEEE80211_CRC_LEN); 2687 2688 BWI_UNLOCK(sc); 2689 2690 wh = mtod(m, struct ieee80211_frame_min *); 2691 ni = ieee80211_find_rxnode(ic, wh); 2692 if (ni != NULL) { 2693 type = ieee80211_input(ni, m, rssi - noise, noise); 2694 ieee80211_free_node(ni); 2695 } else 2696 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2697 if (type == IEEE80211_FC0_TYPE_DATA) { 2698 rx_data = 1; 2699 sc->sc_rx_rate = rate; 2700 } 2701 2702 BWI_LOCK(sc); 2703next: 2704 idx = (idx + 1) % BWI_RX_NDESC; 2705 2706 if (sc->sc_flags & BWI_F_STOP) { 2707 /* 2708 * Take the fast lane, don't do 2709 * any damage to softc 2710 */ 2711 return -1; 2712 } 2713 } 2714 2715 rbd->rbd_idx = idx; 2716 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2717 BUS_DMASYNC_PREWRITE); 2718 2719 return rx_data; 2720} 2721 2722static int 2723bwi_rxeof32(struct bwi_softc *sc) 2724{ 2725 uint32_t val, rx_ctrl; 2726 int end_idx, rx_data; 2727 2728 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2729 2730 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2731 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2732 sizeof(struct bwi_desc32); 2733 2734 rx_data = bwi_rxeof(sc, end_idx); 2735 if (rx_data >= 0) { 2736 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2737 end_idx * sizeof(struct bwi_desc32)); 2738 } 2739 return rx_data; 2740} 2741 2742static int 2743bwi_rxeof64(struct bwi_softc *sc) 2744{ 2745 /* TODO:64 */ 2746 return 0; 2747} 2748 2749static void 2750bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2751{ 2752 int i; 2753 2754 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2755 2756#define NRETRY 10 2757 2758 for (i = 0; i < NRETRY; ++i) { 2759 uint32_t status; 2760 2761 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2762 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2763 BWI_RX32_STATUS_STATE_DISABLED) 2764 break; 2765 2766 DELAY(1000); 2767 } 2768 if (i == NRETRY) 2769 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2770 2771#undef NRETRY 2772 2773 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2774} 2775 2776static void 2777bwi_free_txstats32(struct bwi_softc *sc) 2778{ 2779 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2780} 2781 2782static void 2783bwi_free_rx_ring32(struct bwi_softc *sc) 2784{ 2785 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2786 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2787 int i; 2788 2789 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2790 2791 for (i = 0; i < BWI_RX_NDESC; ++i) { 2792 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2793 2794 if (rb->rb_mbuf != NULL) { 2795 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2796 m_freem(rb->rb_mbuf); 2797 rb->rb_mbuf = NULL; 2798 } 2799 } 2800} 2801 2802static void 2803bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2804{ 2805 struct bwi_ring_data *rd; 2806 struct bwi_txbuf_data *tbd; 2807 struct ifnet *ifp = sc->sc_ifp; 2808 uint32_t state, val; 2809 int i; 2810 2811 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2812 rd = &sc->sc_tx_rdata[ring_idx]; 2813 tbd = &sc->sc_tx_bdata[ring_idx]; 2814 2815#define NRETRY 10 2816 2817 for (i = 0; i < NRETRY; ++i) { 2818 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2819 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2820 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2821 state == BWI_TX32_STATUS_STATE_IDLE || 2822 state == BWI_TX32_STATUS_STATE_STOPPED) 2823 break; 2824 2825 DELAY(1000); 2826 } 2827 if (i == NRETRY) { 2828 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2829 __func__, ring_idx); 2830 } 2831 2832 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2833 for (i = 0; i < NRETRY; ++i) { 2834 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2835 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2836 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2837 break; 2838 2839 DELAY(1000); 2840 } 2841 if (i == NRETRY) 2842 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2843 __func__, ring_idx); 2844 2845#undef NRETRY 2846 2847 DELAY(1000); 2848 2849 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2850 2851 for (i = 0; i < BWI_TX_NDESC; ++i) { 2852 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2853 2854 if (tb->tb_mbuf != NULL) { 2855 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2856 m_freem(tb->tb_mbuf); 2857 tb->tb_mbuf = NULL; 2858 } 2859 if (tb->tb_ni != NULL) { 2860 ieee80211_free_node(tb->tb_ni); 2861 tb->tb_ni = NULL; 2862 } 2863 } 2864} 2865 2866static void 2867bwi_free_txstats64(struct bwi_softc *sc) 2868{ 2869 /* TODO:64 */ 2870} 2871 2872static void 2873bwi_free_rx_ring64(struct bwi_softc *sc) 2874{ 2875 /* TODO:64 */ 2876} 2877 2878static void 2879bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2880{ 2881 /* TODO:64 */ 2882} 2883 2884/* XXX does not belong here */ 2885#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2886#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2887 2888static __inline void 2889bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2890{ 2891 uint32_t plcp; 2892 2893 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2894 IEEE80211_OFDM_PLCP_RATE_MASK) | 2895 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2896 *plcp0 = htole32(plcp); 2897} 2898 2899static __inline void 2900bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2901 uint8_t rate) 2902{ 2903 int len, service, pkt_bitlen; 2904 2905 pkt_bitlen = pkt_len * NBBY; 2906 len = howmany(pkt_bitlen * 2, rate); 2907 2908 service = IEEE80211_PLCP_SERVICE_LOCKED; 2909 if (rate == (11 * 2)) { 2910 int pkt_bitlen1; 2911 2912 /* 2913 * PLCP service field needs to be adjusted, 2914 * if TX rate is 11Mbytes/s 2915 */ 2916 pkt_bitlen1 = len * 11; 2917 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2918 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2919 } 2920 2921 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2922 plcp->i_service = service; 2923 plcp->i_length = htole16(len); 2924 /* NOTE: do NOT touch i_crc */ 2925} 2926 2927static __inline void 2928bwi_plcp_header(const struct ieee80211_rate_table *rt, 2929 void *plcp, int pkt_len, uint8_t rate) 2930{ 2931 enum ieee80211_phytype modtype; 2932 2933 /* 2934 * Assume caller has zeroed 'plcp' 2935 */ 2936 modtype = ieee80211_rate2phytype(rt, rate); 2937 if (modtype == IEEE80211_T_OFDM) 2938 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2939 else if (modtype == IEEE80211_T_DS) 2940 bwi_ds_plcp_header(plcp, pkt_len, rate); 2941 else 2942 panic("unsupport modulation type %u\n", modtype); 2943} 2944 2945static int 2946bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2947 struct ieee80211_node *ni) 2948{ 2949 struct ieee80211vap *vap = ni->ni_vap; 2950 struct ifnet *ifp = sc->sc_ifp; 2951 struct ieee80211com *ic = ifp->if_l2com; 2952 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2953 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2954 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2955 struct bwi_mac *mac; 2956 struct bwi_txbuf_hdr *hdr; 2957 struct ieee80211_frame *wh; 2958 const struct ieee80211_txparam *tp; 2959 uint8_t rate, rate_fb; 2960 uint32_t mac_ctrl; 2961 uint16_t phy_ctrl; 2962 bus_addr_t paddr; 2963 int type, ismcast, pkt_len, error, rix; 2964#if 0 2965 const uint8_t *p; 2966 int i; 2967#endif 2968 2969 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2970 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2971 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2972 2973 wh = mtod(m, struct ieee80211_frame *); 2974 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2975 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2976 2977 /* Get 802.11 frame len before prepending TX header */ 2978 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2979 2980 /* 2981 * Find TX rate 2982 */ 2983 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2984 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2985 rate = rate_fb = tp->mgmtrate; 2986 } else if (ismcast) { 2987 rate = rate_fb = tp->mcastrate; 2988 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2989 rate = rate_fb = tp->ucastrate; 2990 } else { 2991 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2992 rate = ni->ni_txrate; 2993 2994 if (rix > 0) { 2995 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2996 IEEE80211_RATE_VAL; 2997 } else { 2998 rate_fb = rate; 2999 } 3000 } 3001 tb->tb_rate[0] = rate; 3002 tb->tb_rate[1] = rate_fb; 3003 sc->sc_tx_rate = rate; 3004 3005 /* 3006 * TX radio tap 3007 */ 3008 if (ieee80211_radiotap_active_vap(vap)) { 3009 sc->sc_tx_th.wt_flags = 0; 3010 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3011 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3012 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3013 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3014 rate != (1 * 2)) { 3015 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3016 } 3017 sc->sc_tx_th.wt_rate = rate; 3018 3019 ieee80211_radiotap_tx(vap, m); 3020 } 3021 3022 /* 3023 * Setup the embedded TX header 3024 */ 3025 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3026 if (m == NULL) { 3027 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3028 return ENOBUFS; 3029 } 3030 hdr = mtod(m, struct bwi_txbuf_hdr *); 3031 3032 bzero(hdr, sizeof(*hdr)); 3033 3034 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3035 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3036 3037 if (!ismcast) { 3038 uint16_t dur; 3039 3040 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3041 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3042 3043 hdr->txh_fb_duration = htole16(dur); 3044 } 3045 3046 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3047 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3048 3049 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3050 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3051 3052 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3053 BWI_TXH_PHY_C_ANTMODE_MASK); 3054 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3055 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3056 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3057 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3058 3059 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3060 if (!ismcast) 3061 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3062 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3063 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3064 3065 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3066 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3067 3068 /* Catch any further usage */ 3069 hdr = NULL; 3070 wh = NULL; 3071 3072 /* DMA load */ 3073 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3074 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3075 if (error && error != EFBIG) { 3076 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3077 __func__, error); 3078 goto back; 3079 } 3080 3081 if (error) { /* error == EFBIG */ 3082 struct mbuf *m_new; 3083 3084 m_new = m_defrag(m, M_NOWAIT); 3085 if (m_new == NULL) { 3086 if_printf(ifp, "%s: can't defrag TX buffer\n", 3087 __func__); 3088 error = ENOBUFS; 3089 goto back; 3090 } else { 3091 m = m_new; 3092 } 3093 3094 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3095 bwi_dma_buf_addr, &paddr, 3096 BUS_DMA_NOWAIT); 3097 if (error) { 3098 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3099 __func__, error); 3100 goto back; 3101 } 3102 } 3103 error = 0; 3104 3105 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3106 3107 tb->tb_mbuf = m; 3108 tb->tb_ni = ni; 3109 3110#if 0 3111 p = mtod(m, const uint8_t *); 3112 for (i = 0; i < m->m_pkthdr.len; ++i) { 3113 if (i != 0 && i % 8 == 0) 3114 printf("\n"); 3115 printf("%02x ", p[i]); 3116 } 3117 printf("\n"); 3118#endif 3119 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3120 idx, pkt_len, m->m_pkthdr.len); 3121 3122 /* Setup TX descriptor */ 3123 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3124 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3125 BUS_DMASYNC_PREWRITE); 3126 3127 /* Kick start */ 3128 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3129 3130back: 3131 if (error) 3132 m_freem(m); 3133 return error; 3134} 3135 3136static int 3137bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3138 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3139{ 3140 struct ifnet *ifp = sc->sc_ifp; 3141 struct ieee80211vap *vap = ni->ni_vap; 3142 struct ieee80211com *ic = ni->ni_ic; 3143 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3144 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3145 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3146 struct bwi_mac *mac; 3147 struct bwi_txbuf_hdr *hdr; 3148 struct ieee80211_frame *wh; 3149 uint8_t rate, rate_fb; 3150 uint32_t mac_ctrl; 3151 uint16_t phy_ctrl; 3152 bus_addr_t paddr; 3153 int ismcast, pkt_len, error; 3154 3155 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3156 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3157 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3158 3159 wh = mtod(m, struct ieee80211_frame *); 3160 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3161 3162 /* Get 802.11 frame len before prepending TX header */ 3163 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3164 3165 /* 3166 * Find TX rate 3167 */ 3168 rate = params->ibp_rate0; 3169 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3170 /* XXX fall back to mcast/mgmt rate? */ 3171 m_freem(m); 3172 return EINVAL; 3173 } 3174 if (params->ibp_try1 != 0) { 3175 rate_fb = params->ibp_rate1; 3176 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3177 /* XXX fall back to rate0? */ 3178 m_freem(m); 3179 return EINVAL; 3180 } 3181 } else 3182 rate_fb = rate; 3183 tb->tb_rate[0] = rate; 3184 tb->tb_rate[1] = rate_fb; 3185 sc->sc_tx_rate = rate; 3186 3187 /* 3188 * TX radio tap 3189 */ 3190 if (ieee80211_radiotap_active_vap(vap)) { 3191 sc->sc_tx_th.wt_flags = 0; 3192 /* XXX IEEE80211_BPF_CRYPTO */ 3193 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3194 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3195 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3196 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3197 sc->sc_tx_th.wt_rate = rate; 3198 3199 ieee80211_radiotap_tx(vap, m); 3200 } 3201 3202 /* 3203 * Setup the embedded TX header 3204 */ 3205 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3206 if (m == NULL) { 3207 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3208 return ENOBUFS; 3209 } 3210 hdr = mtod(m, struct bwi_txbuf_hdr *); 3211 3212 bzero(hdr, sizeof(*hdr)); 3213 3214 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3215 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3216 3217 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3218 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3219 uint16_t dur; 3220 3221 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3222 3223 hdr->txh_fb_duration = htole16(dur); 3224 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3225 } 3226 3227 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3228 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3229 3230 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3231 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3232 3233 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3234 BWI_TXH_PHY_C_ANTMODE_MASK); 3235 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3236 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3237 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3238 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3239 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3240 3241 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3242 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3243 3244 /* Catch any further usage */ 3245 hdr = NULL; 3246 wh = NULL; 3247 3248 /* DMA load */ 3249 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3250 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3251 if (error != 0) { 3252 struct mbuf *m_new; 3253 3254 if (error != EFBIG) { 3255 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3256 __func__, error); 3257 goto back; 3258 } 3259 m_new = m_defrag(m, M_NOWAIT); 3260 if (m_new == NULL) { 3261 if_printf(ifp, "%s: can't defrag TX buffer\n", 3262 __func__); 3263 error = ENOBUFS; 3264 goto back; 3265 } 3266 m = m_new; 3267 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3268 bwi_dma_buf_addr, &paddr, 3269 BUS_DMA_NOWAIT); 3270 if (error) { 3271 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3272 __func__, error); 3273 goto back; 3274 } 3275 } 3276 3277 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3278 3279 tb->tb_mbuf = m; 3280 tb->tb_ni = ni; 3281 3282 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3283 idx, pkt_len, m->m_pkthdr.len); 3284 3285 /* Setup TX descriptor */ 3286 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3287 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3288 BUS_DMASYNC_PREWRITE); 3289 3290 /* Kick start */ 3291 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3292back: 3293 if (error) 3294 m_freem(m); 3295 return error; 3296} 3297 3298static void 3299bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3300{ 3301 idx = (idx + 1) % BWI_TX_NDESC; 3302 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3303 idx * sizeof(struct bwi_desc32)); 3304} 3305 3306static void 3307bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3308{ 3309 /* TODO:64 */ 3310} 3311 3312static void 3313bwi_txeof_status32(struct bwi_softc *sc) 3314{ 3315 struct ifnet *ifp = sc->sc_ifp; 3316 uint32_t val, ctrl_base; 3317 int end_idx; 3318 3319 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3320 3321 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3322 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3323 sizeof(struct bwi_desc32); 3324 3325 bwi_txeof_status(sc, end_idx); 3326 3327 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3328 end_idx * sizeof(struct bwi_desc32)); 3329 3330 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3331 ifp->if_start(ifp); 3332} 3333 3334static void 3335bwi_txeof_status64(struct bwi_softc *sc) 3336{ 3337 /* TODO:64 */ 3338} 3339 3340static void 3341_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3342{ 3343 struct ifnet *ifp = sc->sc_ifp; 3344 struct bwi_txbuf_data *tbd; 3345 struct bwi_txbuf *tb; 3346 int ring_idx, buf_idx; 3347 struct ieee80211_node *ni; 3348 struct ieee80211vap *vap; 3349 3350 if (tx_id == 0) { 3351 if_printf(ifp, "%s: zero tx id\n", __func__); 3352 return; 3353 } 3354 3355 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3356 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3357 3358 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3359 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3360 3361 tbd = &sc->sc_tx_bdata[ring_idx]; 3362 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3363 tbd->tbd_used--; 3364 3365 tb = &tbd->tbd_buf[buf_idx]; 3366 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3367 "acked %d, data_txcnt %d, ni %p\n", 3368 buf_idx, acked, data_txcnt, tb->tb_ni); 3369 3370 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3371 3372 ni = tb->tb_ni; 3373 if (tb->tb_ni != NULL) { 3374 const struct bwi_txbuf_hdr *hdr = 3375 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3376 vap = ni->ni_vap; 3377 3378 /* NB: update rate control only for unicast frames */ 3379 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3380 /* 3381 * Feed back 'acked and data_txcnt'. Note that the 3382 * generic AMRR code only understands one tx rate 3383 * and the estimator doesn't handle real retry counts 3384 * well so to avoid over-aggressive downshifting we 3385 * treat any number of retries as "1". 3386 */ 3387 ieee80211_ratectl_tx_complete(vap, ni, 3388 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3389 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3390 } 3391 3392 /* 3393 * Do any tx complete callback. Note this must 3394 * be done before releasing the node reference. 3395 */ 3396 if (tb->tb_mbuf->m_flags & M_TXCB) 3397 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3398 3399 ieee80211_free_node(tb->tb_ni); 3400 tb->tb_ni = NULL; 3401 } 3402 m_freem(tb->tb_mbuf); 3403 tb->tb_mbuf = NULL; 3404 3405 if (tbd->tbd_used == 0) 3406 sc->sc_tx_timer = 0; 3407 3408 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3409} 3410 3411static void 3412bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3413{ 3414 struct bwi_txstats_data *st = sc->sc_txstats; 3415 int idx; 3416 3417 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3418 3419 idx = st->stats_idx; 3420 while (idx != end_idx) { 3421 const struct bwi_txstats *stats = &st->stats[idx]; 3422 3423 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3424 int data_txcnt; 3425 3426 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3427 BWI_TXS_TXCNT_DATA); 3428 _bwi_txeof(sc, le16toh(stats->txs_id), 3429 stats->txs_flags & BWI_TXS_F_ACKED, 3430 data_txcnt); 3431 } 3432 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3433 } 3434 st->stats_idx = idx; 3435} 3436 3437static void 3438bwi_txeof(struct bwi_softc *sc) 3439{ 3440 struct ifnet *ifp = sc->sc_ifp; 3441 3442 for (;;) { 3443 uint32_t tx_status0, tx_status1; 3444 uint16_t tx_id; 3445 int data_txcnt; 3446 3447 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3448 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3449 break; 3450 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3451 3452 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3453 data_txcnt = __SHIFTOUT(tx_status0, 3454 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3455 3456 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3457 continue; 3458 3459 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3460 data_txcnt); 3461 } 3462 3463 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3464 ifp->if_start(ifp); 3465} 3466 3467static int 3468bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3469{ 3470 bwi_power_on(sc, 1); 3471 return bwi_set_clock_mode(sc, clk_mode); 3472} 3473 3474static void 3475bwi_bbp_power_off(struct bwi_softc *sc) 3476{ 3477 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3478 bwi_power_off(sc, 1); 3479} 3480 3481static int 3482bwi_get_pwron_delay(struct bwi_softc *sc) 3483{ 3484 struct bwi_regwin *com, *old; 3485 struct bwi_clock_freq freq; 3486 uint32_t val; 3487 int error; 3488 3489 com = &sc->sc_com_regwin; 3490 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3491 3492 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3493 return 0; 3494 3495 error = bwi_regwin_switch(sc, com, &old); 3496 if (error) 3497 return error; 3498 3499 bwi_get_clock_freq(sc, &freq); 3500 3501 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3502 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3503 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3504 3505 return bwi_regwin_switch(sc, old, NULL); 3506} 3507 3508static int 3509bwi_bus_attach(struct bwi_softc *sc) 3510{ 3511 struct bwi_regwin *bus, *old; 3512 int error; 3513 3514 bus = &sc->sc_bus_regwin; 3515 3516 error = bwi_regwin_switch(sc, bus, &old); 3517 if (error) 3518 return error; 3519 3520 if (!bwi_regwin_is_enabled(sc, bus)) 3521 bwi_regwin_enable(sc, bus, 0); 3522 3523 /* Disable interripts */ 3524 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3525 3526 return bwi_regwin_switch(sc, old, NULL); 3527} 3528 3529static const char * 3530bwi_regwin_name(const struct bwi_regwin *rw) 3531{ 3532 switch (rw->rw_type) { 3533 case BWI_REGWIN_T_COM: 3534 return "COM"; 3535 case BWI_REGWIN_T_BUSPCI: 3536 return "PCI"; 3537 case BWI_REGWIN_T_MAC: 3538 return "MAC"; 3539 case BWI_REGWIN_T_BUSPCIE: 3540 return "PCIE"; 3541 } 3542 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3543 return NULL; 3544} 3545 3546static uint32_t 3547bwi_regwin_disable_bits(struct bwi_softc *sc) 3548{ 3549 uint32_t busrev; 3550 3551 /* XXX cache this */ 3552 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3553 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3554 "bus rev %u\n", busrev); 3555 3556 if (busrev == BWI_BUSREV_0) 3557 return BWI_STATE_LO_DISABLE1; 3558 else if (busrev == BWI_BUSREV_1) 3559 return BWI_STATE_LO_DISABLE2; 3560 else 3561 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3562} 3563 3564int 3565bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3566{ 3567 uint32_t val, disable_bits; 3568 3569 disable_bits = bwi_regwin_disable_bits(sc); 3570 val = CSR_READ_4(sc, BWI_STATE_LO); 3571 3572 if ((val & (BWI_STATE_LO_CLOCK | 3573 BWI_STATE_LO_RESET | 3574 disable_bits)) == BWI_STATE_LO_CLOCK) { 3575 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3576 bwi_regwin_name(rw)); 3577 return 1; 3578 } else { 3579 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3580 bwi_regwin_name(rw)); 3581 return 0; 3582 } 3583} 3584 3585void 3586bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3587{ 3588 uint32_t state_lo, disable_bits; 3589 int i; 3590 3591 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3592 3593 /* 3594 * If current regwin is in 'reset' state, it was already disabled. 3595 */ 3596 if (state_lo & BWI_STATE_LO_RESET) { 3597 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3598 "%s was already disabled\n", bwi_regwin_name(rw)); 3599 return; 3600 } 3601 3602 disable_bits = bwi_regwin_disable_bits(sc); 3603 3604 /* 3605 * Disable normal clock 3606 */ 3607 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3608 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3609 3610 /* 3611 * Wait until normal clock is disabled 3612 */ 3613#define NRETRY 1000 3614 for (i = 0; i < NRETRY; ++i) { 3615 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3616 if (state_lo & disable_bits) 3617 break; 3618 DELAY(10); 3619 } 3620 if (i == NRETRY) { 3621 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3622 bwi_regwin_name(rw)); 3623 } 3624 3625 for (i = 0; i < NRETRY; ++i) { 3626 uint32_t state_hi; 3627 3628 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3629 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3630 break; 3631 DELAY(10); 3632 } 3633 if (i == NRETRY) { 3634 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3635 bwi_regwin_name(rw)); 3636 } 3637#undef NRETRY 3638 3639 /* 3640 * Reset and disable regwin with gated clock 3641 */ 3642 state_lo = BWI_STATE_LO_RESET | disable_bits | 3643 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3644 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3645 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3646 3647 /* Flush pending bus write */ 3648 CSR_READ_4(sc, BWI_STATE_LO); 3649 DELAY(1); 3650 3651 /* Reset and disable regwin */ 3652 state_lo = BWI_STATE_LO_RESET | disable_bits | 3653 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3654 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3655 3656 /* Flush pending bus write */ 3657 CSR_READ_4(sc, BWI_STATE_LO); 3658 DELAY(1); 3659} 3660 3661void 3662bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3663{ 3664 uint32_t state_lo, state_hi, imstate; 3665 3666 bwi_regwin_disable(sc, rw, flags); 3667 3668 /* Reset regwin with gated clock */ 3669 state_lo = BWI_STATE_LO_RESET | 3670 BWI_STATE_LO_CLOCK | 3671 BWI_STATE_LO_GATED_CLOCK | 3672 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3673 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3674 3675 /* Flush pending bus write */ 3676 CSR_READ_4(sc, BWI_STATE_LO); 3677 DELAY(1); 3678 3679 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3680 if (state_hi & BWI_STATE_HI_SERROR) 3681 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3682 3683 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3684 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3685 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3686 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3687 } 3688 3689 /* Enable regwin with gated clock */ 3690 state_lo = BWI_STATE_LO_CLOCK | 3691 BWI_STATE_LO_GATED_CLOCK | 3692 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3693 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3694 3695 /* Flush pending bus write */ 3696 CSR_READ_4(sc, BWI_STATE_LO); 3697 DELAY(1); 3698 3699 /* Enable regwin with normal clock */ 3700 state_lo = BWI_STATE_LO_CLOCK | 3701 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3702 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3703 3704 /* Flush pending bus write */ 3705 CSR_READ_4(sc, BWI_STATE_LO); 3706 DELAY(1); 3707} 3708 3709static void 3710bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3711{ 3712 struct ifnet *ifp = sc->sc_ifp; 3713 struct bwi_mac *mac; 3714 struct bwi_myaddr_bssid buf; 3715 const uint8_t *p; 3716 uint32_t val; 3717 int n, i; 3718 3719 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3720 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3721 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3722 3723 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3724 3725 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3726 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3727 3728 n = sizeof(buf) / sizeof(val); 3729 p = (const uint8_t *)&buf; 3730 for (i = 0; i < n; ++i) { 3731 int j; 3732 3733 val = 0; 3734 for (j = 0; j < sizeof(val); ++j) 3735 val |= ((uint32_t)(*p++)) << (j * 8); 3736 3737 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3738 } 3739} 3740 3741static void 3742bwi_updateslot(struct ieee80211com *ic) 3743{ 3744 struct bwi_softc *sc = ic->ic_softc; 3745 struct bwi_mac *mac; 3746 3747 BWI_LOCK(sc); 3748 if (ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) { 3749 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3750 3751 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3752 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3753 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3754 3755 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3756 } 3757 BWI_UNLOCK(sc); 3758} 3759 3760static void 3761bwi_calibrate(void *xsc) 3762{ 3763 struct bwi_softc *sc = xsc; 3764#ifdef INVARIANTS 3765 struct ifnet *ifp = sc->sc_ifp; 3766 struct ieee80211com *ic = ifp->if_l2com; 3767#endif 3768 struct bwi_mac *mac; 3769 3770 BWI_ASSERT_LOCKED(sc); 3771 3772 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3773 ("opmode %d", ic->ic_opmode)); 3774 3775 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3776 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3777 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3778 3779 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3780 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3781 3782 /* XXX 15 seconds */ 3783 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3784} 3785 3786static int 3787bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3788{ 3789 struct bwi_mac *mac; 3790 3791 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3792 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3793 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3794 3795 return bwi_rf_calc_rssi(mac, hdr); 3796} 3797 3798static int 3799bwi_calc_noise(struct bwi_softc *sc) 3800{ 3801 struct bwi_mac *mac; 3802 3803 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3804 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3805 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3806 3807 return bwi_rf_calc_noise(mac); 3808} 3809 3810static __inline uint8_t 3811bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3812{ 3813 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3814 return (ieee80211_plcp2rate(plcp, type)); 3815} 3816 3817static void 3818bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3819 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3820{ 3821 const struct ieee80211_frame_min *wh; 3822 3823 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3824 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3825 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3826 3827 wh = mtod(m, const struct ieee80211_frame_min *); 3828 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3829 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3830 3831 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3832 sc->sc_rx_th.wr_rate = rate; 3833 sc->sc_rx_th.wr_antsignal = rssi; 3834 sc->sc_rx_th.wr_antnoise = noise; 3835} 3836 3837static void 3838bwi_led_attach(struct bwi_softc *sc) 3839{ 3840 const uint8_t *led_act = NULL; 3841 uint16_t gpio, val[BWI_LED_MAX]; 3842 int i; 3843 3844#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3845 3846 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3847 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3848 led_act = bwi_vendor_led_act[i].led_act; 3849 break; 3850 } 3851 } 3852 if (led_act == NULL) 3853 led_act = bwi_default_led_act; 3854 3855#undef N 3856 3857 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3858 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3859 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3860 3861 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3862 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3863 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3864 3865 for (i = 0; i < BWI_LED_MAX; ++i) { 3866 struct bwi_led *led = &sc->sc_leds[i]; 3867 3868 if (val[i] == 0xff) { 3869 led->l_act = led_act[i]; 3870 } else { 3871 if (val[i] & BWI_LED_ACT_LOW) 3872 led->l_flags |= BWI_LED_F_ACTLOW; 3873 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3874 } 3875 led->l_mask = (1 << i); 3876 3877 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3878 led->l_act == BWI_LED_ACT_BLINK_POLL || 3879 led->l_act == BWI_LED_ACT_BLINK) { 3880 led->l_flags |= BWI_LED_F_BLINK; 3881 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3882 led->l_flags |= BWI_LED_F_POLLABLE; 3883 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3884 led->l_flags |= BWI_LED_F_SLOW; 3885 3886 if (sc->sc_blink_led == NULL) { 3887 sc->sc_blink_led = led; 3888 if (led->l_flags & BWI_LED_F_SLOW) 3889 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3890 } 3891 } 3892 3893 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3894 "%dth led, act %d, lowact %d\n", i, 3895 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3896 } 3897 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3898} 3899 3900static __inline uint16_t 3901bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3902{ 3903 if (led->l_flags & BWI_LED_F_ACTLOW) 3904 on = !on; 3905 if (on) 3906 val |= led->l_mask; 3907 else 3908 val &= ~led->l_mask; 3909 return val; 3910} 3911 3912static void 3913bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3914{ 3915 struct ifnet *ifp = sc->sc_ifp; 3916 struct ieee80211com *ic = ifp->if_l2com; 3917 uint16_t val; 3918 int i; 3919 3920 if (nstate == IEEE80211_S_INIT) { 3921 callout_stop(&sc->sc_led_blink_ch); 3922 sc->sc_led_blinking = 0; 3923 } 3924 3925 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3926 return; 3927 3928 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3929 for (i = 0; i < BWI_LED_MAX; ++i) { 3930 struct bwi_led *led = &sc->sc_leds[i]; 3931 int on; 3932 3933 if (led->l_act == BWI_LED_ACT_UNKN || 3934 led->l_act == BWI_LED_ACT_NULL) 3935 continue; 3936 3937 if ((led->l_flags & BWI_LED_F_BLINK) && 3938 nstate != IEEE80211_S_INIT) 3939 continue; 3940 3941 switch (led->l_act) { 3942 case BWI_LED_ACT_ON: /* Always on */ 3943 on = 1; 3944 break; 3945 case BWI_LED_ACT_OFF: /* Always off */ 3946 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3947 on = 0; 3948 break; 3949 default: 3950 on = 1; 3951 switch (nstate) { 3952 case IEEE80211_S_INIT: 3953 on = 0; 3954 break; 3955 case IEEE80211_S_RUN: 3956 if (led->l_act == BWI_LED_ACT_11G && 3957 ic->ic_curmode != IEEE80211_MODE_11G) 3958 on = 0; 3959 break; 3960 default: 3961 if (led->l_act == BWI_LED_ACT_ASSOC) 3962 on = 0; 3963 break; 3964 } 3965 break; 3966 } 3967 3968 val = bwi_led_onoff(led, val, on); 3969 } 3970 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3971} 3972static void 3973bwi_led_event(struct bwi_softc *sc, int event) 3974{ 3975 struct bwi_led *led = sc->sc_blink_led; 3976 int rate; 3977 3978 if (event == BWI_LED_EVENT_POLL) { 3979 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3980 return; 3981 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3982 return; 3983 } 3984 3985 sc->sc_led_ticks = ticks; 3986 if (sc->sc_led_blinking) 3987 return; 3988 3989 switch (event) { 3990 case BWI_LED_EVENT_RX: 3991 rate = sc->sc_rx_rate; 3992 break; 3993 case BWI_LED_EVENT_TX: 3994 rate = sc->sc_tx_rate; 3995 break; 3996 case BWI_LED_EVENT_POLL: 3997 rate = 0; 3998 break; 3999 default: 4000 panic("unknown LED event %d\n", event); 4001 break; 4002 } 4003 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 4004 bwi_led_duration[rate].off_dur); 4005} 4006 4007static void 4008bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4009{ 4010 struct bwi_led *led = sc->sc_blink_led; 4011 uint16_t val; 4012 4013 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4014 val = bwi_led_onoff(led, val, 1); 4015 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4016 4017 if (led->l_flags & BWI_LED_F_SLOW) { 4018 BWI_LED_SLOWDOWN(on_dur); 4019 BWI_LED_SLOWDOWN(off_dur); 4020 } 4021 4022 sc->sc_led_blinking = 1; 4023 sc->sc_led_blink_offdur = off_dur; 4024 4025 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4026} 4027 4028static void 4029bwi_led_blink_next(void *xsc) 4030{ 4031 struct bwi_softc *sc = xsc; 4032 uint16_t val; 4033 4034 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4035 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4036 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4037 4038 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4039 bwi_led_blink_end, sc); 4040} 4041 4042static void 4043bwi_led_blink_end(void *xsc) 4044{ 4045 struct bwi_softc *sc = xsc; 4046 sc->sc_led_blinking = 0; 4047} 4048 4049static void 4050bwi_restart(void *xsc, int pending) 4051{ 4052 struct bwi_softc *sc = xsc; 4053 struct ifnet *ifp = sc->sc_ifp; 4054 4055 if_printf(ifp, "%s begin, help!\n", __func__); 4056 BWI_LOCK(sc); 4057 bwi_init_statechg(xsc, 0); 4058#if 0 4059 bwi_start_locked(ifp); 4060#endif 4061 BWI_UNLOCK(sc); 4062} 4063