if_bwi.c revision 193079
1/* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/bwi/if_bwi.c 193079 2009-05-30 01:33:05Z sam $"); 39 40#include "opt_inet.h" 41#include "opt_bwi.h" 42 43#include <sys/param.h> 44#include <sys/endian.h> 45#include <sys/kernel.h> 46#include <sys/bus.h> 47#include <sys/malloc.h> 48#include <sys/proc.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53#include <sys/systm.h> 54#include <sys/taskqueue.h> 55 56#include <net/if.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59#include <net/if_types.h> 60#include <net/if_arp.h> 61#include <net/ethernet.h> 62#include <net/if_llc.h> 63 64#include <net80211/ieee80211_var.h> 65#include <net80211/ieee80211_radiotap.h> 66#include <net80211/ieee80211_regdomain.h> 67#include <net80211/ieee80211_amrr.h> 68#include <net80211/ieee80211_phy.h> 69 70#include <net/bpf.h> 71 72#ifdef INET 73#include <netinet/in.h> 74#include <netinet/if_ether.h> 75#endif 76 77#include <machine/bus.h> 78 79#include <dev/pci/pcivar.h> 80#include <dev/pci/pcireg.h> 81 82#include <dev/bwi/bitops.h> 83#include <dev/bwi/if_bwireg.h> 84#include <dev/bwi/if_bwivar.h> 85#include <dev/bwi/bwimac.h> 86#include <dev/bwi/bwirf.h> 87 88struct bwi_clock_freq { 89 u_int clkfreq_min; 90 u_int clkfreq_max; 91}; 92 93struct bwi_myaddr_bssid { 94 uint8_t myaddr[IEEE80211_ADDR_LEN]; 95 uint8_t bssid[IEEE80211_ADDR_LEN]; 96} __packed; 97 98static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 99 const char [IFNAMSIZ], int, int, int, 100 const uint8_t [IEEE80211_ADDR_LEN], 101 const uint8_t [IEEE80211_ADDR_LEN]); 102static void bwi_vap_delete(struct ieee80211vap *); 103static void bwi_init(void *); 104static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 105static void bwi_start(struct ifnet *); 106static void bwi_start_locked(struct ifnet *); 107static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 108 const struct ieee80211_bpf_params *); 109static void bwi_watchdog(struct ifnet *); 110static void bwi_scan_start(struct ieee80211com *); 111static void bwi_set_channel(struct ieee80211com *); 112static void bwi_scan_end(struct ieee80211com *); 113static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 114static void bwi_updateslot(struct ifnet *); 115static struct ieee80211_node *bwi_node_alloc(struct ieee80211vap *, 116 const uint8_t [IEEE80211_ADDR_LEN]); 117static void bwi_newassoc(struct ieee80211_node *, int); 118static int bwi_media_change(struct ifnet *); 119 120static void bwi_calibrate(void *); 121 122static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 123static int bwi_calc_noise(struct bwi_softc *); 124static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *); 125static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *); 126static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 127 struct bwi_rxbuf_hdr *, const void *, int, int, int); 128 129static void bwi_restart(void *, int); 130static void bwi_init_statechg(struct bwi_softc *, int); 131static void bwi_stop(struct bwi_softc *, int); 132static void bwi_stop_locked(struct bwi_softc *, int); 133static int bwi_newbuf(struct bwi_softc *, int, int); 134static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *); 136static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *, 138 const struct ieee80211_bpf_params *); 139 140static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 141 bus_addr_t, int, int); 142static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 143 144static int bwi_init_tx_ring32(struct bwi_softc *, int); 145static int bwi_init_rx_ring32(struct bwi_softc *); 146static int bwi_init_txstats32(struct bwi_softc *); 147static void bwi_free_tx_ring32(struct bwi_softc *, int); 148static void bwi_free_rx_ring32(struct bwi_softc *); 149static void bwi_free_txstats32(struct bwi_softc *); 150static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 151static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 152 int, bus_addr_t, int); 153static int bwi_rxeof32(struct bwi_softc *); 154static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 155static void bwi_txeof_status32(struct bwi_softc *); 156 157static int bwi_init_tx_ring64(struct bwi_softc *, int); 158static int bwi_init_rx_ring64(struct bwi_softc *); 159static int bwi_init_txstats64(struct bwi_softc *); 160static void bwi_free_tx_ring64(struct bwi_softc *, int); 161static void bwi_free_rx_ring64(struct bwi_softc *); 162static void bwi_free_txstats64(struct bwi_softc *); 163static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 164static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 165 int, bus_addr_t, int); 166static int bwi_rxeof64(struct bwi_softc *); 167static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 168static void bwi_txeof_status64(struct bwi_softc *); 169 170static int bwi_rxeof(struct bwi_softc *, int); 171static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 172static void bwi_txeof(struct bwi_softc *); 173static void bwi_txeof_status(struct bwi_softc *, int); 174static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 175static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 176 177static int bwi_dma_alloc(struct bwi_softc *); 178static void bwi_dma_free(struct bwi_softc *); 179static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 180 struct bwi_ring_data *, bus_size_t, 181 uint32_t); 182static int bwi_dma_mbuf_create(struct bwi_softc *); 183static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 184static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 185static void bwi_dma_txstats_free(struct bwi_softc *); 186static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 187static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 188 bus_size_t, int); 189 190static void bwi_power_on(struct bwi_softc *, int); 191static int bwi_power_off(struct bwi_softc *, int); 192static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 193static int bwi_set_clock_delay(struct bwi_softc *); 194static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 195static int bwi_get_pwron_delay(struct bwi_softc *sc); 196static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 197 const uint8_t *); 198static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 199 200static void bwi_get_card_flags(struct bwi_softc *); 201static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 202 203static int bwi_bus_attach(struct bwi_softc *); 204static int bwi_bbp_attach(struct bwi_softc *); 205static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 206static void bwi_bbp_power_off(struct bwi_softc *); 207 208static const char *bwi_regwin_name(const struct bwi_regwin *); 209static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 210static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 211static int bwi_regwin_select(struct bwi_softc *, int); 212 213static void bwi_led_attach(struct bwi_softc *); 214static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 215static void bwi_led_event(struct bwi_softc *, int); 216static void bwi_led_blink_start(struct bwi_softc *, int, int); 217static void bwi_led_blink_next(void *); 218static void bwi_led_blink_end(void *); 219 220static const struct { 221 uint16_t did_min; 222 uint16_t did_max; 223 uint16_t bbp_id; 224} bwi_bbpid_map[] = { 225 { 0x4301, 0x4301, 0x4301 }, 226 { 0x4305, 0x4307, 0x4307 }, 227 { 0x4403, 0x4403, 0x4402 }, 228 { 0x4610, 0x4615, 0x4610 }, 229 { 0x4710, 0x4715, 0x4710 }, 230 { 0x4720, 0x4725, 0x4309 } 231}; 232 233static const struct { 234 uint16_t bbp_id; 235 int nregwin; 236} bwi_regwin_count[] = { 237 { 0x4301, 5 }, 238 { 0x4306, 6 }, 239 { 0x4307, 5 }, 240 { 0x4310, 8 }, 241 { 0x4401, 3 }, 242 { 0x4402, 3 }, 243 { 0x4610, 9 }, 244 { 0x4704, 9 }, 245 { 0x4710, 9 }, 246 { 0x5365, 7 } 247}; 248 249#define CLKSRC(src) \ 250[BWI_CLKSRC_ ## src] = { \ 251 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 252 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 253} 254 255static const struct { 256 u_int freq_min; 257 u_int freq_max; 258} bwi_clkfreq[BWI_CLKSRC_MAX] = { 259 CLKSRC(LP_OSC), 260 CLKSRC(CS_OSC), 261 CLKSRC(PCI) 262}; 263 264#undef CLKSRC 265 266#define VENDOR_LED_ACT(vendor) \ 267{ \ 268 .vid = PCI_VENDOR_##vendor, \ 269 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 270} 271 272static const struct { 273#define PCI_VENDOR_COMPAQ 0x0e11 274#define PCI_VENDOR_LINKSYS 0x1737 275 uint16_t vid; 276 uint8_t led_act[BWI_LED_MAX]; 277} bwi_vendor_led_act[] = { 278 VENDOR_LED_ACT(COMPAQ), 279 VENDOR_LED_ACT(LINKSYS) 280#undef PCI_VENDOR_LINKSYS 281#undef PCI_VENDOR_COMPAQ 282}; 283 284static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 285 { BWI_VENDOR_LED_ACT_DEFAULT }; 286 287#undef VENDOR_LED_ACT 288 289static const struct { 290 int on_dur; 291 int off_dur; 292} bwi_led_duration[109] = { 293 [0] = { 400, 100 }, 294 [2] = { 150, 75 }, 295 [4] = { 90, 45 }, 296 [11] = { 66, 34 }, 297 [12] = { 53, 26 }, 298 [18] = { 42, 21 }, 299 [22] = { 35, 17 }, 300 [24] = { 32, 16 }, 301 [36] = { 21, 10 }, 302 [48] = { 16, 8 }, 303 [72] = { 11, 5 }, 304 [96] = { 9, 4 }, 305 [108] = { 7, 3 } 306}; 307 308#ifdef BWI_DEBUG 309#ifdef BWI_DEBUG_VERBOSE 310static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 311#else 312static uint32_t bwi_debug; 313#endif 314TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 315#endif /* BWI_DEBUG */ 316 317static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 318 319uint16_t 320bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 321{ 322 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 323} 324 325static __inline void 326bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 327 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 328 int tx) 329{ 330 struct bwi_desc32 *desc = &desc_array[desc_idx]; 331 uint32_t ctrl, addr, addr_hi, addr_lo; 332 333 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 334 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 335 336 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 337 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 338 339 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 340 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 341 if (desc_idx == ndesc - 1) 342 ctrl |= BWI_DESC32_C_EOR; 343 if (tx) { 344 /* XXX */ 345 ctrl |= BWI_DESC32_C_FRAME_START | 346 BWI_DESC32_C_FRAME_END | 347 BWI_DESC32_C_INTR; 348 } 349 350 desc->addr = htole32(addr); 351 desc->ctrl = htole32(ctrl); 352} 353 354int 355bwi_attach(struct bwi_softc *sc) 356{ 357 struct ieee80211com *ic; 358 device_t dev = sc->sc_dev; 359 struct ifnet *ifp; 360 struct bwi_mac *mac; 361 struct bwi_phy *phy; 362 int i, error; 363 uint8_t bands; 364 uint8_t macaddr[IEEE80211_ADDR_LEN]; 365 366 BWI_LOCK_INIT(sc); 367 368 /* 369 * Initialize taskq and various tasks 370 */ 371 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 372 taskqueue_thread_enqueue, &sc->sc_tq); 373 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 374 device_get_nameunit(dev)); 375 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 376 377 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 378 379 /* 380 * Initialize sysctl variables 381 */ 382 sc->sc_fw_version = BWI_FW_VERSION3; 383 sc->sc_led_idle = (2350 * hz) / 1000; 384 sc->sc_led_blink = 1; 385 sc->sc_txpwr_calib = 1; 386#ifdef BWI_DEBUG 387 sc->sc_debug = bwi_debug; 388#endif 389 bwi_power_on(sc, 1); 390 391 error = bwi_bbp_attach(sc); 392 if (error) 393 goto fail; 394 395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 396 if (error) 397 goto fail; 398 399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 400 error = bwi_set_clock_delay(sc); 401 if (error) 402 goto fail; 403 404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 405 if (error) 406 goto fail; 407 408 error = bwi_get_pwron_delay(sc); 409 if (error) 410 goto fail; 411 } 412 413 error = bwi_bus_attach(sc); 414 if (error) 415 goto fail; 416 417 bwi_get_card_flags(sc); 418 419 bwi_led_attach(sc); 420 421 for (i = 0; i < sc->sc_nmac; ++i) { 422 struct bwi_regwin *old; 423 424 mac = &sc->sc_mac[i]; 425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 426 if (error) 427 goto fail; 428 429 error = bwi_mac_lateattach(mac); 430 if (error) 431 goto fail; 432 433 error = bwi_regwin_switch(sc, old, NULL); 434 if (error) 435 goto fail; 436 } 437 438 /* 439 * XXX First MAC is known to exist 440 * TODO2 441 */ 442 mac = &sc->sc_mac[0]; 443 phy = &mac->mac_phy; 444 445 bwi_bbp_power_off(sc); 446 447 error = bwi_dma_alloc(sc); 448 if (error) 449 goto fail; 450 451 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 452 if (ifp == NULL) { 453 device_printf(dev, "can not if_alloc()\n"); 454 error = ENOSPC; 455 goto fail; 456 } 457 ic = ifp->if_l2com; 458 459 /* set these up early for if_printf use */ 460 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 461 462 ifp->if_softc = sc; 463 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 464 ifp->if_init = bwi_init; 465 ifp->if_ioctl = bwi_ioctl; 466 ifp->if_start = bwi_start; 467 ifp->if_watchdog = bwi_watchdog; 468 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 469 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 470 IFQ_SET_READY(&ifp->if_snd); 471 472 /* 473 * Setup ratesets, phytype, channels and get MAC address 474 */ 475 bands = 0; 476 if (phy->phy_mode == IEEE80211_MODE_11B || 477 phy->phy_mode == IEEE80211_MODE_11G) { 478 setbit(&bands, IEEE80211_MODE_11B); 479 if (phy->phy_mode == IEEE80211_MODE_11B) { 480 ic->ic_phytype = IEEE80211_T_DS; 481 } else { 482 ic->ic_phytype = IEEE80211_T_OFDM; 483 setbit(&bands, IEEE80211_MODE_11G); 484 } 485 486 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 487 if (IEEE80211_IS_MULTICAST(macaddr)) { 488 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 489 if (IEEE80211_IS_MULTICAST(macaddr)) { 490 device_printf(dev, 491 "invalid MAC address: %6D\n", 492 macaddr, ":"); 493 } 494 } 495 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 496 /* TODO:11A */ 497 setbit(&bands, IEEE80211_MODE_11A); 498 error = ENXIO; 499 goto fail; 500 } else { 501 panic("unknown phymode %d\n", phy->phy_mode); 502 } 503 504 /* Get locale */ 505 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 506 BWI_SPROM_CARD_INFO_LOCALE); 507 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 508 /* XXX use locale */ 509 ieee80211_init_channels(ic, NULL, &bands); 510 511 ic->ic_ifp = ifp; 512 ic->ic_caps = IEEE80211_C_STA | 513 IEEE80211_C_SHSLOT | 514 IEEE80211_C_SHPREAMBLE | 515 IEEE80211_C_WPA | 516 IEEE80211_C_BGSCAN | 517 IEEE80211_C_MONITOR; 518 ic->ic_opmode = IEEE80211_M_STA; 519 ieee80211_ifattach(ic, macaddr); 520 521 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 522 523 /* override default methods */ 524 ic->ic_vap_create = bwi_vap_create; 525 ic->ic_vap_delete = bwi_vap_delete; 526 ic->ic_raw_xmit = bwi_raw_xmit; 527 ic->ic_updateslot = bwi_updateslot; 528 ic->ic_node_alloc = bwi_node_alloc; 529 ic->ic_scan_start = bwi_scan_start; 530 ic->ic_scan_end = bwi_scan_end; 531 ic->ic_set_channel = bwi_set_channel; 532 533 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 534 535 ieee80211_radiotap_attach(ic, 536 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 537 BWI_TX_RADIOTAP_PRESENT, 538 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 539 BWI_RX_RADIOTAP_PRESENT); 540 541 /* 542 * Add sysctl nodes 543 */ 544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 547 "Firmware version"); 548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 550 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 551 "# ticks before LED enters idle state"); 552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 554 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 555 "Allow LED to blink"); 556 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 558 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 559 "Enable software TX power calibration"); 560#ifdef BWI_DEBUG 561 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 562 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 563 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 564#endif 565 if (bootverbose) 566 ieee80211_announce(ic); 567 568 return (0); 569fail: 570 BWI_LOCK_DESTROY(sc); 571 return (error); 572} 573 574int 575bwi_detach(struct bwi_softc *sc) 576{ 577 struct ifnet *ifp = sc->sc_ifp; 578 struct ieee80211com *ic = ifp->if_l2com; 579 int i; 580 581 bwi_stop(sc, 1); 582 callout_drain(&sc->sc_calib_ch); 583 ieee80211_ifdetach(ic); 584 585 for (i = 0; i < sc->sc_nmac; ++i) 586 bwi_mac_detach(&sc->sc_mac[i]); 587 bwi_dma_free(sc); 588 if_free(ifp); 589 taskqueue_free(sc->sc_tq); 590 591 BWI_LOCK_DESTROY(sc); 592 593 return (0); 594} 595 596static struct ieee80211vap * 597bwi_vap_create(struct ieee80211com *ic, 598 const char name[IFNAMSIZ], int unit, int opmode, int flags, 599 const uint8_t bssid[IEEE80211_ADDR_LEN], 600 const uint8_t mac[IEEE80211_ADDR_LEN]) 601{ 602 struct bwi_vap *bvp; 603 struct ieee80211vap *vap; 604 605 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 606 return NULL; 607 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 608 M_80211_VAP, M_WAITOK | M_ZERO); 609 if (bvp == NULL) 610 return NULL; 611 vap = &bvp->bv_vap; 612 /* enable s/w bmiss handling for sta mode */ 613 ieee80211_vap_setup(ic, vap, name, unit, opmode, 614 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 615 616 /* override default methods */ 617 bvp->bv_newstate = vap->iv_newstate; 618 vap->iv_newstate = bwi_newstate; 619#if 0 620 vap->iv_update_beacon = bwi_beacon_update; 621#endif 622 ieee80211_amrr_init(&bvp->bv_amrr, vap, 623 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 624 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 625 500 /*ms*/); 626 627 /* complete setup */ 628 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 629 ic->ic_opmode = opmode; 630 return vap; 631} 632 633static void 634bwi_vap_delete(struct ieee80211vap *vap) 635{ 636 struct bwi_vap *bvp = BWI_VAP(vap); 637 638 ieee80211_amrr_cleanup(&bvp->bv_amrr); 639 ieee80211_vap_detach(vap); 640 free(bvp, M_80211_VAP); 641} 642 643void 644bwi_suspend(struct bwi_softc *sc) 645{ 646 bwi_stop(sc, 1); 647} 648 649void 650bwi_resume(struct bwi_softc *sc) 651{ 652 struct ifnet *ifp = sc->sc_ifp; 653 654 if (ifp->if_flags & IFF_UP) 655 bwi_init(sc); 656} 657 658int 659bwi_shutdown(struct bwi_softc *sc) 660{ 661 bwi_stop(sc, 1); 662 return 0; 663} 664 665static void 666bwi_power_on(struct bwi_softc *sc, int with_pll) 667{ 668 uint32_t gpio_in, gpio_out, gpio_en; 669 uint16_t status; 670 671 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 672 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 673 goto back; 674 675 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 676 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 677 678 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 679 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 680 if (with_pll) { 681 /* Turn off PLL first */ 682 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 683 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 684 } 685 686 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 687 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 688 DELAY(1000); 689 690 if (with_pll) { 691 /* Turn on PLL */ 692 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 693 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 694 DELAY(5000); 695 } 696 697back: 698 /* Clear "Signaled Target Abort" */ 699 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 700 status &= ~PCIM_STATUS_STABORT; 701 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 702} 703 704static int 705bwi_power_off(struct bwi_softc *sc, int with_pll) 706{ 707 uint32_t gpio_out, gpio_en; 708 709 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 710 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 711 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 712 713 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 714 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 715 if (with_pll) { 716 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 717 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 718 } 719 720 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 721 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 722 return 0; 723} 724 725int 726bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 727 struct bwi_regwin **old_rw) 728{ 729 int error; 730 731 if (old_rw != NULL) 732 *old_rw = NULL; 733 734 if (!BWI_REGWIN_EXIST(rw)) 735 return EINVAL; 736 737 if (sc->sc_cur_regwin != rw) { 738 error = bwi_regwin_select(sc, rw->rw_id); 739 if (error) { 740 device_printf(sc->sc_dev, "can't select regwin %d\n", 741 rw->rw_id); 742 return error; 743 } 744 } 745 746 if (old_rw != NULL) 747 *old_rw = sc->sc_cur_regwin; 748 sc->sc_cur_regwin = rw; 749 return 0; 750} 751 752static int 753bwi_regwin_select(struct bwi_softc *sc, int id) 754{ 755 uint32_t win = BWI_PCIM_REGWIN(id); 756 int i; 757 758#define RETRY_MAX 50 759 for (i = 0; i < RETRY_MAX; ++i) { 760 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 761 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 762 return 0; 763 DELAY(10); 764 } 765#undef RETRY_MAX 766 767 return ENXIO; 768} 769 770static void 771bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 772{ 773 uint32_t val; 774 775 val = CSR_READ_4(sc, BWI_ID_HI); 776 *type = BWI_ID_HI_REGWIN_TYPE(val); 777 *rev = BWI_ID_HI_REGWIN_REV(val); 778 779 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 780 "vendor 0x%04x\n", *type, *rev, 781 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 782} 783 784static int 785bwi_bbp_attach(struct bwi_softc *sc) 786{ 787#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 788 uint16_t bbp_id, rw_type; 789 uint8_t rw_rev; 790 uint32_t info; 791 int error, nregwin, i; 792 793 /* 794 * Get 0th regwin information 795 * NOTE: 0th regwin should exist 796 */ 797 error = bwi_regwin_select(sc, 0); 798 if (error) { 799 device_printf(sc->sc_dev, "can't select regwin 0\n"); 800 return error; 801 } 802 bwi_regwin_info(sc, &rw_type, &rw_rev); 803 804 /* 805 * Find out BBP id 806 */ 807 bbp_id = 0; 808 info = 0; 809 if (rw_type == BWI_REGWIN_T_COM) { 810 info = CSR_READ_4(sc, BWI_INFO); 811 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 812 813 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 814 815 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 816 } else { 817 for (i = 0; i < N(bwi_bbpid_map); ++i) { 818 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 819 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 820 bbp_id = bwi_bbpid_map[i].bbp_id; 821 break; 822 } 823 } 824 if (bbp_id == 0) { 825 device_printf(sc->sc_dev, "no BBP id for device id " 826 "0x%04x\n", sc->sc_pci_did); 827 return ENXIO; 828 } 829 830 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 831 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 832 } 833 834 /* 835 * Find out number of regwins 836 */ 837 nregwin = 0; 838 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 839 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 840 } else { 841 for (i = 0; i < N(bwi_regwin_count); ++i) { 842 if (bwi_regwin_count[i].bbp_id == bbp_id) { 843 nregwin = bwi_regwin_count[i].nregwin; 844 break; 845 } 846 } 847 if (nregwin == 0) { 848 device_printf(sc->sc_dev, "no number of win for " 849 "BBP id 0x%04x\n", bbp_id); 850 return ENXIO; 851 } 852 } 853 854 /* Record BBP id/rev for later using */ 855 sc->sc_bbp_id = bbp_id; 856 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 857 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 858 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 859 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 860 861 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 862 nregwin, sc->sc_cap); 863 864 /* 865 * Create rest of the regwins 866 */ 867 868 /* Don't re-create common regwin, if it is already created */ 869 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 870 871 for (; i < nregwin; ++i) { 872 /* 873 * Get regwin information 874 */ 875 error = bwi_regwin_select(sc, i); 876 if (error) { 877 device_printf(sc->sc_dev, 878 "can't select regwin %d\n", i); 879 return error; 880 } 881 bwi_regwin_info(sc, &rw_type, &rw_rev); 882 883 /* 884 * Try attach: 885 * 1) Bus (PCI/PCIE) regwin 886 * 2) MAC regwin 887 * Ignore rest types of regwin 888 */ 889 if (rw_type == BWI_REGWIN_T_BUSPCI || 890 rw_type == BWI_REGWIN_T_BUSPCIE) { 891 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 892 device_printf(sc->sc_dev, 893 "bus regwin already exists\n"); 894 } else { 895 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 896 rw_type, rw_rev); 897 } 898 } else if (rw_type == BWI_REGWIN_T_MAC) { 899 /* XXX ignore return value */ 900 bwi_mac_attach(sc, i, rw_rev); 901 } 902 } 903 904 /* At least one MAC shold exist */ 905 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 906 device_printf(sc->sc_dev, "no MAC was found\n"); 907 return ENXIO; 908 } 909 KASSERT(sc->sc_nmac > 0, ("no mac's")); 910 911 /* Bus regwin must exist */ 912 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 913 device_printf(sc->sc_dev, "no bus regwin was found\n"); 914 return ENXIO; 915 } 916 917 /* Start with first MAC */ 918 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 919 if (error) 920 return error; 921 922 return 0; 923#undef N 924} 925 926int 927bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 928{ 929 struct bwi_regwin *old, *bus; 930 uint32_t val; 931 int error; 932 933 bus = &sc->sc_bus_regwin; 934 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 935 936 /* 937 * Tell bus to generate requested interrupts 938 */ 939 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 940 /* 941 * NOTE: Read BWI_FLAGS from MAC regwin 942 */ 943 val = CSR_READ_4(sc, BWI_FLAGS); 944 945 error = bwi_regwin_switch(sc, bus, &old); 946 if (error) 947 return error; 948 949 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 950 } else { 951 uint32_t mac_mask; 952 953 mac_mask = 1 << mac->mac_id; 954 955 error = bwi_regwin_switch(sc, bus, &old); 956 if (error) 957 return error; 958 959 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 960 val |= mac_mask << 8; 961 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 962 } 963 964 if (sc->sc_flags & BWI_F_BUS_INITED) 965 goto back; 966 967 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 968 /* 969 * Enable prefetch and burst 970 */ 971 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 972 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 973 974 if (bus->rw_rev < 5) { 975 struct bwi_regwin *com = &sc->sc_com_regwin; 976 977 /* 978 * Configure timeouts for bus operation 979 */ 980 981 /* 982 * Set service timeout and request timeout 983 */ 984 CSR_SETBITS_4(sc, BWI_CONF_LO, 985 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 986 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 987 988 /* 989 * If there is common regwin, we switch to that regwin 990 * and switch back to bus regwin once we have done. 991 */ 992 if (BWI_REGWIN_EXIST(com)) { 993 error = bwi_regwin_switch(sc, com, NULL); 994 if (error) 995 return error; 996 } 997 998 /* Let bus know what we have changed */ 999 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 1000 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 1001 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 1002 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 1003 1004 if (BWI_REGWIN_EXIST(com)) { 1005 error = bwi_regwin_switch(sc, bus, NULL); 1006 if (error) 1007 return error; 1008 } 1009 } else if (bus->rw_rev >= 11) { 1010 /* 1011 * Enable memory read multiple 1012 */ 1013 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1014 } 1015 } else { 1016 /* TODO:PCIE */ 1017 } 1018 1019 sc->sc_flags |= BWI_F_BUS_INITED; 1020back: 1021 return bwi_regwin_switch(sc, old, NULL); 1022} 1023 1024static void 1025bwi_get_card_flags(struct bwi_softc *sc) 1026{ 1027#define PCI_VENDOR_APPLE 0x106b 1028#define PCI_VENDOR_DELL 0x1028 1029 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1030 if (sc->sc_card_flags == 0xffff) 1031 sc->sc_card_flags = 0; 1032 1033 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1034 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1035 sc->sc_pci_revid == 0x74) 1036 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1037 1038 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1039 sc->sc_pci_subdid == 0x4e && /* XXX */ 1040 sc->sc_pci_revid > 0x40) 1041 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1042 1043 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1044#undef PCI_VENDOR_DELL 1045#undef PCI_VENDOR_APPLE 1046} 1047 1048static void 1049bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1050{ 1051 int i; 1052 1053 for (i = 0; i < 3; ++i) { 1054 *((uint16_t *)eaddr + i) = 1055 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1056 } 1057} 1058 1059static void 1060bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1061{ 1062 struct bwi_regwin *com; 1063 uint32_t val; 1064 u_int div; 1065 int src; 1066 1067 bzero(freq, sizeof(*freq)); 1068 com = &sc->sc_com_regwin; 1069 1070 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1071 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1072 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1073 1074 /* 1075 * Calculate clock frequency 1076 */ 1077 src = -1; 1078 div = 0; 1079 if (com->rw_rev < 6) { 1080 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1081 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1082 src = BWI_CLKSRC_PCI; 1083 div = 64; 1084 } else { 1085 src = BWI_CLKSRC_CS_OSC; 1086 div = 32; 1087 } 1088 } else if (com->rw_rev < 10) { 1089 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1090 1091 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1092 if (src == BWI_CLKSRC_LP_OSC) { 1093 div = 1; 1094 } else { 1095 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1096 1097 /* Unknown source */ 1098 if (src >= BWI_CLKSRC_MAX) 1099 src = BWI_CLKSRC_CS_OSC; 1100 } 1101 } else { 1102 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1103 1104 src = BWI_CLKSRC_CS_OSC; 1105 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1106 } 1107 1108 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1109 KASSERT(div != 0, ("div zero")); 1110 1111 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1112 src == BWI_CLKSRC_PCI ? "PCI" : 1113 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1114 1115 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1116 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1117 1118 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1119 freq->clkfreq_min, freq->clkfreq_max); 1120} 1121 1122static int 1123bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1124{ 1125 struct bwi_regwin *old, *com; 1126 uint32_t clk_ctrl, clk_src; 1127 int error, pwr_off = 0; 1128 1129 com = &sc->sc_com_regwin; 1130 if (!BWI_REGWIN_EXIST(com)) 1131 return 0; 1132 1133 if (com->rw_rev >= 10 || com->rw_rev < 6) 1134 return 0; 1135 1136 /* 1137 * For common regwin whose rev is [6, 10), the chip 1138 * must be capable to change clock mode. 1139 */ 1140 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1141 return 0; 1142 1143 error = bwi_regwin_switch(sc, com, &old); 1144 if (error) 1145 return error; 1146 1147 if (clk_mode == BWI_CLOCK_MODE_FAST) 1148 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1149 1150 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1151 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1152 1153 switch (clk_mode) { 1154 case BWI_CLOCK_MODE_FAST: 1155 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1156 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1157 break; 1158 case BWI_CLOCK_MODE_SLOW: 1159 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1160 break; 1161 case BWI_CLOCK_MODE_DYN: 1162 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1163 BWI_CLOCK_CTRL_IGNPLL | 1164 BWI_CLOCK_CTRL_NODYN); 1165 if (clk_src != BWI_CLKSRC_CS_OSC) { 1166 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1167 pwr_off = 1; 1168 } 1169 break; 1170 } 1171 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1172 1173 if (pwr_off) 1174 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1175 1176 return bwi_regwin_switch(sc, old, NULL); 1177} 1178 1179static int 1180bwi_set_clock_delay(struct bwi_softc *sc) 1181{ 1182 struct bwi_regwin *old, *com; 1183 int error; 1184 1185 com = &sc->sc_com_regwin; 1186 if (!BWI_REGWIN_EXIST(com)) 1187 return 0; 1188 1189 error = bwi_regwin_switch(sc, com, &old); 1190 if (error) 1191 return error; 1192 1193 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1194 if (sc->sc_bbp_rev == 0) 1195 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1196 else if (sc->sc_bbp_rev == 1) 1197 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1198 } 1199 1200 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1201 if (com->rw_rev >= 10) { 1202 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1203 } else { 1204 struct bwi_clock_freq freq; 1205 1206 bwi_get_clock_freq(sc, &freq); 1207 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1208 howmany(freq.clkfreq_max * 150, 1000000)); 1209 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1210 howmany(freq.clkfreq_max * 15, 1000000)); 1211 } 1212 } 1213 1214 return bwi_regwin_switch(sc, old, NULL); 1215} 1216 1217static void 1218bwi_init(void *xsc) 1219{ 1220 struct bwi_softc *sc = xsc; 1221 struct ifnet *ifp = sc->sc_ifp; 1222 struct ieee80211com *ic = ifp->if_l2com; 1223 1224 BWI_LOCK(sc); 1225 bwi_init_statechg(sc, 1); 1226 BWI_UNLOCK(sc); 1227 1228 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1229 ieee80211_start_all(ic); /* start all vap's */ 1230} 1231 1232static void 1233bwi_init_statechg(struct bwi_softc *sc, int statechg) 1234{ 1235 struct ifnet *ifp = sc->sc_ifp; 1236 struct bwi_mac *mac; 1237 int error; 1238 1239 bwi_stop_locked(sc, statechg); 1240 1241 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1242 1243 /* TODO: 2 MAC */ 1244 1245 mac = &sc->sc_mac[0]; 1246 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1247 if (error) { 1248 if_printf(ifp, "%s: error %d on regwin switch\n", 1249 __func__, error); 1250 goto bad; 1251 } 1252 error = bwi_mac_init(mac); 1253 if (error) { 1254 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1255 goto bad; 1256 } 1257 1258 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1259 1260 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1261 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1262 1263 bwi_mac_reset_hwkeys(mac); 1264 1265 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1266 int i; 1267 1268#define NRETRY 1000 1269 /* 1270 * Drain any possible pending TX status 1271 */ 1272 for (i = 0; i < NRETRY; ++i) { 1273 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1274 BWI_TXSTATUS0_VALID) == 0) 1275 break; 1276 CSR_READ_4(sc, BWI_TXSTATUS1); 1277 } 1278 if (i == NRETRY) 1279 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1280#undef NRETRY 1281 } 1282 1283 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1284 bwi_mac_updateslot(mac, 1); 1285 1286 /* Start MAC */ 1287 error = bwi_mac_start(mac); 1288 if (error) { 1289 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1290 goto bad; 1291 } 1292 1293 /* Clear stop flag before enabling interrupt */ 1294 sc->sc_flags &= ~BWI_F_STOP; 1295 1296 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1297 1298 /* Enable intrs */ 1299 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1300 return; 1301bad: 1302 bwi_stop_locked(sc, 1); 1303} 1304 1305static int 1306bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1307{ 1308#define IS_RUNNING(ifp) \ 1309 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1310 struct bwi_softc *sc = ifp->if_softc; 1311 struct ieee80211com *ic = ifp->if_l2com; 1312 struct ifreq *ifr = (struct ifreq *) data; 1313 int error = 0, startall = 0; 1314 1315 switch (cmd) { 1316 case SIOCSIFFLAGS: 1317 BWI_LOCK(sc); 1318 if (IS_RUNNING(ifp)) { 1319 struct bwi_mac *mac; 1320 int promisc = -1; 1321 1322 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1323 ("current regwin type %d", 1324 sc->sc_cur_regwin->rw_type)); 1325 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1326 1327 if ((ifp->if_flags & IFF_PROMISC) && 1328 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1329 promisc = 1; 1330 sc->sc_flags |= BWI_F_PROMISC; 1331 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1332 (sc->sc_flags & BWI_F_PROMISC)) { 1333 promisc = 0; 1334 sc->sc_flags &= ~BWI_F_PROMISC; 1335 } 1336 1337 if (promisc >= 0) 1338 bwi_mac_set_promisc(mac, promisc); 1339 } 1340 1341 if (ifp->if_flags & IFF_UP) { 1342 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1343 bwi_init_statechg(sc, 1); 1344 startall = 1; 1345 } 1346 } else { 1347 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1348 bwi_stop_locked(sc, 1); 1349 } 1350 BWI_UNLOCK(sc); 1351 if (startall) 1352 ieee80211_start_all(ic); 1353 break; 1354 case SIOCGIFMEDIA: 1355 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1356 break; 1357 case SIOCGIFADDR: 1358 error = ether_ioctl(ifp, cmd, data); 1359 break; 1360 default: 1361 error = EINVAL; 1362 break; 1363 } 1364 return error; 1365#undef IS_RUNNING 1366} 1367 1368static void 1369bwi_start(struct ifnet *ifp) 1370{ 1371 struct bwi_softc *sc = ifp->if_softc; 1372 1373 BWI_LOCK(sc); 1374 bwi_start_locked(ifp); 1375 BWI_UNLOCK(sc); 1376} 1377 1378static void 1379bwi_start_locked(struct ifnet *ifp) 1380{ 1381 struct bwi_softc *sc = ifp->if_softc; 1382 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1383 struct ieee80211_frame *wh; 1384 struct ieee80211_node *ni; 1385 struct ieee80211_key *k; 1386 struct mbuf *m; 1387 int trans, idx; 1388 1389 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1390 return; 1391 1392 trans = 0; 1393 idx = tbd->tbd_idx; 1394 1395 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1396 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1397 if (m == NULL) 1398 break; 1399 1400 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1401 wh = mtod(m, struct ieee80211_frame *); 1402 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1403 k = ieee80211_crypto_encap(ni, m); 1404 if (k == NULL) { 1405 ieee80211_free_node(ni); 1406 m_freem(m); 1407 ifp->if_oerrors++; 1408 continue; 1409 } 1410 } 1411 wh = NULL; /* Catch any invalid use */ 1412 1413 if (bwi_encap(sc, idx, m, ni) != 0) { 1414 /* 'm' is freed in bwi_encap() if we reach here */ 1415 if (ni != NULL) 1416 ieee80211_free_node(ni); 1417 ifp->if_oerrors++; 1418 continue; 1419 } 1420 1421 trans = 1; 1422 tbd->tbd_used++; 1423 idx = (idx + 1) % BWI_TX_NDESC; 1424 1425 ifp->if_opackets++; 1426 1427 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1428 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1429 break; 1430 } 1431 } 1432 tbd->tbd_idx = idx; 1433 1434 if (trans) 1435 ifp->if_timer = 5; 1436} 1437 1438static int 1439bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1440 const struct ieee80211_bpf_params *params) 1441{ 1442 struct ieee80211com *ic = ni->ni_ic; 1443 struct ifnet *ifp = ic->ic_ifp; 1444 struct bwi_softc *sc = ifp->if_softc; 1445 /* XXX wme? */ 1446 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1447 int idx, error; 1448 1449 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1450 ieee80211_free_node(ni); 1451 m_freem(m); 1452 return ENETDOWN; 1453 } 1454 1455 BWI_LOCK(sc); 1456 idx = tbd->tbd_idx; 1457 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1458 if (params == NULL) { 1459 /* 1460 * Legacy path; interpret frame contents to decide 1461 * precisely how to send the frame. 1462 */ 1463 error = bwi_encap(sc, idx, m, ni); 1464 } else { 1465 /* 1466 * Caller supplied explicit parameters to use in 1467 * sending the frame. 1468 */ 1469 error = bwi_encap_raw(sc, idx, m, ni, params); 1470 } 1471 if (error == 0) { 1472 ifp->if_opackets++; 1473 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1474 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1475 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1476 ifp->if_timer = 5; 1477 } else { 1478 /* NB: m is reclaimed on encap failure */ 1479 ieee80211_free_node(ni); 1480 ifp->if_oerrors++; 1481 } 1482 BWI_UNLOCK(sc); 1483 return error; 1484} 1485 1486static void 1487bwi_watchdog(struct ifnet *ifp) 1488{ 1489 struct bwi_softc *sc = ifp->if_softc; 1490 1491 BWI_LOCK(sc); 1492 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1493 if_printf(ifp, "watchdog timeout\n"); 1494 ifp->if_oerrors++; 1495 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1496 } 1497 BWI_UNLOCK(sc); 1498} 1499 1500static void 1501bwi_stop(struct bwi_softc *sc, int statechg) 1502{ 1503 BWI_LOCK(sc); 1504 bwi_stop_locked(sc, statechg); 1505 BWI_UNLOCK(sc); 1506} 1507 1508static void 1509bwi_stop_locked(struct bwi_softc *sc, int statechg) 1510{ 1511 struct ifnet *ifp = sc->sc_ifp; 1512 struct bwi_mac *mac; 1513 int i, error, pwr_off = 0; 1514 1515 BWI_ASSERT_LOCKED(sc); 1516 1517 callout_stop(&sc->sc_calib_ch); 1518 callout_stop(&sc->sc_led_blink_ch); 1519 sc->sc_led_blinking = 0; 1520 sc->sc_flags |= BWI_F_STOP; 1521 1522 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1523 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1524 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1525 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1526 1527 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1528 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1529 bwi_mac_stop(mac); 1530 } 1531 1532 for (i = 0; i < sc->sc_nmac; ++i) { 1533 struct bwi_regwin *old_rw; 1534 1535 mac = &sc->sc_mac[i]; 1536 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1537 continue; 1538 1539 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1540 if (error) 1541 continue; 1542 1543 bwi_mac_shutdown(mac); 1544 pwr_off = 1; 1545 1546 bwi_regwin_switch(sc, old_rw, NULL); 1547 } 1548 1549 if (pwr_off) 1550 bwi_bbp_power_off(sc); 1551 1552 sc->sc_tx_timer = 0; 1553 ifp->if_timer = 0; 1554 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1555} 1556 1557void 1558bwi_intr(void *xsc) 1559{ 1560 struct bwi_softc *sc = xsc; 1561 struct ifnet *ifp = sc->sc_ifp; 1562 struct bwi_mac *mac; 1563 uint32_t intr_status; 1564 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1565 int i, txrx_error, tx = 0, rx_data = -1; 1566 1567 BWI_LOCK(sc); 1568 1569 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1570 (sc->sc_flags & BWI_F_STOP)) { 1571 BWI_UNLOCK(sc); 1572 return; 1573 } 1574 /* 1575 * Get interrupt status 1576 */ 1577 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1578 if (intr_status == 0xffffffff) { /* Not for us */ 1579 BWI_UNLOCK(sc); 1580 return; 1581 } 1582 1583 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1584 1585 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1586 if (intr_status == 0) { /* Nothing is interesting */ 1587 BWI_UNLOCK(sc); 1588 return; 1589 } 1590 1591 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1592 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1593 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1594 1595 txrx_error = 0; 1596 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1597 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1598 uint32_t mask; 1599 1600 if (BWI_TXRX_IS_RX(i)) 1601 mask = BWI_TXRX_RX_INTRS; 1602 else 1603 mask = BWI_TXRX_TX_INTRS; 1604 1605 txrx_intr_status[i] = 1606 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1607 1608 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1609 i, txrx_intr_status[i]); 1610 1611 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1612 if_printf(ifp, 1613 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1614 __func__, i, txrx_intr_status[i]); 1615 txrx_error = 1; 1616 } 1617 } 1618 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1619 1620 /* 1621 * Acknowledge interrupt 1622 */ 1623 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1624 1625 for (i = 0; i < BWI_TXRX_NRING; ++i) 1626 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1627 1628 /* Disable all interrupts */ 1629 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1630 1631 if (intr_status & BWI_INTR_PHY_TXERR) { 1632 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1633 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1634 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1635 BWI_UNLOCK(sc); 1636 return; 1637 } 1638 } 1639 1640 if (txrx_error) { 1641 /* TODO: reset device */ 1642 } 1643 1644 if (intr_status & BWI_INTR_TBTT) 1645 bwi_mac_config_ps(mac); 1646 1647 if (intr_status & BWI_INTR_EO_ATIM) 1648 if_printf(ifp, "EO_ATIM\n"); 1649 1650 if (intr_status & BWI_INTR_PMQ) { 1651 for (;;) { 1652 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1653 break; 1654 } 1655 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1656 } 1657 1658 if (intr_status & BWI_INTR_NOISE) 1659 if_printf(ifp, "intr noise\n"); 1660 1661 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1662 rx_data = sc->sc_rxeof(sc); 1663 if (sc->sc_flags & BWI_F_STOP) { 1664 BWI_UNLOCK(sc); 1665 return; 1666 } 1667 } 1668 1669 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1670 sc->sc_txeof_status(sc); 1671 tx = 1; 1672 } 1673 1674 if (intr_status & BWI_INTR_TX_DONE) { 1675 bwi_txeof(sc); 1676 tx = 1; 1677 } 1678 1679 /* Re-enable interrupts */ 1680 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1681 1682 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1683 int evt = BWI_LED_EVENT_NONE; 1684 1685 if (tx && rx_data > 0) { 1686 if (sc->sc_rx_rate > sc->sc_tx_rate) 1687 evt = BWI_LED_EVENT_RX; 1688 else 1689 evt = BWI_LED_EVENT_TX; 1690 } else if (tx) { 1691 evt = BWI_LED_EVENT_TX; 1692 } else if (rx_data > 0) { 1693 evt = BWI_LED_EVENT_RX; 1694 } else if (rx_data == 0) { 1695 evt = BWI_LED_EVENT_POLL; 1696 } 1697 1698 if (evt != BWI_LED_EVENT_NONE) 1699 bwi_led_event(sc, evt); 1700 } 1701 1702 BWI_UNLOCK(sc); 1703} 1704 1705static void 1706bwi_scan_start(struct ieee80211com *ic) 1707{ 1708 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1709 1710 BWI_LOCK(sc); 1711 /* Enable MAC beacon promiscuity */ 1712 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1713 BWI_UNLOCK(sc); 1714} 1715 1716static void 1717bwi_set_channel(struct ieee80211com *ic) 1718{ 1719 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1720 struct ieee80211_channel *c = ic->ic_curchan; 1721 struct bwi_mac *mac; 1722 1723 BWI_LOCK(sc); 1724 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1725 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1726 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1727 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1728 1729 sc->sc_rates = ieee80211_get_ratetable(c); 1730 1731 /* 1732 * Setup radio tap channel freq and flags 1733 */ 1734 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1735 htole16(c->ic_freq); 1736 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1737 htole16(c->ic_flags & 0xffff); 1738 1739 BWI_UNLOCK(sc); 1740} 1741 1742static void 1743bwi_scan_end(struct ieee80211com *ic) 1744{ 1745 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1746 1747 BWI_LOCK(sc); 1748 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1749 BWI_UNLOCK(sc); 1750} 1751 1752static int 1753bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1754{ 1755 struct bwi_vap *bvp = BWI_VAP(vap); 1756 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1757 struct bwi_softc *sc = ifp->if_softc; 1758 struct bwi_mac *mac; 1759 struct ieee80211_node *ni; 1760 int error; 1761 1762 BWI_LOCK(sc); 1763 1764 callout_stop(&sc->sc_calib_ch); 1765 1766 if (nstate == IEEE80211_S_INIT) 1767 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1768 1769 bwi_led_newstate(sc, nstate); 1770 1771 error = bvp->bv_newstate(vap, nstate, arg); 1772 if (error != 0) 1773 goto back; 1774 1775 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1776 /* Nothing to do */ 1777 } else if (nstate == IEEE80211_S_RUN) { 1778 ni = vap->iv_bss; 1779 1780 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1781 1782 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1783 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1784 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1785 1786 /* Initial TX power calibration */ 1787 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1788#ifdef notyet 1789 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1790#else 1791 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1792#endif 1793 if (vap->iv_opmode == IEEE80211_M_STA) { 1794 /* fake a join to init the tx rate */ 1795 bwi_newassoc(ni, 1); 1796 } 1797 1798 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1799 } else { 1800 bwi_set_bssid(sc, bwi_zero_addr); 1801 } 1802back: 1803 BWI_UNLOCK(sc); 1804 1805 return error; 1806} 1807 1808/* ARGUSED */ 1809static struct ieee80211_node * 1810bwi_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1811{ 1812 struct bwi_node *bn; 1813 1814 bn = malloc(sizeof(struct bwi_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1815 return bn != NULL ? &bn->ni : NULL; 1816} 1817 1818static void 1819bwi_newassoc(struct ieee80211_node *ni, int isnew) 1820{ 1821 struct ieee80211vap *vap = ni->ni_vap; 1822 1823 ieee80211_amrr_node_init(&BWI_VAP(vap)->bv_amrr, 1824 &BWI_NODE(ni)->amn, ni); 1825} 1826 1827static int 1828bwi_media_change(struct ifnet *ifp) 1829{ 1830 int error = ieee80211_media_change(ifp); 1831 /* NB: only the fixed rate can change and that doesn't need a reset */ 1832 return (error == ENETRESET ? 0 : error); 1833} 1834 1835static int 1836bwi_dma_alloc(struct bwi_softc *sc) 1837{ 1838 int error, i, has_txstats; 1839 bus_addr_t lowaddr = 0; 1840 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1841 uint32_t txrx_ctrl_step = 0; 1842 1843 has_txstats = 0; 1844 for (i = 0; i < sc->sc_nmac; ++i) { 1845 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1846 has_txstats = 1; 1847 break; 1848 } 1849 } 1850 1851 switch (sc->sc_bus_space) { 1852 case BWI_BUS_SPACE_30BIT: 1853 case BWI_BUS_SPACE_32BIT: 1854 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1855 lowaddr = BWI_BUS_SPACE_MAXADDR; 1856 else 1857 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1858 desc_sz = sizeof(struct bwi_desc32); 1859 txrx_ctrl_step = 0x20; 1860 1861 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1862 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1863 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1864 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1865 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1866 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1867 sc->sc_rxeof = bwi_rxeof32; 1868 sc->sc_start_tx = bwi_start_tx32; 1869 if (has_txstats) { 1870 sc->sc_init_txstats = bwi_init_txstats32; 1871 sc->sc_free_txstats = bwi_free_txstats32; 1872 sc->sc_txeof_status = bwi_txeof_status32; 1873 } 1874 break; 1875 1876 case BWI_BUS_SPACE_64BIT: 1877 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1878 desc_sz = sizeof(struct bwi_desc64); 1879 txrx_ctrl_step = 0x40; 1880 1881 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1882 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1883 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1884 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1885 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1886 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1887 sc->sc_rxeof = bwi_rxeof64; 1888 sc->sc_start_tx = bwi_start_tx64; 1889 if (has_txstats) { 1890 sc->sc_init_txstats = bwi_init_txstats64; 1891 sc->sc_free_txstats = bwi_free_txstats64; 1892 sc->sc_txeof_status = bwi_txeof_status64; 1893 } 1894 break; 1895 } 1896 1897 KASSERT(lowaddr != 0, ("lowaddr zero")); 1898 KASSERT(desc_sz != 0, ("desc_sz zero")); 1899 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1900 1901 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1902 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1903 1904 /* 1905 * Create top level DMA tag 1906 */ 1907 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1908 BWI_ALIGN, 0, /* alignment, bounds */ 1909 lowaddr, /* lowaddr */ 1910 BUS_SPACE_MAXADDR, /* highaddr */ 1911 NULL, NULL, /* filter, filterarg */ 1912 MAXBSIZE, /* maxsize */ 1913 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1914 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1915 BUS_DMA_ALLOCNOW, /* flags */ 1916 NULL, NULL, /* lockfunc, lockarg */ 1917 &sc->sc_parent_dtag); 1918 if (error) { 1919 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1920 return error; 1921 } 1922 1923#define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1924 1925 /* 1926 * Create TX ring DMA stuffs 1927 */ 1928 error = bus_dma_tag_create(sc->sc_parent_dtag, 1929 BWI_RING_ALIGN, 0, 1930 BUS_SPACE_MAXADDR, 1931 BUS_SPACE_MAXADDR, 1932 NULL, NULL, 1933 tx_ring_sz, 1934 1, 1935 BUS_SPACE_MAXSIZE_32BIT, 1936 BUS_DMA_ALLOCNOW, 1937 NULL, NULL, 1938 &sc->sc_txring_dtag); 1939 if (error) { 1940 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1941 return error; 1942 } 1943 1944 for (i = 0; i < BWI_TX_NRING; ++i) { 1945 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1946 &sc->sc_tx_rdata[i], tx_ring_sz, 1947 TXRX_CTRL(i)); 1948 if (error) { 1949 device_printf(sc->sc_dev, "%dth TX ring " 1950 "DMA alloc failed\n", i); 1951 return error; 1952 } 1953 } 1954 1955 /* 1956 * Create RX ring DMA stuffs 1957 */ 1958 error = bus_dma_tag_create(sc->sc_parent_dtag, 1959 BWI_RING_ALIGN, 0, 1960 BUS_SPACE_MAXADDR, 1961 BUS_SPACE_MAXADDR, 1962 NULL, NULL, 1963 rx_ring_sz, 1964 1, 1965 BUS_SPACE_MAXSIZE_32BIT, 1966 BUS_DMA_ALLOCNOW, 1967 NULL, NULL, 1968 &sc->sc_rxring_dtag); 1969 if (error) { 1970 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1971 return error; 1972 } 1973 1974 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1975 rx_ring_sz, TXRX_CTRL(0)); 1976 if (error) { 1977 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1978 return error; 1979 } 1980 1981 if (has_txstats) { 1982 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1983 if (error) { 1984 device_printf(sc->sc_dev, 1985 "TX stats DMA alloc failed\n"); 1986 return error; 1987 } 1988 } 1989 1990#undef TXRX_CTRL 1991 1992 return bwi_dma_mbuf_create(sc); 1993} 1994 1995static void 1996bwi_dma_free(struct bwi_softc *sc) 1997{ 1998 if (sc->sc_txring_dtag != NULL) { 1999 int i; 2000 2001 for (i = 0; i < BWI_TX_NRING; ++i) { 2002 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2003 2004 if (rd->rdata_desc != NULL) { 2005 bus_dmamap_unload(sc->sc_txring_dtag, 2006 rd->rdata_dmap); 2007 bus_dmamem_free(sc->sc_txring_dtag, 2008 rd->rdata_desc, 2009 rd->rdata_dmap); 2010 } 2011 } 2012 bus_dma_tag_destroy(sc->sc_txring_dtag); 2013 } 2014 2015 if (sc->sc_rxring_dtag != NULL) { 2016 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2017 2018 if (rd->rdata_desc != NULL) { 2019 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2020 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2021 rd->rdata_dmap); 2022 } 2023 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2024 } 2025 2026 bwi_dma_txstats_free(sc); 2027 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2028 2029 if (sc->sc_parent_dtag != NULL) 2030 bus_dma_tag_destroy(sc->sc_parent_dtag); 2031} 2032 2033static int 2034bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2035 struct bwi_ring_data *rd, bus_size_t size, 2036 uint32_t txrx_ctrl) 2037{ 2038 int error; 2039 2040 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2041 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2042 &rd->rdata_dmap); 2043 if (error) { 2044 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2045 return error; 2046 } 2047 2048 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2049 bwi_dma_ring_addr, &rd->rdata_paddr, 2050 BUS_DMA_NOWAIT); 2051 if (error) { 2052 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2053 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2054 rd->rdata_desc = NULL; 2055 return error; 2056 } 2057 2058 rd->rdata_txrx_ctrl = txrx_ctrl; 2059 return 0; 2060} 2061 2062static int 2063bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2064 bus_size_t desc_sz) 2065{ 2066 struct bwi_txstats_data *st; 2067 bus_size_t dma_size; 2068 int error; 2069 2070 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2071 if (st == NULL) { 2072 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2073 return ENOMEM; 2074 } 2075 sc->sc_txstats = st; 2076 2077 /* 2078 * Create TX stats descriptor DMA stuffs 2079 */ 2080 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2081 2082 error = bus_dma_tag_create(sc->sc_parent_dtag, 2083 BWI_RING_ALIGN, 2084 0, 2085 BUS_SPACE_MAXADDR, 2086 BUS_SPACE_MAXADDR, 2087 NULL, NULL, 2088 dma_size, 2089 1, 2090 BUS_SPACE_MAXSIZE_32BIT, 2091 BUS_DMA_ALLOCNOW, 2092 NULL, NULL, 2093 &st->stats_ring_dtag); 2094 if (error) { 2095 device_printf(sc->sc_dev, "can't create txstats ring " 2096 "DMA tag\n"); 2097 return error; 2098 } 2099 2100 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2101 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2102 &st->stats_ring_dmap); 2103 if (error) { 2104 device_printf(sc->sc_dev, "can't allocate txstats ring " 2105 "DMA mem\n"); 2106 bus_dma_tag_destroy(st->stats_ring_dtag); 2107 st->stats_ring_dtag = NULL; 2108 return error; 2109 } 2110 2111 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2112 st->stats_ring, dma_size, 2113 bwi_dma_ring_addr, &st->stats_ring_paddr, 2114 BUS_DMA_NOWAIT); 2115 if (error) { 2116 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2117 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2118 st->stats_ring_dmap); 2119 bus_dma_tag_destroy(st->stats_ring_dtag); 2120 st->stats_ring_dtag = NULL; 2121 return error; 2122 } 2123 2124 /* 2125 * Create TX stats DMA stuffs 2126 */ 2127 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2128 BWI_ALIGN); 2129 2130 error = bus_dma_tag_create(sc->sc_parent_dtag, 2131 BWI_ALIGN, 2132 0, 2133 BUS_SPACE_MAXADDR, 2134 BUS_SPACE_MAXADDR, 2135 NULL, NULL, 2136 dma_size, 2137 1, 2138 BUS_SPACE_MAXSIZE_32BIT, 2139 BUS_DMA_ALLOCNOW, 2140 NULL, NULL, 2141 &st->stats_dtag); 2142 if (error) { 2143 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2144 return error; 2145 } 2146 2147 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2148 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2149 &st->stats_dmap); 2150 if (error) { 2151 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2152 bus_dma_tag_destroy(st->stats_dtag); 2153 st->stats_dtag = NULL; 2154 return error; 2155 } 2156 2157 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2158 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2159 BUS_DMA_NOWAIT); 2160 if (error) { 2161 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2162 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2163 bus_dma_tag_destroy(st->stats_dtag); 2164 st->stats_dtag = NULL; 2165 return error; 2166 } 2167 2168 st->stats_ctrl_base = ctrl_base; 2169 return 0; 2170} 2171 2172static void 2173bwi_dma_txstats_free(struct bwi_softc *sc) 2174{ 2175 struct bwi_txstats_data *st; 2176 2177 if (sc->sc_txstats == NULL) 2178 return; 2179 st = sc->sc_txstats; 2180 2181 if (st->stats_ring_dtag != NULL) { 2182 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2183 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2184 st->stats_ring_dmap); 2185 bus_dma_tag_destroy(st->stats_ring_dtag); 2186 } 2187 2188 if (st->stats_dtag != NULL) { 2189 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2190 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2191 bus_dma_tag_destroy(st->stats_dtag); 2192 } 2193 2194 free(st, M_DEVBUF); 2195} 2196 2197static void 2198bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2199{ 2200 KASSERT(nseg == 1, ("too many segments\n")); 2201 *((bus_addr_t *)arg) = seg->ds_addr; 2202} 2203 2204static int 2205bwi_dma_mbuf_create(struct bwi_softc *sc) 2206{ 2207 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2208 int i, j, k, ntx, error; 2209 2210 /* 2211 * Create TX/RX mbuf DMA tag 2212 */ 2213 error = bus_dma_tag_create(sc->sc_parent_dtag, 2214 1, 2215 0, 2216 BUS_SPACE_MAXADDR, 2217 BUS_SPACE_MAXADDR, 2218 NULL, NULL, 2219 MCLBYTES, 2220 1, 2221 BUS_SPACE_MAXSIZE_32BIT, 2222 BUS_DMA_ALLOCNOW, 2223 NULL, NULL, 2224 &sc->sc_buf_dtag); 2225 if (error) { 2226 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2227 return error; 2228 } 2229 2230 ntx = 0; 2231 2232 /* 2233 * Create TX mbuf DMA map 2234 */ 2235 for (i = 0; i < BWI_TX_NRING; ++i) { 2236 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2237 2238 for (j = 0; j < BWI_TX_NDESC; ++j) { 2239 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2240 &tbd->tbd_buf[j].tb_dmap); 2241 if (error) { 2242 device_printf(sc->sc_dev, "can't create " 2243 "%dth tbd, %dth DMA map\n", i, j); 2244 2245 ntx = i; 2246 for (k = 0; k < j; ++k) { 2247 bus_dmamap_destroy(sc->sc_buf_dtag, 2248 tbd->tbd_buf[k].tb_dmap); 2249 } 2250 goto fail; 2251 } 2252 } 2253 } 2254 ntx = BWI_TX_NRING; 2255 2256 /* 2257 * Create RX mbuf DMA map and a spare DMA map 2258 */ 2259 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2260 &rbd->rbd_tmp_dmap); 2261 if (error) { 2262 device_printf(sc->sc_dev, 2263 "can't create spare RX buf DMA map\n"); 2264 goto fail; 2265 } 2266 2267 for (j = 0; j < BWI_RX_NDESC; ++j) { 2268 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2269 &rbd->rbd_buf[j].rb_dmap); 2270 if (error) { 2271 device_printf(sc->sc_dev, "can't create %dth " 2272 "RX buf DMA map\n", j); 2273 2274 for (k = 0; k < j; ++k) { 2275 bus_dmamap_destroy(sc->sc_buf_dtag, 2276 rbd->rbd_buf[j].rb_dmap); 2277 } 2278 bus_dmamap_destroy(sc->sc_buf_dtag, 2279 rbd->rbd_tmp_dmap); 2280 goto fail; 2281 } 2282 } 2283 2284 return 0; 2285fail: 2286 bwi_dma_mbuf_destroy(sc, ntx, 0); 2287 return error; 2288} 2289 2290static void 2291bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2292{ 2293 int i, j; 2294 2295 if (sc->sc_buf_dtag == NULL) 2296 return; 2297 2298 for (i = 0; i < ntx; ++i) { 2299 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2300 2301 for (j = 0; j < BWI_TX_NDESC; ++j) { 2302 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2303 2304 if (tb->tb_mbuf != NULL) { 2305 bus_dmamap_unload(sc->sc_buf_dtag, 2306 tb->tb_dmap); 2307 m_freem(tb->tb_mbuf); 2308 } 2309 if (tb->tb_ni != NULL) 2310 ieee80211_free_node(tb->tb_ni); 2311 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2312 } 2313 } 2314 2315 if (nrx) { 2316 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2317 2318 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2319 for (j = 0; j < BWI_RX_NDESC; ++j) { 2320 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2321 2322 if (rb->rb_mbuf != NULL) { 2323 bus_dmamap_unload(sc->sc_buf_dtag, 2324 rb->rb_dmap); 2325 m_freem(rb->rb_mbuf); 2326 } 2327 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2328 } 2329 } 2330 2331 bus_dma_tag_destroy(sc->sc_buf_dtag); 2332 sc->sc_buf_dtag = NULL; 2333} 2334 2335static void 2336bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2337{ 2338 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2339} 2340 2341static void 2342bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2343{ 2344 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2345} 2346 2347static int 2348bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2349{ 2350 struct bwi_ring_data *rd; 2351 struct bwi_txbuf_data *tbd; 2352 uint32_t val, addr_hi, addr_lo; 2353 2354 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2355 rd = &sc->sc_tx_rdata[ring_idx]; 2356 tbd = &sc->sc_tx_bdata[ring_idx]; 2357 2358 tbd->tbd_idx = 0; 2359 tbd->tbd_used = 0; 2360 2361 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2362 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2363 BUS_DMASYNC_PREWRITE); 2364 2365 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2366 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2367 2368 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2369 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2370 BWI_TXRX32_RINGINFO_FUNC_MASK); 2371 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2372 2373 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2374 BWI_TXRX32_CTRL_ENABLE; 2375 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2376 2377 return 0; 2378} 2379 2380static void 2381bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2382 bus_addr_t paddr, int hdr_size, int ndesc) 2383{ 2384 uint32_t val, addr_hi, addr_lo; 2385 2386 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2387 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2388 2389 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2390 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2391 BWI_TXRX32_RINGINFO_FUNC_MASK); 2392 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2393 2394 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2395 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2396 BWI_TXRX32_CTRL_ENABLE; 2397 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2398 2399 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2400 (ndesc - 1) * sizeof(struct bwi_desc32)); 2401} 2402 2403static int 2404bwi_init_rx_ring32(struct bwi_softc *sc) 2405{ 2406 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2407 int i, error; 2408 2409 sc->sc_rx_bdata.rbd_idx = 0; 2410 2411 for (i = 0; i < BWI_RX_NDESC; ++i) { 2412 error = bwi_newbuf(sc, i, 1); 2413 if (error) { 2414 device_printf(sc->sc_dev, 2415 "can't allocate %dth RX buffer\n", i); 2416 return error; 2417 } 2418 } 2419 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2420 BUS_DMASYNC_PREWRITE); 2421 2422 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2423 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2424 return 0; 2425} 2426 2427static int 2428bwi_init_txstats32(struct bwi_softc *sc) 2429{ 2430 struct bwi_txstats_data *st = sc->sc_txstats; 2431 bus_addr_t stats_paddr; 2432 int i; 2433 2434 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2435 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2436 2437 st->stats_idx = 0; 2438 2439 stats_paddr = st->stats_paddr; 2440 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2441 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2442 stats_paddr, sizeof(struct bwi_txstats), 0); 2443 stats_paddr += sizeof(struct bwi_txstats); 2444 } 2445 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2446 BUS_DMASYNC_PREWRITE); 2447 2448 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2449 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2450 return 0; 2451} 2452 2453static void 2454bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2455 int buf_len) 2456{ 2457 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2458 2459 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2460 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2461 paddr, buf_len, 0); 2462} 2463 2464static void 2465bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2466 int buf_idx, bus_addr_t paddr, int buf_len) 2467{ 2468 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2469 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2470 paddr, buf_len, 1); 2471} 2472 2473static int 2474bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2475{ 2476 /* TODO:64 */ 2477 return EOPNOTSUPP; 2478} 2479 2480static int 2481bwi_init_rx_ring64(struct bwi_softc *sc) 2482{ 2483 /* TODO:64 */ 2484 return EOPNOTSUPP; 2485} 2486 2487static int 2488bwi_init_txstats64(struct bwi_softc *sc) 2489{ 2490 /* TODO:64 */ 2491 return EOPNOTSUPP; 2492} 2493 2494static void 2495bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2496 int buf_len) 2497{ 2498 /* TODO:64 */ 2499} 2500 2501static void 2502bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2503 int buf_idx, bus_addr_t paddr, int buf_len) 2504{ 2505 /* TODO:64 */ 2506} 2507 2508static void 2509bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2510 bus_size_t mapsz __unused, int error) 2511{ 2512 if (!error) { 2513 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2514 *((bus_addr_t *)arg) = seg->ds_addr; 2515 } 2516} 2517 2518static int 2519bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2520{ 2521 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2522 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2523 struct bwi_rxbuf_hdr *hdr; 2524 bus_dmamap_t map; 2525 bus_addr_t paddr; 2526 struct mbuf *m; 2527 int error; 2528 2529 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2530 2531 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2532 if (m == NULL) { 2533 error = ENOBUFS; 2534 2535 /* 2536 * If the NIC is up and running, we need to: 2537 * - Clear RX buffer's header. 2538 * - Restore RX descriptor settings. 2539 */ 2540 if (init) 2541 return error; 2542 else 2543 goto back; 2544 } 2545 m->m_len = m->m_pkthdr.len = MCLBYTES; 2546 2547 /* 2548 * Try to load RX buf into temporary DMA map 2549 */ 2550 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2551 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2552 if (error) { 2553 m_freem(m); 2554 2555 /* 2556 * See the comment above 2557 */ 2558 if (init) 2559 return error; 2560 else 2561 goto back; 2562 } 2563 2564 if (!init) 2565 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2566 rxbuf->rb_mbuf = m; 2567 rxbuf->rb_paddr = paddr; 2568 2569 /* 2570 * Swap RX buf's DMA map with the loaded temporary one 2571 */ 2572 map = rxbuf->rb_dmap; 2573 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2574 rbd->rbd_tmp_dmap = map; 2575 2576back: 2577 /* 2578 * Clear RX buf header 2579 */ 2580 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2581 bzero(hdr, sizeof(*hdr)); 2582 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2583 2584 /* 2585 * Setup RX buf descriptor 2586 */ 2587 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2588 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2589 return error; 2590} 2591 2592static void 2593bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2594 const uint8_t *addr) 2595{ 2596 int i; 2597 2598 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2599 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2600 2601 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2602 uint16_t addr_val; 2603 2604 addr_val = (uint16_t)addr[i * 2] | 2605 (((uint16_t)addr[(i * 2) + 1]) << 8); 2606 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2607 } 2608} 2609 2610static int 2611bwi_rxeof(struct bwi_softc *sc, int end_idx) 2612{ 2613 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2614 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2615 struct ifnet *ifp = sc->sc_ifp; 2616 struct ieee80211com *ic = ifp->if_l2com; 2617 int idx, rx_data = 0; 2618 2619 idx = rbd->rbd_idx; 2620 while (idx != end_idx) { 2621 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2622 struct bwi_rxbuf_hdr *hdr; 2623 struct ieee80211_frame_min *wh; 2624 struct ieee80211_node *ni; 2625 struct mbuf *m; 2626 const void *plcp; 2627 uint16_t flags2; 2628 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2629 2630 m = rb->rb_mbuf; 2631 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2632 BUS_DMASYNC_POSTREAD); 2633 2634 if (bwi_newbuf(sc, idx, 0)) { 2635 ifp->if_ierrors++; 2636 goto next; 2637 } 2638 2639 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2640 flags2 = le16toh(hdr->rxh_flags2); 2641 2642 hdr_extra = 0; 2643 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2644 hdr_extra = 2; 2645 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2646 2647 buflen = le16toh(hdr->rxh_buflen); 2648 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2649 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2650 __func__, hdr_extra); 2651 ifp->if_ierrors++; 2652 m_freem(m); 2653 goto next; 2654 } 2655 2656 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra); 2657 rssi = bwi_calc_rssi(sc, hdr); 2658 noise = bwi_calc_noise(sc); 2659 2660 m->m_pkthdr.rcvif = ifp; 2661 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2662 m_adj(m, sizeof(*hdr) + wh_ofs); 2663 2664 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2665 rate = bwi_ofdm_plcp2rate(plcp); 2666 else 2667 rate = bwi_ds_plcp2rate(plcp); 2668 2669 /* RX radio tap */ 2670 if (ieee80211_radiotap_active(ic)) 2671 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi, noise); 2672 2673 m_adj(m, -IEEE80211_CRC_LEN); 2674 2675 BWI_UNLOCK(sc); 2676 2677 wh = mtod(m, struct ieee80211_frame_min *); 2678 ni = ieee80211_find_rxnode(ic, wh); 2679 if (ni != NULL) { 2680 type = ieee80211_input(ni, m, rssi - noise, noise); 2681 ieee80211_free_node(ni); 2682 } else 2683 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2684 if (type == IEEE80211_FC0_TYPE_DATA) { 2685 rx_data = 1; 2686 sc->sc_rx_rate = rate; 2687 } 2688 2689 BWI_LOCK(sc); 2690next: 2691 idx = (idx + 1) % BWI_RX_NDESC; 2692 2693 if (sc->sc_flags & BWI_F_STOP) { 2694 /* 2695 * Take the fast lane, don't do 2696 * any damage to softc 2697 */ 2698 return -1; 2699 } 2700 } 2701 2702 rbd->rbd_idx = idx; 2703 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2704 BUS_DMASYNC_PREWRITE); 2705 2706 return rx_data; 2707} 2708 2709static int 2710bwi_rxeof32(struct bwi_softc *sc) 2711{ 2712 uint32_t val, rx_ctrl; 2713 int end_idx, rx_data; 2714 2715 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2716 2717 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2718 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2719 sizeof(struct bwi_desc32); 2720 2721 rx_data = bwi_rxeof(sc, end_idx); 2722 if (rx_data >= 0) { 2723 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2724 end_idx * sizeof(struct bwi_desc32)); 2725 } 2726 return rx_data; 2727} 2728 2729static int 2730bwi_rxeof64(struct bwi_softc *sc) 2731{ 2732 /* TODO:64 */ 2733 return 0; 2734} 2735 2736static void 2737bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2738{ 2739 int i; 2740 2741 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2742 2743#define NRETRY 10 2744 2745 for (i = 0; i < NRETRY; ++i) { 2746 uint32_t status; 2747 2748 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2749 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2750 BWI_RX32_STATUS_STATE_DISABLED) 2751 break; 2752 2753 DELAY(1000); 2754 } 2755 if (i == NRETRY) 2756 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2757 2758#undef NRETRY 2759 2760 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2761} 2762 2763static void 2764bwi_free_txstats32(struct bwi_softc *sc) 2765{ 2766 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2767} 2768 2769static void 2770bwi_free_rx_ring32(struct bwi_softc *sc) 2771{ 2772 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2773 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2774 int i; 2775 2776 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2777 2778 for (i = 0; i < BWI_RX_NDESC; ++i) { 2779 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2780 2781 if (rb->rb_mbuf != NULL) { 2782 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2783 m_freem(rb->rb_mbuf); 2784 rb->rb_mbuf = NULL; 2785 } 2786 } 2787} 2788 2789static void 2790bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2791{ 2792 struct bwi_ring_data *rd; 2793 struct bwi_txbuf_data *tbd; 2794 struct ifnet *ifp = sc->sc_ifp; 2795 uint32_t state, val; 2796 int i; 2797 2798 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2799 rd = &sc->sc_tx_rdata[ring_idx]; 2800 tbd = &sc->sc_tx_bdata[ring_idx]; 2801 2802#define NRETRY 10 2803 2804 for (i = 0; i < NRETRY; ++i) { 2805 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2806 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2807 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2808 state == BWI_TX32_STATUS_STATE_IDLE || 2809 state == BWI_TX32_STATUS_STATE_STOPPED) 2810 break; 2811 2812 DELAY(1000); 2813 } 2814 if (i == NRETRY) { 2815 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2816 __func__, ring_idx); 2817 } 2818 2819 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2820 for (i = 0; i < NRETRY; ++i) { 2821 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2822 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2823 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2824 break; 2825 2826 DELAY(1000); 2827 } 2828 if (i == NRETRY) 2829 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2830 __func__, ring_idx); 2831 2832#undef NRETRY 2833 2834 DELAY(1000); 2835 2836 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2837 2838 for (i = 0; i < BWI_TX_NDESC; ++i) { 2839 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2840 2841 if (tb->tb_mbuf != NULL) { 2842 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2843 m_freem(tb->tb_mbuf); 2844 tb->tb_mbuf = NULL; 2845 } 2846 if (tb->tb_ni != NULL) { 2847 ieee80211_free_node(tb->tb_ni); 2848 tb->tb_ni = NULL; 2849 } 2850 } 2851} 2852 2853static void 2854bwi_free_txstats64(struct bwi_softc *sc) 2855{ 2856 /* TODO:64 */ 2857} 2858 2859static void 2860bwi_free_rx_ring64(struct bwi_softc *sc) 2861{ 2862 /* TODO:64 */ 2863} 2864 2865static void 2866bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2867{ 2868 /* TODO:64 */ 2869} 2870 2871/* XXX does not belong here */ 2872#define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2873#define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2874 2875static __inline void 2876bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2877{ 2878 uint32_t plcp; 2879 2880 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2881 IEEE80211_OFDM_PLCP_RATE_MASK) | 2882 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2883 *plcp0 = htole32(plcp); 2884} 2885 2886static __inline void 2887bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2888 uint8_t rate) 2889{ 2890 int len, service, pkt_bitlen; 2891 2892 pkt_bitlen = pkt_len * NBBY; 2893 len = howmany(pkt_bitlen * 2, rate); 2894 2895 service = IEEE80211_PLCP_SERVICE_LOCKED; 2896 if (rate == (11 * 2)) { 2897 int pkt_bitlen1; 2898 2899 /* 2900 * PLCP service field needs to be adjusted, 2901 * if TX rate is 11Mbytes/s 2902 */ 2903 pkt_bitlen1 = len * 11; 2904 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2905 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2906 } 2907 2908 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2909 plcp->i_service = service; 2910 plcp->i_length = htole16(len); 2911 /* NOTE: do NOT touch i_crc */ 2912} 2913 2914static __inline void 2915bwi_plcp_header(const struct ieee80211_rate_table *rt, 2916 void *plcp, int pkt_len, uint8_t rate) 2917{ 2918 enum ieee80211_phytype modtype; 2919 2920 /* 2921 * Assume caller has zeroed 'plcp' 2922 */ 2923 modtype = ieee80211_rate2phytype(rt, rate); 2924 if (modtype == IEEE80211_T_OFDM) 2925 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2926 else if (modtype == IEEE80211_T_DS) 2927 bwi_ds_plcp_header(plcp, pkt_len, rate); 2928 else 2929 panic("unsupport modulation type %u\n", modtype); 2930} 2931 2932static int 2933bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2934 struct ieee80211_node *ni) 2935{ 2936 struct ieee80211vap *vap = ni->ni_vap; 2937 struct ifnet *ifp = sc->sc_ifp; 2938 struct ieee80211com *ic = ifp->if_l2com; 2939 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2940 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2941 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2942 struct bwi_mac *mac; 2943 struct bwi_txbuf_hdr *hdr; 2944 struct ieee80211_frame *wh; 2945 const struct ieee80211_txparam *tp; 2946 uint8_t rate, rate_fb; 2947 uint32_t mac_ctrl; 2948 uint16_t phy_ctrl; 2949 bus_addr_t paddr; 2950 int type, ismcast, pkt_len, error, rix; 2951#if 0 2952 const uint8_t *p; 2953 int i; 2954#endif 2955 2956 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2957 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2958 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2959 2960 wh = mtod(m, struct ieee80211_frame *); 2961 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2962 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2963 2964 /* Get 802.11 frame len before prepending TX header */ 2965 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2966 2967 /* 2968 * Find TX rate 2969 */ 2970 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2971 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2972 rate = rate_fb = tp->mgmtrate; 2973 } else if (ismcast) { 2974 rate = rate_fb = tp->mcastrate; 2975 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2976 rate = rate_fb = tp->ucastrate; 2977 } else { 2978 rix = ieee80211_amrr_choose(ni, &BWI_NODE(ni)->amn); 2979 rate = ni->ni_txrate; 2980 2981 if (rix > 0) { 2982 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2983 IEEE80211_RATE_VAL; 2984 } else { 2985 rate_fb = rate; 2986 } 2987 } 2988 tb->tb_rate[0] = rate; 2989 tb->tb_rate[1] = rate_fb; 2990 sc->sc_tx_rate = rate; 2991 2992 /* 2993 * TX radio tap 2994 */ 2995 if (ieee80211_radiotap_active_vap(vap)) { 2996 sc->sc_tx_th.wt_flags = 0; 2997 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2998 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2999 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3000 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3001 rate != (1 * 2)) { 3002 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3003 } 3004 sc->sc_tx_th.wt_rate = rate; 3005 3006 ieee80211_radiotap_tx(vap, m); 3007 } 3008 3009 /* 3010 * Setup the embedded TX header 3011 */ 3012 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3013 if (m == NULL) { 3014 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3015 return ENOBUFS; 3016 } 3017 hdr = mtod(m, struct bwi_txbuf_hdr *); 3018 3019 bzero(hdr, sizeof(*hdr)); 3020 3021 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3022 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3023 3024 if (!ismcast) { 3025 uint16_t dur; 3026 3027 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3028 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3029 3030 hdr->txh_fb_duration = htole16(dur); 3031 } 3032 3033 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3034 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3035 3036 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3037 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3038 3039 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3040 BWI_TXH_PHY_C_ANTMODE_MASK); 3041 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3042 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3043 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3044 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3045 3046 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3047 if (!ismcast) 3048 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3049 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3050 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3051 3052 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3053 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3054 3055 /* Catch any further usage */ 3056 hdr = NULL; 3057 wh = NULL; 3058 3059 /* DMA load */ 3060 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3061 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3062 if (error && error != EFBIG) { 3063 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3064 __func__, error); 3065 goto back; 3066 } 3067 3068 if (error) { /* error == EFBIG */ 3069 struct mbuf *m_new; 3070 3071 m_new = m_defrag(m, M_DONTWAIT); 3072 if (m_new == NULL) { 3073 if_printf(ifp, "%s: can't defrag TX buffer\n", 3074 __func__); 3075 error = ENOBUFS; 3076 goto back; 3077 } else { 3078 m = m_new; 3079 } 3080 3081 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3082 bwi_dma_buf_addr, &paddr, 3083 BUS_DMA_NOWAIT); 3084 if (error) { 3085 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3086 __func__, error); 3087 goto back; 3088 } 3089 } 3090 error = 0; 3091 3092 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3093 3094 tb->tb_mbuf = m; 3095 tb->tb_ni = ni; 3096 3097#if 0 3098 p = mtod(m, const uint8_t *); 3099 for (i = 0; i < m->m_pkthdr.len; ++i) { 3100 if (i != 0 && i % 8 == 0) 3101 printf("\n"); 3102 printf("%02x ", p[i]); 3103 } 3104 printf("\n"); 3105#endif 3106 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3107 idx, pkt_len, m->m_pkthdr.len); 3108 3109 /* Setup TX descriptor */ 3110 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3111 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3112 BUS_DMASYNC_PREWRITE); 3113 3114 /* Kick start */ 3115 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3116 3117back: 3118 if (error) 3119 m_freem(m); 3120 return error; 3121} 3122 3123static int 3124bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3125 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3126{ 3127 struct ifnet *ifp = sc->sc_ifp; 3128 struct ieee80211vap *vap = ni->ni_vap; 3129 struct ieee80211com *ic = ni->ni_ic; 3130 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3131 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3132 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3133 struct bwi_mac *mac; 3134 struct bwi_txbuf_hdr *hdr; 3135 struct ieee80211_frame *wh; 3136 uint8_t rate, rate_fb; 3137 uint32_t mac_ctrl; 3138 uint16_t phy_ctrl; 3139 bus_addr_t paddr; 3140 int ismcast, pkt_len, error; 3141 3142 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3143 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3144 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3145 3146 wh = mtod(m, struct ieee80211_frame *); 3147 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3148 3149 /* Get 802.11 frame len before prepending TX header */ 3150 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3151 3152 /* 3153 * Find TX rate 3154 */ 3155 rate = params->ibp_rate0; 3156 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3157 /* XXX fall back to mcast/mgmt rate? */ 3158 m_freem(m); 3159 return EINVAL; 3160 } 3161 if (params->ibp_try1 != 0) { 3162 rate_fb = params->ibp_rate1; 3163 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3164 /* XXX fall back to rate0? */ 3165 m_freem(m); 3166 return EINVAL; 3167 } 3168 } else 3169 rate_fb = rate; 3170 tb->tb_rate[0] = rate; 3171 tb->tb_rate[1] = rate_fb; 3172 sc->sc_tx_rate = rate; 3173 3174 /* 3175 * TX radio tap 3176 */ 3177 if (ieee80211_radiotap_active_vap(vap)) { 3178 sc->sc_tx_th.wt_flags = 0; 3179 /* XXX IEEE80211_BPF_CRYPTO */ 3180 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3181 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3182 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3183 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3184 sc->sc_tx_th.wt_rate = rate; 3185 3186 ieee80211_radiotap_tx(vap, m); 3187 } 3188 3189 /* 3190 * Setup the embedded TX header 3191 */ 3192 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3193 if (m == NULL) { 3194 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3195 return ENOBUFS; 3196 } 3197 hdr = mtod(m, struct bwi_txbuf_hdr *); 3198 3199 bzero(hdr, sizeof(*hdr)); 3200 3201 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3202 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3203 3204 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3205 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3206 uint16_t dur; 3207 3208 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3209 3210 hdr->txh_fb_duration = htole16(dur); 3211 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3212 } 3213 3214 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3215 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3216 3217 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3218 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3219 3220 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3221 BWI_TXH_PHY_C_ANTMODE_MASK); 3222 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3223 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3224 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3225 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3226 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3227 3228 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3229 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3230 3231 /* Catch any further usage */ 3232 hdr = NULL; 3233 wh = NULL; 3234 3235 /* DMA load */ 3236 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3237 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3238 if (error != 0) { 3239 struct mbuf *m_new; 3240 3241 if (error != EFBIG) { 3242 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3243 __func__, error); 3244 goto back; 3245 } 3246 m_new = m_defrag(m, M_DONTWAIT); 3247 if (m_new == NULL) { 3248 if_printf(ifp, "%s: can't defrag TX buffer\n", 3249 __func__); 3250 error = ENOBUFS; 3251 goto back; 3252 } 3253 m = m_new; 3254 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3255 bwi_dma_buf_addr, &paddr, 3256 BUS_DMA_NOWAIT); 3257 if (error) { 3258 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3259 __func__, error); 3260 goto back; 3261 } 3262 } 3263 3264 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3265 3266 tb->tb_mbuf = m; 3267 tb->tb_ni = ni; 3268 3269 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3270 idx, pkt_len, m->m_pkthdr.len); 3271 3272 /* Setup TX descriptor */ 3273 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3274 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3275 BUS_DMASYNC_PREWRITE); 3276 3277 /* Kick start */ 3278 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3279back: 3280 if (error) 3281 m_freem(m); 3282 return error; 3283} 3284 3285static void 3286bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3287{ 3288 idx = (idx + 1) % BWI_TX_NDESC; 3289 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3290 idx * sizeof(struct bwi_desc32)); 3291} 3292 3293static void 3294bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3295{ 3296 /* TODO:64 */ 3297} 3298 3299static void 3300bwi_txeof_status32(struct bwi_softc *sc) 3301{ 3302 struct ifnet *ifp = sc->sc_ifp; 3303 uint32_t val, ctrl_base; 3304 int end_idx; 3305 3306 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3307 3308 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3309 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3310 sizeof(struct bwi_desc32); 3311 3312 bwi_txeof_status(sc, end_idx); 3313 3314 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3315 end_idx * sizeof(struct bwi_desc32)); 3316 3317 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3318 ifp->if_start(ifp); 3319} 3320 3321static void 3322bwi_txeof_status64(struct bwi_softc *sc) 3323{ 3324 /* TODO:64 */ 3325} 3326 3327static void 3328_bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3329{ 3330 struct ifnet *ifp = sc->sc_ifp; 3331 struct bwi_txbuf_data *tbd; 3332 struct bwi_txbuf *tb; 3333 int ring_idx, buf_idx; 3334 struct ieee80211_node *ni; 3335 3336 if (tx_id == 0) { 3337 if_printf(ifp, "%s: zero tx id\n", __func__); 3338 return; 3339 } 3340 3341 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3342 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3343 3344 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3345 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3346 3347 tbd = &sc->sc_tx_bdata[ring_idx]; 3348 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3349 tbd->tbd_used--; 3350 3351 tb = &tbd->tbd_buf[buf_idx]; 3352 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3353 "acked %d, data_txcnt %d, ni %p\n", 3354 buf_idx, acked, data_txcnt, tb->tb_ni); 3355 3356 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3357 3358 ni = tb->tb_ni; 3359 if (tb->tb_ni != NULL) { 3360 struct bwi_node *bn = (struct bwi_node *) tb->tb_ni; 3361 const struct bwi_txbuf_hdr *hdr = 3362 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3363 3364 /* NB: update rate control only for unicast frames */ 3365 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3366 /* 3367 * Feed back 'acked and data_txcnt'. Note that the 3368 * generic AMRR code only understands one tx rate 3369 * and the estimator doesn't handle real retry counts 3370 * well so to avoid over-aggressive downshifting we 3371 * treat any number of retries as "1". 3372 */ 3373 ieee80211_amrr_tx_complete(&bn->amn, acked, 3374 data_txcnt > 1); 3375 } 3376 3377 /* 3378 * Do any tx complete callback. Note this must 3379 * be done before releasing the node reference. 3380 */ 3381 if (tb->tb_mbuf->m_flags & M_TXCB) 3382 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3383 3384 ieee80211_free_node(tb->tb_ni); 3385 tb->tb_ni = NULL; 3386 } 3387 m_freem(tb->tb_mbuf); 3388 tb->tb_mbuf = NULL; 3389 3390 if (tbd->tbd_used == 0) 3391 ifp->if_timer = 0; 3392 3393 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3394} 3395 3396static void 3397bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3398{ 3399 struct bwi_txstats_data *st = sc->sc_txstats; 3400 int idx; 3401 3402 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3403 3404 idx = st->stats_idx; 3405 while (idx != end_idx) { 3406 const struct bwi_txstats *stats = &st->stats[idx]; 3407 3408 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3409 int data_txcnt; 3410 3411 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3412 BWI_TXS_TXCNT_DATA); 3413 _bwi_txeof(sc, le16toh(stats->txs_id), 3414 stats->txs_flags & BWI_TXS_F_ACKED, 3415 data_txcnt); 3416 } 3417 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3418 } 3419 st->stats_idx = idx; 3420} 3421 3422static void 3423bwi_txeof(struct bwi_softc *sc) 3424{ 3425 struct ifnet *ifp = sc->sc_ifp; 3426 3427 for (;;) { 3428 uint32_t tx_status0, tx_status1; 3429 uint16_t tx_id; 3430 int data_txcnt; 3431 3432 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3433 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3434 break; 3435 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3436 3437 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3438 data_txcnt = __SHIFTOUT(tx_status0, 3439 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3440 3441 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3442 continue; 3443 3444 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3445 data_txcnt); 3446 } 3447 3448 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3449 ifp->if_start(ifp); 3450} 3451 3452static int 3453bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3454{ 3455 bwi_power_on(sc, 1); 3456 return bwi_set_clock_mode(sc, clk_mode); 3457} 3458 3459static void 3460bwi_bbp_power_off(struct bwi_softc *sc) 3461{ 3462 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3463 bwi_power_off(sc, 1); 3464} 3465 3466static int 3467bwi_get_pwron_delay(struct bwi_softc *sc) 3468{ 3469 struct bwi_regwin *com, *old; 3470 struct bwi_clock_freq freq; 3471 uint32_t val; 3472 int error; 3473 3474 com = &sc->sc_com_regwin; 3475 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3476 3477 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3478 return 0; 3479 3480 error = bwi_regwin_switch(sc, com, &old); 3481 if (error) 3482 return error; 3483 3484 bwi_get_clock_freq(sc, &freq); 3485 3486 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3487 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3488 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3489 3490 return bwi_regwin_switch(sc, old, NULL); 3491} 3492 3493static int 3494bwi_bus_attach(struct bwi_softc *sc) 3495{ 3496 struct bwi_regwin *bus, *old; 3497 int error; 3498 3499 bus = &sc->sc_bus_regwin; 3500 3501 error = bwi_regwin_switch(sc, bus, &old); 3502 if (error) 3503 return error; 3504 3505 if (!bwi_regwin_is_enabled(sc, bus)) 3506 bwi_regwin_enable(sc, bus, 0); 3507 3508 /* Disable interripts */ 3509 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3510 3511 return bwi_regwin_switch(sc, old, NULL); 3512} 3513 3514static const char * 3515bwi_regwin_name(const struct bwi_regwin *rw) 3516{ 3517 switch (rw->rw_type) { 3518 case BWI_REGWIN_T_COM: 3519 return "COM"; 3520 case BWI_REGWIN_T_BUSPCI: 3521 return "PCI"; 3522 case BWI_REGWIN_T_MAC: 3523 return "MAC"; 3524 case BWI_REGWIN_T_BUSPCIE: 3525 return "PCIE"; 3526 } 3527 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3528 return NULL; 3529} 3530 3531static uint32_t 3532bwi_regwin_disable_bits(struct bwi_softc *sc) 3533{ 3534 uint32_t busrev; 3535 3536 /* XXX cache this */ 3537 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3538 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3539 "bus rev %u\n", busrev); 3540 3541 if (busrev == BWI_BUSREV_0) 3542 return BWI_STATE_LO_DISABLE1; 3543 else if (busrev == BWI_BUSREV_1) 3544 return BWI_STATE_LO_DISABLE2; 3545 else 3546 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3547} 3548 3549int 3550bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3551{ 3552 uint32_t val, disable_bits; 3553 3554 disable_bits = bwi_regwin_disable_bits(sc); 3555 val = CSR_READ_4(sc, BWI_STATE_LO); 3556 3557 if ((val & (BWI_STATE_LO_CLOCK | 3558 BWI_STATE_LO_RESET | 3559 disable_bits)) == BWI_STATE_LO_CLOCK) { 3560 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3561 bwi_regwin_name(rw)); 3562 return 1; 3563 } else { 3564 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3565 bwi_regwin_name(rw)); 3566 return 0; 3567 } 3568} 3569 3570void 3571bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3572{ 3573 uint32_t state_lo, disable_bits; 3574 int i; 3575 3576 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3577 3578 /* 3579 * If current regwin is in 'reset' state, it was already disabled. 3580 */ 3581 if (state_lo & BWI_STATE_LO_RESET) { 3582 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3583 "%s was already disabled\n", bwi_regwin_name(rw)); 3584 return; 3585 } 3586 3587 disable_bits = bwi_regwin_disable_bits(sc); 3588 3589 /* 3590 * Disable normal clock 3591 */ 3592 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3593 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3594 3595 /* 3596 * Wait until normal clock is disabled 3597 */ 3598#define NRETRY 1000 3599 for (i = 0; i < NRETRY; ++i) { 3600 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3601 if (state_lo & disable_bits) 3602 break; 3603 DELAY(10); 3604 } 3605 if (i == NRETRY) { 3606 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3607 bwi_regwin_name(rw)); 3608 } 3609 3610 for (i = 0; i < NRETRY; ++i) { 3611 uint32_t state_hi; 3612 3613 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3614 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3615 break; 3616 DELAY(10); 3617 } 3618 if (i == NRETRY) { 3619 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3620 bwi_regwin_name(rw)); 3621 } 3622#undef NRETRY 3623 3624 /* 3625 * Reset and disable regwin with gated clock 3626 */ 3627 state_lo = BWI_STATE_LO_RESET | disable_bits | 3628 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3629 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3630 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3631 3632 /* Flush pending bus write */ 3633 CSR_READ_4(sc, BWI_STATE_LO); 3634 DELAY(1); 3635 3636 /* Reset and disable regwin */ 3637 state_lo = BWI_STATE_LO_RESET | disable_bits | 3638 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3639 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3640 3641 /* Flush pending bus write */ 3642 CSR_READ_4(sc, BWI_STATE_LO); 3643 DELAY(1); 3644} 3645 3646void 3647bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3648{ 3649 uint32_t state_lo, state_hi, imstate; 3650 3651 bwi_regwin_disable(sc, rw, flags); 3652 3653 /* Reset regwin with gated clock */ 3654 state_lo = BWI_STATE_LO_RESET | 3655 BWI_STATE_LO_CLOCK | 3656 BWI_STATE_LO_GATED_CLOCK | 3657 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3658 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3659 3660 /* Flush pending bus write */ 3661 CSR_READ_4(sc, BWI_STATE_LO); 3662 DELAY(1); 3663 3664 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3665 if (state_hi & BWI_STATE_HI_SERROR) 3666 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3667 3668 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3669 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3670 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3671 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3672 } 3673 3674 /* Enable regwin with gated clock */ 3675 state_lo = BWI_STATE_LO_CLOCK | 3676 BWI_STATE_LO_GATED_CLOCK | 3677 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3678 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3679 3680 /* Flush pending bus write */ 3681 CSR_READ_4(sc, BWI_STATE_LO); 3682 DELAY(1); 3683 3684 /* Enable regwin with normal clock */ 3685 state_lo = BWI_STATE_LO_CLOCK | 3686 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3687 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3688 3689 /* Flush pending bus write */ 3690 CSR_READ_4(sc, BWI_STATE_LO); 3691 DELAY(1); 3692} 3693 3694static void 3695bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3696{ 3697 struct ifnet *ifp = sc->sc_ifp; 3698 struct bwi_mac *mac; 3699 struct bwi_myaddr_bssid buf; 3700 const uint8_t *p; 3701 uint32_t val; 3702 int n, i; 3703 3704 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3705 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3706 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3707 3708 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3709 3710 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3711 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3712 3713 n = sizeof(buf) / sizeof(val); 3714 p = (const uint8_t *)&buf; 3715 for (i = 0; i < n; ++i) { 3716 int j; 3717 3718 val = 0; 3719 for (j = 0; j < sizeof(val); ++j) 3720 val |= ((uint32_t)(*p++)) << (j * 8); 3721 3722 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3723 } 3724} 3725 3726static void 3727bwi_updateslot(struct ifnet *ifp) 3728{ 3729 struct bwi_softc *sc = ifp->if_softc; 3730 struct ieee80211com *ic = ifp->if_l2com; 3731 struct bwi_mac *mac; 3732 3733 BWI_LOCK(sc); 3734 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3735 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3736 3737 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3738 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3739 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3740 3741 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3742 } 3743 BWI_UNLOCK(sc); 3744} 3745 3746static void 3747bwi_calibrate(void *xsc) 3748{ 3749 struct bwi_softc *sc = xsc; 3750#ifdef INVARIANTS 3751 struct ifnet *ifp = sc->sc_ifp; 3752 struct ieee80211com *ic = ifp->if_l2com; 3753#endif 3754 struct bwi_mac *mac; 3755 3756 BWI_ASSERT_LOCKED(sc); 3757 3758 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3759 ("opmode %d", ic->ic_opmode)); 3760 3761 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3762 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3763 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3764 3765 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3766 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3767 3768 /* XXX 15 seconds */ 3769 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3770} 3771 3772static int 3773bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3774{ 3775 struct bwi_mac *mac; 3776 3777 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3778 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3779 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3780 3781 return bwi_rf_calc_rssi(mac, hdr); 3782} 3783 3784static int 3785bwi_calc_noise(struct bwi_softc *sc) 3786{ 3787 struct bwi_mac *mac; 3788 3789 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3790 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3791 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3792 3793 return bwi_rf_calc_noise(mac); 3794} 3795 3796static __inline uint8_t 3797bwi_ofdm_plcp2rate(const uint32_t *plcp0) 3798{ 3799 uint32_t plcp; 3800 uint8_t plcp_rate; 3801 3802 plcp = le32toh(*plcp0); 3803 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK); 3804 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM); 3805} 3806 3807static __inline uint8_t 3808bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr) 3809{ 3810 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS); 3811} 3812 3813static void 3814bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3815 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3816{ 3817 const struct ieee80211_frame_min *wh; 3818 3819 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3820 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3821 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3822 3823 wh = mtod(m, const struct ieee80211_frame_min *); 3824 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3825 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3826 3827 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3828 sc->sc_rx_th.wr_rate = rate; 3829 sc->sc_rx_th.wr_antsignal = rssi; 3830 sc->sc_rx_th.wr_antnoise = noise; 3831} 3832 3833static void 3834bwi_led_attach(struct bwi_softc *sc) 3835{ 3836 const uint8_t *led_act = NULL; 3837 uint16_t gpio, val[BWI_LED_MAX]; 3838 int i; 3839 3840#define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3841 3842 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3843 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3844 led_act = bwi_vendor_led_act[i].led_act; 3845 break; 3846 } 3847 } 3848 if (led_act == NULL) 3849 led_act = bwi_default_led_act; 3850 3851#undef N 3852 3853 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3854 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3855 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3856 3857 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3858 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3859 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3860 3861 for (i = 0; i < BWI_LED_MAX; ++i) { 3862 struct bwi_led *led = &sc->sc_leds[i]; 3863 3864 if (val[i] == 0xff) { 3865 led->l_act = led_act[i]; 3866 } else { 3867 if (val[i] & BWI_LED_ACT_LOW) 3868 led->l_flags |= BWI_LED_F_ACTLOW; 3869 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3870 } 3871 led->l_mask = (1 << i); 3872 3873 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3874 led->l_act == BWI_LED_ACT_BLINK_POLL || 3875 led->l_act == BWI_LED_ACT_BLINK) { 3876 led->l_flags |= BWI_LED_F_BLINK; 3877 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3878 led->l_flags |= BWI_LED_F_POLLABLE; 3879 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3880 led->l_flags |= BWI_LED_F_SLOW; 3881 3882 if (sc->sc_blink_led == NULL) { 3883 sc->sc_blink_led = led; 3884 if (led->l_flags & BWI_LED_F_SLOW) 3885 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3886 } 3887 } 3888 3889 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3890 "%dth led, act %d, lowact %d\n", i, 3891 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3892 } 3893 callout_init(&sc->sc_led_blink_ch, CALLOUT_MPSAFE); 3894} 3895 3896static __inline uint16_t 3897bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3898{ 3899 if (led->l_flags & BWI_LED_F_ACTLOW) 3900 on = !on; 3901 if (on) 3902 val |= led->l_mask; 3903 else 3904 val &= ~led->l_mask; 3905 return val; 3906} 3907 3908static void 3909bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3910{ 3911 struct ifnet *ifp = sc->sc_ifp; 3912 struct ieee80211com *ic = ifp->if_l2com; 3913 uint16_t val; 3914 int i; 3915 3916 if (nstate == IEEE80211_S_INIT) { 3917 callout_stop(&sc->sc_led_blink_ch); 3918 sc->sc_led_blinking = 0; 3919 } 3920 3921 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3922 return; 3923 3924 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3925 for (i = 0; i < BWI_LED_MAX; ++i) { 3926 struct bwi_led *led = &sc->sc_leds[i]; 3927 int on; 3928 3929 if (led->l_act == BWI_LED_ACT_UNKN || 3930 led->l_act == BWI_LED_ACT_NULL) 3931 continue; 3932 3933 if ((led->l_flags & BWI_LED_F_BLINK) && 3934 nstate != IEEE80211_S_INIT) 3935 continue; 3936 3937 switch (led->l_act) { 3938 case BWI_LED_ACT_ON: /* Always on */ 3939 on = 1; 3940 break; 3941 case BWI_LED_ACT_OFF: /* Always off */ 3942 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3943 on = 0; 3944 break; 3945 default: 3946 on = 1; 3947 switch (nstate) { 3948 case IEEE80211_S_INIT: 3949 on = 0; 3950 break; 3951 case IEEE80211_S_RUN: 3952 if (led->l_act == BWI_LED_ACT_11G && 3953 ic->ic_curmode != IEEE80211_MODE_11G) 3954 on = 0; 3955 break; 3956 default: 3957 if (led->l_act == BWI_LED_ACT_ASSOC) 3958 on = 0; 3959 break; 3960 } 3961 break; 3962 } 3963 3964 val = bwi_led_onoff(led, val, on); 3965 } 3966 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3967} 3968static void 3969bwi_led_event(struct bwi_softc *sc, int event) 3970{ 3971 struct bwi_led *led = sc->sc_blink_led; 3972 int rate; 3973 3974 if (event == BWI_LED_EVENT_POLL) { 3975 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3976 return; 3977 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3978 return; 3979 } 3980 3981 sc->sc_led_ticks = ticks; 3982 if (sc->sc_led_blinking) 3983 return; 3984 3985 switch (event) { 3986 case BWI_LED_EVENT_RX: 3987 rate = sc->sc_rx_rate; 3988 break; 3989 case BWI_LED_EVENT_TX: 3990 rate = sc->sc_tx_rate; 3991 break; 3992 case BWI_LED_EVENT_POLL: 3993 rate = 0; 3994 break; 3995 default: 3996 panic("unknown LED event %d\n", event); 3997 break; 3998 } 3999 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 4000 bwi_led_duration[rate].off_dur); 4001} 4002 4003static void 4004bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4005{ 4006 struct bwi_led *led = sc->sc_blink_led; 4007 uint16_t val; 4008 4009 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4010 val = bwi_led_onoff(led, val, 1); 4011 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4012 4013 if (led->l_flags & BWI_LED_F_SLOW) { 4014 BWI_LED_SLOWDOWN(on_dur); 4015 BWI_LED_SLOWDOWN(off_dur); 4016 } 4017 4018 sc->sc_led_blinking = 1; 4019 sc->sc_led_blink_offdur = off_dur; 4020 4021 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4022} 4023 4024static void 4025bwi_led_blink_next(void *xsc) 4026{ 4027 struct bwi_softc *sc = xsc; 4028 uint16_t val; 4029 4030 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4031 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4032 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4033 4034 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4035 bwi_led_blink_end, sc); 4036} 4037 4038static void 4039bwi_led_blink_end(void *xsc) 4040{ 4041 struct bwi_softc *sc = xsc; 4042 sc->sc_led_blinking = 0; 4043} 4044 4045static void 4046bwi_restart(void *xsc, int pending) 4047{ 4048 struct bwi_softc *sc = xsc; 4049 struct ifnet *ifp = sc->sc_ifp; 4050 4051 if_printf(ifp, "%s begin, help!\n", __func__); 4052 BWI_LOCK(sc); 4053 bwi_init_statechg(xsc, 0); 4054 BWI_UNLOCK(sc); 4055#if 0 4056 bwi_start_locked(ifp); 4057#endif 4058} 4059