1/*- 2 * Copyright (c) 2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2015 Broadcom Corporation 4 * All rights reserved. 5 * 6 * This file is derived from the pcie_core.h and pcie2_core.h headers 7 * from Broadcom's Linux driver sources as distributed by dd-wrt. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 16 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 18 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 19 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 * $FreeBSD$ 22 */ 23 24#ifndef _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ 25#define _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ 26 27#define BHND_PCIE2_CLK_CONTROL 0x000 28 29#define BHND_PCIE2_RC_PM_CONTROL 0x004 30#define BHND_PCIE2_RC_PM_STATUS 0x008 31#define BHND_PCIE2_EP_PM_CONTROL 0x00C 32#define BHND_PCIE2_EP_PM_STATUS 0x010 33#define BHND_PCIE2_EP_LTR_CONTROL 0x014 34#define BHND_PCIE2_EP_LTR_STATUS 0x018 35#define BHND_PCIE2_EP_OBFF_STATUS 0x01C 36#define BHND_PCIE2_PCIE_ERR_STATUS 0x020 37#define BHND_PCIE2_RC_AXI_CONFIG 0x100 38#define BHND_PCIE2_EP_AXI_CONFIG 0x104 39#define BHND_PCIE2_RXDEBUG_STATUS0 0x108 40#define BHND_PCIE2_RXDEBUG_CONTROL0 0x10C 41 42#define BHND_PCIE2_CONFIGINDADDR 0x120 43#define BHND_PCIE2_CONFIGINDDATA 0x124 44 45#define BHND_PCIE2_CFG_ADDR 0x1F8 46#define BHND_PCIE2_CFG_DATA 0x1FC 47 48#define BHND_PCIE2_SYS_EQ_PAGE 0x200 49#define BHND_PCIE2_SYS_MSI_PAGE 0x204 50#define BHND_PCIE2_SYS_MSI_INTREN 0x208 51#define BHND_PCIE2_SYS_MSI_CTRL0 0x210 52#define BHND_PCIE2_SYS_MSI_CTRL1 0x214 53#define BHND_PCIE2_SYS_MSI_CTRL2 0x218 54#define BHND_PCIE2_SYS_MSI_CTRL3 0x21C 55#define BHND_PCIE2_SYS_MSI_CTRL4 0x220 56#define BHND_PCIE2_SYS_MSI_CTRL5 0x224 57 58#define BHND_PCIE2_SYS_EQ_HEAD0 0x250 59#define BHND_PCIE2_SYS_EQ_TAIL0 0x254 60#define BHND_PCIE2_SYS_EQ_HEAD1 0x258 61#define BHND_PCIE2_SYS_EQ_TAIL1 0x25C 62#define BHND_PCIE2_SYS_EQ_HEAD2 0x260 63#define BHND_PCIE2_SYS_EQ_TAIL2 0x264 64#define BHND_PCIE2_SYS_EQ_HEAD3 0x268 65#define BHND_PCIE2_SYS_EQ_TAIL3 0x26C 66#define BHND_PCIE2_SYS_EQ_HEAD4 0x270 67#define BHND_PCIE2_SYS_EQ_TAIL4 0x274 68#define BHND_PCIE2_SYS_EQ_HEAD5 0x278 69#define BHND_PCIE2_SYS_EQ_TAIL5 0x27C 70 71#define BHND_PCIE2_SYS_RC_INTX_EN 0x330 72#define BHND_PCIE2_SYS_RC_INTX_CSR 0x334 73#define BHND_PCIE2_SYS_MSI_REQ 0x340 74#define BHND_PCIE2_SYS_HOST_INTR_EN 0x344 75#define BHND_PCIE2_SYS_HOST_INTR_CSR 0x348 76#define BHND_PCIE2_SYS_HOST_INTR0 0x350 77#define BHND_PCIE2_SYS_HOST_INTR1 0x354 78#define BHND_PCIE2_SYS_HOST_INTR2 0x358 79#define BHND_PCIE2_SYS_HOST_INTR3 0x35C 80#define BHND_PCIE2_SYS_EP_INT_EN0 0x360 81#define BHND_PCIE2_SYS_EP_INT_EN1 0x364 82#define BHND_PCIE2_SYS_EP_INT_CSR0 0x370 83#define BHND_PCIE2_SYS_EP_INT_CSR1 0x374 84 85#define BHND_PCIE2_MDIO_CTL 0x128 /**< mdio control */ 86#define BHND_PCIE2_MDIO_WRDATA 0x12C /**< mdio data write */ 87#define BHND_PCIE2_MDIO_RDDATA 0x130 /**< mdio data read */ 88 89 90/* DMA doorbell registers (>= rev5) */ 91#define BHND_PCIE2_DB0_HOST2DEV0 0x140 92#define BHND_PCIE2_DB0_HOST2DEV1 0x144 93#define BHND_PCIE2_DB0_DEV2HOST0 0x148 94#define BHND_PCIE2_DB0_DEV2HOST1 0x14C 95 96#define BHND_PCIE2_DB1_HOST2DEV0 0x150 97#define BHND_PCIE2_DB1_HOST2DEV1 0x154 98#define BHND_PCIE2_DB1_DEV2HOST0 0x158 99#define BHND_PCIE2_DB1_DEV2HOST1 0x15C 100 101#define BHND_PCIE2_DB2_HOST2DEV0 0x160 102#define BHND_PCIE2_DB2_HOST2DEV1 0x164 103#define BHND_PCIE2_DB2_DEV2HOST0 0x168 104#define BHND_PCIE2_DB2_DEV2HOST1 0x16C 105 106#define BHND_PCIE2_DB3_HOST2DEV0 0x170 107#define BHND_PCIE2_DB3_HOST2DEV1 0x174 108#define BHND_PCIE2_DB3_DEV2HOST0 0x178 109#define BHND_PCIE2_DB3_DEV2HOST1 0x17C 110 111#define BHND_PCIE2_DATAINTF 0x180 112#define BHND_PCIE2_INTRLAZY0_DEV2HOST 0x188 113#define BHND_PCIE2_INTRLAZY0_HOST2DEV 0x18c 114#define BHND_PCIE2_INTSTAT0_HOST2DEV 0x190 115#define BHND_PCIE2_INTMASK0_HOST2DEV 0x194 116#define BHND_PCIE2_INTSTAT0_DEV2HOST 0x198 117#define BHND_PCIE2_INTMASK0_DEV2HOST 0x19c 118#define BHND_PCIE2_LTR_STATE 0x1A0 119#define BHND_PCIE2_PWR_INT_STATUS 0x1A4 120#define BHND_PCIE2_PWR_INT_MASK 0x1A8 121 122/* DMA channel registers */ 123#define BHND_PCIE2_DMA0_HOST2DEV_TX 0x200 124#define BHND_PCIE2_DMA0_HOST2DEV_RX 0x220 125#define BHND_PCIE2_DMA0_DEV2HOST_TX 0x240 126#define BHND_PCIE2_DMA0_DEV2HOST_RX 0x260 127 128#define BHND_PCIE2_DMA1_HOST2DEV_TX 0x280 129#define BHND_PCIE2_DMA1_HOST2DEV_RX 0x2A0 130#define BHND_PCIE2_DMA1_DEV2HOST_TX 0x2C0 131#define BHND_PCIE2_DMA1_DEV2HOST_RX 0x2E0 132 133#define BHND_PCIE2_DMA2_HOST2DEV_TX 0x300 134#define BHND_PCIE2_DMA2_HOST2DEV_RX 0x320 135#define BHND_PCIE2_DMA2_DEV2HOST_TX 0x340 136#define BHND_PCIE2_DMA2_DEV2HOST_RX 0x360 137 138#define BHND_PCIE2_DMA3_HOST2DEV_TX 0x380 139#define BHND_PCIE2_DMA3_HOST2DEV_RX 0x3A0 140#define BHND_PCIE2_DMA3_DEV2HOST_TX 0x3C0 141#define BHND_PCIE2_DMA3_DEV2HOST_RX 0x3E0 142 143#define BHND_PCIE2_PCIE_FUNC0_CFG 0x400 /**< PCIe function 0 config space */ 144#define BHND_PCIE2_PCIE_FUNC1_CFG 0x500 /**< PCIe function 1 config space */ 145#define BHND_PCIE2_PCIE_FUNC2_CFG 0x600 /**< PCIe function 2 config space */ 146#define BHND_PCIE2_PCIE_FUNC3_CFG 0x700 /**< PCIe function 3 config space */ 147#define BHND_PCIE2_SPROM 0x800 /**< SPROM shadow */ 148 149#define BHND_PCIE2_FUNC0_IMAP0_0 0xC00 150#define BHND_PCIE2_FUNC0_IMAP0_1 0xC04 151#define BHND_PCIE2_FUNC0_IMAP0_2 0xC08 152#define BHND_PCIE2_FUNC0_IMAP0_3 0xC0C 153#define BHND_PCIE2_FUNC0_IMAP0_4 0xC10 154#define BHND_PCIE2_FUNC0_IMAP0_5 0xC14 155#define BHND_PCIE2_FUNC0_IMAP0_6 0xC18 156#define BHND_PCIE2_FUNC0_IMAP0_7 0xC1C 157 158#define BHND_PCIE2_FUNC1_IMAP0_0 0xC20 159#define BHND_PCIE2_FUNC1_IMAP0_1 0xC24 160#define BHND_PCIE2_FUNC1_IMAP0_2 0xC28 161#define BHND_PCIE2_FUNC1_IMAP0_3 0xC2C 162#define BHND_PCIE2_FUNC1_IMAP0_4 0xC30 163#define BHND_PCIE2_FUNC1_IMAP0_5 0xC34 164#define BHND_PCIE2_FUNC1_IMAP0_6 0xC38 165#define BHND_PCIE2_FUNC1_IMAP0_7 0xC3C 166 167#define BHND_PCIE2_FUNC0_IMAP1 0xC80 168#define BHND_PCIE2_FUNC1_IMAP1 0xC88 169#define BHND_PCIE2_FUNC0_IMAP2 0xCC0 170#define BHND_PCIE2_FUNC1_IMAP2 0xCC8 171 172#define BHND_PCIE2_IARR0_LOWER 0xD00 173#define BHND_PCIE2_IARR0_UPPER 0xD04 174#define BHND_PCIE2_IARR1_LOWER 0xD08 175#define BHND_PCIE2_IARR1_UPPER 0xD0C 176#define BHND_PCIE2_IARR2_LOWER 0xD10 177#define BHND_PCIE2_IARR2_UPPER 0xD14 178#define BHND_PCIE2_OARR0 0xD20 179#define BHND_PCIE2_OARR1 0xD28 180#define BHND_PCIE2_OARR2 0xD30 181#define BHND_PCIE2_OMAP0_LOWER 0xD40 182#define BHND_PCIE2_OMAP0_UPPER 0xD44 183#define BHND_PCIE2_OMAP1_LOWER 0xD48 184#define BHND_PCIE2_OMAP1_UPPER 0xD4C 185#define BHND_PCIE2_OMAP2_LOWER 0xD50 186#define BHND_PCIE2_OMAP2_UPPER 0xD54 187#define BHND_PCIE2_FUNC1_IARR1_SIZE 0xD58 188#define BHND_PCIE2_FUNC1_IARR2_SIZE 0xD5C 189#define BHND_PCIE2_MEM_CONTROL 0xF00 190#define BHND_PCIE2_MEM_ECC_ERRLOG0 0xF04 191#define BHND_PCIE2_MEM_ECC_ERRLOG1 0xF08 192#define BHND_PCIE2_LINK_STATUS 0xF0C 193#define BHND_PCIE2_STRAP_STATUS 0xF10 194#define BHND_PCIE2_RESET_STATUS 0xF14 195#define BHND_PCIE2_RESETEN_IN_LINKDOWN 0xF18 196#define BHND_PCIE2_MISC_INTR_EN 0xF1C 197#define BHND_PCIE2_TX_DEBUG_CFG 0xF20 198#define BHND_PCIE2_MISC_CONFIG 0xF24 199#define BHND_PCIE2_MISC_STATUS 0xF28 200#define BHND_PCIE2_INTR_EN 0xF30 201#define BHND_PCIE2_INTR_CLEAR 0xF34 202#define BHND_PCIE2_INTR_STATUS 0xF38 203 204/* BHND_PCIE2_MDIO_CTL */ 205#define BHND_PCIE2_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ 206#define BHND_PCIE2_MDIOCTL_DIVISOR_VAL 0x2 207#define BHND_PCIE2_MDIOCTL_REGADDR_SHIFT 8 /* Regaddr shift */ 208#define BHND_PCIE2_MDIOCTL_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ 209#define BHND_PCIE2_MDIOCTL_DEVADDR_SHIFT 24 /* Physmedia devaddr shift */ 210#define BHND_PCIE2_MDIOCTL_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ 211#define BHND_PCIE2_MDIOCTL_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ 212#define BHND_PCIE2_MDIOCTL_READ 0x20000000 /* IP slave bypass */ 213 214/* BHND_PCIE2_MDIO_DATA */ 215#define BHND_PCIE2_MDIODATA_DONE 0x80000000 /* rd/wr transaction done */ 216#define BHND_PCIE2_MDIODATA_MASK 0x7FFFFFFF /* rd/wr transaction data */ 217#define BHND_PCIE2_MDIODATA_DEVADDR_SHIFT 4 /* Physmedia devaddr shift */ 218 219/* BHND_PCIE2_DMA[0-4]_HOST2DEV_(TX|RX) per-channel register offsets */ 220#define BHND_PCIE2_DMA_CTRL 0x0 /**< enable, et al */ 221#define BHND_PCIE2_DMA_PTR 0x4 /**< last descriptor posted to chip */ 222#define BHND_PCIE2_DMA_ADDRL 0x8 /**< descriptor ring base address low 32-bits (8K aligned) */ 223#define BHND_PCIE2_DMA_ADDRH 0xC /**< descriptor ring base address bits 63:32 (8K aligned) */ 224#define BHND_PCIE2_DMA_STATUS0 0x10 /**< current descriptor, xmt state */ 225#define BHND_PCIE2_DMA_STATUS1 0x10 /**< active descriptor, xmt error */ 226 227 228#endif /* _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ */ 229