chipc.c revision 301971
1/*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bhnd/cores/chipc/chipc.c 301971 2016-06-16 19:57:24Z landonf $"); 33 34/* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 41 * flash, etc. 42 * 43 * The purpose of this driver is memory resource management for ChipCommon drivers 44 * like UART, PMU, flash. ChipCommon core has several memory regions. 45 * 46 * ChipCommon driver has memory resource manager. Driver 47 * gets information about BHND core ports/regions and map them 48 * into drivers' resources. 49 * 50 * Here is overview of mapping: 51 * 52 * ------------------------------------------------------ 53 * | Port.Region| Purpose | 54 * ------------------------------------------------------ 55 * | 0.0 | PMU, SPI(0x40), UART(0x300) | 56 * | 1.0 | ? | 57 * | 1.1 | MMIO flash (SPI & CFI) | 58 * ------------------------------------------------------ 59 */ 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/lock.h> 64#include <sys/bus.h> 65#include <sys/rman.h> 66#include <sys/malloc.h> 67#include <sys/module.h> 68#include <sys/mutex.h> 69#include <sys/systm.h> 70 71#include <machine/bus.h> 72#include <machine/resource.h> 73 74#include <dev/bhnd/bhnd.h> 75#include <dev/bhnd/bhndvar.h> 76 77#include "chipcreg.h" 78#include "chipcvar.h" 79#include "chipc_private.h" 80 81devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 82 83static struct bhnd_device_quirk chipc_quirks[]; 84 85/* Supported device identifiers */ 86static const struct bhnd_device chipc_devices[] = { 87 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 88 BHND_DEVICE_END 89}; 90 91 92/* Device quirks table */ 93static struct bhnd_device_quirk chipc_quirks[] = { 94 /* HND OTP controller revisions */ 95 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 96 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 97 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 98 99 /* IPX OTP controller revisions */ 100 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 101 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 102 103 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 104 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 105 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 106 107 /* 4706 variant quirks */ 108 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 109 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 110 111 /* 4331 quirks*/ 112 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 113 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 114 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 115 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 116 117 /* 4360 quirks */ 118 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 119 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 120 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 121 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 122 123 BHND_DEVICE_QUIRK_END 124}; 125 126 127/* 128 * Here is resource configuration hints for child devices 129 * 130 * [Flash] There are 2 flash resources: 131 * - resource ID (rid) = 0: memory-mapped flash memory 132 * - resource ID (rid) = 1: memory-mapped flash registers (i.e for SPI) 133 * 134 * [UART] Uses IRQ and memory resources: 135 * - resource ID (rid) = 0: memory-mapped registers 136 * - IRQ resource ID (rid) = 0: shared IRQ line for Tx/Rx. 137 */ 138 139static const struct chipc_hint { 140 const char *name; 141 int unit; 142 int type; 143 int rid; 144 rman_res_t base; /* relative to parent resource */ 145 rman_res_t size; 146 u_int port; /* ignored if SYS_RES_IRQ */ 147 u_int region; 148} chipc_hints[] = { 149 // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs 150 // FIXME: IRQ shouldn't be hardcoded 151 /* device unit type rid base size port,region */ 152 { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, 153 { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, 154 { "uart", 0, SYS_RES_IRQ, 0, 2, 1 }, 155 { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, 156 { "uart", 1, SYS_RES_IRQ, 0, 2, 1 }, 157 { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, 158 { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 159 { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, 160 { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 161 { NULL } 162}; 163 164 165static int chipc_try_activate_resource( 166 struct chipc_softc *sc, device_t child, 167 int type, int rid, struct resource *r, 168 bool req_direct); 169 170static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 171 struct chipc_caps *caps); 172static int chipc_read_caps(struct chipc_softc *sc, 173 struct chipc_caps *caps); 174 175static bool chipc_should_enable_sprom( 176 struct chipc_softc *sc); 177 178static int chipc_init_rman(struct chipc_softc *sc); 179static void chipc_free_rman(struct chipc_softc *sc); 180static struct rman *chipc_get_rman(struct chipc_softc *sc, 181 int type); 182 183/* quirk and capability flag convenience macros */ 184#define CHIPC_QUIRK(_sc, _name) \ 185 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 186 187#define CHIPC_CAP(_sc, _name) \ 188 ((_sc)->caps._name) 189 190#define CHIPC_ASSERT_QUIRK(_sc, name) \ 191 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 192 193#define CHIPC_ASSERT_CAP(_sc, name) \ 194 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 195 196static int 197chipc_probe(device_t dev) 198{ 199 const struct bhnd_device *id; 200 201 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 202 if (id == NULL) 203 return (ENXIO); 204 205 bhnd_set_default_core_desc(dev); 206 return (BUS_PROBE_DEFAULT); 207} 208 209static int 210chipc_attach(device_t dev) 211{ 212 struct chipc_softc *sc; 213 bhnd_addr_t enum_addr; 214 uint32_t ccid_reg; 215 uint8_t chip_type; 216 int error; 217 218 sc = device_get_softc(dev); 219 sc->dev = dev; 220 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 221 sizeof(chipc_devices[0])); 222 sc->sprom_refcnt = 0; 223 224 CHIPC_LOCK_INIT(sc); 225 STAILQ_INIT(&sc->mem_regions); 226 227 /* Set up resource management */ 228 if ((error = chipc_init_rman(sc))) { 229 device_printf(sc->dev, 230 "failed to initialize chipc resource state: %d\n", error); 231 goto failed; 232 } 233 234 /* Allocate the region containing our core registers */ 235 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 236 error = ENXIO; 237 goto failed; 238 } 239 240 error = chipc_retain_region(sc, sc->core_region, 241 RF_ALLOCATED|RF_ACTIVE); 242 if (error) { 243 sc->core_region = NULL; 244 goto failed; 245 } else { 246 sc->core = sc->core_region->cr_res; 247 } 248 249 /* Fetch our chipset identification data */ 250 ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); 251 chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); 252 253 switch (chip_type) { 254 case BHND_CHIPTYPE_SIBA: 255 /* enumeration space starts at the ChipCommon register base. */ 256 enum_addr = rman_get_start(sc->core->res); 257 break; 258 case BHND_CHIPTYPE_BCMA: 259 case BHND_CHIPTYPE_BCMA_ALT: 260 enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); 261 break; 262 default: 263 device_printf(dev, "unsupported chip type %hhu\n", chip_type); 264 error = ENODEV; 265 goto failed; 266 } 267 268 sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); 269 270 /* Fetch and parse capability register(s) */ 271 if ((error = chipc_read_caps(sc, &sc->caps))) 272 goto failed; 273 274 if (bootverbose) 275 chipc_print_caps(sc->dev, &sc->caps); 276 277 /* Probe and attach children */ 278 bus_generic_probe(dev); 279 if ((error = bus_generic_attach(dev))) 280 goto failed; 281 282 return (0); 283 284failed: 285 device_delete_children(sc->dev); 286 287 if (sc->core_region != NULL) { 288 chipc_release_region(sc, sc->core_region, 289 RF_ALLOCATED|RF_ACTIVE); 290 } 291 292 chipc_free_rman(sc); 293 CHIPC_LOCK_DESTROY(sc); 294 return (error); 295} 296 297static int 298chipc_detach(device_t dev) 299{ 300 struct chipc_softc *sc; 301 int error; 302 303 sc = device_get_softc(dev); 304 305 if ((error = bus_generic_detach(dev))) 306 return (error); 307 308 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 309 chipc_free_rman(sc); 310 311 CHIPC_LOCK_DESTROY(sc); 312 313 return (0); 314} 315 316/** 317 * Determine the NVRAM data source for this device. 318 * 319 * The SPROM, OTP, and flash capability flags must be fully populated in 320 * @p caps. 321 * 322 * @param sc chipc driver state. 323 * @param caps capability flags to be used to derive NVRAM configuration. 324 */ 325static bhnd_nvram_src 326chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 327{ 328 uint32_t otp_st, srom_ctrl; 329 330 /* Very early devices vend SPROM/OTP/CIS (if at all) via the 331 * host bridge interface instead of ChipCommon. */ 332 if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 333 return (BHND_NVRAM_SRC_UNKNOWN); 334 335 /* 336 * Later chipset revisions standardized the SPROM capability flags and 337 * register interfaces. 338 * 339 * We check for hardware presence in order of precedence. For example, 340 * SPROM is is always used in preference to internal OTP if found. 341 */ 342 if (caps->sprom) { 343 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 344 if (srom_ctrl & CHIPC_SRC_PRESENT) 345 return (BHND_NVRAM_SRC_SPROM); 346 } 347 348 /* Check for programmed OTP H/W subregion (contains SROM data) */ 349 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 350 /* TODO: need access to HND-OTP device */ 351 if (!CHIPC_QUIRK(sc, OTP_HND)) { 352 device_printf(sc->dev, 353 "NVRAM unavailable: unsupported OTP controller.\n"); 354 return (BHND_NVRAM_SRC_UNKNOWN); 355 } 356 357 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 358 if (otp_st & CHIPC_OTPS_GUP_HW) 359 return (BHND_NVRAM_SRC_OTP); 360 } 361 362 /* Check for flash */ 363 if (caps->flash_type != CHIPC_FLASH_NONE) 364 return (BHND_NVRAM_SRC_FLASH); 365 366 /* No NVRAM hardware capability declared */ 367 return (BHND_NVRAM_SRC_UNKNOWN); 368} 369 370/* Read and parse chipc capabilities */ 371static int 372chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 373{ 374 uint32_t cap_reg; 375 uint32_t cap_ext_reg; 376 uint32_t regval; 377 378 /* Fetch cap registers */ 379 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 380 cap_ext_reg = 0; 381 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 382 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 383 384 /* Extract values */ 385 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 386 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 387 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 388 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 389 390 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 391 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 392 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 393 394 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 395 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 396 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 397 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 398 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 399 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 400 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 401 402 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 403 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 404 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 405 406 /* Fetch OTP size for later IPX controller revisions */ 407 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 408 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 409 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 410 } 411 412 /* Determine flash type and parameters */ 413 caps->cfi_width = 0; 414 415 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 416 case CHIPC_CAP_SFLASH_ST: 417 caps->flash_type = CHIPC_SFLASH_ST; 418 break; 419 case CHIPC_CAP_SFLASH_AT: 420 caps->flash_type = CHIPC_SFLASH_AT; 421 break; 422 case CHIPC_CAP_NFLASH: 423 caps->flash_type = CHIPC_NFLASH; 424 break; 425 case CHIPC_CAP_PFLASH: 426 caps->flash_type = CHIPC_PFLASH_CFI; 427 428 /* determine cfi width */ 429 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 430 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 431 caps->cfi_width = 2; 432 else 433 caps->cfi_width = 1; 434 435 break; 436 case CHIPC_CAP_FLASH_NONE: 437 caps->flash_type = CHIPC_FLASH_NONE; 438 break; 439 440 } 441 442 /* Handle 4706_NFLASH fallback */ 443 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 444 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 445 { 446 caps->flash_type = CHIPC_NFLASH_4706; 447 } 448 449 450 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 451 * capability flags have been populated. */ 452 caps->nvram_src = chipc_find_nvram_src(sc, caps); 453 454 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 455 * data is placed within the OTP general use region. */ 456 caps->sprom_offset = 0; 457 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 458 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 459 460 /* Bit offset to GUP HW subregion containing SPROM data */ 461 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 462 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 463 464 /* Convert to bytes */ 465 caps->sprom_offset /= 8; 466 } 467 468 return (0); 469} 470 471static int 472chipc_suspend(device_t dev) 473{ 474 return (bus_generic_suspend(dev)); 475} 476 477static int 478chipc_resume(device_t dev) 479{ 480 return (bus_generic_resume(dev)); 481} 482 483static void 484chipc_probe_nomatch(device_t dev, device_t child) 485{ 486 struct resource_list *rl; 487 const char *name; 488 489 name = device_get_name(child); 490 if (name == NULL) 491 name = "unknown device"; 492 493 device_printf(dev, "<%s> at", name); 494 495 rl = BUS_GET_RESOURCE_LIST(dev, child); 496 if (rl != NULL) { 497 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 498 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 499 } 500 501 printf(" (no driver attached)\n"); 502} 503 504static int 505chipc_print_child(device_t dev, device_t child) 506{ 507 struct resource_list *rl; 508 int retval = 0; 509 510 retval += bus_print_child_header(dev, child); 511 512 rl = BUS_GET_RESOURCE_LIST(dev, child); 513 if (rl != NULL) { 514 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 515 "%#jx"); 516 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 517 "%jd"); 518 } 519 520 retval += bus_print_child_domain(dev, child); 521 retval += bus_print_child_footer(dev, child); 522 523 return (retval); 524} 525 526static int 527chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 528 size_t buflen) 529{ 530 if (buflen == 0) 531 return (EOVERFLOW); 532 533 *buf = '\0'; 534 return (0); 535} 536 537static int 538chipc_child_location_str(device_t dev, device_t child, char *buf, 539 size_t buflen) 540{ 541 if (buflen == 0) 542 return (EOVERFLOW); 543 544 *buf = '\0'; 545 return (ENXIO); 546} 547 548static device_t 549chipc_add_child(device_t dev, u_int order, const char *name, int unit) 550{ 551 struct chipc_devinfo *dinfo; 552 const struct chipc_hint *hint; 553 device_t child; 554 devclass_t child_dc; 555 int error; 556 int busrel_unit; 557 558 child = device_add_child_ordered(dev, order, name, unit); 559 if (child == NULL) 560 return (NULL); 561 562 /* system-wide device unit */ 563 unit = device_get_unit(child); 564 child_dc = device_get_devclass(child); 565 566 busrel_unit = 0; 567 for (int i = 0; i < unit; i++) { 568 device_t tmp; 569 570 tmp = devclass_get_device(child_dc, i); 571 if (tmp != NULL && (device_get_parent(tmp) == dev)) 572 busrel_unit++; 573 } 574 575 /* bus-wide device unit (override unit for further hint matching) */ 576 unit = busrel_unit; 577 578 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 579 if (dinfo == NULL) { 580 device_delete_child(dev, child); 581 return (NULL); 582 } 583 584 resource_list_init(&dinfo->resources); 585 device_set_ivars(child, dinfo); 586 587 /* Hint matching requires a device name */ 588 if (name == NULL) 589 return (child); 590 591 /* Use hint table to set child resources */ 592 for (hint = chipc_hints; hint->name != NULL; hint++) { 593 bhnd_addr_t region_addr; 594 bhnd_size_t region_size; 595 596 /* Check device name */ 597 if (strcmp(hint->name, name) != 0) 598 continue; 599 600 /* Check device unit */ 601 if (hint->unit >= 0 && unit != hint->unit) 602 continue; 603 604 switch (hint->type) { 605 case SYS_RES_IRQ: 606 /* Add child resource */ 607 error = bus_set_resource(child, hint->type, hint->rid, 608 hint->base, hint->size); 609 if (error) { 610 device_printf(dev, 611 "bus_set_resource() failed for %s: %d\n", 612 device_get_nameunit(child), error); 613 goto failed; 614 } 615 break; 616 617 case SYS_RES_MEMORY: 618 /* Fetch region address and size */ 619 error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, 620 hint->port, hint->region, ®ion_addr, 621 ®ion_size); 622 if (error) { 623 device_printf(dev, 624 "lookup of %s%u.%u failed: %d\n", 625 bhnd_port_type_name(BHND_PORT_DEVICE), 626 hint->port, hint->region, error); 627 goto failed; 628 } 629 630 /* Verify requested range is mappable */ 631 if (hint->base > region_size || 632 (hint->size != RM_MAX_END && 633 (hint->size > region_size || 634 region_size - hint->base < hint->size ))) 635 { 636 device_printf(dev, 637 "%s%u.%u region cannot map requested range " 638 "%#jx+%#jx\n", 639 bhnd_port_type_name(BHND_PORT_DEVICE), 640 hint->port, hint->region, hint->base, 641 hint->size); 642 } 643 644 /* 645 * Add child resource. If hint doesn't define the end 646 * of resource window (RX_MAX_END), use end of region. 647 */ 648 649 error = bus_set_resource(child, 650 hint->type, 651 hint->rid, region_addr + hint->base, 652 (hint->size == RM_MAX_END) ? 653 region_size - hint->base : 654 hint->size); 655 if (error) { 656 device_printf(dev, 657 "bus_set_resource() failed for %s: %d\n", 658 device_get_nameunit(child), error); 659 goto failed; 660 } 661 break; 662 default: 663 device_printf(child, "unknown hint resource type: %d\n", 664 hint->type); 665 break; 666 } 667 } 668 669 return (child); 670 671failed: 672 device_delete_child(dev, child); 673 return (NULL); 674} 675 676static void 677chipc_child_deleted(device_t dev, device_t child) 678{ 679 struct chipc_devinfo *dinfo = device_get_ivars(child); 680 681 if (dinfo != NULL) { 682 resource_list_free(&dinfo->resources); 683 free(dinfo, M_BHND); 684 } 685 686 device_set_ivars(child, NULL); 687} 688 689static struct resource_list * 690chipc_get_resource_list(device_t dev, device_t child) 691{ 692 struct chipc_devinfo *dinfo = device_get_ivars(child); 693 return (&dinfo->resources); 694} 695 696 697/* Allocate region records for the given port, and add the port's memory 698 * range to the mem_rman */ 699static int 700chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 701 u_int port) 702{ 703 struct chipc_region *cr; 704 rman_res_t start, end; 705 u_int num_regions; 706 int error; 707 708 num_regions = bhnd_get_region_count(sc->dev, port, port); 709 for (u_int region = 0; region < num_regions; region++) { 710 /* Allocate new region record */ 711 cr = chipc_alloc_region(sc, type, port, region); 712 if (cr == NULL) 713 return (ENODEV); 714 715 /* Can't manage regions that cannot be allocated */ 716 if (cr->cr_rid < 0) { 717 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 718 "%s%u.%u", bhnd_port_type_name(type), port, region); 719 chipc_free_region(sc, cr); 720 continue; 721 } 722 723 /* Add to rman's managed range */ 724 start = cr->cr_addr; 725 end = cr->cr_end; 726 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 727 chipc_free_region(sc, cr); 728 return (error); 729 } 730 731 /* Add to region list */ 732 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 733 } 734 735 return (0); 736} 737 738/* Initialize memory state for all chipc port regions */ 739static int 740chipc_init_rman(struct chipc_softc *sc) 741{ 742 u_int num_ports; 743 int error; 744 745 /* Port types for which we'll register chipc_region mappings */ 746 bhnd_port_type types[] = { 747 BHND_PORT_DEVICE 748 }; 749 750 /* Initialize resource manager */ 751 sc->mem_rman.rm_start = 0; 752 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 753 sc->mem_rman.rm_type = RMAN_ARRAY; 754 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 755 if ((error = rman_init(&sc->mem_rman))) { 756 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 757 error); 758 return (error); 759 } 760 761 /* Populate per-port-region state */ 762 for (u_int i = 0; i < nitems(types); i++) { 763 num_ports = bhnd_get_port_count(sc->dev, types[i]); 764 for (u_int port = 0; port < num_ports; port++) { 765 error = chipc_rman_init_regions(sc, types[i], port); 766 if (error) { 767 device_printf(sc->dev, 768 "region init failed for %s%u: %d\n", 769 bhnd_port_type_name(types[i]), port, 770 error); 771 772 goto failed; 773 } 774 } 775 } 776 777 return (0); 778 779failed: 780 chipc_free_rman(sc); 781 return (error); 782} 783 784/* Free memory management state */ 785static void 786chipc_free_rman(struct chipc_softc *sc) 787{ 788 struct chipc_region *cr, *cr_next; 789 790 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 791 chipc_free_region(sc, cr); 792 793 rman_fini(&sc->mem_rman); 794} 795 796/** 797 * Return the rman instance for a given resource @p type, if any. 798 * 799 * @param sc The chipc device state. 800 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 801 */ 802static struct rman * 803chipc_get_rman(struct chipc_softc *sc, int type) 804{ 805 switch (type) { 806 case SYS_RES_MEMORY: 807 return (&sc->mem_rman); 808 809 case SYS_RES_IRQ: 810 /* IRQs can be used with RF_SHAREABLE, so we don't perform 811 * any local proxying of resource requests. */ 812 return (NULL); 813 814 default: 815 return (NULL); 816 }; 817} 818 819static struct resource * 820chipc_alloc_resource(device_t dev, device_t child, int type, 821 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 822{ 823 struct chipc_softc *sc; 824 struct chipc_region *cr; 825 struct resource_list_entry *rle; 826 struct resource *rv; 827 struct rman *rm; 828 int error; 829 bool passthrough, isdefault; 830 831 sc = device_get_softc(dev); 832 passthrough = (device_get_parent(child) != dev); 833 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 834 rle = NULL; 835 836 /* Fetch the resource manager, delegate request if necessary */ 837 rm = chipc_get_rman(sc, type); 838 if (rm == NULL) { 839 /* Requested resource type is delegated to our parent */ 840 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 841 start, end, count, flags); 842 return (rv); 843 } 844 845 /* Populate defaults */ 846 if (!passthrough && isdefault) { 847 /* Fetch the resource list entry. */ 848 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 849 type, *rid); 850 if (rle == NULL) { 851 device_printf(dev, 852 "default resource %#x type %d for child %s " 853 "not found\n", *rid, type, 854 device_get_nameunit(child)); 855 return (NULL); 856 } 857 858 if (rle->res != NULL) { 859 device_printf(dev, 860 "resource entry %#x type %d for child %s is busy " 861 "[%d]\n", 862 *rid, type, device_get_nameunit(child), 863 rman_get_flags(rle->res)); 864 865 return (NULL); 866 } 867 868 start = rle->start; 869 end = rle->end; 870 count = ulmax(count, rle->count); 871 } 872 873 /* Locate a mapping region */ 874 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 875 /* Resource requests outside our shared port regions can be 876 * delegated to our parent. */ 877 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 878 start, end, count, flags); 879 return (rv); 880 } 881 882 /* Try to retain a region reference */ 883 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 884 return (NULL); 885 886 /* Make our rman reservation */ 887 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 888 child); 889 if (rv == NULL) { 890 chipc_release_region(sc, cr, RF_ALLOCATED); 891 return (NULL); 892 } 893 894 rman_set_rid(rv, *rid); 895 896 /* Activate */ 897 if (flags & RF_ACTIVE) { 898 error = bus_activate_resource(child, type, *rid, rv); 899 if (error) { 900 device_printf(dev, 901 "failed to activate entry %#x type %d for " 902 "child %s: %d\n", 903 *rid, type, device_get_nameunit(child), error); 904 905 chipc_release_region(sc, cr, RF_ALLOCATED); 906 rman_release_resource(rv); 907 908 return (NULL); 909 } 910 } 911 912 /* Update child's resource list entry */ 913 if (rle != NULL) { 914 rle->res = rv; 915 rle->start = rman_get_start(rv); 916 rle->end = rman_get_end(rv); 917 rle->count = rman_get_size(rv); 918 } 919 920 return (rv); 921} 922 923static int 924chipc_release_resource(device_t dev, device_t child, int type, int rid, 925 struct resource *r) 926{ 927 struct chipc_softc *sc; 928 struct chipc_region *cr; 929 struct rman *rm; 930 struct resource_list_entry *rle; 931 int error; 932 933 sc = device_get_softc(dev); 934 935 /* Handled by parent bus? */ 936 rm = chipc_get_rman(sc, type); 937 if (rm == NULL || !rman_is_region_manager(r, rm)) { 938 return (bus_generic_rl_release_resource(dev, child, type, rid, 939 r)); 940 } 941 942 /* Locate the mapping region */ 943 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 944 if (cr == NULL) 945 return (EINVAL); 946 947 /* Deactivate resources */ 948 if (rman_get_flags(r) & RF_ACTIVE) { 949 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 950 if (error) 951 return (error); 952 } 953 954 if ((error = rman_release_resource(r))) 955 return (error); 956 957 /* Drop allocation reference */ 958 chipc_release_region(sc, cr, RF_ALLOCATED); 959 960 /* Clear reference from the resource list entry if exists */ 961 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 962 if (rle != NULL) 963 rle->res = NULL; 964 965 return (0); 966} 967 968static int 969chipc_adjust_resource(device_t dev, device_t child, int type, 970 struct resource *r, rman_res_t start, rman_res_t end) 971{ 972 struct chipc_softc *sc; 973 struct chipc_region *cr; 974 struct rman *rm; 975 976 sc = device_get_softc(dev); 977 978 /* Handled by parent bus? */ 979 rm = chipc_get_rman(sc, type); 980 if (rm == NULL || !rman_is_region_manager(r, rm)) { 981 return (bus_generic_adjust_resource(dev, child, type, r, start, 982 end)); 983 } 984 985 /* The range is limited to the existing region mapping */ 986 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 987 if (cr == NULL) 988 return (EINVAL); 989 990 if (end <= start) 991 return (EINVAL); 992 993 if (start < cr->cr_addr || end > cr->cr_end) 994 return (EINVAL); 995 996 /* Range falls within the existing region */ 997 return (rman_adjust_resource(r, start, end)); 998} 999 1000/** 1001 * Retain an RF_ACTIVE reference to the region mapping @p r, and 1002 * configure @p r with its subregion values. 1003 * 1004 * @param sc Driver instance state. 1005 * @param child Requesting child device. 1006 * @param type resource type of @p r. 1007 * @param rid resource id of @p r 1008 * @param r resource to be activated. 1009 * @param req_direct If true, failure to allocate a direct bhnd resource 1010 * will be treated as an error. If false, the resource will not be marked 1011 * as RF_ACTIVE if bhnd direct resource allocation fails. 1012 */ 1013static int 1014chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 1015 int rid, struct resource *r, bool req_direct) 1016{ 1017 struct rman *rm; 1018 struct chipc_region *cr; 1019 bhnd_size_t cr_offset; 1020 rman_res_t r_start, r_end, r_size; 1021 int error; 1022 1023 rm = chipc_get_rman(sc, type); 1024 if (rm == NULL || !rman_is_region_manager(r, rm)) 1025 return (EINVAL); 1026 1027 r_start = rman_get_start(r); 1028 r_end = rman_get_end(r); 1029 r_size = rman_get_size(r); 1030 1031 /* Find the corresponding chipc region */ 1032 cr = chipc_find_region(sc, r_start, r_end); 1033 if (cr == NULL) 1034 return (EINVAL); 1035 1036 /* Calculate subregion offset within the chipc region */ 1037 cr_offset = r_start - cr->cr_addr; 1038 1039 /* Retain (and activate, if necessary) the chipc region */ 1040 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1041 return (error); 1042 1043 /* Configure child resource with its subregion values. */ 1044 if (cr->cr_res->direct) { 1045 error = chipc_init_child_resource(r, cr->cr_res->res, 1046 cr_offset, r_size); 1047 if (error) 1048 goto cleanup; 1049 1050 /* Mark active */ 1051 if ((error = rman_activate_resource(r))) 1052 goto cleanup; 1053 } else if (req_direct) { 1054 error = ENOMEM; 1055 goto cleanup; 1056 } 1057 1058 return (0); 1059 1060cleanup: 1061 chipc_release_region(sc, cr, RF_ACTIVE); 1062 return (error); 1063} 1064 1065static int 1066chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1067 int rid, struct bhnd_resource *r) 1068{ 1069 struct chipc_softc *sc; 1070 struct rman *rm; 1071 int error; 1072 1073 sc = device_get_softc(dev); 1074 1075 /* Delegate non-locally managed resources to parent */ 1076 rm = chipc_get_rman(sc, type); 1077 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1078 return (bhnd_bus_generic_activate_resource(dev, child, type, 1079 rid, r)); 1080 } 1081 1082 /* Try activating the chipc region resource */ 1083 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1084 false); 1085 if (error) 1086 return (error); 1087 1088 /* Mark the child resource as direct according to the returned resource 1089 * state */ 1090 if (rman_get_flags(r->res) & RF_ACTIVE) 1091 r->direct = true; 1092 1093 return (0); 1094} 1095 1096static int 1097chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1098 struct resource *r) 1099{ 1100 struct chipc_softc *sc; 1101 struct rman *rm; 1102 1103 sc = device_get_softc(dev); 1104 1105 /* Delegate non-locally managed resources to parent */ 1106 rm = chipc_get_rman(sc, type); 1107 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1108 return (bus_generic_activate_resource(dev, child, type, rid, 1109 r)); 1110 } 1111 1112 /* Try activating the chipc region-based resource */ 1113 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1114} 1115 1116/** 1117 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1118 */ 1119static int 1120chipc_deactivate_resource(device_t dev, device_t child, int type, 1121 int rid, struct resource *r) 1122{ 1123 struct chipc_softc *sc; 1124 struct chipc_region *cr; 1125 struct rman *rm; 1126 int error; 1127 1128 sc = device_get_softc(dev); 1129 1130 /* Handled by parent bus? */ 1131 rm = chipc_get_rman(sc, type); 1132 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1133 return (bus_generic_deactivate_resource(dev, child, type, rid, 1134 r)); 1135 } 1136 1137 /* Find the corresponding chipc region */ 1138 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1139 if (cr == NULL) 1140 return (EINVAL); 1141 1142 /* Mark inactive */ 1143 if ((error = rman_deactivate_resource(r))) 1144 return (error); 1145 1146 /* Drop associated RF_ACTIVE reference */ 1147 chipc_release_region(sc, cr, RF_ACTIVE); 1148 1149 return (0); 1150} 1151 1152/** 1153 * Examine bus state and make a best effort determination of whether it's 1154 * likely safe to enable the muxed SPROM pins. 1155 * 1156 * On devices that do not use SPROM pin muxing, always returns true. 1157 * 1158 * @param sc chipc driver state. 1159 */ 1160static bool 1161chipc_should_enable_sprom(struct chipc_softc *sc) 1162{ 1163 device_t *devs; 1164 device_t hostb; 1165 device_t parent; 1166 int devcount; 1167 int error; 1168 bool result; 1169 1170 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1171 1172 /* Nothing to do? */ 1173 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1174 return (true); 1175 1176 parent = device_get_parent(sc->dev); 1177 hostb = bhnd_find_hostb_device(parent); 1178 1179 if ((error = device_get_children(parent, &devs, &devcount))) 1180 return (false); 1181 1182 /* Reject any active devices other than ChipCommon, or the 1183 * host bridge (if any). */ 1184 result = true; 1185 for (int i = 0; i < devcount; i++) { 1186 if (devs[i] == hostb || devs[i] == sc->dev) 1187 continue; 1188 1189 if (!device_is_attached(devs[i])) 1190 continue; 1191 1192 if (device_is_suspended(devs[i])) 1193 continue; 1194 1195 /* Active device; assume SPROM is busy */ 1196 result = false; 1197 break; 1198 } 1199 1200 free(devs, M_TEMP); 1201 return (result); 1202} 1203 1204/** 1205 * If required by this device, enable access to the SPROM. 1206 * 1207 * @param sc chipc driver state. 1208 */ 1209static int 1210chipc_enable_sprom_pins(device_t dev) 1211{ 1212 struct chipc_softc *sc; 1213 uint32_t cctrl; 1214 int error; 1215 1216 sc = device_get_softc(dev); 1217 1218 /* Nothing to do? */ 1219 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1220 return (0); 1221 1222 /* Make sure we're holding Giant for newbus */ 1223 mtx_lock(&Giant); 1224 CHIPC_LOCK(sc); 1225 1226 /* Already enabled? */ 1227 if (sc->sprom_refcnt >= 1) { 1228 error = 0; 1229 goto finished; 1230 } 1231 1232 /* Check whether bus is busy */ 1233 if (!chipc_should_enable_sprom(sc)) { 1234 error = EBUSY; 1235 goto finished; 1236 } 1237 1238 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1239 1240 /* 4331 devices */ 1241 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1242 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1243 1244 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1245 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1246 1247 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1248 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1249 1250 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1251 error = 0; 1252 goto finished; 1253 } 1254 1255 /* 4360 devices */ 1256 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1257 /* Unimplemented */ 1258 } 1259 1260 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1261 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1262 error = ENXIO; 1263 1264finished: 1265 /* Bump the reference count */ 1266 if (error == 0) 1267 sc->sprom_refcnt++; 1268 1269 CHIPC_UNLOCK(sc); 1270 mtx_unlock(&Giant); 1271 1272 return (error); 1273} 1274 1275/** 1276 * If required by this device, revert any GPIO/pin configuration applied 1277 * to allow SPROM access. 1278 * 1279 * @param sc chipc driver state. 1280 */ 1281static void 1282chipc_disable_sprom_pins(device_t dev) 1283{ 1284 struct chipc_softc *sc; 1285 uint32_t cctrl; 1286 1287 sc = device_get_softc(dev); 1288 1289 /* Nothing to do? */ 1290 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1291 return; 1292 1293 CHIPC_LOCK(sc); 1294 1295 /* Check reference count, skip disable if in-use. */ 1296 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1297 sc->sprom_refcnt--; 1298 if (sc->sprom_refcnt > 0) 1299 goto finished; 1300 1301 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1302 1303 /* 4331 devices */ 1304 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1305 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1306 1307 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1308 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1309 1310 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1311 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1312 1313 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1314 goto finished; 1315 } 1316 1317 /* 4360 devices */ 1318 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1319 /* Unimplemented */ 1320 } 1321 1322finished: 1323 CHIPC_UNLOCK(sc); 1324} 1325 1326static void 1327chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1328{ 1329 struct chipc_softc *sc; 1330 uint32_t cctrl; 1331 1332 sc = device_get_softc(dev); 1333 1334 CHIPC_LOCK(sc); 1335 1336 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1337 cctrl = (cctrl & ~mask) | (value | mask); 1338 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1339 1340 CHIPC_UNLOCK(sc); 1341} 1342 1343static struct chipc_caps * 1344chipc_get_caps(device_t dev) 1345{ 1346 struct chipc_softc *sc; 1347 1348 sc = device_get_softc(dev); 1349 return (&sc->caps); 1350} 1351 1352static uint32_t 1353chipc_get_flash_cfg(device_t dev) 1354{ 1355 struct chipc_softc *sc; 1356 1357 sc = device_get_softc(dev); 1358 return (bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG)); 1359} 1360 1361static device_method_t chipc_methods[] = { 1362 /* Device interface */ 1363 DEVMETHOD(device_probe, chipc_probe), 1364 DEVMETHOD(device_attach, chipc_attach), 1365 DEVMETHOD(device_detach, chipc_detach), 1366 DEVMETHOD(device_suspend, chipc_suspend), 1367 DEVMETHOD(device_resume, chipc_resume), 1368 1369 /* Bus interface */ 1370 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1371 DEVMETHOD(bus_print_child, chipc_print_child), 1372 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1373 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1374 1375 DEVMETHOD(bus_add_child, chipc_add_child), 1376 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1377 1378 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1379 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1380 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1381 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1382 DEVMETHOD(bus_release_resource, chipc_release_resource), 1383 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1384 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1385 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1386 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1387 1388 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1389 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1390 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1391 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1392 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1393 1394 /* BHND bus inteface */ 1395 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1396 1397 /* ChipCommon interface */ 1398 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1399 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1400 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1401 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1402 DEVMETHOD(bhnd_chipc_get_flash_cfg, chipc_get_flash_cfg), 1403 1404 DEVMETHOD_END 1405}; 1406 1407DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1408EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0, 1409 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1410MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1411MODULE_VERSION(bhnd_chipc, 1); 1412