1/*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34/* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 41 * GPIO, flash, etc. 42 */ 43 44#include <sys/param.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/bus.h> 48#include <sys/rman.h> 49#include <sys/malloc.h> 50#include <sys/module.h> 51#include <sys/mutex.h> 52#include <sys/systm.h> 53 54#include <machine/bus.h> 55#include <machine/resource.h> 56 57#include <dev/bhnd/bhnd.h> 58#include <dev/bhnd/bhndvar.h> 59 60#include "chipcreg.h" 61#include "chipcvar.h" 62 63#include "chipc_private.h" 64 65devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 66 67static struct bhnd_device_quirk chipc_quirks[]; 68 69/* Supported device identifiers */ 70static const struct bhnd_device chipc_devices[] = { 71 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 72 BHND_DEVICE_END 73}; 74 75 76/* Device quirks table */ 77static struct bhnd_device_quirk chipc_quirks[] = { 78 /* HND OTP controller revisions */ 79 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 80 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 81 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 82 83 /* IPX OTP controller revisions */ 84 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 85 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 86 87 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 88 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 89 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 90 91 /* 4706 variant quirks */ 92 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 93 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 94 95 /* 4331 quirks*/ 96 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 97 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 98 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 99 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 100 101 /* 4360 quirks */ 102 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 103 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 104 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 105 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 106 107 BHND_DEVICE_QUIRK_END 108}; 109 110// FIXME: IRQ shouldn't be hard-coded 111#define CHIPC_MIPS_IRQ 2 112 113static int chipc_add_children(struct chipc_softc *sc); 114 115static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 116 struct chipc_caps *caps); 117static int chipc_read_caps(struct chipc_softc *sc, 118 struct chipc_caps *caps); 119 120static bool chipc_should_enable_sprom( 121 struct chipc_softc *sc); 122 123static int chipc_try_activate_resource( 124 struct chipc_softc *sc, device_t child, 125 int type, int rid, struct resource *r, 126 bool req_direct); 127 128static int chipc_init_rman(struct chipc_softc *sc); 129static void chipc_free_rman(struct chipc_softc *sc); 130static struct rman *chipc_get_rman(struct chipc_softc *sc, 131 int type); 132 133/* quirk and capability flag convenience macros */ 134#define CHIPC_QUIRK(_sc, _name) \ 135 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 136 137#define CHIPC_CAP(_sc, _name) \ 138 ((_sc)->caps._name) 139 140#define CHIPC_ASSERT_QUIRK(_sc, name) \ 141 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 142 143#define CHIPC_ASSERT_CAP(_sc, name) \ 144 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 145 146static int 147chipc_probe(device_t dev) 148{ 149 const struct bhnd_device *id; 150 151 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 152 if (id == NULL) 153 return (ENXIO); 154 155 bhnd_set_default_core_desc(dev); 156 return (BUS_PROBE_DEFAULT); 157} 158 159static int 160chipc_attach(device_t dev) 161{ 162 struct chipc_softc *sc; 163 int error; 164 165 sc = device_get_softc(dev); 166 sc->dev = dev; 167 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 168 sizeof(chipc_devices[0])); 169 sc->sprom_refcnt = 0; 170 171 CHIPC_LOCK_INIT(sc); 172 STAILQ_INIT(&sc->mem_regions); 173 174 /* Set up resource management */ 175 if ((error = chipc_init_rman(sc))) { 176 device_printf(sc->dev, 177 "failed to initialize chipc resource state: %d\n", error); 178 goto failed; 179 } 180 181 /* Allocate the region containing the chipc register block */ 182 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 183 error = ENXIO; 184 goto failed; 185 } 186 187 error = chipc_retain_region(sc, sc->core_region, 188 RF_ALLOCATED|RF_ACTIVE); 189 if (error) { 190 sc->core_region = NULL; 191 goto failed; 192 } 193 194 /* Save a direct reference to our chipc registers */ 195 sc->core = sc->core_region->cr_res; 196 197 /* Fetch and parse capability register(s) */ 198 if ((error = chipc_read_caps(sc, &sc->caps))) 199 goto failed; 200 201 if (bootverbose) 202 chipc_print_caps(sc->dev, &sc->caps); 203 204 /* Attach all supported child devices */ 205 if ((error = chipc_add_children(sc))) 206 goto failed; 207 208 if ((error = bus_generic_attach(dev))) 209 goto failed; 210 211 return (0); 212 213failed: 214 device_delete_children(sc->dev); 215 216 if (sc->core_region != NULL) { 217 chipc_release_region(sc, sc->core_region, 218 RF_ALLOCATED|RF_ACTIVE); 219 } 220 221 chipc_free_rman(sc); 222 CHIPC_LOCK_DESTROY(sc); 223 return (error); 224} 225 226static int 227chipc_detach(device_t dev) 228{ 229 struct chipc_softc *sc; 230 int error; 231 232 sc = device_get_softc(dev); 233 234 if ((error = bus_generic_detach(dev))) 235 return (error); 236 237 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 238 chipc_free_rman(sc); 239 240 CHIPC_LOCK_DESTROY(sc); 241 242 return (0); 243} 244 245static int 246chipc_add_children(struct chipc_softc *sc) 247{ 248 device_t child; 249 const char *flash_bus; 250 int error; 251 252 /* SPROM/OTP */ 253 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 254 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 255 { 256 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 257 if (child == NULL) { 258 device_printf(sc->dev, "failed to add nvram device\n"); 259 return (ENXIO); 260 } 261 262 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 263 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 264 CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); 265 if (error) 266 return (error); 267 } 268 269#ifdef notyet 270 /* 271 * PMU/SLOWCLK/INSTACLK 272 * 273 * On AOB ("Always on Bus") devices, a PMU core (if it exists) is 274 * enumerated directly by the bhnd(4) bus -- not chipc. 275 * 276 * Otherwise, we always add a PMU child device, and let the 277 * chipc bhnd_pmu drivers probe for it. If the core supports an 278 * earlier non-PMU clock/power register interface, one of the instaclk, 279 * powerctl, or null bhnd_pmu drivers will claim the device. 280 */ 281 if (!sc->caps.aob || (sc->caps.aob && !sc->caps.pmu)) { 282 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 283 if (child == NULL) { 284 device_printf(sc->dev, "failed to add pmu\n"); 285 return (ENXIO); 286 } 287 288 /* Associate the applicable register block */ 289 error = 0; 290 if (sc->caps.pmu) { 291 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 292 CHIPC_PMU, CHIPC_PMU_SIZE, 0, 0); 293 } else if (sc->caps.power_control) { 294 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 295 CHIPC_PWRCTL, CHIPC_PWRCTL_SIZE, 0, 0); 296 } 297 298 if (error) 299 return (error); 300 301 } 302#endif /* notyet */ 303 304 /* All remaining devices are SoC-only */ 305 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 306 return (0); 307 308 /* UARTs */ 309 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 310 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 311 if (child == NULL) { 312 device_printf(sc->dev, "failed to add uart%u\n", i); 313 return (ENXIO); 314 } 315 316 /* Shared IRQ */ 317 error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, 318 1); 319 if (error) { 320 device_printf(sc->dev, "failed to set uart%u irq %u\n", 321 i, CHIPC_MIPS_IRQ); 322 return (error); 323 } 324 325 /* UART registers are mapped sequentially */ 326 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 327 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 328 if (error) 329 return (error); 330 } 331 332 /* Flash */ 333 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 334 if (flash_bus != NULL) { 335 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 336 if (child == NULL) { 337 device_printf(sc->dev, "failed to add %s device\n", 338 flash_bus); 339 return (ENXIO); 340 } 341 342 /* flash memory mapping */ 343 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, 344 0, RM_MAX_END, 1, 1); 345 if (error) 346 return (error); 347 348 /* flashctrl registers */ 349 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, 350 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 351 if (error) 352 return (error); 353 } 354 355 return (0); 356} 357 358/** 359 * Determine the NVRAM data source for this device. 360 * 361 * The SPROM, OTP, and flash capability flags must be fully populated in 362 * @p caps. 363 * 364 * @param sc chipc driver state. 365 * @param caps capability flags to be used to derive NVRAM configuration. 366 */ 367static bhnd_nvram_src 368chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 369{ 370 uint32_t otp_st, srom_ctrl; 371 372 /* Very early devices vend SPROM/OTP/CIS (if at all) via the 373 * host bridge interface instead of ChipCommon. */ 374 if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 375 return (BHND_NVRAM_SRC_UNKNOWN); 376 377 /* 378 * Later chipset revisions standardized the SPROM capability flags and 379 * register interfaces. 380 * 381 * We check for hardware presence in order of precedence. For example, 382 * SPROM is is always used in preference to internal OTP if found. 383 */ 384 if (caps->sprom) { 385 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 386 if (srom_ctrl & CHIPC_SRC_PRESENT) 387 return (BHND_NVRAM_SRC_SPROM); 388 } 389 390 /* Check for programmed OTP H/W subregion (contains SROM data) */ 391 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 392 /* TODO: need access to HND-OTP device */ 393 if (!CHIPC_QUIRK(sc, OTP_HND)) { 394 device_printf(sc->dev, 395 "NVRAM unavailable: unsupported OTP controller.\n"); 396 return (BHND_NVRAM_SRC_UNKNOWN); 397 } 398 399 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 400 if (otp_st & CHIPC_OTPS_GUP_HW) 401 return (BHND_NVRAM_SRC_OTP); 402 } 403 404 /* Check for flash */ 405 if (caps->flash_type != CHIPC_FLASH_NONE) 406 return (BHND_NVRAM_SRC_FLASH); 407 408 /* No NVRAM hardware capability declared */ 409 return (BHND_NVRAM_SRC_UNKNOWN); 410} 411 412/* Read and parse chipc capabilities */ 413static int 414chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 415{ 416 uint32_t cap_reg; 417 uint32_t cap_ext_reg; 418 uint32_t regval; 419 420 /* Fetch cap registers */ 421 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 422 cap_ext_reg = 0; 423 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 424 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 425 426 /* Extract values */ 427 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 428 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 429 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 430 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 431 432 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 433 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 434 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 435 436 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 437 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 438 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 439 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 440 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 441 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 442 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 443 444 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 445 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 446 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 447 448 /* Fetch OTP size for later IPX controller revisions */ 449 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 450 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 451 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 452 } 453 454 /* Determine flash type and parameters */ 455 caps->cfi_width = 0; 456 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 457 case CHIPC_CAP_SFLASH_ST: 458 caps->flash_type = CHIPC_SFLASH_ST; 459 break; 460 case CHIPC_CAP_SFLASH_AT: 461 caps->flash_type = CHIPC_SFLASH_AT; 462 break; 463 case CHIPC_CAP_NFLASH: 464 /* unimplemented */ 465 caps->flash_type = CHIPC_NFLASH; 466 break; 467 case CHIPC_CAP_PFLASH: 468 caps->flash_type = CHIPC_PFLASH_CFI; 469 470 /* determine cfi width */ 471 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 472 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 473 caps->cfi_width = 2; 474 else 475 caps->cfi_width = 1; 476 477 break; 478 case CHIPC_CAP_FLASH_NONE: 479 caps->flash_type = CHIPC_FLASH_NONE; 480 break; 481 482 } 483 484 /* Handle 4706_NFLASH fallback */ 485 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 486 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 487 { 488 caps->flash_type = CHIPC_NFLASH_4706; 489 } 490 491 492 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 493 * capability flags have been populated. */ 494 caps->nvram_src = chipc_find_nvram_src(sc, caps); 495 496 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 497 * data is placed within the OTP general use region. */ 498 caps->sprom_offset = 0; 499 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 500 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 501 502 /* Bit offset to GUP HW subregion containing SPROM data */ 503 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 504 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 505 506 /* Convert to bytes */ 507 caps->sprom_offset /= 8; 508 } 509 510 return (0); 511} 512 513static int 514chipc_suspend(device_t dev) 515{ 516 return (bus_generic_suspend(dev)); 517} 518 519static int 520chipc_resume(device_t dev) 521{ 522 return (bus_generic_resume(dev)); 523} 524 525static void 526chipc_probe_nomatch(device_t dev, device_t child) 527{ 528 struct resource_list *rl; 529 const char *name; 530 531 name = device_get_name(child); 532 if (name == NULL) 533 name = "unknown device"; 534 535 device_printf(dev, "<%s> at", name); 536 537 rl = BUS_GET_RESOURCE_LIST(dev, child); 538 if (rl != NULL) { 539 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 540 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 541 } 542 543 printf(" (no driver attached)\n"); 544} 545 546static int 547chipc_print_child(device_t dev, device_t child) 548{ 549 struct resource_list *rl; 550 int retval = 0; 551 552 retval += bus_print_child_header(dev, child); 553 554 rl = BUS_GET_RESOURCE_LIST(dev, child); 555 if (rl != NULL) { 556 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 557 "%#jx"); 558 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 559 "%jd"); 560 } 561 562 retval += bus_print_child_domain(dev, child); 563 retval += bus_print_child_footer(dev, child); 564 565 return (retval); 566} 567 568static int 569chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 570 size_t buflen) 571{ 572 if (buflen == 0) 573 return (EOVERFLOW); 574 575 *buf = '\0'; 576 return (0); 577} 578 579static int 580chipc_child_location_str(device_t dev, device_t child, char *buf, 581 size_t buflen) 582{ 583 if (buflen == 0) 584 return (EOVERFLOW); 585 586 *buf = '\0'; 587 return (ENXIO); 588} 589 590static device_t 591chipc_add_child(device_t dev, u_int order, const char *name, int unit) 592{ 593 struct chipc_softc *sc; 594 struct chipc_devinfo *dinfo; 595 device_t child; 596 597 sc = device_get_softc(dev); 598 599 child = device_add_child_ordered(dev, order, name, unit); 600 if (child == NULL) 601 return (NULL); 602 603 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 604 if (dinfo == NULL) { 605 device_delete_child(dev, child); 606 return (NULL); 607 } 608 609 resource_list_init(&dinfo->resources); 610 device_set_ivars(child, dinfo); 611 612 return (child); 613} 614 615static void 616chipc_child_deleted(device_t dev, device_t child) 617{ 618 struct chipc_devinfo *dinfo = device_get_ivars(child); 619 620 if (dinfo != NULL) { 621 resource_list_free(&dinfo->resources); 622 free(dinfo, M_BHND); 623 } 624 625 device_set_ivars(child, NULL); 626} 627 628static struct resource_list * 629chipc_get_resource_list(device_t dev, device_t child) 630{ 631 struct chipc_devinfo *dinfo = device_get_ivars(child); 632 return (&dinfo->resources); 633} 634 635 636/* Allocate region records for the given port, and add the port's memory 637 * range to the mem_rman */ 638static int 639chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 640 u_int port) 641{ 642 struct chipc_region *cr; 643 rman_res_t start, end; 644 u_int num_regions; 645 int error; 646 647 num_regions = bhnd_get_region_count(sc->dev, type, port); 648 for (u_int region = 0; region < num_regions; region++) { 649 /* Allocate new region record */ 650 cr = chipc_alloc_region(sc, type, port, region); 651 if (cr == NULL) 652 return (ENODEV); 653 654 /* Can't manage regions that cannot be allocated */ 655 if (cr->cr_rid < 0) { 656 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 657 "%s%u.%u", bhnd_port_type_name(type), port, region); 658 chipc_free_region(sc, cr); 659 continue; 660 } 661 662 /* Add to rman's managed range */ 663 start = cr->cr_addr; 664 end = cr->cr_end; 665 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 666 chipc_free_region(sc, cr); 667 return (error); 668 } 669 670 /* Add to region list */ 671 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 672 } 673 674 return (0); 675} 676 677/* Initialize memory state for all chipc port regions */ 678static int 679chipc_init_rman(struct chipc_softc *sc) 680{ 681 u_int num_ports; 682 int error; 683 684 /* Port types for which we'll register chipc_region mappings */ 685 bhnd_port_type types[] = { 686 BHND_PORT_DEVICE 687 }; 688 689 /* Initialize resource manager */ 690 sc->mem_rman.rm_start = 0; 691 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 692 sc->mem_rman.rm_type = RMAN_ARRAY; 693 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 694 if ((error = rman_init(&sc->mem_rman))) { 695 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 696 error); 697 return (error); 698 } 699 700 /* Populate per-port-region state */ 701 for (u_int i = 0; i < nitems(types); i++) { 702 num_ports = bhnd_get_port_count(sc->dev, types[i]); 703 for (u_int port = 0; port < num_ports; port++) { 704 error = chipc_rman_init_regions(sc, types[i], port); 705 if (error) { 706 device_printf(sc->dev, 707 "region init failed for %s%u: %d\n", 708 bhnd_port_type_name(types[i]), port, 709 error); 710 711 goto failed; 712 } 713 } 714 } 715 716 return (0); 717 718failed: 719 chipc_free_rman(sc); 720 return (error); 721} 722 723/* Free memory management state */ 724static void 725chipc_free_rman(struct chipc_softc *sc) 726{ 727 struct chipc_region *cr, *cr_next; 728 729 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 730 chipc_free_region(sc, cr); 731 732 rman_fini(&sc->mem_rman); 733} 734 735/** 736 * Return the rman instance for a given resource @p type, if any. 737 * 738 * @param sc The chipc device state. 739 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 740 */ 741static struct rman * 742chipc_get_rman(struct chipc_softc *sc, int type) 743{ 744 switch (type) { 745 case SYS_RES_MEMORY: 746 return (&sc->mem_rman); 747 748 case SYS_RES_IRQ: 749 /* IRQs can be used with RF_SHAREABLE, so we don't perform 750 * any local proxying of resource requests. */ 751 return (NULL); 752 753 default: 754 return (NULL); 755 }; 756} 757 758static struct resource * 759chipc_alloc_resource(device_t dev, device_t child, int type, 760 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 761{ 762 struct chipc_softc *sc; 763 struct chipc_region *cr; 764 struct resource_list_entry *rle; 765 struct resource *rv; 766 struct rman *rm; 767 int error; 768 bool passthrough, isdefault; 769 770 sc = device_get_softc(dev); 771 passthrough = (device_get_parent(child) != dev); 772 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 773 rle = NULL; 774 775 /* Fetch the resource manager, delegate request if necessary */ 776 rm = chipc_get_rman(sc, type); 777 if (rm == NULL) { 778 /* Requested resource type is delegated to our parent */ 779 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 780 start, end, count, flags); 781 return (rv); 782 } 783 784 /* Populate defaults */ 785 if (!passthrough && isdefault) { 786 /* Fetch the resource list entry. */ 787 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 788 type, *rid); 789 if (rle == NULL) { 790 device_printf(dev, 791 "default resource %#x type %d for child %s " 792 "not found\n", *rid, type, 793 device_get_nameunit(child)); 794 return (NULL); 795 } 796 797 if (rle->res != NULL) { 798 device_printf(dev, 799 "resource entry %#x type %d for child %s is busy " 800 "[%d]\n", 801 *rid, type, device_get_nameunit(child), 802 rman_get_flags(rle->res)); 803 804 return (NULL); 805 } 806 807 start = rle->start; 808 end = rle->end; 809 count = ulmax(count, rle->count); 810 } 811 812 /* Locate a mapping region */ 813 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 814 /* Resource requests outside our shared port regions can be 815 * delegated to our parent. */ 816 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 817 start, end, count, flags); 818 return (rv); 819 } 820 821 /* Try to retain a region reference */ 822 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 823 return (NULL); 824 825 /* Make our rman reservation */ 826 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 827 child); 828 if (rv == NULL) { 829 chipc_release_region(sc, cr, RF_ALLOCATED); 830 return (NULL); 831 } 832 833 rman_set_rid(rv, *rid); 834 835 /* Activate */ 836 if (flags & RF_ACTIVE) { 837 error = bus_activate_resource(child, type, *rid, rv); 838 if (error) { 839 device_printf(dev, 840 "failed to activate entry %#x type %d for " 841 "child %s: %d\n", 842 *rid, type, device_get_nameunit(child), error); 843 844 chipc_release_region(sc, cr, RF_ALLOCATED); 845 rman_release_resource(rv); 846 847 return (NULL); 848 } 849 } 850 851 /* Update child's resource list entry */ 852 if (rle != NULL) { 853 rle->res = rv; 854 rle->start = rman_get_start(rv); 855 rle->end = rman_get_end(rv); 856 rle->count = rman_get_size(rv); 857 } 858 859 return (rv); 860} 861 862static int 863chipc_release_resource(device_t dev, device_t child, int type, int rid, 864 struct resource *r) 865{ 866 struct chipc_softc *sc; 867 struct chipc_region *cr; 868 struct rman *rm; 869 struct resource_list_entry *rle; 870 int error; 871 872 sc = device_get_softc(dev); 873 874 /* Handled by parent bus? */ 875 rm = chipc_get_rman(sc, type); 876 if (rm == NULL || !rman_is_region_manager(r, rm)) { 877 return (bus_generic_rl_release_resource(dev, child, type, rid, 878 r)); 879 } 880 881 /* Locate the mapping region */ 882 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 883 if (cr == NULL) 884 return (EINVAL); 885 886 /* Deactivate resources */ 887 if (rman_get_flags(r) & RF_ACTIVE) { 888 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 889 if (error) 890 return (error); 891 } 892 893 if ((error = rman_release_resource(r))) 894 return (error); 895 896 /* Drop allocation reference */ 897 chipc_release_region(sc, cr, RF_ALLOCATED); 898 899 /* Clear reference from the resource list entry if exists */ 900 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 901 if (rle != NULL) 902 rle->res = NULL; 903 904 return (0); 905} 906 907static int 908chipc_adjust_resource(device_t dev, device_t child, int type, 909 struct resource *r, rman_res_t start, rman_res_t end) 910{ 911 struct chipc_softc *sc; 912 struct chipc_region *cr; 913 struct rman *rm; 914 915 sc = device_get_softc(dev); 916 917 /* Handled by parent bus? */ 918 rm = chipc_get_rman(sc, type); 919 if (rm == NULL || !rman_is_region_manager(r, rm)) { 920 return (bus_generic_adjust_resource(dev, child, type, r, start, 921 end)); 922 } 923 924 /* The range is limited to the existing region mapping */ 925 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 926 if (cr == NULL) 927 return (EINVAL); 928 929 if (end <= start) 930 return (EINVAL); 931 932 if (start < cr->cr_addr || end > cr->cr_end) 933 return (EINVAL); 934 935 /* Range falls within the existing region */ 936 return (rman_adjust_resource(r, start, end)); 937} 938 939/** 940 * Retain an RF_ACTIVE reference to the region mapping @p r, and 941 * configure @p r with its subregion values. 942 * 943 * @param sc Driver instance state. 944 * @param child Requesting child device. 945 * @param type resource type of @p r. 946 * @param rid resource id of @p r 947 * @param r resource to be activated. 948 * @param req_direct If true, failure to allocate a direct bhnd resource 949 * will be treated as an error. If false, the resource will not be marked 950 * as RF_ACTIVE if bhnd direct resource allocation fails. 951 */ 952static int 953chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 954 int rid, struct resource *r, bool req_direct) 955{ 956 struct rman *rm; 957 struct chipc_region *cr; 958 bhnd_size_t cr_offset; 959 rman_res_t r_start, r_end, r_size; 960 int error; 961 962 rm = chipc_get_rman(sc, type); 963 if (rm == NULL || !rman_is_region_manager(r, rm)) 964 return (EINVAL); 965 966 r_start = rman_get_start(r); 967 r_end = rman_get_end(r); 968 r_size = rman_get_size(r); 969 970 /* Find the corresponding chipc region */ 971 cr = chipc_find_region(sc, r_start, r_end); 972 if (cr == NULL) 973 return (EINVAL); 974 975 /* Calculate subregion offset within the chipc region */ 976 cr_offset = r_start - cr->cr_addr; 977 978 /* Retain (and activate, if necessary) the chipc region */ 979 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 980 return (error); 981 982 /* Configure child resource with its subregion values. */ 983 if (cr->cr_res->direct) { 984 error = chipc_init_child_resource(r, cr->cr_res->res, 985 cr_offset, r_size); 986 if (error) 987 goto cleanup; 988 989 /* Mark active */ 990 if ((error = rman_activate_resource(r))) 991 goto cleanup; 992 } else if (req_direct) { 993 error = ENOMEM; 994 goto cleanup; 995 } 996 997 return (0); 998 999cleanup: 1000 chipc_release_region(sc, cr, RF_ACTIVE); 1001 return (error); 1002} 1003 1004static int 1005chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1006 int rid, struct bhnd_resource *r) 1007{ 1008 struct chipc_softc *sc; 1009 struct rman *rm; 1010 int error; 1011 1012 sc = device_get_softc(dev); 1013 1014 /* Delegate non-locally managed resources to parent */ 1015 rm = chipc_get_rman(sc, type); 1016 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1017 return (bhnd_bus_generic_activate_resource(dev, child, type, 1018 rid, r)); 1019 } 1020 1021 /* Try activating the chipc region resource */ 1022 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1023 false); 1024 if (error) 1025 return (error); 1026 1027 /* Mark the child resource as direct according to the returned resource 1028 * state */ 1029 if (rman_get_flags(r->res) & RF_ACTIVE) 1030 r->direct = true; 1031 1032 return (0); 1033} 1034 1035static int 1036chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1037 struct resource *r) 1038{ 1039 struct chipc_softc *sc; 1040 struct rman *rm; 1041 1042 sc = device_get_softc(dev); 1043 1044 /* Delegate non-locally managed resources to parent */ 1045 rm = chipc_get_rman(sc, type); 1046 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1047 return (bus_generic_activate_resource(dev, child, type, rid, 1048 r)); 1049 } 1050 1051 /* Try activating the chipc region-based resource */ 1052 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1053} 1054 1055/** 1056 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1057 */ 1058static int 1059chipc_deactivate_resource(device_t dev, device_t child, int type, 1060 int rid, struct resource *r) 1061{ 1062 struct chipc_softc *sc; 1063 struct chipc_region *cr; 1064 struct rman *rm; 1065 int error; 1066 1067 sc = device_get_softc(dev); 1068 1069 /* Handled by parent bus? */ 1070 rm = chipc_get_rman(sc, type); 1071 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1072 return (bus_generic_deactivate_resource(dev, child, type, rid, 1073 r)); 1074 } 1075 1076 /* Find the corresponding chipc region */ 1077 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1078 if (cr == NULL) 1079 return (EINVAL); 1080 1081 /* Mark inactive */ 1082 if ((error = rman_deactivate_resource(r))) 1083 return (error); 1084 1085 /* Drop associated RF_ACTIVE reference */ 1086 chipc_release_region(sc, cr, RF_ACTIVE); 1087 1088 return (0); 1089} 1090 1091/** 1092 * Examine bus state and make a best effort determination of whether it's 1093 * likely safe to enable the muxed SPROM pins. 1094 * 1095 * On devices that do not use SPROM pin muxing, always returns true. 1096 * 1097 * @param sc chipc driver state. 1098 */ 1099static bool 1100chipc_should_enable_sprom(struct chipc_softc *sc) 1101{ 1102 device_t *devs; 1103 device_t hostb; 1104 device_t parent; 1105 int devcount; 1106 int error; 1107 bool result; 1108 1109 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1110 1111 /* Nothing to do? */ 1112 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1113 return (true); 1114 1115 parent = device_get_parent(sc->dev); 1116 hostb = bhnd_find_hostb_device(parent); 1117 1118 if ((error = device_get_children(parent, &devs, &devcount))) 1119 return (false); 1120 1121 /* Reject any active devices other than ChipCommon, or the 1122 * host bridge (if any). */ 1123 result = true; 1124 for (int i = 0; i < devcount; i++) { 1125 if (devs[i] == hostb || devs[i] == sc->dev) 1126 continue; 1127 1128 if (!device_is_attached(devs[i])) 1129 continue; 1130 1131 if (device_is_suspended(devs[i])) 1132 continue; 1133 1134 /* Active device; assume SPROM is busy */ 1135 result = false; 1136 break; 1137 } 1138 1139 free(devs, M_TEMP); 1140 return (result); 1141} 1142 1143/** 1144 * If required by this device, enable access to the SPROM. 1145 * 1146 * @param sc chipc driver state. 1147 */ 1148static int 1149chipc_enable_sprom_pins(device_t dev) 1150{ 1151 struct chipc_softc *sc; 1152 uint32_t cctrl; 1153 int error; 1154 1155 sc = device_get_softc(dev); 1156 1157 /* Nothing to do? */ 1158 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1159 return (0); 1160 1161 /* Make sure we're holding Giant for newbus */ 1162 mtx_lock(&Giant); 1163 CHIPC_LOCK(sc); 1164 1165 /* Already enabled? */ 1166 if (sc->sprom_refcnt >= 1) { 1167 error = 0; 1168 goto finished; 1169 } 1170 1171 /* Check whether bus is busy */ 1172 if (!chipc_should_enable_sprom(sc)) { 1173 error = EBUSY; 1174 goto finished; 1175 } 1176 1177 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1178 1179 /* 4331 devices */ 1180 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1181 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1182 1183 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1184 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1185 1186 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1187 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1188 1189 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1190 error = 0; 1191 goto finished; 1192 } 1193 1194 /* 4360 devices */ 1195 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1196 /* Unimplemented */ 1197 } 1198 1199 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1200 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1201 error = ENXIO; 1202 1203finished: 1204 /* Bump the reference count */ 1205 if (error == 0) 1206 sc->sprom_refcnt++; 1207 1208 CHIPC_UNLOCK(sc); 1209 mtx_unlock(&Giant); 1210 1211 return (error); 1212} 1213 1214/** 1215 * If required by this device, revert any GPIO/pin configuration applied 1216 * to allow SPROM access. 1217 * 1218 * @param sc chipc driver state. 1219 */ 1220static void 1221chipc_disable_sprom_pins(device_t dev) 1222{ 1223 struct chipc_softc *sc; 1224 uint32_t cctrl; 1225 1226 sc = device_get_softc(dev); 1227 1228 /* Nothing to do? */ 1229 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1230 return; 1231 1232 CHIPC_LOCK(sc); 1233 1234 /* Check reference count, skip disable if in-use. */ 1235 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1236 sc->sprom_refcnt--; 1237 if (sc->sprom_refcnt > 0) 1238 goto finished; 1239 1240 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1241 1242 /* 4331 devices */ 1243 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1244 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1245 1246 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1247 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1248 1249 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1250 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1251 1252 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1253 goto finished; 1254 } 1255 1256 /* 4360 devices */ 1257 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1258 /* Unimplemented */ 1259 } 1260 1261finished: 1262 CHIPC_UNLOCK(sc); 1263} 1264 1265static void 1266chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1267{ 1268 struct chipc_softc *sc; 1269 uint32_t cctrl; 1270 1271 sc = device_get_softc(dev); 1272 1273 CHIPC_LOCK(sc); 1274 1275 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1276 cctrl = (cctrl & ~mask) | (value | mask); 1277 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1278 1279 CHIPC_UNLOCK(sc); 1280} 1281 1282static struct chipc_caps * 1283chipc_get_caps(device_t dev) 1284{ 1285 struct chipc_softc *sc; 1286 1287 sc = device_get_softc(dev); 1288 return (&sc->caps); 1289} 1290 1291static device_method_t chipc_methods[] = { 1292 /* Device interface */ 1293 DEVMETHOD(device_probe, chipc_probe), 1294 DEVMETHOD(device_attach, chipc_attach), 1295 DEVMETHOD(device_detach, chipc_detach), 1296 DEVMETHOD(device_suspend, chipc_suspend), 1297 DEVMETHOD(device_resume, chipc_resume), 1298 1299 /* Bus interface */ 1300 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1301 DEVMETHOD(bus_print_child, chipc_print_child), 1302 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1303 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1304 1305 DEVMETHOD(bus_add_child, chipc_add_child), 1306 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1307 1308 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1309 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1310 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1311 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1312 DEVMETHOD(bus_release_resource, chipc_release_resource), 1313 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1314 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1315 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1316 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1317 1318 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1319 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1320 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1321 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1322 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1323 1324 /* BHND bus inteface */ 1325 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1326 1327 /* ChipCommon interface */ 1328 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1329 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1330 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1331 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1332 1333 DEVMETHOD_END 1334}; 1335 1336DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1337EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0, 1338 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1339MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1340MODULE_VERSION(bhnd_chipc, 1); 1341