chipc.c revision 301409
1/*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bhnd/cores/chipc/chipc.c 301409 2016-06-04 19:39:05Z landonf $"); 33 34/* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 41 * flash, etc. 42 * 43 * The purpose of this driver is memory resource management for ChipCommon drivers 44 * like UART, PMU, flash. ChipCommon core has several memory regions. 45 * 46 * ChipCommon driver has memory resource manager. Driver 47 * gets information about BHND core ports/regions and map them 48 * into drivers' resources. 49 * 50 * Here is overview of mapping: 51 * 52 * ------------------------------------------------------ 53 * | Port.Region| Purpose | 54 * ------------------------------------------------------ 55 * | 0.0 | PMU, SPI(0x40), UART(0x300) | 56 * | 1.0 | ? | 57 * | 1.1 | MMIO flash (SPI & CFI) | 58 * ------------------------------------------------------ 59 */ 60 61#include <sys/param.h> 62#include <sys/kernel.h> 63#include <sys/lock.h> 64#include <sys/bus.h> 65#include <sys/rman.h> 66#include <sys/malloc.h> 67#include <sys/module.h> 68#include <sys/mutex.h> 69#include <sys/systm.h> 70 71#include <machine/bus.h> 72#include <machine/resource.h> 73 74#include <dev/bhnd/bhnd.h> 75#include <dev/bhnd/bhndvar.h> 76 77#include "chipcreg.h" 78#include "chipcvar.h" 79#include "chipc_private.h" 80 81devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 82 83static struct bhnd_device_quirk chipc_quirks[]; 84 85/* Supported device identifiers */ 86static const struct bhnd_device chipc_devices[] = { 87 BHND_DEVICE(CC, NULL, chipc_quirks), 88 BHND_DEVICE_END 89}; 90 91 92/* Device quirks table */ 93static struct bhnd_device_quirk chipc_quirks[] = { 94 /* core revision quirks */ 95 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 96 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 97 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPLAYOUT_SIZE), 98 99 /* 4706 variant quirks */ 100 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 101 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 102 103 /* 4331 quirks*/ 104 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 105 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 106 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 107 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 108 109 /* 4360 quirks */ 110 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 111 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 112 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 113 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 114 115 BHND_DEVICE_QUIRK_END 116}; 117 118 119/* 120 * Here is resource configuration hints for child devices 121 * 122 * [Flash] There are 2 flash resources: 123 * - resource ID (rid) = 0: memory-mapped flash memory 124 * - resource ID (rid) = 1: memory-mapped flash registers (i.e for SPI) 125 * 126 * [UART] Uses IRQ and memory resources: 127 * - resource ID (rid) = 0: memory-mapped registers 128 * - IRQ resource ID (rid) = 0: shared IRQ line for Tx/Rx. 129 */ 130 131static const struct chipc_hint { 132 const char *name; 133 int unit; 134 int type; 135 int rid; 136 rman_res_t base; /* relative to parent resource */ 137 rman_res_t size; 138 u_int port; /* ignored if SYS_RES_IRQ */ 139 u_int region; 140} chipc_hints[] = { 141 // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs 142 // FIXME: IRQ shouldn't be hardcoded 143 /* device unit type rid base size port,region */ 144 { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, 145 { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, 146 { "uart", 0, SYS_RES_IRQ, 0, 2, 1 }, 147 { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, 148 { "uart", 1, SYS_RES_IRQ, 0, 2, 1 }, 149 { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, 150 { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 151 { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, 152 { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 153 { NULL } 154}; 155 156 157static int chipc_try_activate_resource( 158 struct chipc_softc *sc, device_t child, 159 int type, int rid, struct resource *r, 160 bool req_direct); 161 162static int chipc_read_caps(struct chipc_softc *sc, 163 struct chipc_caps *caps); 164 165static bhnd_nvram_src_t chipc_nvram_identify(struct chipc_softc *sc); 166static bool chipc_should_enable_sprom( 167 struct chipc_softc *sc); 168 169static int chipc_init_rman(struct chipc_softc *sc); 170static void chipc_free_rman(struct chipc_softc *sc); 171static struct rman *chipc_get_rman(struct chipc_softc *sc, 172 int type); 173 174/* quirk and capability flag convenience macros */ 175#define CHIPC_QUIRK(_sc, _name) \ 176 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 177 178#define CHIPC_CAP(_sc, _name) \ 179 ((_sc)->caps._name) 180 181#define CHIPC_ASSERT_QUIRK(_sc, name) \ 182 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 183 184#define CHIPC_ASSERT_CAP(_sc, name) \ 185 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 186 187static int 188chipc_probe(device_t dev) 189{ 190 const struct bhnd_device *id; 191 192 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 193 if (id == NULL) 194 return (ENXIO); 195 196 bhnd_set_default_core_desc(dev); 197 return (BUS_PROBE_DEFAULT); 198} 199 200static int 201chipc_attach(device_t dev) 202{ 203 struct chipc_softc *sc; 204 bhnd_addr_t enum_addr; 205 uint32_t ccid_reg; 206 uint8_t chip_type; 207 int error; 208 209 sc = device_get_softc(dev); 210 sc->dev = dev; 211 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 212 sizeof(chipc_devices[0])); 213 sc->sprom_refcnt = 0; 214 215 CHIPC_LOCK_INIT(sc); 216 STAILQ_INIT(&sc->mem_regions); 217 218 /* Set up resource management */ 219 if ((error = chipc_init_rman(sc))) { 220 device_printf(sc->dev, 221 "failed to initialize chipc resource state: %d\n", error); 222 goto failed; 223 } 224 225 /* Allocate the region containing our core registers */ 226 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 227 error = ENXIO; 228 goto failed; 229 } 230 231 error = chipc_retain_region(sc, sc->core_region, 232 RF_ALLOCATED|RF_ACTIVE); 233 if (error) { 234 sc->core_region = NULL; 235 goto failed; 236 } else { 237 sc->core = sc->core_region->cr_res; 238 } 239 240 /* Fetch our chipset identification data */ 241 ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); 242 chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); 243 244 switch (chip_type) { 245 case BHND_CHIPTYPE_SIBA: 246 /* enumeration space starts at the ChipCommon register base. */ 247 enum_addr = rman_get_start(sc->core->res); 248 break; 249 case BHND_CHIPTYPE_BCMA: 250 case BHND_CHIPTYPE_BCMA_ALT: 251 enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); 252 break; 253 default: 254 device_printf(dev, "unsupported chip type %hhu\n", chip_type); 255 error = ENODEV; 256 goto failed; 257 } 258 259 sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); 260 261 /* Fetch and parse capability register(s) */ 262 if ((error = chipc_read_caps(sc, &sc->caps))) 263 goto failed; 264 265 if (bootverbose) 266 chipc_print_caps(sc->dev, &sc->caps); 267 268 /* Identify NVRAM source */ 269 sc->nvram_src = chipc_nvram_identify(sc); 270 271 /* Probe and attach children */ 272 bus_generic_probe(dev); 273 if ((error = bus_generic_attach(dev))) 274 goto failed; 275 276 return (0); 277 278failed: 279 if (sc->core_region != NULL) { 280 chipc_release_region(sc, sc->core_region, 281 RF_ALLOCATED|RF_ACTIVE); 282 } 283 284 chipc_free_rman(sc); 285 CHIPC_LOCK_DESTROY(sc); 286 return (error); 287} 288 289static int 290chipc_detach(device_t dev) 291{ 292 struct chipc_softc *sc; 293 int error; 294 295 sc = device_get_softc(dev); 296 297 if ((error = bus_generic_detach(dev))) 298 return (error); 299 300 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 301 chipc_free_rman(sc); 302 303 CHIPC_LOCK_DESTROY(sc); 304 305 return (0); 306} 307 308/* Read and parse chipc capabilities */ 309static int 310chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 311{ 312 uint32_t cap_reg; 313 uint32_t cap_ext_reg; 314 uint32_t regval; 315 316 /* Fetch cap registers */ 317 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 318 cap_ext_reg = 0; 319 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 320 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 321 322 /* Extract values */ 323 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 324 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 325 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 326 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 327 328 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 329 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 330 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 331 332 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 333 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 334 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 335 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 336 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 337 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 338 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 339 340 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 341 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 342 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 343 344 /* Fetch OTP size for later IPX controller revisions */ 345 if (CHIPC_QUIRK(sc, IPX_OTPLAYOUT_SIZE)) { 346 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 347 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 348 } 349 350 /* Determine flash type and parameters */ 351 caps->cfi_width = 0; 352 353 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 354 case CHIPC_CAP_SFLASH_ST: 355 caps->flash_type = CHIPC_SFLASH_ST; 356 break; 357 case CHIPC_CAP_SFLASH_AT: 358 caps->flash_type = CHIPC_SFLASH_AT; 359 break; 360 case CHIPC_CAP_NFLASH: 361 caps->flash_type = CHIPC_NFLASH; 362 break; 363 case CHIPC_CAP_PFLASH: 364 caps->flash_type = CHIPC_PFLASH_CFI; 365 366 /* determine cfi width */ 367 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 368 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 369 caps->cfi_width = 2; 370 else 371 caps->cfi_width = 1; 372 373 break; 374 case CHIPC_CAP_FLASH_NONE: 375 caps->flash_type = CHIPC_FLASH_NONE; 376 break; 377 378 } 379 380 /* Handle 4706_NFLASH fallback */ 381 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 382 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 383 { 384 caps->flash_type = CHIPC_NFLASH_4706; 385 } 386 387 return (0); 388} 389 390/** 391 * Determine the NVRAM data source for this device. 392 * 393 * @param sc chipc driver state. 394 */ 395static bhnd_nvram_src_t 396chipc_nvram_identify(struct chipc_softc *sc) 397{ 398 uint32_t srom_ctrl; 399 400 /* Very early devices vend SPROM/OTP/CIS (if at all) via the 401 * host bridge interface instead of ChipCommon. */ 402 if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 403 return (BHND_NVRAM_SRC_UNKNOWN); 404 405 /* 406 * Later chipset revisions standardized the SPROM capability flags and 407 * register interfaces. 408 * 409 * We check for hardware presence in order of precedence. For example, 410 * SPROM is is always used in preference to internal OTP if found. 411 */ 412 if (CHIPC_CAP(sc, sprom)) { 413 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 414 if (srom_ctrl & CHIPC_SRC_PRESENT) 415 return (BHND_NVRAM_SRC_SPROM); 416 } 417 418 /* Check for OTP */ 419 if (CHIPC_CAP(sc, otp_size) != 0) 420 return (BHND_NVRAM_SRC_OTP); 421 422 /* Check for flash */ 423 if (CHIPC_CAP(sc, flash_type) != CHIPC_FLASH_NONE) 424 return (BHND_NVRAM_SRC_FLASH); 425 426 /* No NVRAM hardware capability declared */ 427 return (BHND_NVRAM_SRC_UNKNOWN); 428} 429 430static int 431chipc_suspend(device_t dev) 432{ 433 return (bus_generic_suspend(dev)); 434} 435 436static int 437chipc_resume(device_t dev) 438{ 439 return (bus_generic_resume(dev)); 440} 441 442static void 443chipc_probe_nomatch(device_t dev, device_t child) 444{ 445 struct resource_list *rl; 446 const char *name; 447 448 name = device_get_name(child); 449 if (name == NULL) 450 name = "unknown device"; 451 452 device_printf(dev, "<%s> at", name); 453 454 rl = BUS_GET_RESOURCE_LIST(dev, child); 455 if (rl != NULL) { 456 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 457 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 458 } 459 460 printf(" (no driver attached)\n"); 461} 462 463static int 464chipc_print_child(device_t dev, device_t child) 465{ 466 struct resource_list *rl; 467 int retval = 0; 468 469 retval += bus_print_child_header(dev, child); 470 471 rl = BUS_GET_RESOURCE_LIST(dev, child); 472 if (rl != NULL) { 473 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 474 "%#jx"); 475 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 476 "%jd"); 477 } 478 479 retval += bus_print_child_domain(dev, child); 480 retval += bus_print_child_footer(dev, child); 481 482 return (retval); 483} 484 485static int 486chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 487 size_t buflen) 488{ 489 if (buflen == 0) 490 return (EOVERFLOW); 491 492 *buf = '\0'; 493 return (0); 494} 495 496static int 497chipc_child_location_str(device_t dev, device_t child, char *buf, 498 size_t buflen) 499{ 500 if (buflen == 0) 501 return (EOVERFLOW); 502 503 *buf = '\0'; 504 return (ENXIO); 505} 506 507static device_t 508chipc_add_child(device_t dev, u_int order, const char *name, int unit) 509{ 510 struct chipc_devinfo *dinfo; 511 const struct chipc_hint *hint; 512 device_t child; 513 devclass_t child_dc; 514 int error; 515 int busrel_unit; 516 517 child = device_add_child_ordered(dev, order, name, unit); 518 if (child == NULL) 519 return (NULL); 520 521 /* system-wide device unit */ 522 unit = device_get_unit(child); 523 child_dc = device_get_devclass(child); 524 525 busrel_unit = 0; 526 for (int i = 0; i < unit; i++) { 527 device_t tmp; 528 529 tmp = devclass_get_device(child_dc, i); 530 if (tmp != NULL && (device_get_parent(tmp) == dev)) 531 busrel_unit++; 532 } 533 534 /* bus-wide device unit (override unit for further hint matching) */ 535 unit = busrel_unit; 536 537 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 538 if (dinfo == NULL) { 539 device_delete_child(dev, child); 540 return (NULL); 541 } 542 543 resource_list_init(&dinfo->resources); 544 device_set_ivars(child, dinfo); 545 546 /* Hint matching requires a device name */ 547 if (name == NULL) 548 return (child); 549 550 /* Use hint table to set child resources */ 551 for (hint = chipc_hints; hint->name != NULL; hint++) { 552 bhnd_addr_t region_addr; 553 bhnd_size_t region_size; 554 555 /* Check device name */ 556 if (strcmp(hint->name, name) != 0) 557 continue; 558 559 /* Check device unit */ 560 if (hint->unit >= 0 && unit != hint->unit) 561 continue; 562 563 switch (hint->type) { 564 case SYS_RES_IRQ: 565 /* Add child resource */ 566 error = bus_set_resource(child, hint->type, hint->rid, 567 hint->base, hint->size); 568 if (error) { 569 device_printf(dev, 570 "bus_set_resource() failed for %s: %d\n", 571 device_get_nameunit(child), error); 572 goto failed; 573 } 574 break; 575 576 case SYS_RES_MEMORY: 577 /* Fetch region address and size */ 578 error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, 579 hint->port, hint->region, ®ion_addr, 580 ®ion_size); 581 if (error) { 582 device_printf(dev, 583 "lookup of %s%u.%u failed: %d\n", 584 bhnd_port_type_name(BHND_PORT_DEVICE), 585 hint->port, hint->region, error); 586 goto failed; 587 } 588 589 /* Verify requested range is mappable */ 590 if (hint->base > region_size || 591 (hint->size != RM_MAX_END && 592 (hint->size > region_size || 593 region_size - hint->base < hint->size ))) 594 { 595 device_printf(dev, 596 "%s%u.%u region cannot map requested range " 597 "%#jx+%#jx\n", 598 bhnd_port_type_name(BHND_PORT_DEVICE), 599 hint->port, hint->region, hint->base, 600 hint->size); 601 } 602 603 /* 604 * Add child resource. If hint doesn't define the end 605 * of resource window (RX_MAX_END), use end of region. 606 */ 607 608 error = bus_set_resource(child, 609 hint->type, 610 hint->rid, region_addr + hint->base, 611 (hint->size == RM_MAX_END) ? 612 region_size - hint->base : 613 hint->size); 614 if (error) { 615 device_printf(dev, 616 "bus_set_resource() failed for %s: %d\n", 617 device_get_nameunit(child), error); 618 goto failed; 619 } 620 break; 621 default: 622 device_printf(child, "unknown hint resource type: %d\n", 623 hint->type); 624 break; 625 } 626 } 627 628 return (child); 629 630failed: 631 device_delete_child(dev, child); 632 return (NULL); 633} 634 635static void 636chipc_child_deleted(device_t dev, device_t child) 637{ 638 struct chipc_devinfo *dinfo = device_get_ivars(child); 639 640 if (dinfo != NULL) { 641 resource_list_free(&dinfo->resources); 642 free(dinfo, M_BHND); 643 } 644 645 device_set_ivars(child, NULL); 646} 647 648static struct resource_list * 649chipc_get_resource_list(device_t dev, device_t child) 650{ 651 struct chipc_devinfo *dinfo = device_get_ivars(child); 652 return (&dinfo->resources); 653} 654 655 656/* Allocate region records for the given port, and add the port's memory 657 * range to the mem_rman */ 658static int 659chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 660 u_int port) 661{ 662 struct chipc_region *cr; 663 rman_res_t start, end; 664 u_int num_regions; 665 int error; 666 667 num_regions = bhnd_get_region_count(sc->dev, port, port); 668 for (u_int region = 0; region < num_regions; region++) { 669 /* Allocate new region record */ 670 cr = chipc_alloc_region(sc, type, port, region); 671 if (cr == NULL) 672 return (ENODEV); 673 674 /* Can't manage regions that cannot be allocated */ 675 if (cr->cr_rid < 0) { 676 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 677 "%s%u.%u", bhnd_port_type_name(type), port, region); 678 chipc_free_region(sc, cr); 679 continue; 680 } 681 682 /* Add to rman's managed range */ 683 start = cr->cr_addr; 684 end = cr->cr_end; 685 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 686 chipc_free_region(sc, cr); 687 return (error); 688 } 689 690 /* Add to region list */ 691 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 692 } 693 694 return (0); 695} 696 697/* Initialize memory state for all chipc port regions */ 698static int 699chipc_init_rman(struct chipc_softc *sc) 700{ 701 u_int num_ports; 702 int error; 703 704 /* Port types for which we'll register chipc_region mappings */ 705 bhnd_port_type types[] = { 706 BHND_PORT_DEVICE 707 }; 708 709 /* Initialize resource manager */ 710 sc->mem_rman.rm_start = 0; 711 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 712 sc->mem_rman.rm_type = RMAN_ARRAY; 713 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 714 if ((error = rman_init(&sc->mem_rman))) { 715 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 716 error); 717 return (error); 718 } 719 720 /* Populate per-port-region state */ 721 for (u_int i = 0; i < nitems(types); i++) { 722 num_ports = bhnd_get_port_count(sc->dev, types[i]); 723 for (u_int port = 0; port < num_ports; port++) { 724 error = chipc_rman_init_regions(sc, types[i], port); 725 if (error) { 726 device_printf(sc->dev, 727 "region init failed for %s%u: %d\n", 728 bhnd_port_type_name(types[i]), port, 729 error); 730 731 goto failed; 732 } 733 } 734 } 735 736 return (0); 737 738failed: 739 chipc_free_rman(sc); 740 return (error); 741} 742 743/* Free memory management state */ 744static void 745chipc_free_rman(struct chipc_softc *sc) 746{ 747 struct chipc_region *cr, *cr_next; 748 749 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 750 chipc_free_region(sc, cr); 751 752 rman_fini(&sc->mem_rman); 753} 754 755/** 756 * Return the rman instance for a given resource @p type, if any. 757 * 758 * @param sc The chipc device state. 759 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 760 */ 761static struct rman * 762chipc_get_rman(struct chipc_softc *sc, int type) 763{ 764 switch (type) { 765 case SYS_RES_MEMORY: 766 return (&sc->mem_rman); 767 768 case SYS_RES_IRQ: 769 /* IRQs can be used with RF_SHAREABLE, so we don't perform 770 * any local proxying of resource requests. */ 771 return (NULL); 772 773 default: 774 return (NULL); 775 }; 776} 777 778static struct resource * 779chipc_alloc_resource(device_t dev, device_t child, int type, 780 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 781{ 782 struct chipc_softc *sc; 783 struct chipc_region *cr; 784 struct resource_list_entry *rle; 785 struct resource *rv; 786 struct rman *rm; 787 int error; 788 bool passthrough, isdefault; 789 790 sc = device_get_softc(dev); 791 passthrough = (device_get_parent(child) != dev); 792 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 793 rle = NULL; 794 795 /* Fetch the resource manager, delegate request if necessary */ 796 rm = chipc_get_rman(sc, type); 797 if (rm == NULL) { 798 /* Requested resource type is delegated to our parent */ 799 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 800 start, end, count, flags); 801 return (rv); 802 } 803 804 /* Populate defaults */ 805 if (!passthrough && isdefault) { 806 /* Fetch the resource list entry. */ 807 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 808 type, *rid); 809 if (rle == NULL) { 810 device_printf(dev, 811 "default resource %#x type %d for child %s " 812 "not found\n", *rid, type, 813 device_get_nameunit(child)); 814 return (NULL); 815 } 816 817 if (rle->res != NULL) { 818 device_printf(dev, 819 "resource entry %#x type %d for child %s is busy " 820 "[%d]\n", 821 *rid, type, device_get_nameunit(child), 822 rman_get_flags(rle->res)); 823 824 return (NULL); 825 } 826 827 start = rle->start; 828 end = rle->end; 829 count = ulmax(count, rle->count); 830 } 831 832 /* Locate a mapping region */ 833 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 834 /* Resource requests outside our shared port regions can be 835 * delegated to our parent. */ 836 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 837 start, end, count, flags); 838 return (rv); 839 } 840 841 /* Try to retain a region reference */ 842 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) { 843 CHIPC_UNLOCK(sc); 844 return (NULL); 845 } 846 847 /* Make our rman reservation */ 848 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 849 child); 850 if (rv == NULL) { 851 chipc_release_region(sc, cr, RF_ALLOCATED); 852 return (NULL); 853 } 854 855 rman_set_rid(rv, *rid); 856 857 /* Activate */ 858 if (flags & RF_ACTIVE) { 859 error = bus_activate_resource(child, type, *rid, rv); 860 if (error) { 861 device_printf(dev, 862 "failed to activate entry %#x type %d for " 863 "child %s: %d\n", 864 *rid, type, device_get_nameunit(child), error); 865 866 chipc_release_region(sc, cr, RF_ALLOCATED); 867 rman_release_resource(rv); 868 869 return (NULL); 870 } 871 } 872 873 /* Update child's resource list entry */ 874 if (rle != NULL) { 875 rle->res = rv; 876 rle->start = rman_get_start(rv); 877 rle->end = rman_get_end(rv); 878 rle->count = rman_get_size(rv); 879 } 880 881 return (rv); 882} 883 884static int 885chipc_release_resource(device_t dev, device_t child, int type, int rid, 886 struct resource *r) 887{ 888 struct chipc_softc *sc; 889 struct chipc_region *cr; 890 struct rman *rm; 891 struct resource_list_entry *rle; 892 int error; 893 894 sc = device_get_softc(dev); 895 896 /* Handled by parent bus? */ 897 rm = chipc_get_rman(sc, type); 898 if (rm == NULL || !rman_is_region_manager(r, rm)) { 899 return (bus_generic_rl_release_resource(dev, child, type, rid, 900 r)); 901 } 902 903 /* Locate the mapping region */ 904 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 905 if (cr == NULL) 906 return (EINVAL); 907 908 /* Deactivate resources */ 909 if (rman_get_flags(r) & RF_ACTIVE) { 910 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 911 if (error) 912 return (error); 913 } 914 915 if ((error = rman_release_resource(r))) 916 return (error); 917 918 /* Drop allocation reference */ 919 chipc_release_region(sc, cr, RF_ALLOCATED); 920 921 /* Clear reference from the resource list entry if exists */ 922 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 923 if (rle != NULL) 924 rle->res = NULL; 925 926 return (0); 927} 928 929static int 930chipc_adjust_resource(device_t dev, device_t child, int type, 931 struct resource *r, rman_res_t start, rman_res_t end) 932{ 933 struct chipc_softc *sc; 934 struct chipc_region *cr; 935 struct rman *rm; 936 937 sc = device_get_softc(dev); 938 939 /* Handled by parent bus? */ 940 rm = chipc_get_rman(sc, type); 941 if (rm == NULL || !rman_is_region_manager(r, rm)) { 942 return (bus_generic_adjust_resource(dev, child, type, r, start, 943 end)); 944 } 945 946 /* The range is limited to the existing region mapping */ 947 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 948 if (cr == NULL) 949 return (EINVAL); 950 951 if (end <= start) 952 return (EINVAL); 953 954 if (start < cr->cr_addr || end > cr->cr_end) 955 return (EINVAL); 956 957 /* Range falls within the existing region */ 958 return (rman_adjust_resource(r, start, end)); 959} 960 961/** 962 * Retain an RF_ACTIVE reference to the region mapping @p r, and 963 * configure @p r with its subregion values. 964 * 965 * @param sc Driver instance state. 966 * @param child Requesting child device. 967 * @param type resource type of @p r. 968 * @param rid resource id of @p r 969 * @param r resource to be activated. 970 * @param req_direct If true, failure to allocate a direct bhnd resource 971 * will be treated as an error. If false, the resource will not be marked 972 * as RF_ACTIVE if bhnd direct resource allocation fails. 973 */ 974static int 975chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 976 int rid, struct resource *r, bool req_direct) 977{ 978 struct rman *rm; 979 struct chipc_region *cr; 980 bhnd_size_t cr_offset; 981 rman_res_t r_start, r_end, r_size; 982 int error; 983 984 rm = chipc_get_rman(sc, type); 985 if (rm == NULL || !rman_is_region_manager(r, rm)) 986 return (EINVAL); 987 988 r_start = rman_get_start(r); 989 r_end = rman_get_end(r); 990 r_size = rman_get_size(r); 991 992 /* Find the corresponding chipc region */ 993 cr = chipc_find_region(sc, r_start, r_end); 994 if (cr == NULL) 995 return (EINVAL); 996 997 /* Calculate subregion offset within the chipc region */ 998 cr_offset = r_start - cr->cr_addr; 999 1000 /* Retain (and activate, if necessary) the chipc region */ 1001 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1002 return (error); 1003 1004 /* Configure child resource with its subregion values. */ 1005 if (cr->cr_res->direct) { 1006 error = chipc_init_child_resource(r, cr->cr_res->res, 1007 cr_offset, r_size); 1008 if (error) 1009 goto cleanup; 1010 1011 /* Mark active */ 1012 if ((error = rman_activate_resource(r))) 1013 goto cleanup; 1014 } else if (req_direct) { 1015 error = ENOMEM; 1016 goto cleanup; 1017 } 1018 1019 return (0); 1020 1021cleanup: 1022 chipc_release_region(sc, cr, RF_ACTIVE); 1023 return (error); 1024} 1025 1026static int 1027chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1028 int rid, struct bhnd_resource *r) 1029{ 1030 struct chipc_softc *sc; 1031 struct rman *rm; 1032 int error; 1033 1034 sc = device_get_softc(dev); 1035 1036 /* Delegate non-locally managed resources to parent */ 1037 rm = chipc_get_rman(sc, type); 1038 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1039 return (bhnd_bus_generic_activate_resource(dev, child, type, 1040 rid, r)); 1041 } 1042 1043 /* Try activating the chipc region resource */ 1044 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1045 false); 1046 if (error) 1047 return (error); 1048 1049 /* Mark the child resource as direct according to the returned resource 1050 * state */ 1051 if (rman_get_flags(r->res) & RF_ACTIVE) 1052 r->direct = true; 1053 1054 return (0); 1055} 1056 1057static int 1058chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1059 struct resource *r) 1060{ 1061 struct chipc_softc *sc; 1062 struct rman *rm; 1063 1064 sc = device_get_softc(dev); 1065 1066 /* Delegate non-locally managed resources to parent */ 1067 rm = chipc_get_rman(sc, type); 1068 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1069 return (bus_generic_activate_resource(dev, child, type, rid, 1070 r)); 1071 } 1072 1073 /* Try activating the chipc region-based resource */ 1074 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1075} 1076 1077/** 1078 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1079 */ 1080static int 1081chipc_deactivate_resource(device_t dev, device_t child, int type, 1082 int rid, struct resource *r) 1083{ 1084 struct chipc_softc *sc; 1085 struct chipc_region *cr; 1086 struct rman *rm; 1087 int error; 1088 1089 sc = device_get_softc(dev); 1090 1091 /* Handled by parent bus? */ 1092 rm = chipc_get_rman(sc, type); 1093 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1094 return (bus_generic_deactivate_resource(dev, child, type, rid, 1095 r)); 1096 } 1097 1098 /* Find the corresponding chipc region */ 1099 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1100 if (cr == NULL) 1101 return (EINVAL); 1102 1103 /* Mark inactive */ 1104 if ((error = rman_deactivate_resource(r))) 1105 return (error); 1106 1107 /* Drop associated RF_ACTIVE reference */ 1108 chipc_release_region(sc, cr, RF_ACTIVE); 1109 1110 return (0); 1111} 1112 1113/** 1114 * Examine bus state and make a best effort determination of whether it's 1115 * likely safe to enable the muxed SPROM pins. 1116 * 1117 * On devices that do not use SPROM pin muxing, always returns true. 1118 * 1119 * @param sc chipc driver state. 1120 */ 1121static bool 1122chipc_should_enable_sprom(struct chipc_softc *sc) 1123{ 1124 device_t *devs; 1125 device_t hostb; 1126 device_t parent; 1127 int devcount; 1128 int error; 1129 bool result; 1130 1131 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1132 1133 /* Nothing to do? */ 1134 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1135 return (true); 1136 1137 parent = device_get_parent(sc->dev); 1138 hostb = bhnd_find_hostb_device(parent); 1139 1140 if ((error = device_get_children(parent, &devs, &devcount))) 1141 return (false); 1142 1143 /* Reject any active devices other than ChipCommon, or the 1144 * host bridge (if any). */ 1145 result = true; 1146 for (int i = 0; i < devcount; i++) { 1147 if (devs[i] == hostb || devs[i] == sc->dev) 1148 continue; 1149 1150 if (!device_is_attached(devs[i])) 1151 continue; 1152 1153 if (device_is_suspended(devs[i])) 1154 continue; 1155 1156 /* Active device; assume SPROM is busy */ 1157 result = false; 1158 break; 1159 } 1160 1161 free(devs, M_TEMP); 1162 return (result); 1163} 1164 1165/** 1166 * If required by this device, enable access to the SPROM. 1167 * 1168 * @param sc chipc driver state. 1169 */ 1170static int 1171chipc_enable_sprom_pins(device_t dev) 1172{ 1173 struct chipc_softc *sc; 1174 uint32_t cctrl; 1175 int error; 1176 1177 sc = device_get_softc(dev); 1178 1179 /* Nothing to do? */ 1180 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1181 return (0); 1182 1183 /* Make sure we're holding Giant for newbus */ 1184 mtx_lock(&Giant); 1185 CHIPC_LOCK(sc); 1186 1187 /* Already enabled? */ 1188 if (sc->sprom_refcnt >= 1) { 1189 error = 0; 1190 goto finished; 1191 } 1192 1193 /* Check whether bus is busy */ 1194 if (!chipc_should_enable_sprom(sc)) { 1195 error = EBUSY; 1196 goto finished; 1197 } 1198 1199 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1200 1201 /* 4331 devices */ 1202 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1203 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1204 1205 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1206 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1207 1208 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1209 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1210 1211 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1212 error = 0; 1213 goto finished; 1214 } 1215 1216 /* 4360 devices */ 1217 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1218 /* Unimplemented */ 1219 } 1220 1221 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1222 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1223 error = ENXIO; 1224 1225finished: 1226 /* Bump the reference count */ 1227 if (error == 0) 1228 sc->sprom_refcnt++; 1229 1230 CHIPC_UNLOCK(sc); 1231 mtx_unlock(&Giant); 1232 1233 return (error); 1234} 1235 1236/** 1237 * If required by this device, revert any GPIO/pin configuration applied 1238 * to allow SPROM access. 1239 * 1240 * @param sc chipc driver state. 1241 */ 1242static void 1243chipc_disable_sprom_pins(device_t dev) 1244{ 1245 struct chipc_softc *sc; 1246 uint32_t cctrl; 1247 1248 sc = device_get_softc(dev); 1249 1250 /* Nothing to do? */ 1251 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1252 return; 1253 1254 CHIPC_LOCK(sc); 1255 1256 /* Check reference count, skip disable if in-use. */ 1257 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1258 sc->sprom_refcnt--; 1259 if (sc->sprom_refcnt > 0) 1260 goto finished; 1261 1262 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1263 1264 /* 4331 devices */ 1265 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1266 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1267 1268 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1269 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1270 1271 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1272 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1273 1274 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1275 goto finished; 1276 } 1277 1278 /* 4360 devices */ 1279 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1280 /* Unimplemented */ 1281 } 1282 1283finished: 1284 CHIPC_UNLOCK(sc); 1285} 1286 1287static bhnd_nvram_src_t 1288chipc_nvram_src(device_t dev) 1289{ 1290 struct chipc_softc *sc = device_get_softc(dev); 1291 return (sc->nvram_src); 1292} 1293 1294static void 1295chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1296{ 1297 struct chipc_softc *sc; 1298 uint32_t cctrl; 1299 1300 sc = device_get_softc(dev); 1301 1302 CHIPC_LOCK(sc); 1303 1304 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1305 cctrl = (cctrl & ~mask) | (value | mask); 1306 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1307 1308 CHIPC_UNLOCK(sc); 1309} 1310 1311static struct chipc_caps * 1312chipc_get_caps(device_t dev) 1313{ 1314 struct chipc_softc *sc; 1315 1316 sc = device_get_softc(dev); 1317 return (&sc->caps); 1318} 1319 1320static uint32_t 1321chipc_get_flash_cfg(device_t dev) 1322{ 1323 struct chipc_softc *sc; 1324 1325 sc = device_get_softc(dev); 1326 return (bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG)); 1327} 1328 1329static device_method_t chipc_methods[] = { 1330 /* Device interface */ 1331 DEVMETHOD(device_probe, chipc_probe), 1332 DEVMETHOD(device_attach, chipc_attach), 1333 DEVMETHOD(device_detach, chipc_detach), 1334 DEVMETHOD(device_suspend, chipc_suspend), 1335 DEVMETHOD(device_resume, chipc_resume), 1336 1337 /* Bus interface */ 1338 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1339 DEVMETHOD(bus_print_child, chipc_print_child), 1340 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1341 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1342 1343 DEVMETHOD(bus_add_child, chipc_add_child), 1344 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1345 1346 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1347 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1348 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1349 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1350 DEVMETHOD(bus_release_resource, chipc_release_resource), 1351 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1352 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1353 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1354 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1355 1356 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1357 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1358 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1359 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1360 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1361 1362 /* BHND bus inteface */ 1363 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1364 1365 /* ChipCommon interface */ 1366 DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), 1367 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1368 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1369 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1370 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1371 DEVMETHOD(bhnd_chipc_get_flash_cfg, chipc_get_flash_cfg), 1372 1373 DEVMETHOD_END 1374}; 1375 1376DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1377EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0, 1378 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1379MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1380MODULE_VERSION(bhnd_chipc, 1); 1381