chipc.c revision 301408
1/*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bhnd/cores/chipc/chipc.c 301408 2016-06-04 19:31:06Z landonf $"); 33 34/* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 41 * flash, etc. 42 */ 43 44#include <sys/param.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/bus.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/systm.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <dev/bhnd/bhnd.h> 58#include <dev/bhnd/bhndvar.h> 59 60#include "chipcreg.h" 61#include "chipcvar.h" 62#include "chipc_private.h" 63 64devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 65 66static struct bhnd_device_quirk chipc_quirks[]; 67 68/* Supported device identifiers */ 69static const struct bhnd_device chipc_devices[] = { 70 BHND_DEVICE(CC, NULL, chipc_quirks), 71 BHND_DEVICE_END 72}; 73 74 75/* Device quirks table */ 76static struct bhnd_device_quirk chipc_quirks[] = { 77 /* core revision quirks */ 78 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 79 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 80 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPLAYOUT_SIZE), 81 82 /* 4706 variant quirks */ 83 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 84 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 85 86 /* 4331 quirks*/ 87 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 88 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 89 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 90 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 91 92 /* 4360 quirks */ 93 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 94 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 95 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 96 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 97 98 BHND_DEVICE_QUIRK_END 99}; 100 101 102static const struct chipc_hint { 103 const char *name; 104 int unit; 105 int type; 106 int rid; 107 rman_res_t base; /* relative to parent resource */ 108 rman_res_t size; 109 u_int port; /* ignored if SYS_RES_IRQ */ 110 u_int region; 111} chipc_hints[] = { 112 // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs 113 // FIXME: IRQ shouldn't be hardcoded 114 /* device unit type rid base size port,region */ 115 { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, 116 { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, 117 { "uart", 0, SYS_RES_IRQ, 0, 2, 1 }, 118 { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, 119 { "uart", 1, SYS_RES_IRQ, 0, 2, 1 }, 120 { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, 121 { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 122 { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, 123 { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 124 { NULL } 125}; 126 127 128static int chipc_try_activate_resource( 129 struct chipc_softc *sc, device_t child, 130 int type, int rid, struct resource *r, 131 bool req_direct); 132 133static int chipc_read_caps(struct chipc_softc *sc, 134 struct chipc_caps *caps); 135 136static bhnd_nvram_src_t chipc_nvram_identify(struct chipc_softc *sc); 137static bool chipc_should_enable_sprom( 138 struct chipc_softc *sc); 139 140static int chipc_init_rman(struct chipc_softc *sc); 141static void chipc_free_rman(struct chipc_softc *sc); 142static struct rman *chipc_get_rman(struct chipc_softc *sc, 143 int type); 144 145/* quirk and capability flag convenience macros */ 146#define CHIPC_QUIRK(_sc, _name) \ 147 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 148 149#define CHIPC_CAP(_sc, _name) \ 150 ((_sc)->caps._name) 151 152#define CHIPC_ASSERT_QUIRK(_sc, name) \ 153 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 154 155#define CHIPC_ASSERT_CAP(_sc, name) \ 156 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 157 158static int 159chipc_probe(device_t dev) 160{ 161 const struct bhnd_device *id; 162 163 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 164 if (id == NULL) 165 return (ENXIO); 166 167 bhnd_set_default_core_desc(dev); 168 return (BUS_PROBE_DEFAULT); 169} 170 171static int 172chipc_attach(device_t dev) 173{ 174 struct chipc_softc *sc; 175 bhnd_addr_t enum_addr; 176 uint32_t ccid_reg; 177 uint8_t chip_type; 178 int error; 179 180 sc = device_get_softc(dev); 181 sc->dev = dev; 182 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 183 sizeof(chipc_devices[0])); 184 sc->sprom_refcnt = 0; 185 186 CHIPC_LOCK_INIT(sc); 187 STAILQ_INIT(&sc->mem_regions); 188 189 /* Set up resource management */ 190 if ((error = chipc_init_rman(sc))) { 191 device_printf(sc->dev, 192 "failed to initialize chipc resource state: %d\n", error); 193 goto failed; 194 } 195 196 /* Allocate the region containing our core registers */ 197 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 198 error = ENXIO; 199 goto failed; 200 } 201 202 error = chipc_retain_region(sc, sc->core_region, 203 RF_ALLOCATED|RF_ACTIVE); 204 if (error) { 205 sc->core_region = NULL; 206 goto failed; 207 } else { 208 sc->core = sc->core_region->cr_res; 209 } 210 211 /* Fetch our chipset identification data */ 212 ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); 213 chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); 214 215 switch (chip_type) { 216 case BHND_CHIPTYPE_SIBA: 217 /* enumeration space starts at the ChipCommon register base. */ 218 enum_addr = rman_get_start(sc->core->res); 219 break; 220 case BHND_CHIPTYPE_BCMA: 221 case BHND_CHIPTYPE_BCMA_ALT: 222 enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); 223 break; 224 default: 225 device_printf(dev, "unsupported chip type %hhu\n", chip_type); 226 error = ENODEV; 227 goto failed; 228 } 229 230 sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); 231 232 /* Fetch and parse capability register(s) */ 233 if ((error = chipc_read_caps(sc, &sc->caps))) 234 goto failed; 235 236 if (bootverbose) 237 chipc_print_caps(sc->dev, &sc->caps); 238 239 /* Identify NVRAM source */ 240 sc->nvram_src = chipc_nvram_identify(sc); 241 242 /* Probe and attach children */ 243 bus_generic_probe(dev); 244 if ((error = bus_generic_attach(dev))) 245 goto failed; 246 247 return (0); 248 249failed: 250 if (sc->core_region != NULL) { 251 chipc_release_region(sc, sc->core_region, 252 RF_ALLOCATED|RF_ACTIVE); 253 } 254 255 chipc_free_rman(sc); 256 CHIPC_LOCK_DESTROY(sc); 257 return (error); 258} 259 260static int 261chipc_detach(device_t dev) 262{ 263 struct chipc_softc *sc; 264 int error; 265 266 sc = device_get_softc(dev); 267 268 if ((error = bus_generic_detach(dev))) 269 return (error); 270 271 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 272 chipc_free_rman(sc); 273 274 CHIPC_LOCK_DESTROY(sc); 275 276 return (0); 277} 278 279/* Read and parse chipc capabilities */ 280static int 281chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 282{ 283 uint32_t cap_reg; 284 uint32_t cap_ext_reg; 285 uint32_t regval; 286 287 /* Fetch cap registers */ 288 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 289 cap_ext_reg = 0; 290 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 291 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 292 293 /* Extract values */ 294 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 295 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 296 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 297 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 298 299 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 300 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 301 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 302 303 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 304 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 305 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 306 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 307 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 308 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 309 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 310 311 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 312 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 313 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 314 315 /* Fetch OTP size for later IPX controller revisions */ 316 if (CHIPC_QUIRK(sc, IPX_OTPLAYOUT_SIZE)) { 317 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 318 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 319 } 320 321 /* Determine flash type and parameters */ 322 caps->cfi_width = 0; 323 324 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 325 case CHIPC_CAP_SFLASH_ST: 326 caps->flash_type = CHIPC_SFLASH_ST; 327 break; 328 case CHIPC_CAP_SFLASH_AT: 329 caps->flash_type = CHIPC_SFLASH_AT; 330 break; 331 case CHIPC_CAP_NFLASH: 332 caps->flash_type = CHIPC_NFLASH; 333 break; 334 case CHIPC_CAP_PFLASH: 335 caps->flash_type = CHIPC_PFLASH_CFI; 336 337 /* determine cfi width */ 338 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 339 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 340 caps->cfi_width = 2; 341 else 342 caps->cfi_width = 1; 343 344 break; 345 case CHIPC_CAP_FLASH_NONE: 346 caps->flash_type = CHIPC_FLASH_NONE; 347 break; 348 349 } 350 351 /* Handle 4706_NFLASH fallback */ 352 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 353 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 354 { 355 caps->flash_type = CHIPC_NFLASH_4706; 356 } 357 358 return (0); 359} 360 361/** 362 * Determine the NVRAM data source for this device. 363 * 364 * @param sc chipc driver state. 365 */ 366static bhnd_nvram_src_t 367chipc_nvram_identify(struct chipc_softc *sc) 368{ 369 uint32_t srom_ctrl; 370 371 /* Very early devices vend SPROM/OTP/CIS (if at all) via the 372 * host bridge interface instead of ChipCommon. */ 373 if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 374 return (BHND_NVRAM_SRC_UNKNOWN); 375 376 /* 377 * Later chipset revisions standardized the SPROM capability flags and 378 * register interfaces. 379 * 380 * We check for hardware presence in order of precedence. For example, 381 * SPROM is is always used in preference to internal OTP if found. 382 */ 383 if (CHIPC_CAP(sc, sprom)) { 384 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 385 if (srom_ctrl & CHIPC_SRC_PRESENT) 386 return (BHND_NVRAM_SRC_SPROM); 387 } 388 389 /* Check for OTP */ 390 if (CHIPC_CAP(sc, otp_size) != 0) 391 return (BHND_NVRAM_SRC_OTP); 392 393 /* Check for flash */ 394 if (CHIPC_CAP(sc, flash_type) != CHIPC_FLASH_NONE) 395 return (BHND_NVRAM_SRC_FLASH); 396 397 /* No NVRAM hardware capability declared */ 398 return (BHND_NVRAM_SRC_UNKNOWN); 399} 400 401static int 402chipc_suspend(device_t dev) 403{ 404 return (bus_generic_suspend(dev)); 405} 406 407static int 408chipc_resume(device_t dev) 409{ 410 return (bus_generic_resume(dev)); 411} 412 413static void 414chipc_probe_nomatch(device_t dev, device_t child) 415{ 416 struct resource_list *rl; 417 const char *name; 418 419 name = device_get_name(child); 420 if (name == NULL) 421 name = "unknown device"; 422 423 device_printf(dev, "<%s> at", name); 424 425 rl = BUS_GET_RESOURCE_LIST(dev, child); 426 if (rl != NULL) { 427 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 428 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 429 } 430 431 printf(" (no driver attached)\n"); 432} 433 434static int 435chipc_print_child(device_t dev, device_t child) 436{ 437 struct resource_list *rl; 438 int retval = 0; 439 440 retval += bus_print_child_header(dev, child); 441 442 rl = BUS_GET_RESOURCE_LIST(dev, child); 443 if (rl != NULL) { 444 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 445 "%#jx"); 446 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 447 "%jd"); 448 } 449 450 retval += bus_print_child_domain(dev, child); 451 retval += bus_print_child_footer(dev, child); 452 453 return (retval); 454} 455 456static int 457chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 458 size_t buflen) 459{ 460 if (buflen == 0) 461 return (EOVERFLOW); 462 463 *buf = '\0'; 464 return (0); 465} 466 467static int 468chipc_child_location_str(device_t dev, device_t child, char *buf, 469 size_t buflen) 470{ 471 if (buflen == 0) 472 return (EOVERFLOW); 473 474 *buf = '\0'; 475 return (ENXIO); 476} 477 478static device_t 479chipc_add_child(device_t dev, u_int order, const char *name, int unit) 480{ 481 struct chipc_devinfo *dinfo; 482 const struct chipc_hint *hint; 483 device_t child; 484 devclass_t child_dc; 485 int error; 486 int busrel_unit; 487 488 child = device_add_child_ordered(dev, order, name, unit); 489 if (child == NULL) 490 return (NULL); 491 492 /* system-wide device unit */ 493 unit = device_get_unit(child); 494 child_dc = device_get_devclass(child); 495 496 busrel_unit = 0; 497 for (int i = 0; i < unit; i++) { 498 device_t tmp; 499 500 tmp = devclass_get_device(child_dc, i); 501 if (tmp != NULL && (device_get_parent(tmp) == dev)) 502 busrel_unit++; 503 } 504 505 /* bus-wide device unit (override unit for further hint matching) */ 506 unit = busrel_unit; 507 508 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 509 if (dinfo == NULL) { 510 device_delete_child(dev, child); 511 return (NULL); 512 } 513 514 resource_list_init(&dinfo->resources); 515 device_set_ivars(child, dinfo); 516 517 /* Hint matching requires a device name */ 518 if (name == NULL) 519 return (child); 520 521 /* Use hint table to set child resources */ 522 for (hint = chipc_hints; hint->name != NULL; hint++) { 523 bhnd_addr_t region_addr; 524 bhnd_size_t region_size; 525 526 /* Check device name */ 527 if (strcmp(hint->name, name) != 0) 528 continue; 529 530 /* Check device unit */ 531 if (hint->unit >= 0 && unit != hint->unit) 532 continue; 533 534 switch (hint->type) { 535 case SYS_RES_IRQ: 536 /* Add child resource */ 537 error = bus_set_resource(child, hint->type, hint->rid, 538 hint->base, hint->size); 539 if (error) { 540 device_printf(dev, 541 "bus_set_resource() failed for %s: %d\n", 542 device_get_nameunit(child), error); 543 goto failed; 544 } 545 break; 546 547 case SYS_RES_MEMORY: 548 /* Fetch region address and size */ 549 error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, 550 hint->port, hint->region, ®ion_addr, 551 ®ion_size); 552 if (error) { 553 device_printf(dev, 554 "lookup of %s%u.%u failed: %d\n", 555 bhnd_port_type_name(BHND_PORT_DEVICE), 556 hint->port, hint->region, error); 557 goto failed; 558 } 559 560 /* Verify requested range is mappable */ 561 if (hint->base > region_size || 562 (hint->size != RM_MAX_END && 563 (hint->size > region_size || 564 region_size - hint->base < hint->size ))) 565 { 566 device_printf(dev, 567 "%s%u.%u region cannot map requested range " 568 "%#jx+%#jx\n", 569 bhnd_port_type_name(BHND_PORT_DEVICE), 570 hint->port, hint->region, hint->base, 571 hint->size); 572 } 573 574 /* 575 * Add child resource. If hint doesn't define the end 576 * of resource window (RX_MAX_END), use end of region. 577 */ 578 579 error = bus_set_resource(child, 580 hint->type, 581 hint->rid, region_addr + hint->base, 582 (hint->size == RM_MAX_END) ? 583 region_size - hint->base : 584 hint->size); 585 if (error) { 586 device_printf(dev, 587 "bus_set_resource() failed for %s: %d\n", 588 device_get_nameunit(child), error); 589 goto failed; 590 } 591 break; 592 default: 593 device_printf(child, "unknown hint resource type: %d\n", 594 hint->type); 595 break; 596 } 597 } 598 599 return (child); 600 601failed: 602 device_delete_child(dev, child); 603 return (NULL); 604} 605 606static void 607chipc_child_deleted(device_t dev, device_t child) 608{ 609 struct chipc_devinfo *dinfo = device_get_ivars(child); 610 611 if (dinfo != NULL) { 612 resource_list_free(&dinfo->resources); 613 free(dinfo, M_BHND); 614 } 615 616 device_set_ivars(child, NULL); 617} 618 619static struct resource_list * 620chipc_get_resource_list(device_t dev, device_t child) 621{ 622 struct chipc_devinfo *dinfo = device_get_ivars(child); 623 return (&dinfo->resources); 624} 625 626 627/* Allocate region records for the given port, and add the port's memory 628 * range to the mem_rman */ 629static int 630chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 631 u_int port) 632{ 633 struct chipc_region *cr; 634 rman_res_t start, end; 635 u_int num_regions; 636 int error; 637 638 num_regions = bhnd_get_region_count(sc->dev, port, port); 639 for (u_int region = 0; region < num_regions; region++) { 640 /* Allocate new region record */ 641 cr = chipc_alloc_region(sc, type, port, region); 642 if (cr == NULL) 643 return (ENODEV); 644 645 /* Can't manage regions that cannot be allocated */ 646 if (cr->cr_rid < 0) { 647 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 648 "%s%u.%u", bhnd_port_type_name(type), port, region); 649 chipc_free_region(sc, cr); 650 continue; 651 } 652 653 /* Add to rman's managed range */ 654 start = cr->cr_addr; 655 end = cr->cr_end; 656 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 657 chipc_free_region(sc, cr); 658 return (error); 659 } 660 661 /* Add to region list */ 662 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 663 } 664 665 return (0); 666} 667 668/* Initialize memory state for all chipc port regions */ 669static int 670chipc_init_rman(struct chipc_softc *sc) 671{ 672 u_int num_ports; 673 int error; 674 675 /* Port types for which we'll register chipc_region mappings */ 676 bhnd_port_type types[] = { 677 BHND_PORT_DEVICE 678 }; 679 680 /* Initialize resource manager */ 681 sc->mem_rman.rm_start = 0; 682 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 683 sc->mem_rman.rm_type = RMAN_ARRAY; 684 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 685 if ((error = rman_init(&sc->mem_rman))) { 686 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 687 error); 688 return (error); 689 } 690 691 /* Populate per-port-region state */ 692 for (u_int i = 0; i < nitems(types); i++) { 693 num_ports = bhnd_get_port_count(sc->dev, types[i]); 694 for (u_int port = 0; port < num_ports; port++) { 695 error = chipc_rman_init_regions(sc, types[i], port); 696 if (error) { 697 device_printf(sc->dev, 698 "region init failed for %s%u: %d\n", 699 bhnd_port_type_name(types[i]), port, 700 error); 701 702 goto failed; 703 } 704 } 705 } 706 707 return (0); 708 709failed: 710 chipc_free_rman(sc); 711 return (error); 712} 713 714/* Free memory management state */ 715static void 716chipc_free_rman(struct chipc_softc *sc) 717{ 718 struct chipc_region *cr, *cr_next; 719 720 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 721 chipc_free_region(sc, cr); 722 723 rman_fini(&sc->mem_rman); 724} 725 726/** 727 * Return the rman instance for a given resource @p type, if any. 728 * 729 * @param sc The chipc device state. 730 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 731 */ 732static struct rman * 733chipc_get_rman(struct chipc_softc *sc, int type) 734{ 735 switch (type) { 736 case SYS_RES_MEMORY: 737 return (&sc->mem_rman); 738 739 case SYS_RES_IRQ: 740 /* IRQs can be used with RF_SHAREABLE, so we don't perform 741 * any local proxying of resource requests. */ 742 return (NULL); 743 744 default: 745 return (NULL); 746 }; 747} 748 749static struct resource * 750chipc_alloc_resource(device_t dev, device_t child, int type, 751 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 752{ 753 struct chipc_softc *sc; 754 struct chipc_region *cr; 755 struct resource_list_entry *rle; 756 struct resource *rv; 757 struct rman *rm; 758 int error; 759 bool passthrough, isdefault; 760 761 sc = device_get_softc(dev); 762 passthrough = (device_get_parent(child) != dev); 763 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 764 rle = NULL; 765 766 /* Fetch the resource manager, delegate request if necessary */ 767 rm = chipc_get_rman(sc, type); 768 if (rm == NULL) { 769 /* Requested resource type is delegated to our parent */ 770 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 771 start, end, count, flags); 772 return (rv); 773 } 774 775 /* Populate defaults */ 776 if (!passthrough && isdefault) { 777 /* Fetch the resource list entry. */ 778 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 779 type, *rid); 780 if (rle == NULL) { 781 device_printf(dev, 782 "default resource %#x type %d for child %s " 783 "not found\n", *rid, type, 784 device_get_nameunit(child)); 785 return (NULL); 786 } 787 788 if (rle->res != NULL) { 789 device_printf(dev, 790 "resource entry %#x type %d for child %s is busy " 791 "[%d]\n", 792 *rid, type, device_get_nameunit(child), 793 rman_get_flags(rle->res)); 794 795 return (NULL); 796 } 797 798 start = rle->start; 799 end = rle->end; 800 count = ulmax(count, rle->count); 801 } 802 803 /* Locate a mapping region */ 804 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 805 /* Resource requests outside our shared port regions can be 806 * delegated to our parent. */ 807 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 808 start, end, count, flags); 809 return (rv); 810 } 811 812 /* Try to retain a region reference */ 813 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) { 814 CHIPC_UNLOCK(sc); 815 return (NULL); 816 } 817 818 /* Make our rman reservation */ 819 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 820 child); 821 if (rv == NULL) { 822 chipc_release_region(sc, cr, RF_ALLOCATED); 823 return (NULL); 824 } 825 826 rman_set_rid(rv, *rid); 827 828 /* Activate */ 829 if (flags & RF_ACTIVE) { 830 error = bus_activate_resource(child, type, *rid, rv); 831 if (error) { 832 device_printf(dev, 833 "failed to activate entry %#x type %d for " 834 "child %s: %d\n", 835 *rid, type, device_get_nameunit(child), error); 836 837 chipc_release_region(sc, cr, RF_ALLOCATED); 838 rman_release_resource(rv); 839 840 return (NULL); 841 } 842 } 843 844 /* Update child's resource list entry */ 845 if (rle != NULL) { 846 rle->res = rv; 847 rle->start = rman_get_start(rv); 848 rle->end = rman_get_end(rv); 849 rle->count = rman_get_size(rv); 850 } 851 852 return (rv); 853} 854 855static int 856chipc_release_resource(device_t dev, device_t child, int type, int rid, 857 struct resource *r) 858{ 859 struct chipc_softc *sc; 860 struct chipc_region *cr; 861 struct rman *rm; 862 struct resource_list_entry *rle; 863 int error; 864 865 sc = device_get_softc(dev); 866 867 /* Handled by parent bus? */ 868 rm = chipc_get_rman(sc, type); 869 if (rm == NULL || !rman_is_region_manager(r, rm)) { 870 return (bus_generic_rl_release_resource(dev, child, type, rid, 871 r)); 872 } 873 874 /* Locate the mapping region */ 875 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 876 if (cr == NULL) 877 return (EINVAL); 878 879 /* Deactivate resources */ 880 if (rman_get_flags(r) & RF_ACTIVE) { 881 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 882 if (error) 883 return (error); 884 } 885 886 if ((error = rman_release_resource(r))) 887 return (error); 888 889 /* Drop allocation reference */ 890 chipc_release_region(sc, cr, RF_ALLOCATED); 891 892 /* Clear reference from the resource list entry if exists */ 893 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 894 if (rle != NULL) 895 rle->res = NULL; 896 897 return (0); 898} 899 900static int 901chipc_adjust_resource(device_t dev, device_t child, int type, 902 struct resource *r, rman_res_t start, rman_res_t end) 903{ 904 struct chipc_softc *sc; 905 struct chipc_region *cr; 906 struct rman *rm; 907 908 sc = device_get_softc(dev); 909 910 /* Handled by parent bus? */ 911 rm = chipc_get_rman(sc, type); 912 if (rm == NULL || !rman_is_region_manager(r, rm)) { 913 return (bus_generic_adjust_resource(dev, child, type, r, start, 914 end)); 915 } 916 917 /* The range is limited to the existing region mapping */ 918 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 919 if (cr == NULL) 920 return (EINVAL); 921 922 if (end <= start) 923 return (EINVAL); 924 925 if (start < cr->cr_addr || end > cr->cr_end) 926 return (EINVAL); 927 928 /* Range falls within the existing region */ 929 return (rman_adjust_resource(r, start, end)); 930} 931 932/** 933 * Retain an RF_ACTIVE reference to the region mapping @p r, and 934 * configure @p r with its subregion values. 935 * 936 * @param sc Driver instance state. 937 * @param child Requesting child device. 938 * @param type resource type of @p r. 939 * @param rid resource id of @p r 940 * @param r resource to be activated. 941 * @param req_direct If true, failure to allocate a direct bhnd resource 942 * will be treated as an error. If false, the resource will not be marked 943 * as RF_ACTIVE if bhnd direct resource allocation fails. 944 */ 945static int 946chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 947 int rid, struct resource *r, bool req_direct) 948{ 949 struct rman *rm; 950 struct chipc_region *cr; 951 bhnd_size_t cr_offset; 952 rman_res_t r_start, r_end, r_size; 953 int error; 954 955 rm = chipc_get_rman(sc, type); 956 if (rm == NULL || !rman_is_region_manager(r, rm)) 957 return (EINVAL); 958 959 r_start = rman_get_start(r); 960 r_end = rman_get_end(r); 961 r_size = rman_get_size(r); 962 963 /* Find the corresponding chipc region */ 964 cr = chipc_find_region(sc, r_start, r_end); 965 if (cr == NULL) 966 return (EINVAL); 967 968 /* Calculate subregion offset within the chipc region */ 969 cr_offset = r_start - cr->cr_addr; 970 971 /* Retain (and activate, if necessary) the chipc region */ 972 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 973 return (error); 974 975 /* Configure child resource with its subregion values. */ 976 if (cr->cr_res->direct) { 977 error = chipc_init_child_resource(r, cr->cr_res->res, 978 cr_offset, r_size); 979 if (error) 980 goto cleanup; 981 982 /* Mark active */ 983 if ((error = rman_activate_resource(r))) 984 goto cleanup; 985 } else if (req_direct) { 986 error = ENOMEM; 987 goto cleanup; 988 } 989 990 return (0); 991 992cleanup: 993 chipc_release_region(sc, cr, RF_ACTIVE); 994 return (error); 995} 996 997static int 998chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 999 int rid, struct bhnd_resource *r) 1000{ 1001 struct chipc_softc *sc; 1002 struct rman *rm; 1003 int error; 1004 1005 sc = device_get_softc(dev); 1006 1007 /* Delegate non-locally managed resources to parent */ 1008 rm = chipc_get_rman(sc, type); 1009 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1010 return (bhnd_bus_generic_activate_resource(dev, child, type, 1011 rid, r)); 1012 } 1013 1014 /* Try activating the chipc region resource */ 1015 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1016 false); 1017 if (error) 1018 return (error); 1019 1020 /* Mark the child resource as direct according to the returned resource 1021 * state */ 1022 if (rman_get_flags(r->res) & RF_ACTIVE) 1023 r->direct = true; 1024 1025 return (0); 1026} 1027 1028static int 1029chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1030 struct resource *r) 1031{ 1032 struct chipc_softc *sc; 1033 struct rman *rm; 1034 1035 sc = device_get_softc(dev); 1036 1037 /* Delegate non-locally managed resources to parent */ 1038 rm = chipc_get_rman(sc, type); 1039 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1040 return (bus_generic_activate_resource(dev, child, type, rid, 1041 r)); 1042 } 1043 1044 /* Try activating the chipc region-based resource */ 1045 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1046} 1047 1048/** 1049 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1050 */ 1051static int 1052chipc_deactivate_resource(device_t dev, device_t child, int type, 1053 int rid, struct resource *r) 1054{ 1055 struct chipc_softc *sc; 1056 struct chipc_region *cr; 1057 struct rman *rm; 1058 int error; 1059 1060 sc = device_get_softc(dev); 1061 1062 /* Handled by parent bus? */ 1063 rm = chipc_get_rman(sc, type); 1064 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1065 return (bus_generic_deactivate_resource(dev, child, type, rid, 1066 r)); 1067 } 1068 1069 /* Find the corresponding chipc region */ 1070 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1071 if (cr == NULL) 1072 return (EINVAL); 1073 1074 /* Mark inactive */ 1075 if ((error = rman_deactivate_resource(r))) 1076 return (error); 1077 1078 /* Drop associated RF_ACTIVE reference */ 1079 chipc_release_region(sc, cr, RF_ACTIVE); 1080 1081 return (0); 1082} 1083 1084/** 1085 * Examine bus state and make a best effort determination of whether it's 1086 * likely safe to enable the muxed SPROM pins. 1087 * 1088 * On devices that do not use SPROM pin muxing, always returns true. 1089 * 1090 * @param sc chipc driver state. 1091 */ 1092static bool 1093chipc_should_enable_sprom(struct chipc_softc *sc) 1094{ 1095 device_t *devs; 1096 device_t hostb; 1097 device_t parent; 1098 int devcount; 1099 int error; 1100 bool result; 1101 1102 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1103 1104 /* Nothing to do? */ 1105 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1106 return (true); 1107 1108 parent = device_get_parent(sc->dev); 1109 hostb = bhnd_find_hostb_device(parent); 1110 1111 if ((error = device_get_children(parent, &devs, &devcount))) 1112 return (false); 1113 1114 /* Reject any active devices other than ChipCommon, or the 1115 * host bridge (if any). */ 1116 result = true; 1117 for (int i = 0; i < devcount; i++) { 1118 if (devs[i] == hostb || devs[i] == sc->dev) 1119 continue; 1120 1121 if (!device_is_attached(devs[i])) 1122 continue; 1123 1124 if (device_is_suspended(devs[i])) 1125 continue; 1126 1127 /* Active device; assume SPROM is busy */ 1128 result = false; 1129 break; 1130 } 1131 1132 free(devs, M_TEMP); 1133 return (result); 1134} 1135 1136/** 1137 * If required by this device, enable access to the SPROM. 1138 * 1139 * @param sc chipc driver state. 1140 */ 1141static int 1142chipc_enable_sprom_pins(device_t dev) 1143{ 1144 struct chipc_softc *sc; 1145 uint32_t cctrl; 1146 int error; 1147 1148 sc = device_get_softc(dev); 1149 1150 /* Nothing to do? */ 1151 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1152 return (0); 1153 1154 /* Make sure we're holding Giant for newbus */ 1155 mtx_lock(&Giant); 1156 CHIPC_LOCK(sc); 1157 1158 /* Already enabled? */ 1159 if (sc->sprom_refcnt >= 1) { 1160 error = 0; 1161 goto finished; 1162 } 1163 1164 /* Check whether bus is busy */ 1165 if (!chipc_should_enable_sprom(sc)) { 1166 error = EBUSY; 1167 goto finished; 1168 } 1169 1170 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1171 1172 /* 4331 devices */ 1173 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1174 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1175 1176 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1177 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1178 1179 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1180 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1181 1182 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1183 error = 0; 1184 goto finished; 1185 } 1186 1187 /* 4360 devices */ 1188 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1189 /* Unimplemented */ 1190 } 1191 1192 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1193 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1194 error = ENXIO; 1195 1196finished: 1197 /* Bump the reference count */ 1198 if (error == 0) 1199 sc->sprom_refcnt++; 1200 1201 CHIPC_UNLOCK(sc); 1202 mtx_unlock(&Giant); 1203 1204 return (error); 1205} 1206 1207/** 1208 * If required by this device, revert any GPIO/pin configuration applied 1209 * to allow SPROM access. 1210 * 1211 * @param sc chipc driver state. 1212 */ 1213static void 1214chipc_disable_sprom_pins(device_t dev) 1215{ 1216 struct chipc_softc *sc; 1217 uint32_t cctrl; 1218 1219 sc = device_get_softc(dev); 1220 1221 /* Nothing to do? */ 1222 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1223 return; 1224 1225 CHIPC_LOCK(sc); 1226 1227 /* Check reference count, skip disable if in-use. */ 1228 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1229 sc->sprom_refcnt--; 1230 if (sc->sprom_refcnt > 0) 1231 goto finished; 1232 1233 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1234 1235 /* 4331 devices */ 1236 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1237 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1238 1239 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1240 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1241 1242 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1243 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1244 1245 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1246 goto finished; 1247 } 1248 1249 /* 4360 devices */ 1250 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1251 /* Unimplemented */ 1252 } 1253 1254finished: 1255 CHIPC_UNLOCK(sc); 1256} 1257 1258static bhnd_nvram_src_t 1259chipc_nvram_src(device_t dev) 1260{ 1261 struct chipc_softc *sc = device_get_softc(dev); 1262 return (sc->nvram_src); 1263} 1264 1265static void 1266chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1267{ 1268 struct chipc_softc *sc; 1269 uint32_t cctrl; 1270 1271 sc = device_get_softc(dev); 1272 1273 CHIPC_LOCK(sc); 1274 1275 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1276 cctrl = (cctrl & ~mask) | (value | mask); 1277 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1278 1279 CHIPC_UNLOCK(sc); 1280} 1281 1282static struct chipc_caps * 1283chipc_get_caps(device_t dev) 1284{ 1285 struct chipc_softc *sc; 1286 1287 sc = device_get_softc(dev); 1288 return (&sc->caps); 1289} 1290 1291static device_method_t chipc_methods[] = { 1292 /* Device interface */ 1293 DEVMETHOD(device_probe, chipc_probe), 1294 DEVMETHOD(device_attach, chipc_attach), 1295 DEVMETHOD(device_detach, chipc_detach), 1296 DEVMETHOD(device_suspend, chipc_suspend), 1297 DEVMETHOD(device_resume, chipc_resume), 1298 1299 /* Bus interface */ 1300 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1301 DEVMETHOD(bus_print_child, chipc_print_child), 1302 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1303 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1304 1305 DEVMETHOD(bus_add_child, chipc_add_child), 1306 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1307 1308 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1309 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1310 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1311 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1312 DEVMETHOD(bus_release_resource, chipc_release_resource), 1313 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1314 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1315 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1316 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1317 1318 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1319 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1320 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1321 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1322 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1323 1324 /* BHND bus inteface */ 1325 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1326 1327 /* ChipCommon interface */ 1328 DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), 1329 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1330 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1331 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1332 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1333 1334 DEVMETHOD_END 1335}; 1336 1337DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1338DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0); 1339MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1340MODULE_VERSION(bhnd_chipc, 1); 1341