chipc.c revision 300703
1/*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bhnd/cores/chipc/chipc.c 300703 2016-05-26 00:44:16Z adrian $"); 33 34/* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 41 * flash, etc. 42 */ 43 44#include <sys/param.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/bus.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/systm.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <dev/bhnd/bhnd.h> 58#include <dev/bhnd/bhndvar.h> 59 60#include "chipcreg.h" 61#include "chipcvar.h" 62#include "chipc_private.h" 63 64devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 65 66static struct bhnd_device_quirk chipc_quirks[]; 67 68/* Supported device identifiers */ 69static const struct bhnd_device chipc_devices[] = { 70 BHND_DEVICE(CC, NULL, chipc_quirks), 71 BHND_DEVICE_END 72}; 73 74 75/* Device quirks table */ 76static struct bhnd_device_quirk chipc_quirks[] = { 77 /* core revision quirks */ 78 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 79 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 80 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPLAYOUT_SIZE), 81 82 /* 4706 variant quirks */ 83 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 84 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 85 86 /* 4331 quirks*/ 87 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 88 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 89 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 90 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 91 92 /* 4360 quirks */ 93 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 94 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 95 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 96 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 97 98 BHND_DEVICE_QUIRK_END 99}; 100 101 102static const struct chipc_hint { 103 const char *name; 104 int unit; 105 int type; 106 int rid; 107 rman_res_t base; /* relative to parent resource */ 108 rman_res_t size; 109 u_int port; /* ignored if SYS_RES_IRQ */ 110 u_int region; 111} chipc_hints[] = { 112 // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs 113 /* device unit type rid base size port,region */ 114 { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, 115 { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, 116 { "uart", 0, SYS_RES_IRQ, 0, 0, RM_MAX_END }, 117 { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, 118 { "uart", 1, SYS_RES_IRQ, 0, 0, RM_MAX_END }, 119 { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, 120 { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 121 { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, 122 { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 123 { NULL } 124}; 125 126 127static int chipc_try_activate_resource( 128 struct chipc_softc *sc, device_t child, 129 int type, int rid, struct resource *r, 130 bool req_direct); 131 132static int chipc_read_caps(struct chipc_softc *sc, 133 struct chipc_caps *caps); 134 135static bhnd_nvram_src_t chipc_nvram_identify(struct chipc_softc *sc); 136static bool chipc_should_enable_sprom( 137 struct chipc_softc *sc); 138 139static int chipc_init_rman(struct chipc_softc *sc); 140static void chipc_free_rman(struct chipc_softc *sc); 141static struct rman *chipc_get_rman(struct chipc_softc *sc, 142 int type); 143 144/* quirk and capability flag convenience macros */ 145#define CHIPC_QUIRK(_sc, _name) \ 146 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 147 148#define CHIPC_CAP(_sc, _name) \ 149 ((_sc)->caps._name) 150 151#define CHIPC_ASSERT_QUIRK(_sc, name) \ 152 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 153 154#define CHIPC_ASSERT_CAP(_sc, name) \ 155 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 156 157static int 158chipc_probe(device_t dev) 159{ 160 const struct bhnd_device *id; 161 162 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 163 if (id == NULL) 164 return (ENXIO); 165 166 bhnd_set_default_core_desc(dev); 167 return (BUS_PROBE_DEFAULT); 168} 169 170static int 171chipc_attach(device_t dev) 172{ 173 struct chipc_softc *sc; 174 bhnd_addr_t enum_addr; 175 uint32_t ccid_reg; 176 uint8_t chip_type; 177 int error; 178 179 sc = device_get_softc(dev); 180 sc->dev = dev; 181 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 182 sizeof(chipc_devices[0])); 183 sc->sprom_refcnt = 0; 184 185 CHIPC_LOCK_INIT(sc); 186 STAILQ_INIT(&sc->mem_regions); 187 188 /* Set up resource management */ 189 if ((error = chipc_init_rman(sc))) { 190 device_printf(sc->dev, 191 "failed to initialize chipc resource state: %d\n", error); 192 goto failed; 193 } 194 195 /* Allocate the region containing our core registers */ 196 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 197 error = ENXIO; 198 goto failed; 199 } 200 201 error = chipc_retain_region(sc, sc->core_region, 202 RF_ALLOCATED|RF_ACTIVE); 203 if (error) { 204 sc->core_region = NULL; 205 goto failed; 206 } else { 207 sc->core = sc->core_region->cr_res; 208 } 209 210 /* Fetch our chipset identification data */ 211 ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); 212 chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); 213 214 switch (chip_type) { 215 case BHND_CHIPTYPE_SIBA: 216 /* enumeration space starts at the ChipCommon register base. */ 217 enum_addr = rman_get_start(sc->core->res); 218 break; 219 case BHND_CHIPTYPE_BCMA: 220 case BHND_CHIPTYPE_BCMA_ALT: 221 enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); 222 break; 223 default: 224 device_printf(dev, "unsupported chip type %hhu\n", chip_type); 225 error = ENODEV; 226 goto failed; 227 } 228 229 sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); 230 231 /* Fetch and parse capability register(s) */ 232 if ((error = chipc_read_caps(sc, &sc->caps))) 233 goto failed; 234 235 if (bootverbose) 236 chipc_print_caps(sc->dev, &sc->caps); 237 238 /* Identify NVRAM source */ 239 sc->nvram_src = chipc_nvram_identify(sc); 240 241 /* Probe and attach children */ 242 bus_generic_probe(dev); 243 if ((error = bus_generic_attach(dev))) 244 goto failed; 245 246 return (0); 247 248failed: 249 if (sc->core_region != NULL) { 250 chipc_release_region(sc, sc->core_region, 251 RF_ALLOCATED|RF_ACTIVE); 252 } 253 254 chipc_free_rman(sc); 255 CHIPC_LOCK_DESTROY(sc); 256 return (error); 257} 258 259static int 260chipc_detach(device_t dev) 261{ 262 struct chipc_softc *sc; 263 int error; 264 265 sc = device_get_softc(dev); 266 267 if ((error = bus_generic_detach(dev))) 268 return (error); 269 270 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 271 chipc_free_rman(sc); 272 273 CHIPC_LOCK_DESTROY(sc); 274 275 return (0); 276} 277 278/* Read and parse chipc capabilities */ 279static int 280chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 281{ 282 uint32_t cap_reg; 283 uint32_t cap_ext_reg; 284 uint32_t regval; 285 286 /* Fetch cap registers */ 287 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 288 cap_ext_reg = 0; 289 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 290 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 291 292 /* Extract values */ 293 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 294 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 295 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 296 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 297 298 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 299 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 300 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 301 302 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 303 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 304 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 305 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 306 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 307 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 308 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 309 310 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 311 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 312 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 313 314 /* Fetch OTP size for later IPX controller revisions */ 315 if (CHIPC_QUIRK(sc, IPX_OTPLAYOUT_SIZE)) { 316 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 317 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 318 } 319 320 /* Determine flash type and parameters */ 321 caps->cfi_width = 0; 322 323 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 324 case CHIPC_CAP_SFLASH_ST: 325 caps->flash_type = CHIPC_SFLASH_ST; 326 break; 327 case CHIPC_CAP_SFLASH_AT: 328 caps->flash_type = CHIPC_SFLASH_AT; 329 break; 330 case CHIPC_CAP_NFLASH: 331 caps->flash_type = CHIPC_NFLASH; 332 break; 333 case CHIPC_CAP_PFLASH: 334 caps->flash_type = CHIPC_PFLASH_CFI; 335 336 /* determine cfi width */ 337 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 338 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 339 caps->cfi_width = 2; 340 else 341 caps->cfi_width = 1; 342 343 break; 344 case CHIPC_CAP_FLASH_NONE: 345 caps->flash_type = CHIPC_FLASH_NONE; 346 break; 347 348 } 349 350 /* Handle 4706_NFLASH fallback */ 351 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 352 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 353 { 354 caps->flash_type = CHIPC_NFLASH_4706; 355 } 356 357 return (0); 358} 359 360/** 361 * Determine the NVRAM data source for this device. 362 * 363 * @param sc chipc driver state. 364 */ 365static bhnd_nvram_src_t 366chipc_nvram_identify(struct chipc_softc *sc) 367{ 368 uint32_t srom_ctrl; 369 370 /* Very early devices vend SPROM/OTP/CIS (if at all) via the 371 * host bridge interface instead of ChipCommon. */ 372 if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 373 return (BHND_NVRAM_SRC_UNKNOWN); 374 375 /* 376 * Later chipset revisions standardized the SPROM capability flags and 377 * register interfaces. 378 * 379 * We check for hardware presence in order of precedence. For example, 380 * SPROM is is always used in preference to internal OTP if found. 381 */ 382 if (CHIPC_CAP(sc, sprom)) { 383 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 384 if (srom_ctrl & CHIPC_SRC_PRESENT) 385 return (BHND_NVRAM_SRC_SPROM); 386 } 387 388 /* Check for OTP */ 389 if (CHIPC_CAP(sc, otp_size) != 0) 390 return (BHND_NVRAM_SRC_OTP); 391 392 /* Check for flash */ 393 if (CHIPC_CAP(sc, flash_type) != CHIPC_FLASH_NONE) 394 return (BHND_NVRAM_SRC_FLASH); 395 396 /* No NVRAM hardware capability declared */ 397 return (BHND_NVRAM_SRC_UNKNOWN); 398} 399 400static int 401chipc_suspend(device_t dev) 402{ 403 return (bus_generic_suspend(dev)); 404} 405 406static int 407chipc_resume(device_t dev) 408{ 409 return (bus_generic_resume(dev)); 410} 411 412static void 413chipc_probe_nomatch(device_t dev, device_t child) 414{ 415 struct resource_list *rl; 416 const char *name; 417 418 name = device_get_name(child); 419 if (name == NULL) 420 name = "unknown device"; 421 422 device_printf(dev, "<%s> at", name); 423 424 rl = BUS_GET_RESOURCE_LIST(dev, child); 425 if (rl != NULL) { 426 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 427 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 428 } 429 430 printf(" (no driver attached)\n"); 431} 432 433static int 434chipc_print_child(device_t dev, device_t child) 435{ 436 struct resource_list *rl; 437 int retval = 0; 438 439 retval += bus_print_child_header(dev, child); 440 441 rl = BUS_GET_RESOURCE_LIST(dev, child); 442 if (rl != NULL) { 443 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 444 "%#jx"); 445 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 446 "%jd"); 447 } 448 449 retval += bus_print_child_domain(dev, child); 450 retval += bus_print_child_footer(dev, child); 451 452 return (retval); 453} 454 455static int 456chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 457 size_t buflen) 458{ 459 if (buflen == 0) 460 return (EOVERFLOW); 461 462 *buf = '\0'; 463 return (0); 464} 465 466static int 467chipc_child_location_str(device_t dev, device_t child, char *buf, 468 size_t buflen) 469{ 470 if (buflen == 0) 471 return (EOVERFLOW); 472 473 *buf = '\0'; 474 return (ENXIO); 475} 476 477static device_t 478chipc_add_child(device_t dev, u_int order, const char *name, int unit) 479{ 480 struct chipc_devinfo *dinfo; 481 const struct chipc_hint *hint; 482 device_t child; 483 int error; 484 485 child = device_add_child_ordered(dev, order, name, unit); 486 if (child == NULL) 487 return (NULL); 488 489 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 490 if (dinfo == NULL) { 491 device_delete_child(dev, child); 492 return (NULL); 493 } 494 495 resource_list_init(&dinfo->resources); 496 device_set_ivars(child, dinfo); 497 498 /* Hint matching requires a device name */ 499 if (name == NULL) 500 return (child); 501 502 /* Use hint table to set child resources */ 503 for (hint = chipc_hints; hint->name != NULL; hint++) { 504 bhnd_addr_t region_addr; 505 bhnd_size_t region_size; 506 507 if (strcmp(hint->name, name) != 0) 508 continue; 509 510 switch (hint->type) { 511 case SYS_RES_IRQ: 512 /* Add child resource */ 513 error = bus_set_resource(child, hint->type, hint->rid, 514 hint->base, hint->size); 515 if (error) { 516 device_printf(dev, 517 "bus_set_resource() failed for %s: %d\n", 518 device_get_nameunit(child), error); 519 goto failed; 520 } 521 break; 522 523 case SYS_RES_MEMORY: 524 /* Fetch region address and size */ 525 error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, 526 hint->port, hint->region, ®ion_addr, 527 ®ion_size); 528 if (error) { 529 device_printf(dev, 530 "lookup of %s%u.%u failed: %d\n", 531 bhnd_port_type_name(BHND_PORT_DEVICE), 532 hint->port, hint->region, error); 533 goto failed; 534 } 535 536 /* Verify requested range is mappable */ 537 if (hint->base > region_size || 538 hint->size > region_size || 539 region_size - hint->base < hint->size ) 540 { 541 device_printf(dev, 542 "%s%u.%u region cannot map requested range " 543 "%#jx+%#jx\n", 544 bhnd_port_type_name(BHND_PORT_DEVICE), 545 hint->port, hint->region, hint->base, 546 hint->size); 547 } 548 549 /* Add child resource */ 550 error = bus_set_resource(child, hint->type, 551 hint->rid, region_addr + hint->base, hint->size); 552 if (error) { 553 device_printf(dev, 554 "bus_set_resource() failed for %s: %d\n", 555 device_get_nameunit(child), error); 556 goto failed; 557 } 558 break; 559 default: 560 device_printf(child, "unknown hint resource type: %d\n", 561 hint->type); 562 break; 563 } 564 } 565 566 return (child); 567 568failed: 569 device_delete_child(dev, child); 570 return (NULL); 571} 572 573static void 574chipc_child_deleted(device_t dev, device_t child) 575{ 576 struct chipc_devinfo *dinfo = device_get_ivars(child); 577 578 if (dinfo != NULL) { 579 resource_list_free(&dinfo->resources); 580 free(dinfo, M_BHND); 581 } 582 583 device_set_ivars(child, NULL); 584} 585 586static struct resource_list * 587chipc_get_resource_list(device_t dev, device_t child) 588{ 589 struct chipc_devinfo *dinfo = device_get_ivars(child); 590 return (&dinfo->resources); 591} 592 593 594/* Allocate region records for the given port, and add the port's memory 595 * range to the mem_rman */ 596static int 597chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 598 u_int port) 599{ 600 struct chipc_region *cr; 601 rman_res_t start, end; 602 u_int num_regions; 603 int error; 604 605 num_regions = bhnd_get_region_count(sc->dev, port, port); 606 for (u_int region = 0; region < num_regions; region++) { 607 /* Allocate new region record */ 608 cr = chipc_alloc_region(sc, type, port, region); 609 if (cr == NULL) 610 return (ENODEV); 611 612 /* Can't manage regions that cannot be allocated */ 613 if (cr->cr_rid < 0) { 614 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 615 "%s%u.%u", bhnd_port_type_name(type), port, region); 616 chipc_free_region(sc, cr); 617 continue; 618 } 619 620 /* Add to rman's managed range */ 621 start = cr->cr_addr; 622 end = cr->cr_end; 623 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 624 chipc_free_region(sc, cr); 625 return (error); 626 } 627 628 /* Add to region list */ 629 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 630 } 631 632 return (0); 633} 634 635/* Initialize memory state for all chipc port regions */ 636static int 637chipc_init_rman(struct chipc_softc *sc) 638{ 639 u_int num_ports; 640 int error; 641 642 /* Port types for which we'll register chipc_region mappings */ 643 bhnd_port_type types[] = { 644 BHND_PORT_DEVICE 645 }; 646 647 /* Initialize resource manager */ 648 sc->mem_rman.rm_start = 0; 649 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 650 sc->mem_rman.rm_type = RMAN_ARRAY; 651 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 652 if ((error = rman_init(&sc->mem_rman))) { 653 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 654 error); 655 return (error); 656 } 657 658 /* Populate per-port-region state */ 659 for (u_int i = 0; i < nitems(types); i++) { 660 num_ports = bhnd_get_port_count(sc->dev, types[i]); 661 for (u_int port = 0; port < num_ports; port++) { 662 error = chipc_rman_init_regions(sc, types[i], port); 663 if (error) { 664 device_printf(sc->dev, 665 "region init failed for %s%u: %d\n", 666 bhnd_port_type_name(types[i]), port, 667 error); 668 669 goto failed; 670 } 671 } 672 } 673 674 return (0); 675 676failed: 677 chipc_free_rman(sc); 678 return (error); 679} 680 681/* Free memory management state */ 682static void 683chipc_free_rman(struct chipc_softc *sc) 684{ 685 struct chipc_region *cr, *cr_next; 686 687 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 688 chipc_free_region(sc, cr); 689 690 rman_fini(&sc->mem_rman); 691} 692 693/** 694 * Return the rman instance for a given resource @p type, if any. 695 * 696 * @param sc The chipc device state. 697 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 698 */ 699static struct rman * 700chipc_get_rman(struct chipc_softc *sc, int type) 701{ 702 switch (type) { 703 case SYS_RES_MEMORY: 704 return (&sc->mem_rman); 705 706 case SYS_RES_IRQ: 707 /* IRQs can be used with RF_SHAREABLE, so we don't perform 708 * any local proxying of resource requests. */ 709 return (NULL); 710 711 default: 712 return (NULL); 713 }; 714} 715 716static struct resource * 717chipc_alloc_resource(device_t dev, device_t child, int type, 718 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 719{ 720 struct chipc_softc *sc; 721 struct chipc_region *cr; 722 struct resource_list_entry *rle; 723 struct resource *rv; 724 struct rman *rm; 725 int error; 726 bool passthrough, isdefault; 727 728 sc = device_get_softc(dev); 729 passthrough = (device_get_parent(child) != dev); 730 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 731 rle = NULL; 732 733 /* Fetch the resource manager, delegate request if necessary */ 734 rm = chipc_get_rman(sc, type); 735 if (rm == NULL) { 736 /* Requested resource type is delegated to our parent */ 737 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 738 start, end, count, flags); 739 return (rv); 740 } 741 742 /* Populate defaults */ 743 if (!passthrough && isdefault) { 744 /* Fetch the resource list entry. */ 745 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 746 type, *rid); 747 if (rle == NULL) { 748 device_printf(dev, 749 "default resource %#x type %d for child %s " 750 "not found\n", *rid, type, 751 device_get_nameunit(child)); 752 return (NULL); 753 } 754 755 if (rle->res != NULL) { 756 device_printf(dev, 757 "resource entry %#x type %d for child %s is busy\n", 758 *rid, type, device_get_nameunit(child)); 759 760 return (NULL); 761 } 762 763 start = rle->start; 764 end = rle->end; 765 count = ulmax(count, rle->count); 766 } 767 768 /* Locate a mapping region */ 769 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 770 /* Resource requests outside our shared port regions can be 771 * delegated to our parent. */ 772 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 773 start, end, count, flags); 774 return (rv); 775 } 776 777 /* Try to retain a region reference */ 778 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) { 779 CHIPC_UNLOCK(sc); 780 return (NULL); 781 } 782 783 /* Make our rman reservation */ 784 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 785 child); 786 if (rv == NULL) { 787 chipc_release_region(sc, cr, RF_ALLOCATED); 788 return (NULL); 789 } 790 791 rman_set_rid(rv, *rid); 792 793 /* Activate */ 794 if (flags & RF_ACTIVE) { 795 error = bus_activate_resource(child, type, *rid, rv); 796 if (error) { 797 device_printf(dev, 798 "failed to activate entry %#x type %d for " 799 "child %s: %d\n", 800 *rid, type, device_get_nameunit(child), error); 801 802 chipc_release_region(sc, cr, RF_ALLOCATED); 803 rman_release_resource(rv); 804 805 return (NULL); 806 } 807 } 808 809 /* Update child's resource list entry */ 810 if (rle != NULL) { 811 rle->res = rv; 812 rle->start = rman_get_start(rv); 813 rle->end = rman_get_end(rv); 814 rle->count = rman_get_size(rv); 815 } 816 817 return (rv); 818} 819 820static int 821chipc_release_resource(device_t dev, device_t child, int type, int rid, 822 struct resource *r) 823{ 824 struct chipc_softc *sc; 825 struct chipc_region *cr; 826 struct rman *rm; 827 int error; 828 829 sc = device_get_softc(dev); 830 831 /* Handled by parent bus? */ 832 rm = chipc_get_rman(sc, type); 833 if (rm == NULL || !rman_is_region_manager(r, rm)) { 834 return (bus_generic_rl_release_resource(dev, child, type, rid, 835 r)); 836 } 837 838 /* Locate the mapping region */ 839 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 840 if (cr == NULL) 841 return (EINVAL); 842 843 /* Deactivate resources */ 844 if (rman_get_flags(r) & RF_ACTIVE) { 845 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 846 if (error) 847 return (error); 848 } 849 850 if ((error = rman_release_resource(r))) 851 return (error); 852 853 /* Drop allocation reference */ 854 chipc_release_region(sc, cr, RF_ALLOCATED); 855 856 return (0); 857} 858 859static int 860chipc_adjust_resource(device_t dev, device_t child, int type, 861 struct resource *r, rman_res_t start, rman_res_t end) 862{ 863 struct chipc_softc *sc; 864 struct chipc_region *cr; 865 struct rman *rm; 866 867 sc = device_get_softc(dev); 868 869 /* Handled by parent bus? */ 870 rm = chipc_get_rman(sc, type); 871 if (rm == NULL || !rman_is_region_manager(r, rm)) { 872 return (bus_generic_adjust_resource(dev, child, type, r, start, 873 end)); 874 } 875 876 /* The range is limited to the existing region mapping */ 877 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 878 if (cr == NULL) 879 return (EINVAL); 880 881 if (end <= start) 882 return (EINVAL); 883 884 if (start < cr->cr_addr || end > cr->cr_end) 885 return (EINVAL); 886 887 /* Range falls within the existing region */ 888 return (rman_adjust_resource(r, start, end)); 889} 890 891/** 892 * Retain an RF_ACTIVE reference to the region mapping @p r, and 893 * configure @p r with its subregion values. 894 * 895 * @param sc Driver instance state. 896 * @param child Requesting child device. 897 * @param type resource type of @p r. 898 * @param rid resource id of @p r 899 * @param r resource to be activated. 900 * @param req_direct If true, failure to allocate a direct bhnd resource 901 * will be treated as an error. If false, the resource will not be marked 902 * as RF_ACTIVE if bhnd direct resource allocation fails. 903 */ 904static int 905chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 906 int rid, struct resource *r, bool req_direct) 907{ 908 struct rman *rm; 909 struct chipc_region *cr; 910 bhnd_size_t cr_offset; 911 rman_res_t r_start, r_end, r_size; 912 int error; 913 914 rm = chipc_get_rman(sc, type); 915 if (rm == NULL || !rman_is_region_manager(r, rm)) 916 return (EINVAL); 917 918 r_start = rman_get_start(r); 919 r_end = rman_get_end(r); 920 r_size = rman_get_size(r); 921 922 /* Find the corresponding chipc region */ 923 cr = chipc_find_region(sc, r_start, r_end); 924 if (cr == NULL) 925 return (EINVAL); 926 927 /* Calculate subregion offset within the chipc region */ 928 cr_offset = r_start - cr->cr_addr; 929 930 /* Retain (and activate, if necessary) the chipc region */ 931 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 932 return (error); 933 934 /* Configure child resource with its subregion values. */ 935 if (cr->cr_res->direct) { 936 error = chipc_init_child_resource(r, cr->cr_res->res, 937 cr_offset, r_size); 938 if (error) 939 goto cleanup; 940 941 /* Mark active */ 942 if ((error = rman_activate_resource(r))) 943 goto cleanup; 944 } else if (req_direct) { 945 error = ENOMEM; 946 goto cleanup; 947 } 948 949 return (0); 950 951cleanup: 952 chipc_release_region(sc, cr, RF_ACTIVE); 953 return (error); 954} 955 956static int 957chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 958 int rid, struct bhnd_resource *r) 959{ 960 struct chipc_softc *sc; 961 struct rman *rm; 962 int error; 963 964 sc = device_get_softc(dev); 965 966 /* Delegate non-locally managed resources to parent */ 967 rm = chipc_get_rman(sc, type); 968 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 969 return (bhnd_bus_generic_activate_resource(dev, child, type, 970 rid, r)); 971 } 972 973 /* Try activating the chipc region resource */ 974 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 975 false); 976 if (error) 977 return (error); 978 979 /* Mark the child resource as direct according to the returned resource 980 * state */ 981 if (rman_get_flags(r->res) & RF_ACTIVE) 982 r->direct = true; 983 984 return (0); 985} 986 987static int 988chipc_activate_resource(device_t dev, device_t child, int type, int rid, 989 struct resource *r) 990{ 991 struct chipc_softc *sc; 992 struct rman *rm; 993 994 sc = device_get_softc(dev); 995 996 /* Delegate non-locally managed resources to parent */ 997 rm = chipc_get_rman(sc, type); 998 if (rm == NULL || !rman_is_region_manager(r, rm)) { 999 return (bus_generic_activate_resource(dev, child, type, rid, 1000 r)); 1001 } 1002 1003 /* Try activating the chipc region-based resource */ 1004 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1005} 1006 1007/** 1008 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1009 */ 1010static int 1011chipc_deactivate_resource(device_t dev, device_t child, int type, 1012 int rid, struct resource *r) 1013{ 1014 struct chipc_softc *sc; 1015 struct chipc_region *cr; 1016 struct rman *rm; 1017 int error; 1018 1019 sc = device_get_softc(dev); 1020 1021 /* Handled by parent bus? */ 1022 rm = chipc_get_rman(sc, type); 1023 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1024 return (bus_generic_deactivate_resource(dev, child, type, rid, 1025 r)); 1026 } 1027 1028 /* Find the corresponding chipc region */ 1029 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1030 if (cr == NULL) 1031 return (EINVAL); 1032 1033 /* Mark inactive */ 1034 if ((error = rman_deactivate_resource(r))) 1035 return (error); 1036 1037 /* Drop associated RF_ACTIVE reference */ 1038 chipc_release_region(sc, cr, RF_ACTIVE); 1039 1040 return (0); 1041} 1042 1043/** 1044 * Examine bus state and make a best effort determination of whether it's 1045 * likely safe to enable the muxed SPROM pins. 1046 * 1047 * On devices that do not use SPROM pin muxing, always returns true. 1048 * 1049 * @param sc chipc driver state. 1050 */ 1051static bool 1052chipc_should_enable_sprom(struct chipc_softc *sc) 1053{ 1054 device_t *devs; 1055 device_t hostb; 1056 device_t parent; 1057 int devcount; 1058 int error; 1059 bool result; 1060 1061 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1062 1063 /* Nothing to do? */ 1064 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1065 return (true); 1066 1067 parent = device_get_parent(sc->dev); 1068 hostb = bhnd_find_hostb_device(parent); 1069 1070 if ((error = device_get_children(parent, &devs, &devcount))) 1071 return (false); 1072 1073 /* Reject any active devices other than ChipCommon, or the 1074 * host bridge (if any). */ 1075 result = true; 1076 for (int i = 0; i < devcount; i++) { 1077 if (devs[i] == hostb || devs[i] == sc->dev) 1078 continue; 1079 1080 if (!device_is_attached(devs[i])) 1081 continue; 1082 1083 if (device_is_suspended(devs[i])) 1084 continue; 1085 1086 /* Active device; assume SPROM is busy */ 1087 result = false; 1088 break; 1089 } 1090 1091 free(devs, M_TEMP); 1092 return (result); 1093} 1094 1095/** 1096 * If required by this device, enable access to the SPROM. 1097 * 1098 * @param sc chipc driver state. 1099 */ 1100static int 1101chipc_enable_sprom_pins(device_t dev) 1102{ 1103 struct chipc_softc *sc; 1104 uint32_t cctrl; 1105 int error; 1106 1107 sc = device_get_softc(dev); 1108 1109 /* Nothing to do? */ 1110 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1111 return (0); 1112 1113 /* Make sure we're holding Giant for newbus */ 1114 mtx_lock(&Giant); 1115 CHIPC_LOCK(sc); 1116 1117 /* Already enabled? */ 1118 if (sc->sprom_refcnt >= 1) { 1119 error = 0; 1120 goto finished; 1121 } 1122 1123 /* Check whether bus is busy */ 1124 if (!chipc_should_enable_sprom(sc)) { 1125 error = EBUSY; 1126 goto finished; 1127 } 1128 1129 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1130 1131 /* 4331 devices */ 1132 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1133 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1134 1135 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1136 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1137 1138 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1139 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1140 1141 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1142 error = 0; 1143 goto finished; 1144 } 1145 1146 /* 4360 devices */ 1147 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1148 /* Unimplemented */ 1149 } 1150 1151 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1152 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1153 error = ENXIO; 1154 1155finished: 1156 /* Bump the reference count */ 1157 if (error == 0) 1158 sc->sprom_refcnt++; 1159 1160 CHIPC_UNLOCK(sc); 1161 mtx_unlock(&Giant); 1162 1163 return (error); 1164} 1165 1166/** 1167 * If required by this device, revert any GPIO/pin configuration applied 1168 * to allow SPROM access. 1169 * 1170 * @param sc chipc driver state. 1171 */ 1172static void 1173chipc_disable_sprom_pins(device_t dev) 1174{ 1175 struct chipc_softc *sc; 1176 uint32_t cctrl; 1177 1178 sc = device_get_softc(dev); 1179 1180 /* Nothing to do? */ 1181 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1182 return; 1183 1184 CHIPC_LOCK(sc); 1185 1186 /* Check reference count, skip disable if in-use. */ 1187 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1188 sc->sprom_refcnt--; 1189 if (sc->sprom_refcnt > 0) 1190 goto finished; 1191 1192 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1193 1194 /* 4331 devices */ 1195 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1196 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1197 1198 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1199 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1200 1201 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1202 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1203 1204 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1205 goto finished; 1206 } 1207 1208 /* 4360 devices */ 1209 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1210 /* Unimplemented */ 1211 } 1212 1213finished: 1214 CHIPC_UNLOCK(sc); 1215} 1216 1217static bhnd_nvram_src_t 1218chipc_nvram_src(device_t dev) 1219{ 1220 struct chipc_softc *sc = device_get_softc(dev); 1221 return (sc->nvram_src); 1222} 1223 1224static void 1225chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1226{ 1227 struct chipc_softc *sc; 1228 uint32_t cctrl; 1229 1230 sc = device_get_softc(dev); 1231 1232 CHIPC_LOCK(sc); 1233 1234 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1235 cctrl = (cctrl & ~mask) | (value | mask); 1236 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1237 1238 CHIPC_UNLOCK(sc); 1239} 1240 1241static device_method_t chipc_methods[] = { 1242 /* Device interface */ 1243 DEVMETHOD(device_probe, chipc_probe), 1244 DEVMETHOD(device_attach, chipc_attach), 1245 DEVMETHOD(device_detach, chipc_detach), 1246 DEVMETHOD(device_suspend, chipc_suspend), 1247 DEVMETHOD(device_resume, chipc_resume), 1248 1249 /* Bus interface */ 1250 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1251 DEVMETHOD(bus_print_child, chipc_print_child), 1252 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1253 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1254 1255 DEVMETHOD(bus_add_child, chipc_add_child), 1256 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1257 1258 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1259 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1260 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1261 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1262 DEVMETHOD(bus_release_resource, chipc_release_resource), 1263 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1264 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1265 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1266 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1267 1268 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1269 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1270 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1271 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1272 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1273 1274 /* BHND bus inteface */ 1275 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1276 1277 /* ChipCommon interface */ 1278 DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), 1279 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1280 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1281 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1282 1283 DEVMETHOD_END 1284}; 1285 1286DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1287DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0); 1288MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1289MODULE_VERSION(bhnd_chipc, 1); 1290