chipc.c revision 300702
1/*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/bhnd/cores/chipc/chipc.c 300702 2016-05-26 00:43:08Z adrian $"); 33 34/* 35 * Broadcom ChipCommon driver. 36 * 37 * With the exception of some very early chipsets, the ChipCommon core 38 * has been included in all HND SoCs and chipsets based on the siba(4) 39 * and bcma(4) interconnects, providing a common interface to chipset 40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, 41 * flash, etc. 42 */ 43 44#include <sys/param.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/bus.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/systm.h> 52 53#include <machine/bus.h> 54#include <sys/rman.h> 55#include <machine/resource.h> 56 57#include <dev/bhnd/bhnd.h> 58#include <dev/bhnd/bhndvar.h> 59 60#include "chipcreg.h" 61#include "chipcvar.h" 62#include "chipc_private.h" 63 64devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 65 66static struct bhnd_device_quirk chipc_quirks[]; 67 68/* Supported device identifiers */ 69static const struct bhnd_device chipc_devices[] = { 70 BHND_DEVICE(CC, NULL, chipc_quirks), 71 BHND_DEVICE_END 72}; 73 74 75/* Device quirks table */ 76static struct bhnd_device_quirk chipc_quirks[] = { 77 /* core revision quirks */ 78 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 79 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 80 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPLAYOUT_SIZE), 81 82 /* 4706 variant quirks */ 83 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 84 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 85 86 /* 4331 quirks*/ 87 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 88 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 89 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 90 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 91 92 /* 4360 quirks */ 93 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 94 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 95 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 96 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 97 98 BHND_DEVICE_QUIRK_END 99}; 100 101 102static const struct chipc_hint { 103 const char *name; 104 int unit; 105 int type; 106 int rid; 107 rman_res_t base; /* relative to parent resource */ 108 rman_res_t size; 109 u_int port; /* ignored if SYS_RES_IRQ */ 110 u_int region; 111} chipc_hints[] = { 112 // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs 113 /* device unit type rid base size port,region */ 114 { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, 115 { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, 116 { "uart", 0, SYS_RES_IRQ, 0, 0, RM_MAX_END }, 117 { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, 118 { "uart", 1, SYS_RES_IRQ, 0, 0, RM_MAX_END }, 119 { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, 120 { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 121 { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, 122 { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, 123 { NULL } 124}; 125 126 127static int chipc_try_activate_resource( 128 struct chipc_softc *sc, device_t child, 129 int type, int rid, struct resource *r, 130 bool req_direct); 131 132static int chipc_read_caps(struct chipc_softc *sc, 133 struct chipc_caps *caps); 134 135static bhnd_nvram_src_t chipc_nvram_identify(struct chipc_softc *sc); 136static bool chipc_should_enable_sprom( 137 struct chipc_softc *sc); 138 139static int chipc_init_rman(struct chipc_softc *sc); 140static void chipc_free_rman(struct chipc_softc *sc); 141static struct rman *chipc_get_rman(struct chipc_softc *sc, 142 int type); 143 144/* quirk and capability flag convenience macros */ 145#define CHIPC_QUIRK(_sc, _name) \ 146 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 147 148#define CHIPC_CAP(_sc, _name) \ 149 ((_sc)->caps._name) 150 151#define CHIPC_ASSERT_QUIRK(_sc, name) \ 152 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 153 154#define CHIPC_ASSERT_CAP(_sc, name) \ 155 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 156 157static int 158chipc_probe(device_t dev) 159{ 160 const struct bhnd_device *id; 161 162 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 163 if (id == NULL) 164 return (ENXIO); 165 166 bhnd_set_default_core_desc(dev); 167 return (BUS_PROBE_DEFAULT); 168} 169 170static int 171chipc_attach(device_t dev) 172{ 173 struct chipc_softc *sc; 174 bhnd_addr_t enum_addr; 175 uint32_t ccid_reg; 176 uint8_t chip_type; 177 int error; 178 179 sc = device_get_softc(dev); 180 sc->dev = dev; 181 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 182 sizeof(chipc_devices[0])); 183 sc->sprom_refcnt = 0; 184 185 CHIPC_LOCK_INIT(sc); 186 STAILQ_INIT(&sc->mem_regions); 187 188 /* Set up resource management */ 189 if ((error = chipc_init_rman(sc))) { 190 device_printf(sc->dev, 191 "failed to initialize chipc resource state: %d\n", error); 192 goto failed; 193 } 194 195 /* Allocate the region containing our core registers */ 196 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 197 error = ENXIO; 198 goto failed; 199 } 200 201 error = chipc_retain_region(sc, sc->core_region, 202 RF_ALLOCATED|RF_ACTIVE); 203 if (error) { 204 sc->core_region = NULL; 205 goto failed; 206 } else { 207 sc->core = sc->core_region->cr_res; 208 } 209 210 /* Fetch our chipset identification data */ 211 ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); 212 chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); 213 214 switch (chip_type) { 215 case BHND_CHIPTYPE_SIBA: 216 /* enumeration space starts at the ChipCommon register base. */ 217 enum_addr = rman_get_start(sc->core->res); 218 break; 219 case BHND_CHIPTYPE_BCMA: 220 case BHND_CHIPTYPE_BCMA_ALT: 221 enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); 222 break; 223 default: 224 device_printf(dev, "unsupported chip type %hhu\n", chip_type); 225 error = ENODEV; 226 goto failed; 227 } 228 229 sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); 230 231 /* Fetch and parse capability register(s) */ 232 if ((error = chipc_read_caps(sc, &sc->caps))) 233 goto failed; 234 235 if (bootverbose) 236 chipc_print_caps(sc->dev, &sc->caps); 237 238 /* Identify NVRAM source */ 239 sc->nvram_src = chipc_nvram_identify(sc); 240 241 /* Probe and attach children */ 242 bus_generic_probe(dev); 243 if ((error = bus_generic_attach(dev))) 244 goto failed; 245 246 return (0); 247 248failed: 249 if (sc->core_region != NULL) { 250 chipc_release_region(sc, sc->core_region, 251 RF_ALLOCATED|RF_ACTIVE); 252 } 253 254 chipc_free_rman(sc); 255 CHIPC_LOCK_DESTROY(sc); 256 return (error); 257} 258 259static int 260chipc_detach(device_t dev) 261{ 262 struct chipc_softc *sc; 263 int error; 264 265 sc = device_get_softc(dev); 266 267 if ((error = bus_generic_detach(dev))) 268 return (error); 269 270 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 271 chipc_free_rman(sc); 272 bhnd_sprom_fini(&sc->sprom); 273 274 CHIPC_LOCK_DESTROY(sc); 275 276 return (0); 277} 278 279/* Read and parse chipc capabilities */ 280static int 281chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 282{ 283 uint32_t cap_reg; 284 uint32_t cap_ext_reg; 285 uint32_t regval; 286 287 /* Fetch cap registers */ 288 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 289 cap_ext_reg = 0; 290 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 291 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 292 293 /* Extract values */ 294 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 295 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 296 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 297 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 298 299 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 300 caps->power_control = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 301 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 302 303 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 304 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 305 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 306 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 307 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 308 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 309 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 310 311 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 312 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 313 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 314 315 /* Fetch OTP size for later IPX controller revisions */ 316 if (CHIPC_QUIRK(sc, IPX_OTPLAYOUT_SIZE)) { 317 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 318 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 319 } 320 321 /* Determine flash type and parameters */ 322 caps->cfi_width = 0; 323 324 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 325 case CHIPC_CAP_SFLASH_ST: 326 caps->flash_type = CHIPC_SFLASH_ST; 327 break; 328 case CHIPC_CAP_SFLASH_AT: 329 caps->flash_type = CHIPC_SFLASH_AT; 330 break; 331 case CHIPC_CAP_NFLASH: 332 caps->flash_type = CHIPC_NFLASH; 333 break; 334 case CHIPC_CAP_PFLASH: 335 caps->flash_type = CHIPC_PFLASH_CFI; 336 337 /* determine cfi width */ 338 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 339 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 340 caps->cfi_width = 2; 341 else 342 caps->cfi_width = 1; 343 344 break; 345 case CHIPC_CAP_FLASH_NONE: 346 caps->flash_type = CHIPC_FLASH_NONE; 347 break; 348 349 } 350 351 /* Handle 4706_NFLASH fallback */ 352 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 353 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 354 { 355 caps->flash_type = CHIPC_NFLASH_4706; 356 } 357 358 return (0); 359} 360 361/** 362 * Determine the NVRAM data source for this device. 363 * 364 * @param sc chipc driver state. 365 */ 366static bhnd_nvram_src_t 367chipc_nvram_identify(struct chipc_softc *sc) 368{ 369 uint32_t srom_ctrl; 370 371 /* Very early devices vend SPROM/OTP/CIS (if at all) via the 372 * host bridge interface instead of ChipCommon. */ 373 if (!CHIPC_QUIRK(sc, SUPPORTS_SPROM)) 374 return (BHND_NVRAM_SRC_UNKNOWN); 375 376 /* 377 * Later chipset revisions standardized the SPROM capability flags and 378 * register interfaces. 379 * 380 * We check for hardware presence in order of precedence. For example, 381 * SPROM is is always used in preference to internal OTP if found. 382 */ 383 if (CHIPC_CAP(sc, sprom)) { 384 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 385 if (srom_ctrl & CHIPC_SRC_PRESENT) 386 return (BHND_NVRAM_SRC_SPROM); 387 } 388 389 /* Check for OTP */ 390 if (CHIPC_CAP(sc, otp_size) != 0) 391 return (BHND_NVRAM_SRC_OTP); 392 393 /* Check for flash */ 394 if (CHIPC_CAP(sc, flash_type) != CHIPC_FLASH_NONE) 395 return (BHND_NVRAM_SRC_FLASH); 396 397 /* No NVRAM hardware capability declared */ 398 return (BHND_NVRAM_SRC_UNKNOWN); 399} 400 401static int 402chipc_suspend(device_t dev) 403{ 404 return (bus_generic_suspend(dev)); 405} 406 407static int 408chipc_resume(device_t dev) 409{ 410 return (bus_generic_resume(dev)); 411} 412 413static void 414chipc_probe_nomatch(device_t dev, device_t child) 415{ 416 struct resource_list *rl; 417 const char *name; 418 419 name = device_get_name(child); 420 if (name == NULL) 421 name = "unknown device"; 422 423 device_printf(dev, "<%s> at", name); 424 425 rl = BUS_GET_RESOURCE_LIST(dev, child); 426 if (rl != NULL) { 427 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 428 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 429 } 430 431 printf(" (no driver attached)\n"); 432} 433 434static int 435chipc_print_child(device_t dev, device_t child) 436{ 437 struct resource_list *rl; 438 int retval = 0; 439 440 retval += bus_print_child_header(dev, child); 441 442 rl = BUS_GET_RESOURCE_LIST(dev, child); 443 if (rl != NULL) { 444 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 445 "%#jx"); 446 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 447 "%jd"); 448 } 449 450 retval += bus_print_child_domain(dev, child); 451 retval += bus_print_child_footer(dev, child); 452 453 return (retval); 454} 455 456static int 457chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 458 size_t buflen) 459{ 460 if (buflen == 0) 461 return (EOVERFLOW); 462 463 *buf = '\0'; 464 return (0); 465} 466 467static int 468chipc_child_location_str(device_t dev, device_t child, char *buf, 469 size_t buflen) 470{ 471 if (buflen == 0) 472 return (EOVERFLOW); 473 474 *buf = '\0'; 475 return (ENXIO); 476} 477 478static device_t 479chipc_add_child(device_t dev, u_int order, const char *name, int unit) 480{ 481 struct chipc_devinfo *dinfo; 482 const struct chipc_hint *hint; 483 device_t child; 484 int error; 485 486 child = device_add_child_ordered(dev, order, name, unit); 487 if (child == NULL) 488 return (NULL); 489 490 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 491 if (dinfo == NULL) { 492 device_delete_child(dev, child); 493 return (NULL); 494 } 495 496 resource_list_init(&dinfo->resources); 497 device_set_ivars(child, dinfo); 498 499 /* Hint matching requires a device name */ 500 if (name == NULL) 501 return (child); 502 503 /* Use hint table to set child resources */ 504 for (hint = chipc_hints; hint->name != NULL; hint++) { 505 bhnd_addr_t region_addr; 506 bhnd_size_t region_size; 507 508 if (strcmp(hint->name, name) != 0) 509 continue; 510 511 switch (hint->type) { 512 case SYS_RES_IRQ: 513 /* Add child resource */ 514 error = bus_set_resource(child, hint->type, hint->rid, 515 hint->base, hint->size); 516 if (error) { 517 device_printf(dev, 518 "bus_set_resource() failed for %s: %d\n", 519 device_get_nameunit(child), error); 520 goto failed; 521 } 522 break; 523 524 case SYS_RES_MEMORY: 525 /* Fetch region address and size */ 526 error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, 527 hint->port, hint->region, ®ion_addr, 528 ®ion_size); 529 if (error) { 530 device_printf(dev, 531 "lookup of %s%u.%u failed: %d\n", 532 bhnd_port_type_name(BHND_PORT_DEVICE), 533 hint->port, hint->region, error); 534 goto failed; 535 } 536 537 /* Verify requested range is mappable */ 538 if (hint->base > region_size || 539 hint->size > region_size || 540 region_size - hint->base < hint->size ) 541 { 542 device_printf(dev, 543 "%s%u.%u region cannot map requested range " 544 "%#jx+%#jx\n", 545 bhnd_port_type_name(BHND_PORT_DEVICE), 546 hint->port, hint->region, hint->base, 547 hint->size); 548 } 549 550 /* Add child resource */ 551 error = bus_set_resource(child, hint->type, 552 hint->rid, region_addr + hint->base, hint->size); 553 if (error) { 554 device_printf(dev, 555 "bus_set_resource() failed for %s: %d\n", 556 device_get_nameunit(child), error); 557 goto failed; 558 } 559 break; 560 default: 561 device_printf(child, "unknown hint resource type: %d\n", 562 hint->type); 563 break; 564 } 565 } 566 567 return (child); 568 569failed: 570 device_delete_child(dev, child); 571 return (NULL); 572} 573 574static void 575chipc_child_deleted(device_t dev, device_t child) 576{ 577 struct chipc_devinfo *dinfo = device_get_ivars(child); 578 579 if (dinfo != NULL) { 580 resource_list_free(&dinfo->resources); 581 free(dinfo, M_BHND); 582 } 583 584 device_set_ivars(child, NULL); 585} 586 587static struct resource_list * 588chipc_get_resource_list(device_t dev, device_t child) 589{ 590 struct chipc_devinfo *dinfo = device_get_ivars(child); 591 return (&dinfo->resources); 592} 593 594 595/* Allocate region records for the given port, and add the port's memory 596 * range to the mem_rman */ 597static int 598chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 599 u_int port) 600{ 601 struct chipc_region *cr; 602 rman_res_t start, end; 603 u_int num_regions; 604 int error; 605 606 num_regions = bhnd_get_region_count(sc->dev, port, port); 607 for (u_int region = 0; region < num_regions; region++) { 608 /* Allocate new region record */ 609 cr = chipc_alloc_region(sc, type, port, region); 610 if (cr == NULL) 611 return (ENODEV); 612 613 /* Can't manage regions that cannot be allocated */ 614 if (cr->cr_rid < 0) { 615 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 616 "%s%u.%u", bhnd_port_type_name(type), port, region); 617 chipc_free_region(sc, cr); 618 continue; 619 } 620 621 /* Add to rman's managed range */ 622 start = cr->cr_addr; 623 end = cr->cr_end; 624 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 625 chipc_free_region(sc, cr); 626 return (error); 627 } 628 629 /* Add to region list */ 630 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 631 } 632 633 return (0); 634} 635 636/* Initialize memory state for all chipc port regions */ 637static int 638chipc_init_rman(struct chipc_softc *sc) 639{ 640 u_int num_ports; 641 int error; 642 643 /* Port types for which we'll register chipc_region mappings */ 644 bhnd_port_type types[] = { 645 BHND_PORT_DEVICE 646 }; 647 648 /* Initialize resource manager */ 649 sc->mem_rman.rm_start = 0; 650 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 651 sc->mem_rman.rm_type = RMAN_ARRAY; 652 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 653 if ((error = rman_init(&sc->mem_rman))) { 654 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 655 error); 656 return (error); 657 } 658 659 /* Populate per-port-region state */ 660 for (u_int i = 0; i < nitems(types); i++) { 661 num_ports = bhnd_get_port_count(sc->dev, types[i]); 662 for (u_int port = 0; port < num_ports; port++) { 663 error = chipc_rman_init_regions(sc, types[i], port); 664 if (error) { 665 device_printf(sc->dev, 666 "region init failed for %s%u: %d\n", 667 bhnd_port_type_name(types[i]), port, 668 error); 669 670 goto failed; 671 } 672 } 673 } 674 675 return (0); 676 677failed: 678 chipc_free_rman(sc); 679 return (error); 680} 681 682/* Free memory management state */ 683static void 684chipc_free_rman(struct chipc_softc *sc) 685{ 686 struct chipc_region *cr, *cr_next; 687 688 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 689 chipc_free_region(sc, cr); 690 691 rman_fini(&sc->mem_rman); 692} 693 694/** 695 * Return the rman instance for a given resource @p type, if any. 696 * 697 * @param sc The chipc device state. 698 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 699 */ 700static struct rman * 701chipc_get_rman(struct chipc_softc *sc, int type) 702{ 703 switch (type) { 704 case SYS_RES_MEMORY: 705 return (&sc->mem_rman); 706 707 case SYS_RES_IRQ: 708 /* IRQs can be used with RF_SHAREABLE, so we don't perform 709 * any local proxying of resource requests. */ 710 return (NULL); 711 712 default: 713 return (NULL); 714 }; 715} 716 717static struct resource * 718chipc_alloc_resource(device_t dev, device_t child, int type, 719 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 720{ 721 struct chipc_softc *sc; 722 struct chipc_region *cr; 723 struct resource_list_entry *rle; 724 struct resource *rv; 725 struct rman *rm; 726 int error; 727 bool passthrough, isdefault; 728 729 sc = device_get_softc(dev); 730 passthrough = (device_get_parent(child) != dev); 731 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 732 rle = NULL; 733 734 /* Fetch the resource manager, delegate request if necessary */ 735 rm = chipc_get_rman(sc, type); 736 if (rm == NULL) { 737 /* Requested resource type is delegated to our parent */ 738 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 739 start, end, count, flags); 740 return (rv); 741 } 742 743 /* Populate defaults */ 744 if (!passthrough && isdefault) { 745 /* Fetch the resource list entry. */ 746 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 747 type, *rid); 748 if (rle == NULL) { 749 device_printf(dev, 750 "default resource %#x type %d for child %s " 751 "not found\n", *rid, type, 752 device_get_nameunit(child)); 753 return (NULL); 754 } 755 756 if (rle->res != NULL) { 757 device_printf(dev, 758 "resource entry %#x type %d for child %s is busy\n", 759 *rid, type, device_get_nameunit(child)); 760 761 return (NULL); 762 } 763 764 start = rle->start; 765 end = rle->end; 766 count = ulmax(count, rle->count); 767 } 768 769 /* Locate a mapping region */ 770 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 771 /* Resource requests outside our shared port regions can be 772 * delegated to our parent. */ 773 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 774 start, end, count, flags); 775 return (rv); 776 } 777 778 /* Try to retain a region reference */ 779 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) { 780 CHIPC_UNLOCK(sc); 781 return (NULL); 782 } 783 784 /* Make our rman reservation */ 785 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 786 child); 787 if (rv == NULL) { 788 chipc_release_region(sc, cr, RF_ALLOCATED); 789 return (NULL); 790 } 791 792 rman_set_rid(rv, *rid); 793 794 /* Activate */ 795 if (flags & RF_ACTIVE) { 796 error = bus_activate_resource(child, type, *rid, rv); 797 if (error) { 798 device_printf(dev, 799 "failed to activate entry %#x type %d for " 800 "child %s: %d\n", 801 *rid, type, device_get_nameunit(child), error); 802 803 chipc_release_region(sc, cr, RF_ALLOCATED); 804 rman_release_resource(rv); 805 806 return (NULL); 807 } 808 } 809 810 /* Update child's resource list entry */ 811 if (rle != NULL) { 812 rle->res = rv; 813 rle->start = rman_get_start(rv); 814 rle->end = rman_get_end(rv); 815 rle->count = rman_get_size(rv); 816 } 817 818 return (rv); 819} 820 821static int 822chipc_release_resource(device_t dev, device_t child, int type, int rid, 823 struct resource *r) 824{ 825 struct chipc_softc *sc; 826 struct chipc_region *cr; 827 struct rman *rm; 828 int error; 829 830 sc = device_get_softc(dev); 831 832 /* Handled by parent bus? */ 833 rm = chipc_get_rman(sc, type); 834 if (rm == NULL || !rman_is_region_manager(r, rm)) { 835 return (bus_generic_rl_release_resource(dev, child, type, rid, 836 r)); 837 } 838 839 /* Locate the mapping region */ 840 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 841 if (cr == NULL) 842 return (EINVAL); 843 844 /* Deactivate resources */ 845 if (rman_get_flags(r) & RF_ACTIVE) { 846 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 847 if (error) 848 return (error); 849 } 850 851 if ((error = rman_release_resource(r))) 852 return (error); 853 854 /* Drop allocation reference */ 855 chipc_release_region(sc, cr, RF_ALLOCATED); 856 857 return (0); 858} 859 860static int 861chipc_adjust_resource(device_t dev, device_t child, int type, 862 struct resource *r, rman_res_t start, rman_res_t end) 863{ 864 struct chipc_softc *sc; 865 struct chipc_region *cr; 866 struct rman *rm; 867 868 sc = device_get_softc(dev); 869 870 /* Handled by parent bus? */ 871 rm = chipc_get_rman(sc, type); 872 if (rm == NULL || !rman_is_region_manager(r, rm)) { 873 return (bus_generic_adjust_resource(dev, child, type, r, start, 874 end)); 875 } 876 877 /* The range is limited to the existing region mapping */ 878 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 879 if (cr == NULL) 880 return (EINVAL); 881 882 if (end <= start) 883 return (EINVAL); 884 885 if (start < cr->cr_addr || end > cr->cr_end) 886 return (EINVAL); 887 888 /* Range falls within the existing region */ 889 return (rman_adjust_resource(r, start, end)); 890} 891 892/** 893 * Retain an RF_ACTIVE reference to the region mapping @p r, and 894 * configure @p r with its subregion values. 895 * 896 * @param sc Driver instance state. 897 * @param child Requesting child device. 898 * @param type resource type of @p r. 899 * @param rid resource id of @p r 900 * @param r resource to be activated. 901 * @param req_direct If true, failure to allocate a direct bhnd resource 902 * will be treated as an error. If false, the resource will not be marked 903 * as RF_ACTIVE if bhnd direct resource allocation fails. 904 */ 905static int 906chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 907 int rid, struct resource *r, bool req_direct) 908{ 909 struct rman *rm; 910 struct chipc_region *cr; 911 bhnd_size_t cr_offset; 912 rman_res_t r_start, r_end, r_size; 913 int error; 914 915 rm = chipc_get_rman(sc, type); 916 if (rm == NULL || !rman_is_region_manager(r, rm)) 917 return (EINVAL); 918 919 r_start = rman_get_start(r); 920 r_end = rman_get_end(r); 921 r_size = rman_get_size(r); 922 923 /* Find the corresponding chipc region */ 924 cr = chipc_find_region(sc, r_start, r_end); 925 if (cr == NULL) 926 return (EINVAL); 927 928 /* Calculate subregion offset within the chipc region */ 929 cr_offset = r_start - cr->cr_addr; 930 931 /* Retain (and activate, if necessary) the chipc region */ 932 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 933 return (error); 934 935 /* Configure child resource with its subregion values. */ 936 if (cr->cr_res->direct) { 937 error = chipc_init_child_resource(r, cr->cr_res->res, 938 cr_offset, r_size); 939 if (error) 940 goto cleanup; 941 942 /* Mark active */ 943 if ((error = rman_activate_resource(r))) 944 goto cleanup; 945 } else if (req_direct) { 946 error = ENOMEM; 947 goto cleanup; 948 } 949 950 return (0); 951 952cleanup: 953 chipc_release_region(sc, cr, RF_ACTIVE); 954 return (error); 955} 956 957static int 958chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 959 int rid, struct bhnd_resource *r) 960{ 961 struct chipc_softc *sc; 962 struct rman *rm; 963 int error; 964 965 sc = device_get_softc(dev); 966 967 /* Delegate non-locally managed resources to parent */ 968 rm = chipc_get_rman(sc, type); 969 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 970 return (bhnd_bus_generic_activate_resource(dev, child, type, 971 rid, r)); 972 } 973 974 /* Try activating the chipc region resource */ 975 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 976 false); 977 if (error) 978 return (error); 979 980 /* Mark the child resource as direct according to the returned resource 981 * state */ 982 if (rman_get_flags(r->res) & RF_ACTIVE) 983 r->direct = true; 984 985 return (0); 986} 987 988static int 989chipc_activate_resource(device_t dev, device_t child, int type, int rid, 990 struct resource *r) 991{ 992 struct chipc_softc *sc; 993 struct rman *rm; 994 995 sc = device_get_softc(dev); 996 997 /* Delegate non-locally managed resources to parent */ 998 rm = chipc_get_rman(sc, type); 999 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1000 return (bus_generic_activate_resource(dev, child, type, rid, 1001 r)); 1002 } 1003 1004 /* Try activating the chipc region-based resource */ 1005 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1006} 1007 1008/** 1009 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1010 */ 1011static int 1012chipc_deactivate_resource(device_t dev, device_t child, int type, 1013 int rid, struct resource *r) 1014{ 1015 struct chipc_softc *sc; 1016 struct chipc_region *cr; 1017 struct rman *rm; 1018 int error; 1019 1020 sc = device_get_softc(dev); 1021 1022 /* Handled by parent bus? */ 1023 rm = chipc_get_rman(sc, type); 1024 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1025 return (bus_generic_deactivate_resource(dev, child, type, rid, 1026 r)); 1027 } 1028 1029 /* Find the corresponding chipc region */ 1030 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1031 if (cr == NULL) 1032 return (EINVAL); 1033 1034 /* Mark inactive */ 1035 if ((error = rman_deactivate_resource(r))) 1036 return (error); 1037 1038 /* Drop associated RF_ACTIVE reference */ 1039 chipc_release_region(sc, cr, RF_ACTIVE); 1040 1041 return (0); 1042} 1043 1044/** 1045 * Examine bus state and make a best effort determination of whether it's 1046 * likely safe to enable the muxed SPROM pins. 1047 * 1048 * On devices that do not use SPROM pin muxing, always returns true. 1049 * 1050 * @param sc chipc driver state. 1051 */ 1052static bool 1053chipc_should_enable_sprom(struct chipc_softc *sc) 1054{ 1055 device_t *devs; 1056 device_t hostb; 1057 device_t parent; 1058 int devcount; 1059 int error; 1060 bool result; 1061 1062 mtx_assert(&Giant, MA_OWNED); /* for newbus */ 1063 1064 /* Nothing to do? */ 1065 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1066 return (true); 1067 1068 parent = device_get_parent(sc->dev); 1069 hostb = bhnd_find_hostb_device(parent); 1070 1071 if ((error = device_get_children(parent, &devs, &devcount))) 1072 return (false); 1073 1074 /* Reject any active devices other than ChipCommon, or the 1075 * host bridge (if any). */ 1076 result = true; 1077 for (int i = 0; i < devcount; i++) { 1078 if (devs[i] == hostb || devs[i] == sc->dev) 1079 continue; 1080 1081 if (!device_is_attached(devs[i])) 1082 continue; 1083 1084 if (device_is_suspended(devs[i])) 1085 continue; 1086 1087 /* Active device; assume SPROM is busy */ 1088 result = false; 1089 break; 1090 } 1091 1092 free(devs, M_TEMP); 1093 return (result); 1094} 1095 1096/** 1097 * If required by this device, enable access to the SPROM. 1098 * 1099 * @param sc chipc driver state. 1100 */ 1101static int 1102chipc_enable_sprom_pins(device_t dev) 1103{ 1104 struct chipc_softc *sc; 1105 uint32_t cctrl; 1106 int error; 1107 1108 sc = device_get_softc(dev); 1109 1110 /* Nothing to do? */ 1111 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1112 return (0); 1113 1114 /* Make sure we're holding Giant for newbus */ 1115 mtx_lock(&Giant); 1116 CHIPC_LOCK(sc); 1117 1118 /* Already enabled? */ 1119 if (sc->sprom_refcnt >= 1) { 1120 error = 0; 1121 goto finished; 1122 } 1123 1124 /* Check whether bus is busy */ 1125 if (!chipc_should_enable_sprom(sc)) { 1126 error = EBUSY; 1127 goto finished; 1128 } 1129 1130 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1131 1132 /* 4331 devices */ 1133 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1134 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1135 1136 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1137 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1138 1139 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1140 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1141 1142 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1143 error = 0; 1144 goto finished; 1145 } 1146 1147 /* 4360 devices */ 1148 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1149 /* Unimplemented */ 1150 } 1151 1152 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1153 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1154 error = ENXIO; 1155 1156finished: 1157 /* Bump the reference count */ 1158 if (error == 0) 1159 sc->sprom_refcnt++; 1160 1161 CHIPC_UNLOCK(sc); 1162 mtx_unlock(&Giant); 1163 1164 return (error); 1165} 1166 1167/** 1168 * If required by this device, revert any GPIO/pin configuration applied 1169 * to allow SPROM access. 1170 * 1171 * @param sc chipc driver state. 1172 */ 1173static void 1174chipc_disable_sprom_pins(device_t dev) 1175{ 1176 struct chipc_softc *sc; 1177 uint32_t cctrl; 1178 1179 sc = device_get_softc(dev); 1180 1181 /* Nothing to do? */ 1182 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1183 return; 1184 1185 CHIPC_LOCK(sc); 1186 1187 /* Check reference count, skip disable if in-use. */ 1188 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1189 sc->sprom_refcnt--; 1190 if (sc->sprom_refcnt > 0) 1191 goto finished; 1192 1193 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1194 1195 /* 4331 devices */ 1196 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1197 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1198 1199 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1200 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1201 1202 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1203 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1204 1205 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1206 goto finished; 1207 } 1208 1209 /* 4360 devices */ 1210 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1211 /* Unimplemented */ 1212 } 1213 1214finished: 1215 CHIPC_UNLOCK(sc); 1216} 1217 1218static bhnd_nvram_src_t 1219chipc_nvram_src(device_t dev) 1220{ 1221 struct chipc_softc *sc = device_get_softc(dev); 1222 return (sc->nvram_src); 1223} 1224 1225static void 1226chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1227{ 1228 struct chipc_softc *sc; 1229 uint32_t cctrl; 1230 1231 sc = device_get_softc(dev); 1232 1233 CHIPC_LOCK(sc); 1234 1235 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1236 cctrl = (cctrl & ~mask) | (value | mask); 1237 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1238 1239 CHIPC_UNLOCK(sc); 1240} 1241 1242static device_method_t chipc_methods[] = { 1243 /* Device interface */ 1244 DEVMETHOD(device_probe, chipc_probe), 1245 DEVMETHOD(device_attach, chipc_attach), 1246 DEVMETHOD(device_detach, chipc_detach), 1247 DEVMETHOD(device_suspend, chipc_suspend), 1248 DEVMETHOD(device_resume, chipc_resume), 1249 1250 /* Bus interface */ 1251 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1252 DEVMETHOD(bus_print_child, chipc_print_child), 1253 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1254 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1255 1256 DEVMETHOD(bus_add_child, chipc_add_child), 1257 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1258 1259 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1260 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1261 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1262 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1263 DEVMETHOD(bus_release_resource, chipc_release_resource), 1264 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1265 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1266 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1267 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1268 1269 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1270 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1271 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1272 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1273 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1274 1275 /* BHND bus inteface */ 1276 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1277 1278 /* ChipCommon interface */ 1279 DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), 1280 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1281 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), 1282 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), 1283 1284 DEVMETHOD_END 1285}; 1286 1287DEFINE_CLASS_0(bhnd_chipc, chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1288DRIVER_MODULE(bhnd_chipc, bhnd, chipc_driver, bhnd_chipc_devclass, 0, 0); 1289MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1290MODULE_VERSION(bhnd_chipc, 1); 1291