if_athvar.h revision 242391
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 242391 2012-10-31 06:27:58Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <machine/atomic.h> 39 40#include <dev/ath/ath_hal/ah.h> 41#include <dev/ath/ath_hal/ah_desc.h> 42#include <net80211/ieee80211_radiotap.h> 43#include <dev/ath/if_athioctl.h> 44#include <dev/ath/if_athrate.h> 45 46#define ATH_TIMEOUT 1000 47 48/* 49 * There is a separate TX ath_buf pool for management frames. 50 * This ensures that management frames such as probe responses 51 * and BAR frames can be transmitted during periods of high 52 * TX activity. 53 */ 54#define ATH_MGMT_TXBUF 32 55 56/* 57 * 802.11n requires more TX and RX buffers to do AMPDU. 58 */ 59#ifdef ATH_ENABLE_11N 60#define ATH_TXBUF 512 61#define ATH_RXBUF 512 62#endif 63 64#ifndef ATH_RXBUF 65#define ATH_RXBUF 40 /* number of RX buffers */ 66#endif 67#ifndef ATH_TXBUF 68#define ATH_TXBUF 200 /* number of TX buffers */ 69#endif 70#define ATH_BCBUF 4 /* number of beacon buffers */ 71 72#define ATH_TXDESC 10 /* number of descriptors per buffer */ 73#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 74#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 75#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 76 77#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 78#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 79#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 80 81/* 82 * The key cache is used for h/w cipher state and also for 83 * tracking station state such as the current tx antenna. 84 * We also setup a mapping table between key cache slot indices 85 * and station state to short-circuit node lookups on rx. 86 * Different parts have different size key caches. We handle 87 * up to ATH_KEYMAX entries (could dynamically allocate state). 88 */ 89#define ATH_KEYMAX 128 /* max key cache size we handle */ 90#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 91 92struct taskqueue; 93struct kthread; 94struct ath_buf; 95 96#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 97 98/* 99 * Per-TID state 100 * 101 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 102 */ 103struct ath_tid { 104 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 105 u_int axq_depth; /* SW queue depth */ 106 char axq_name[48]; /* lock name */ 107 struct ath_node *an; /* pointer to parent */ 108 int tid; /* tid */ 109 int ac; /* which AC gets this trafic */ 110 int hwq_depth; /* how many buffers are on HW */ 111 112 struct { 113 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 114 u_int axq_depth; /* SW queue depth */ 115 char axq_name[48]; /* lock name */ 116 } filtq; 117 118 /* 119 * Entry on the ath_txq; when there's traffic 120 * to send 121 */ 122 TAILQ_ENTRY(ath_tid) axq_qelem; 123 int sched; 124 int paused; /* >0 if the TID has been paused */ 125 126 /* 127 * These are flags - perhaps later collapse 128 * down to a single uint32_t ? 129 */ 130 int addba_tx_pending; /* TX ADDBA pending */ 131 int bar_wait; /* waiting for BAR */ 132 int bar_tx; /* BAR TXed */ 133 int isfiltered; /* is this node currently filtered */ 134 int clrdmask; /* has clrdmask been set */ 135 136 /* 137 * Is the TID being cleaned up after a transition 138 * from aggregation to non-aggregation? 139 * When this is set to 1, this TID will be paused 140 * and no further traffic will be queued until all 141 * the hardware packets pending for this TID have been 142 * TXed/completed; at which point (non-aggregation) 143 * traffic will resume being TXed. 144 */ 145 int cleanup_inprogress; 146 /* 147 * How many hardware-queued packets are 148 * waiting to be cleaned up. 149 * This is only valid if cleanup_inprogress is 1. 150 */ 151 int incomp; 152 153 /* 154 * The following implements a ring representing 155 * the frames in the current BAW. 156 * To avoid copying the array content each time 157 * the BAW is moved, the baw_head/baw_tail point 158 * to the current BAW begin/end; when the BAW is 159 * shifted the head/tail of the array are also 160 * appropriately shifted. 161 */ 162 /* active tx buffers, beginning at current BAW */ 163 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 164 /* where the baw head is in the array */ 165 int baw_head; 166 /* where the BAW tail is in the array */ 167 int baw_tail; 168}; 169 170/* driver-specific node state */ 171struct ath_node { 172 struct ieee80211_node an_node; /* base class */ 173 u_int8_t an_mgmtrix; /* min h/w rate index */ 174 u_int8_t an_mcastrix; /* mcast h/w rate index */ 175 uint32_t an_is_powersave; /* node is sleeping */ 176 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 177 uint32_t an_tim_set; /* TIM has been set */ 178 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 179 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 180 char an_name[32]; /* eg "wlan0_a1" */ 181 struct mtx an_mtx; /* protecting the ath_node state */ 182 uint32_t an_swq_depth; /* how many SWQ packets for this 183 node */ 184 /* variable-length rate control state follows */ 185}; 186#define ATH_NODE(ni) ((struct ath_node *)(ni)) 187#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 188 189#define ATH_RSSI_LPF_LEN 10 190#define ATH_RSSI_DUMMY_MARKER 0x127 191#define ATH_EP_MUL(x, mul) ((x) * (mul)) 192#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 193#define ATH_LPF_RSSI(x, y, len) \ 194 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 195#define ATH_RSSI_LPF(x, y) do { \ 196 if ((y) >= -20) \ 197 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 198} while (0) 199#define ATH_EP_RND(x,mul) \ 200 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 201#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 202 203typedef enum { 204 ATH_BUFTYPE_NORMAL = 0, 205 ATH_BUFTYPE_MGMT = 1, 206} ath_buf_type_t; 207 208struct ath_buf { 209 TAILQ_ENTRY(ath_buf) bf_list; 210 struct ath_buf * bf_next; /* next buffer in the aggregate */ 211 int bf_nseg; 212 HAL_STATUS bf_rxstatus; 213 uint16_t bf_flags; /* status flags (below) */ 214 uint16_t bf_descid; /* 16 bit descriptor ID */ 215 struct ath_desc *bf_desc; /* virtual addr of desc */ 216 struct ath_desc_status bf_status; /* tx/rx status */ 217 bus_addr_t bf_daddr; /* physical addr of desc */ 218 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 219 struct mbuf *bf_m; /* mbuf for buf */ 220 struct ieee80211_node *bf_node; /* pointer to the node */ 221 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 222 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 223 bus_size_t bf_mapsize; 224#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 225 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 226 227 /* Completion function to call on TX complete (fail or not) */ 228 /* 229 * "fail" here is set to 1 if the queue entries were removed 230 * through a call to ath_tx_draintxq(). 231 */ 232 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 233 234 /* This state is kept to support software retries and aggregation */ 235 struct { 236 uint16_t bfs_seqno; /* sequence number of this packet */ 237 uint16_t bfs_ndelim; /* number of delims for padding */ 238 239 uint8_t bfs_retries; /* retry count */ 240 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 241 uint8_t bfs_nframes; /* number of frames in aggregate */ 242 uint8_t bfs_pri; /* packet AC priority */ 243 244 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 245 246 u_int32_t bfs_aggr:1, /* part of aggregate? */ 247 bfs_aggrburst:1, /* part of aggregate burst? */ 248 bfs_isretried:1, /* retried frame? */ 249 bfs_dobaw:1, /* actually check against BAW? */ 250 bfs_addedbaw:1, /* has been added to the BAW */ 251 bfs_shpream:1, /* use short preamble */ 252 bfs_istxfrag:1, /* is fragmented */ 253 bfs_ismrr:1, /* do multi-rate TX retry */ 254 bfs_doprot:1, /* do RTS/CTS based protection */ 255 bfs_doratelookup:1; /* do rate lookup before each TX */ 256 257 /* 258 * These fields are passed into the 259 * descriptor setup functions. 260 */ 261 262 /* Make this an 8 bit value? */ 263 HAL_PKT_TYPE bfs_atype; /* packet type */ 264 265 uint32_t bfs_pktlen; /* length of this packet */ 266 267 uint16_t bfs_hdrlen; /* length of this packet header */ 268 uint16_t bfs_al; /* length of aggregate */ 269 270 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 271 uint8_t bfs_txrate0; /* first TX rate */ 272 uint8_t bfs_try0; /* first try count */ 273 274 uint16_t bfs_txpower; /* tx power */ 275 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 276 uint8_t bfs_ctsrate; /* CTS rate */ 277 278 /* 16 bit? */ 279 int32_t bfs_keyix; /* crypto key index */ 280 int32_t bfs_txantenna; /* TX antenna config */ 281 282 /* Make this an 8 bit value? */ 283 enum ieee80211_protmode bfs_protmode; 284 285 /* 16 bit? */ 286 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 287 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 288 } bf_state; 289}; 290typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 291 292#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 293#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 294 295/* 296 * DMA state for tx/rx descriptors. 297 */ 298struct ath_descdma { 299 const char* dd_name; 300 struct ath_desc *dd_desc; /* descriptors */ 301 int dd_descsize; /* size of single descriptor */ 302 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 303 bus_size_t dd_desc_len; /* size of dd_desc */ 304 bus_dma_segment_t dd_dseg; 305 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 306 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 307 struct ath_buf *dd_bufptr; /* associated buffers */ 308}; 309 310/* 311 * Data transmit queue state. One of these exists for each 312 * hardware transmit queue. Packets sent to us from above 313 * are assigned to queues based on their priority. Not all 314 * devices support a complete set of hardware transmit queues. 315 * For those devices the array sc_ac2q will map multiple 316 * priorities to fewer hardware queues (typically all to one 317 * hardware queue). 318 */ 319struct ath_txq { 320 struct ath_softc *axq_softc; /* Needed for scheduling */ 321 u_int axq_qnum; /* hardware q number */ 322#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 323 u_int axq_ac; /* WME AC */ 324 u_int axq_flags; 325#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 326 u_int axq_depth; /* queue depth (stat only) */ 327 u_int axq_aggr_depth; /* how many aggregates are queued */ 328 u_int axq_fifo_depth; /* depth of FIFO frames */ 329 u_int axq_intrcnt; /* interrupt count */ 330 u_int32_t *axq_link; /* link ptr in last TX desc */ 331 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 332 struct mtx axq_lock; /* lock on q and link */ 333 char axq_name[12]; /* e.g. "ath0_txq4" */ 334 335 /* Per-TID traffic queue for software -> hardware TX */ 336 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 337}; 338 339#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 340#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 341#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 342#define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 343 MA_NOTOWNED) 344 345#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 346 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 347 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 348 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 349} while (0) 350#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 351#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 352#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 353#define ATH_TXQ_LOCK_ASSERT(_tq) \ 354 mtx_assert(&(_tq)->axq_lock, MA_OWNED) 355#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 356 mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 357#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 358 359#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 360 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 361#define ATH_TID_UNLOCK_ASSERT(_sc, _tid) \ 362 ATH_TXQ_UNLOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 363 364/* 365 * These are for the hardware queue. 366 */ 367#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 368 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 369 (_tq)->axq_depth++; \ 370} while (0) 371#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 372 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 373 (_tq)->axq_depth++; \ 374} while (0) 375#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 376 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 377 (_tq)->axq_depth--; \ 378} while (0) 379#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 380#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 381 382/* 383 * These are for the TID software queue. 384 */ 385#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 386 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 387 (_tq)->axq_depth++; \ 388 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 389} while (0) 390#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 391 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 392 (_tq)->axq_depth++; \ 393 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 394} while (0) 395#define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 396 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 397 (_tq)->axq_depth--; \ 398 atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 399} while (0) 400#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 401#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 402 403/* 404 * These are for the TID filtered frame queue 405 */ 406#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 407 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 408 (_tq)->axq_depth++; \ 409 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 410} while (0) 411#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 412 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 413 (_tq)->axq_depth++; \ 414 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 415} while (0) 416#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 417 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 418 (_tq)->axq_depth--; \ 419 atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 420} while (0) 421#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 422#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 423 424struct ath_vap { 425 struct ieee80211vap av_vap; /* base class */ 426 int av_bslot; /* beacon slot index */ 427 struct ath_buf *av_bcbuf; /* beacon buffer */ 428 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 429 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 430 431 void (*av_recv_mgmt)(struct ieee80211_node *, 432 struct mbuf *, int, int, int); 433 int (*av_newstate)(struct ieee80211vap *, 434 enum ieee80211_state, int); 435 void (*av_bmiss)(struct ieee80211vap *); 436 void (*av_node_ps)(struct ieee80211_node *, int); 437 int (*av_set_tim)(struct ieee80211_node *, int); 438}; 439#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 440 441struct taskqueue; 442struct ath_tx99; 443 444/* 445 * Whether to reset the TX/RX queue with or without 446 * a queue flush. 447 */ 448typedef enum { 449 ATH_RESET_DEFAULT = 0, 450 ATH_RESET_NOLOSS = 1, 451 ATH_RESET_FULL = 2, 452} ATH_RESET_TYPE; 453 454struct ath_rx_methods { 455 void (*recv_stop)(struct ath_softc *sc, int dodelay); 456 int (*recv_start)(struct ath_softc *sc); 457 void (*recv_flush)(struct ath_softc *sc); 458 void (*recv_tasklet)(void *arg, int npending); 459 int (*recv_rxbuf_init)(struct ath_softc *sc, 460 struct ath_buf *bf); 461 int (*recv_setup)(struct ath_softc *sc); 462 int (*recv_teardown)(struct ath_softc *sc); 463}; 464 465/* 466 * Represent the current state of the RX FIFO. 467 */ 468struct ath_rx_edma { 469 struct ath_buf **m_fifo; 470 int m_fifolen; 471 int m_fifo_head; 472 int m_fifo_tail; 473 int m_fifo_depth; 474 struct mbuf *m_rxpending; 475}; 476 477struct ath_tx_edma_fifo { 478 struct ath_buf **m_fifo; 479 int m_fifolen; 480 int m_fifo_head; 481 int m_fifo_tail; 482 int m_fifo_depth; 483}; 484 485struct ath_tx_methods { 486 int (*xmit_setup)(struct ath_softc *sc); 487 int (*xmit_teardown)(struct ath_softc *sc); 488 void (*xmit_attach_comp_func)(struct ath_softc *sc); 489 490 void (*xmit_dma_restart)(struct ath_softc *sc, 491 struct ath_txq *txq); 492 void (*xmit_handoff)(struct ath_softc *sc, 493 struct ath_txq *txq, struct ath_buf *bf); 494 void (*xmit_drain)(struct ath_softc *sc, 495 ATH_RESET_TYPE reset_type); 496}; 497 498struct ath_softc { 499 struct ifnet *sc_ifp; /* interface common */ 500 struct ath_stats sc_stats; /* interface statistics */ 501 struct ath_tx_aggr_stats sc_aggr_stats; 502 struct ath_intr_stats sc_intr_stats; 503 uint64_t sc_debug; 504 uint64_t sc_ktrdebug; 505 int sc_nvaps; /* # vaps */ 506 int sc_nstavaps; /* # station vaps */ 507 int sc_nmeshvaps; /* # mbss vaps */ 508 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 509 u_int8_t sc_nbssid0; /* # vap's using base mac */ 510 uint32_t sc_bssidmask; /* bssid mask */ 511 512 struct ath_rx_methods sc_rx; 513 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 514 struct ath_tx_methods sc_tx; 515 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 516 517 int sc_rx_statuslen; 518 int sc_tx_desclen; 519 int sc_tx_statuslen; 520 int sc_tx_nmaps; /* Number of TX maps */ 521 int sc_edma_bufsize; 522 523 void (*sc_node_cleanup)(struct ieee80211_node *); 524 void (*sc_node_free)(struct ieee80211_node *); 525 device_t sc_dev; 526 HAL_BUS_TAG sc_st; /* bus space tag */ 527 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 528 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 529 struct mtx sc_mtx; /* master lock (recursive) */ 530 struct mtx sc_pcu_mtx; /* PCU access mutex */ 531 char sc_pcu_mtx_name[32]; 532 struct mtx sc_rx_mtx; /* RX access mutex */ 533 char sc_rx_mtx_name[32]; 534 struct mtx sc_tx_mtx; /* TX access mutex */ 535 char sc_tx_mtx_name[32]; 536 struct taskqueue *sc_tq; /* private task queue */ 537 struct ath_hal *sc_ah; /* Atheros HAL */ 538 struct ath_ratectrl *sc_rc; /* tx rate control support */ 539 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 540 void (*sc_setdefantenna)(struct ath_softc *, u_int); 541 unsigned int sc_invalid : 1,/* disable hardware accesses */ 542 sc_mrretry : 1,/* multi-rate retry support */ 543 sc_mrrprot : 1,/* MRR + protection support */ 544 sc_softled : 1,/* enable LED gpio status */ 545 sc_hardled : 1,/* enable MAC LED status */ 546 sc_splitmic : 1,/* split TKIP MIC keys */ 547 sc_needmib : 1,/* enable MIB stats intr */ 548 sc_diversity: 1,/* enable rx diversity */ 549 sc_hasveol : 1,/* tx VEOL support */ 550 sc_ledstate : 1,/* LED on/off state */ 551 sc_blinking : 1,/* LED blink operation active */ 552 sc_mcastkey : 1,/* mcast key cache search */ 553 sc_scanning : 1,/* scanning active */ 554 sc_syncbeacon:1,/* sync/resync beacon timers */ 555 sc_hasclrkey: 1,/* CLR key supported */ 556 sc_xchanmode: 1,/* extended channel mode */ 557 sc_outdoor : 1,/* outdoor operation */ 558 sc_dturbo : 1,/* dynamic turbo in use */ 559 sc_hasbmask : 1,/* bssid mask support */ 560 sc_hasbmatch: 1,/* bssid match disable support*/ 561 sc_hastsfadd: 1,/* tsf adjust support */ 562 sc_beacons : 1,/* beacons running */ 563 sc_swbmiss : 1,/* sta mode using sw bmiss */ 564 sc_stagbeacons:1,/* use staggered beacons */ 565 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 566 sc_resume_up: 1,/* on resume, start all vaps */ 567 sc_tdma : 1,/* TDMA in use */ 568 sc_setcca : 1,/* set/clr CCA with TDMA */ 569 sc_resetcal : 1,/* reset cal state next trip */ 570 sc_rxslink : 1,/* do self-linked final descriptor */ 571 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 572 sc_isedma : 1;/* supports EDMA */ 573 uint32_t sc_eerd; /* regdomain from EEPROM */ 574 uint32_t sc_eecc; /* country code from EEPROM */ 575 /* rate tables */ 576 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 577 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 578 enum ieee80211_phymode sc_curmode; /* current phy mode */ 579 HAL_OPMODE sc_opmode; /* current operating mode */ 580 u_int16_t sc_curtxpow; /* current tx power limit */ 581 u_int16_t sc_curaid; /* current association id */ 582 struct ieee80211_channel *sc_curchan; /* current installed channel */ 583 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 584 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 585 struct { 586 u_int8_t ieeerate; /* IEEE rate */ 587 u_int8_t rxflags; /* radiotap rx flags */ 588 u_int8_t txflags; /* radiotap tx flags */ 589 u_int16_t ledon; /* softled on time */ 590 u_int16_t ledoff; /* softled off time */ 591 } sc_hwmap[32]; /* h/w rate ix mappings */ 592 u_int8_t sc_protrix; /* protection rate index */ 593 u_int8_t sc_lastdatarix; /* last data frame rate index */ 594 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 595 u_int sc_fftxqmin; /* min frames before staging */ 596 u_int sc_fftxqmax; /* max frames before drop */ 597 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 598 599 HAL_INT sc_imask; /* interrupt mask copy */ 600 601 /* 602 * These are modified in the interrupt handler as well as 603 * the task queues and other contexts. Thus these must be 604 * protected by a mutex, or they could clash. 605 * 606 * For now, access to these is behind the ATH_LOCK, 607 * just to save time. 608 */ 609 uint32_t sc_txq_active; /* bitmap of active TXQs */ 610 uint32_t sc_kickpcu; /* whether to kick the PCU */ 611 uint32_t sc_rxproc_cnt; /* In RX processing */ 612 uint32_t sc_txproc_cnt; /* In TX processing */ 613 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 614 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 615 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 616 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 617 618 u_int sc_keymax; /* size of key cache */ 619 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 620 621 /* 622 * Software based LED blinking 623 */ 624 u_int sc_ledpin; /* GPIO pin for driving LED */ 625 u_int sc_ledon; /* pin setting for LED on */ 626 u_int sc_ledidle; /* idle polling interval */ 627 int sc_ledevent; /* time of last LED event */ 628 u_int8_t sc_txrix; /* current tx rate for LED */ 629 u_int16_t sc_ledoff; /* off time for current blink */ 630 struct callout sc_ledtimer; /* led off timer */ 631 632 /* 633 * Hardware based LED blinking 634 */ 635 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 636 int sc_led_net_pin; /* MAC network LED GPIO pin */ 637 638 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 639 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 640 641 struct ath_descdma sc_rxdma; /* RX descriptors */ 642 ath_bufhead sc_rxbuf; /* receive buffer */ 643 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 644 struct task sc_rxtask; /* rx int processing */ 645 u_int8_t sc_defant; /* current default antenna */ 646 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 647 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 648 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 649 struct ath_rx_radiotap_header sc_rx_th; 650 int sc_rx_th_len; 651 u_int sc_monpass; /* frames to pass in mon.mode */ 652 653 struct ath_descdma sc_txdma; /* TX descriptors */ 654 uint16_t sc_txbuf_descid; 655 ath_bufhead sc_txbuf; /* transmit buffer */ 656 int sc_txbuf_cnt; /* how many buffers avail */ 657 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 658 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 659 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 660 struct mtx sc_txbuflock; /* txbuf lock */ 661 char sc_txname[12]; /* e.g. "ath0_buf" */ 662 u_int sc_txqsetup; /* h/w queues setup */ 663 u_int sc_txintrperiod;/* tx interrupt batching */ 664 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 665 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 666 struct task sc_txtask; /* tx int processing */ 667 struct task sc_txqtask; /* tx proc processing */ 668 669 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 670 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 671 char sc_txcompname[12]; /* eg ath0_txcomp */ 672 673 int sc_wd_timer; /* count down for wd timer */ 674 struct callout sc_wd_ch; /* tx watchdog timer */ 675 struct ath_tx_radiotap_header sc_tx_th; 676 int sc_tx_th_len; 677 678 struct ath_descdma sc_bdma; /* beacon descriptors */ 679 ath_bufhead sc_bbuf; /* beacon buffers */ 680 u_int sc_bhalq; /* HAL q for outgoing beacons */ 681 u_int sc_bmisscount; /* missed beacon transmits */ 682 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 683 struct ath_txq *sc_cabq; /* tx q for cab frames */ 684 struct task sc_bmisstask; /* bmiss int processing */ 685 struct task sc_bstucktask; /* stuck beacon processing */ 686 struct task sc_resettask; /* interface reset task */ 687 struct task sc_fataltask; /* fatal task */ 688 enum { 689 OK, /* no change needed */ 690 UPDATE, /* update pending */ 691 COMMIT /* beacon sent, commit change */ 692 } sc_updateslot; /* slot time update fsm */ 693 int sc_slotupdate; /* slot to advance fsm */ 694 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 695 int sc_nbcnvaps; /* # vaps with beacons */ 696 697 struct callout sc_cal_ch; /* callout handle for cals */ 698 int sc_lastlongcal; /* last long cal completed */ 699 int sc_lastcalreset;/* last cal reset done */ 700 int sc_lastani; /* last ANI poll */ 701 int sc_lastshortcal; /* last short calibration */ 702 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 703 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 704 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 705 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 706 u_int sc_tdmaswba; /* TDMA SWBA counter */ 707 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 708 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 709 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 710 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 711 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 712 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 713 int sc_txchainmask; /* currently configured TX chainmask */ 714 int sc_rxchainmask; /* currently configured RX chainmask */ 715 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 716 717 /* Queue limits */ 718 719 /* 720 * To avoid queue starvation in congested conditions, 721 * these parameters tune the maximum number of frames 722 * queued to the data/mcastq before they're dropped. 723 * 724 * This is to prevent: 725 * + a single destination overwhelming everything, including 726 * management/multicast frames; 727 * + multicast frames overwhelming everything (when the 728 * air is sufficiently busy that cabq can't drain.) 729 * 730 * These implement: 731 * + data_minfree is the maximum number of free buffers 732 * overall to successfully allow a data frame. 733 * 734 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 735 */ 736 int sc_txq_data_minfree; 737 int sc_txq_mcastq_maxdepth; 738 739 /* 740 * Aggregation twiddles 741 * 742 * hwq_limit: how busy to keep the hardware queue - don't schedule 743 * further packets to the hardware, regardless of the TID 744 * tid_hwq_lo: how low the per-TID hwq count has to be before the 745 * TID will be scheduled again 746 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 747 * stops being scheduled. 748 */ 749 int sc_hwq_limit; 750 int sc_tid_hwq_lo; 751 int sc_tid_hwq_hi; 752 753 /* DFS related state */ 754 void *sc_dfs; /* Used by an optional DFS module */ 755 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 756 struct task sc_dfstask; /* DFS processing task */ 757 758 /* TX AMPDU handling */ 759 int (*sc_addba_request)(struct ieee80211_node *, 760 struct ieee80211_tx_ampdu *, int, int, int); 761 int (*sc_addba_response)(struct ieee80211_node *, 762 struct ieee80211_tx_ampdu *, int, int, int); 763 void (*sc_addba_stop)(struct ieee80211_node *, 764 struct ieee80211_tx_ampdu *); 765 void (*sc_addba_response_timeout) 766 (struct ieee80211_node *, 767 struct ieee80211_tx_ampdu *); 768 void (*sc_bar_response)(struct ieee80211_node *ni, 769 struct ieee80211_tx_ampdu *tap, 770 int status); 771}; 772 773#define ATH_LOCK_INIT(_sc) \ 774 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 775 NULL, MTX_DEF | MTX_RECURSE) 776#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 777#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 778#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 779#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 780#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 781 782/* 783 * The TX lock is non-reentrant and serialises the TX send operations. 784 * (ath_start(), ath_raw_xmit().) It doesn't yet serialise the TX 785 * completion operations; thus it can't be used (yet!) to protect 786 * hardware / software TXQ operations. 787 */ 788#define ATH_TX_LOCK_INIT(_sc) do {\ 789 snprintf((_sc)->sc_tx_mtx_name, \ 790 sizeof((_sc)->sc_tx_mtx_name), \ 791 "%s TX lock", \ 792 device_get_nameunit((_sc)->sc_dev)); \ 793 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 794 NULL, MTX_DEF); \ 795 } while (0) 796#define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 797#define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 798#define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 799#define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 800 MA_OWNED) 801#define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 802 MA_NOTOWNED) 803 804/* 805 * The PCU lock is non-recursive and should be treated as a spinlock. 806 * Although currently the interrupt code is run in netisr context and 807 * doesn't require this, this may change in the future. 808 * Please keep this in mind when protecting certain code paths 809 * with the PCU lock. 810 * 811 * The PCU lock is used to serialise access to the PCU so things such 812 * as TX, RX, state change (eg channel change), channel reset and updates 813 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 814 * 815 * Although the current single-thread taskqueue mechanism protects the 816 * majority of these situations by simply serialising them, there are 817 * a few others which occur at the same time. These include the TX path 818 * (which only acquires ATH_LOCK when recycling buffers to the free list), 819 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 820 */ 821#define ATH_PCU_LOCK_INIT(_sc) do {\ 822 snprintf((_sc)->sc_pcu_mtx_name, \ 823 sizeof((_sc)->sc_pcu_mtx_name), \ 824 "%s PCU lock", \ 825 device_get_nameunit((_sc)->sc_dev)); \ 826 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 827 NULL, MTX_DEF); \ 828 } while (0) 829#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 830#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 831#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 832#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 833 MA_OWNED) 834#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 835 MA_NOTOWNED) 836 837/* 838 * The RX lock is primarily a(nother) workaround to ensure that the 839 * RX FIFO/list isn't modified by various execution paths. 840 * Even though RX occurs in a single context (the ath taskqueue), the 841 * RX path can be executed via various reset/channel change paths. 842 */ 843#define ATH_RX_LOCK_INIT(_sc) do {\ 844 snprintf((_sc)->sc_rx_mtx_name, \ 845 sizeof((_sc)->sc_rx_mtx_name), \ 846 "%s RX lock", \ 847 device_get_nameunit((_sc)->sc_dev)); \ 848 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 849 NULL, MTX_DEF); \ 850 } while (0) 851#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 852#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 853#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 854#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 855 MA_OWNED) 856#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 857 MA_NOTOWNED) 858 859#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 860 861#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 862 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 863 device_get_nameunit((_sc)->sc_dev)); \ 864 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 865} while (0) 866#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 867#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 868#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 869#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 870 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 871 872#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 873 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 874 "%s_buf", \ 875 device_get_nameunit((_sc)->sc_dev)); \ 876 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 877 MTX_DEF); \ 878} while (0) 879#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 880#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 881#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 882#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 883 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 884 885int ath_attach(u_int16_t, struct ath_softc *); 886int ath_detach(struct ath_softc *); 887void ath_resume(struct ath_softc *); 888void ath_suspend(struct ath_softc *); 889void ath_shutdown(struct ath_softc *); 890void ath_intr(void *); 891 892/* 893 * HAL definitions to comply with local coding convention. 894 */ 895#define ath_hal_detach(_ah) \ 896 ((*(_ah)->ah_detach)((_ah))) 897#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 898 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 899#define ath_hal_macversion(_ah) \ 900 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 901#define ath_hal_getratetable(_ah, _mode) \ 902 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 903#define ath_hal_getmac(_ah, _mac) \ 904 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 905#define ath_hal_setmac(_ah, _mac) \ 906 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 907#define ath_hal_getbssidmask(_ah, _mask) \ 908 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 909#define ath_hal_setbssidmask(_ah, _mask) \ 910 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 911#define ath_hal_intrset(_ah, _mask) \ 912 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 913#define ath_hal_intrget(_ah) \ 914 ((*(_ah)->ah_getInterrupts)((_ah))) 915#define ath_hal_intrpend(_ah) \ 916 ((*(_ah)->ah_isInterruptPending)((_ah))) 917#define ath_hal_getisr(_ah, _pmask) \ 918 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 919#define ath_hal_updatetxtriglevel(_ah, _inc) \ 920 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 921#define ath_hal_setpower(_ah, _mode) \ 922 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 923#define ath_hal_keycachesize(_ah) \ 924 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 925#define ath_hal_keyreset(_ah, _ix) \ 926 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 927#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 928 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 929#define ath_hal_keyisvalid(_ah, _ix) \ 930 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 931#define ath_hal_keysetmac(_ah, _ix, _mac) \ 932 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 933#define ath_hal_getrxfilter(_ah) \ 934 ((*(_ah)->ah_getRxFilter)((_ah))) 935#define ath_hal_setrxfilter(_ah, _filter) \ 936 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 937#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 938 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 939#define ath_hal_waitforbeacon(_ah, _bf) \ 940 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 941#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 942 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 943/* NB: common across all chips */ 944#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 945#define ath_hal_gettsf32(_ah) \ 946 OS_REG_READ(_ah, AR_TSF_L32) 947#define ath_hal_gettsf64(_ah) \ 948 ((*(_ah)->ah_getTsf64)((_ah))) 949#define ath_hal_resettsf(_ah) \ 950 ((*(_ah)->ah_resetTsf)((_ah))) 951#define ath_hal_rxena(_ah) \ 952 ((*(_ah)->ah_enableReceive)((_ah))) 953#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 954 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 955#define ath_hal_gettxbuf(_ah, _q) \ 956 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 957#define ath_hal_numtxpending(_ah, _q) \ 958 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 959#define ath_hal_getrxbuf(_ah, _rxq) \ 960 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 961#define ath_hal_txstart(_ah, _q) \ 962 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 963#define ath_hal_setchannel(_ah, _chan) \ 964 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 965#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 966 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 967#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 968 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 969#define ath_hal_calreset(_ah, _chan) \ 970 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 971#define ath_hal_setledstate(_ah, _state) \ 972 ((*(_ah)->ah_setLedState)((_ah), (_state))) 973#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 974 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 975#define ath_hal_beaconreset(_ah) \ 976 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 977#define ath_hal_beaconsettimers(_ah, _bt) \ 978 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 979#define ath_hal_beacontimers(_ah, _bs) \ 980 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 981#define ath_hal_getnexttbtt(_ah) \ 982 ((*(_ah)->ah_getNextTBTT)((_ah))) 983#define ath_hal_setassocid(_ah, _bss, _associd) \ 984 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 985#define ath_hal_phydisable(_ah) \ 986 ((*(_ah)->ah_phyDisable)((_ah))) 987#define ath_hal_setopmode(_ah) \ 988 ((*(_ah)->ah_setPCUConfig)((_ah))) 989#define ath_hal_stoptxdma(_ah, _qnum) \ 990 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 991#define ath_hal_stoppcurecv(_ah) \ 992 ((*(_ah)->ah_stopPcuReceive)((_ah))) 993#define ath_hal_startpcurecv(_ah) \ 994 ((*(_ah)->ah_startPcuReceive)((_ah))) 995#define ath_hal_stopdmarecv(_ah) \ 996 ((*(_ah)->ah_stopDmaReceive)((_ah))) 997#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 998 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 999 (_indata), (_insize), (_outdata), (_outsize))) 1000#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1001 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1002#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1003 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1004#define ath_hal_resettxqueue(_ah, _q) \ 1005 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1006#define ath_hal_releasetxqueue(_ah, _q) \ 1007 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1008#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1009 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1010#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1011 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1012/* NB: common across all chips */ 1013#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1014#define ath_hal_txqenabled(_ah, _qnum) \ 1015 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1016#define ath_hal_getrfgain(_ah) \ 1017 ((*(_ah)->ah_getRfGain)((_ah))) 1018#define ath_hal_getdefantenna(_ah) \ 1019 ((*(_ah)->ah_getDefAntenna)((_ah))) 1020#define ath_hal_setdefantenna(_ah, _ant) \ 1021 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1022#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1023 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1024#define ath_hal_ani_poll(_ah, _chan) \ 1025 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1026#define ath_hal_mibevent(_ah, _stats) \ 1027 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1028#define ath_hal_setslottime(_ah, _us) \ 1029 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1030#define ath_hal_getslottime(_ah) \ 1031 ((*(_ah)->ah_getSlotTime)((_ah))) 1032#define ath_hal_setacktimeout(_ah, _us) \ 1033 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1034#define ath_hal_getacktimeout(_ah) \ 1035 ((*(_ah)->ah_getAckTimeout)((_ah))) 1036#define ath_hal_setctstimeout(_ah, _us) \ 1037 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1038#define ath_hal_getctstimeout(_ah) \ 1039 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1040#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1041 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1042#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1043 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1044#define ath_hal_ciphersupported(_ah, _cipher) \ 1045 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1046#define ath_hal_getregdomain(_ah, _prd) \ 1047 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1048#define ath_hal_setregdomain(_ah, _rd) \ 1049 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1050#define ath_hal_getcountrycode(_ah, _pcc) \ 1051 (*(_pcc) = (_ah)->ah_countryCode) 1052#define ath_hal_gettkipmic(_ah) \ 1053 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1054#define ath_hal_settkipmic(_ah, _v) \ 1055 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1056#define ath_hal_hastkipsplit(_ah) \ 1057 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1058#define ath_hal_gettkipsplit(_ah) \ 1059 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1060#define ath_hal_settkipsplit(_ah, _v) \ 1061 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1062#define ath_hal_haswmetkipmic(_ah) \ 1063 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1064#define ath_hal_hwphycounters(_ah) \ 1065 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1066#define ath_hal_hasdiversity(_ah) \ 1067 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1068#define ath_hal_getdiversity(_ah) \ 1069 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1070#define ath_hal_setdiversity(_ah, _v) \ 1071 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1072#define ath_hal_getantennaswitch(_ah) \ 1073 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1074#define ath_hal_setantennaswitch(_ah, _v) \ 1075 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1076#define ath_hal_getdiag(_ah, _pv) \ 1077 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1078#define ath_hal_setdiag(_ah, _v) \ 1079 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1080#define ath_hal_getnumtxqueues(_ah, _pv) \ 1081 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1082#define ath_hal_hasveol(_ah) \ 1083 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1084#define ath_hal_hastxpowlimit(_ah) \ 1085 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1086#define ath_hal_settxpowlimit(_ah, _pow) \ 1087 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1088#define ath_hal_gettxpowlimit(_ah, _ppow) \ 1089 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1090#define ath_hal_getmaxtxpow(_ah, _ppow) \ 1091 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1092#define ath_hal_gettpscale(_ah, _scale) \ 1093 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1094#define ath_hal_settpscale(_ah, _v) \ 1095 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1096#define ath_hal_hastpc(_ah) \ 1097 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1098#define ath_hal_gettpc(_ah) \ 1099 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1100#define ath_hal_settpc(_ah, _v) \ 1101 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1102#define ath_hal_hasbursting(_ah) \ 1103 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1104#define ath_hal_setmcastkeysearch(_ah, _v) \ 1105 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1106#define ath_hal_hasmcastkeysearch(_ah) \ 1107 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1108#define ath_hal_getmcastkeysearch(_ah) \ 1109 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1110#define ath_hal_hasfastframes(_ah) \ 1111 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1112#define ath_hal_hasbssidmask(_ah) \ 1113 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1114#define ath_hal_hasbssidmatch(_ah) \ 1115 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1116#define ath_hal_hastsfadjust(_ah) \ 1117 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1118#define ath_hal_gettsfadjust(_ah) \ 1119 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1120#define ath_hal_settsfadjust(_ah, _onoff) \ 1121 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1122#define ath_hal_hasrfsilent(_ah) \ 1123 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1124#define ath_hal_getrfkill(_ah) \ 1125 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1126#define ath_hal_setrfkill(_ah, _onoff) \ 1127 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1128#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1129 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1130#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1131 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1132#define ath_hal_gettpack(_ah, _ptpack) \ 1133 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1134#define ath_hal_settpack(_ah, _tpack) \ 1135 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1136#define ath_hal_gettpcts(_ah, _ptpcts) \ 1137 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1138#define ath_hal_settpcts(_ah, _tpcts) \ 1139 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1140#define ath_hal_hasintmit(_ah) \ 1141 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1142 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1143#define ath_hal_getintmit(_ah) \ 1144 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1145 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1146#define ath_hal_setintmit(_ah, _v) \ 1147 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1148 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1149 1150/* EDMA definitions */ 1151#define ath_hal_hasedma(_ah) \ 1152 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1153 0, NULL) == HAL_OK) 1154#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1155 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1156 == HAL_OK) 1157#define ath_hal_getntxmaps(_ah, _req) \ 1158 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1159 == HAL_OK) 1160#define ath_hal_gettxdesclen(_ah, _req) \ 1161 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1162 == HAL_OK) 1163#define ath_hal_gettxstatuslen(_ah, _req) \ 1164 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1165 == HAL_OK) 1166#define ath_hal_getrxstatuslen(_ah, _req) \ 1167 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1168 == HAL_OK) 1169#define ath_hal_setrxbufsize(_ah, _req) \ 1170 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1171 == HAL_OK) 1172 1173#define ath_hal_getchannoise(_ah, _c) \ 1174 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1175 1176/* 802.11n HAL methods */ 1177#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1178 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1179#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1180 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1181#define ath_hal_setrxchainmask(_ah, _rx) \ 1182 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1183#define ath_hal_settxchainmask(_ah, _tx) \ 1184 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1185#define ath_hal_split4ktrans(_ah) \ 1186 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1187 0, NULL) == HAL_OK) 1188#define ath_hal_self_linked_final_rxdesc(_ah) \ 1189 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1190 0, NULL) == HAL_OK) 1191#define ath_hal_gtxto_supported(_ah) \ 1192 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1193#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1194 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1195 0, NULL) == HAL_OK) 1196#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1197 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1198#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1199 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1200#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1201 _txr0, _txtr0, _keyix, _ant, _flags, \ 1202 _rtsrate, _rtsdura) \ 1203 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1204 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1205 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1206#define ath_hal_setupxtxdesc(_ah, _ds, \ 1207 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1208 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1209 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1210#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1211 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1212 (_first), (_last), (_ds0))) 1213#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1214 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1215#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1216 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1217#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1218 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1219#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1220 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1221#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1222 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1223#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1224 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1225#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1226 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1227 (_size))) 1228 1229#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1230 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1231 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1232 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1233#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1234 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1235 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1236 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1237 (_first), (_last), (_lastaggr))) 1238#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1239 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1240 1241#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1242 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1243 (_series), (_ns), (_flags))) 1244 1245#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1246 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1247#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1248 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1249#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1250 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1251 1252#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1253 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1254#define ath_hal_clr11n_aggr(_ah, _ds) \ 1255 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1256 1257#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1258 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1259#define ath_hal_gpioset(_ah, _gpio, _b) \ 1260 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1261#define ath_hal_gpioget(_ah, _gpio) \ 1262 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1263#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1264 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1265 1266/* 1267 * PCIe suspend/resume/poweron/poweroff related macros 1268 */ 1269#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1270 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1271#define ath_hal_disablepcie(_ah) \ 1272 ((*(_ah)->ah_disablePCIE)((_ah))) 1273 1274/* 1275 * This is badly-named; you need to set the correct parameters 1276 * to begin to receive useful radar events; and even then 1277 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1278 * more information. 1279 */ 1280#define ath_hal_enabledfs(_ah, _param) \ 1281 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1282#define ath_hal_getdfsthresh(_ah, _param) \ 1283 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1284#define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1285 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1286#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1287 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1288 (_buf), (_event))) 1289#define ath_hal_is_fast_clock_enabled(_ah) \ 1290 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1291#define ath_hal_radar_wait(_ah, _chan) \ 1292 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1293#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1294 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1295#define ath_hal_get_chan_ext_busy(_ah) \ 1296 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1297 1298#endif /* _DEV_ATH_ATHVAR_H */ 1299