if_athvar.h revision 239282
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 239282 2012-08-15 06:48:34Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * There is a separate TX ath_buf pool for management frames. 48 * This ensures that management frames such as probe responses 49 * and BAR frames can be transmitted during periods of high 50 * TX activity. 51 */ 52#define ATH_MGMT_TXBUF 32 53 54/* 55 * 802.11n requires more TX and RX buffers to do AMPDU. 56 */ 57#ifdef ATH_ENABLE_11N 58#define ATH_TXBUF 512 59#define ATH_RXBUF 512 60#endif 61 62#ifndef ATH_RXBUF 63#define ATH_RXBUF 40 /* number of RX buffers */ 64#endif 65#ifndef ATH_TXBUF 66#define ATH_TXBUF 200 /* number of TX buffers */ 67#endif 68#define ATH_BCBUF 4 /* number of beacon buffers */ 69 70#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74 75#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78 79/* 80 * The key cache is used for h/w cipher state and also for 81 * tracking station state such as the current tx antenna. 82 * We also setup a mapping table between key cache slot indices 83 * and station state to short-circuit node lookups on rx. 84 * Different parts have different size key caches. We handle 85 * up to ATH_KEYMAX entries (could dynamically allocate state). 86 */ 87#define ATH_KEYMAX 128 /* max key cache size we handle */ 88#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89 90struct taskqueue; 91struct kthread; 92struct ath_buf; 93 94#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95 96/* 97 * Per-TID state 98 * 99 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100 */ 101struct ath_tid { 102 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103 u_int axq_depth; /* SW queue depth */ 104 char axq_name[48]; /* lock name */ 105 struct ath_node *an; /* pointer to parent */ 106 int tid; /* tid */ 107 int ac; /* which AC gets this trafic */ 108 int hwq_depth; /* how many buffers are on HW */ 109 110 /* 111 * Entry on the ath_txq; when there's traffic 112 * to send 113 */ 114 TAILQ_ENTRY(ath_tid) axq_qelem; 115 int sched; 116 int paused; /* >0 if the TID has been paused */ 117 int addba_tx_pending; /* TX ADDBA pending */ 118 int bar_wait; /* waiting for BAR */ 119 int bar_tx; /* BAR TXed */ 120 121 /* 122 * Is the TID being cleaned up after a transition 123 * from aggregation to non-aggregation? 124 * When this is set to 1, this TID will be paused 125 * and no further traffic will be queued until all 126 * the hardware packets pending for this TID have been 127 * TXed/completed; at which point (non-aggregation) 128 * traffic will resume being TXed. 129 */ 130 int cleanup_inprogress; 131 /* 132 * How many hardware-queued packets are 133 * waiting to be cleaned up. 134 * This is only valid if cleanup_inprogress is 1. 135 */ 136 int incomp; 137 138 /* 139 * The following implements a ring representing 140 * the frames in the current BAW. 141 * To avoid copying the array content each time 142 * the BAW is moved, the baw_head/baw_tail point 143 * to the current BAW begin/end; when the BAW is 144 * shifted the head/tail of the array are also 145 * appropriately shifted. 146 */ 147 /* active tx buffers, beginning at current BAW */ 148 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 149 /* where the baw head is in the array */ 150 int baw_head; 151 /* where the BAW tail is in the array */ 152 int baw_tail; 153}; 154 155/* driver-specific node state */ 156struct ath_node { 157 struct ieee80211_node an_node; /* base class */ 158 u_int8_t an_mgmtrix; /* min h/w rate index */ 159 u_int8_t an_mcastrix; /* mcast h/w rate index */ 160 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 161 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 162 char an_name[32]; /* eg "wlan0_a1" */ 163 struct mtx an_mtx; /* protecting the ath_node state */ 164 /* variable-length rate control state follows */ 165}; 166#define ATH_NODE(ni) ((struct ath_node *)(ni)) 167#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 168 169#define ATH_RSSI_LPF_LEN 10 170#define ATH_RSSI_DUMMY_MARKER 0x127 171#define ATH_EP_MUL(x, mul) ((x) * (mul)) 172#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 173#define ATH_LPF_RSSI(x, y, len) \ 174 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 175#define ATH_RSSI_LPF(x, y) do { \ 176 if ((y) >= -20) \ 177 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 178} while (0) 179#define ATH_EP_RND(x,mul) \ 180 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 181#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 182 183typedef enum { 184 ATH_BUFTYPE_NORMAL = 0, 185 ATH_BUFTYPE_MGMT = 1, 186} ath_buf_type_t; 187 188struct ath_buf { 189 TAILQ_ENTRY(ath_buf) bf_list; 190 struct ath_buf * bf_next; /* next buffer in the aggregate */ 191 int bf_nseg; 192 HAL_STATUS bf_rxstatus; 193 uint16_t bf_flags; /* status flags (below) */ 194 uint16_t bf_descid; /* 16 bit descriptor ID */ 195 struct ath_desc *bf_desc; /* virtual addr of desc */ 196 struct ath_desc_status bf_status; /* tx/rx status */ 197 bus_addr_t bf_daddr; /* physical addr of desc */ 198 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 199 struct mbuf *bf_m; /* mbuf for buf */ 200 struct ieee80211_node *bf_node; /* pointer to the node */ 201 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 202 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 203 bus_size_t bf_mapsize; 204#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 205 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 206 207 /* Completion function to call on TX complete (fail or not) */ 208 /* 209 * "fail" here is set to 1 if the queue entries were removed 210 * through a call to ath_tx_draintxq(). 211 */ 212 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 213 214 /* This state is kept to support software retries and aggregation */ 215 struct { 216 uint16_t bfs_seqno; /* sequence number of this packet */ 217 uint16_t bfs_ndelim; /* number of delims for padding */ 218 219 uint8_t bfs_retries; /* retry count */ 220 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 221 uint8_t bfs_nframes; /* number of frames in aggregate */ 222 uint8_t bfs_pri; /* packet AC priority */ 223 224 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 225 226 u_int32_t bfs_aggr:1, /* part of aggregate? */ 227 bfs_aggrburst:1, /* part of aggregate burst? */ 228 bfs_isretried:1, /* retried frame? */ 229 bfs_dobaw:1, /* actually check against BAW? */ 230 bfs_addedbaw:1, /* has been added to the BAW */ 231 bfs_shpream:1, /* use short preamble */ 232 bfs_istxfrag:1, /* is fragmented */ 233 bfs_ismrr:1, /* do multi-rate TX retry */ 234 bfs_doprot:1, /* do RTS/CTS based protection */ 235 bfs_doratelookup:1; /* do rate lookup before each TX */ 236 237 /* 238 * These fields are passed into the 239 * descriptor setup functions. 240 */ 241 242 /* Make this an 8 bit value? */ 243 HAL_PKT_TYPE bfs_atype; /* packet type */ 244 245 uint32_t bfs_pktlen; /* length of this packet */ 246 247 uint16_t bfs_hdrlen; /* length of this packet header */ 248 uint16_t bfs_al; /* length of aggregate */ 249 250 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 251 uint8_t bfs_txrate0; /* first TX rate */ 252 uint8_t bfs_try0; /* first try count */ 253 254 uint16_t bfs_txpower; /* tx power */ 255 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 256 uint8_t bfs_ctsrate; /* CTS rate */ 257 258 /* 16 bit? */ 259 int32_t bfs_keyix; /* crypto key index */ 260 int32_t bfs_txantenna; /* TX antenna config */ 261 262 /* Make this an 8 bit value? */ 263 enum ieee80211_protmode bfs_protmode; 264 265 /* 16 bit? */ 266 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 267 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 268 } bf_state; 269}; 270typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 271 272#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 273#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 274 275/* 276 * DMA state for tx/rx descriptors. 277 */ 278struct ath_descdma { 279 const char* dd_name; 280 struct ath_desc *dd_desc; /* descriptors */ 281 int dd_descsize; /* size of single descriptor */ 282 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 283 bus_size_t dd_desc_len; /* size of dd_desc */ 284 bus_dma_segment_t dd_dseg; 285 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 286 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 287 struct ath_buf *dd_bufptr; /* associated buffers */ 288}; 289 290/* 291 * Data transmit queue state. One of these exists for each 292 * hardware transmit queue. Packets sent to us from above 293 * are assigned to queues based on their priority. Not all 294 * devices support a complete set of hardware transmit queues. 295 * For those devices the array sc_ac2q will map multiple 296 * priorities to fewer hardware queues (typically all to one 297 * hardware queue). 298 */ 299struct ath_txq { 300 struct ath_softc *axq_softc; /* Needed for scheduling */ 301 u_int axq_qnum; /* hardware q number */ 302#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 303 u_int axq_ac; /* WME AC */ 304 u_int axq_flags; 305#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 306 u_int axq_depth; /* queue depth (stat only) */ 307 u_int axq_aggr_depth; /* how many aggregates are queued */ 308 u_int axq_fifo_depth; /* depth of FIFO frames */ 309 u_int axq_intrcnt; /* interrupt count */ 310 u_int32_t *axq_link; /* link ptr in last TX desc */ 311 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 312 struct mtx axq_lock; /* lock on q and link */ 313 char axq_name[12]; /* e.g. "ath0_txq4" */ 314 315 /* Per-TID traffic queue for software -> hardware TX */ 316 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 317}; 318 319#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 320#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 321#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 322 323#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 324 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 325 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 326 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 327} while (0) 328#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 329#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 330#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 331#define ATH_TXQ_LOCK_ASSERT(_tq) \ 332 mtx_assert(&(_tq)->axq_lock, MA_OWNED) 333#define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 334 mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 335#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 336 337#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 338 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 339 340#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 341 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 342 (_tq)->axq_depth++; \ 343} while (0) 344#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 345 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 346 (_tq)->axq_depth++; \ 347} while (0) 348#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 349 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 350 (_tq)->axq_depth--; \ 351} while (0) 352#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 353#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 354 355struct ath_vap { 356 struct ieee80211vap av_vap; /* base class */ 357 int av_bslot; /* beacon slot index */ 358 struct ath_buf *av_bcbuf; /* beacon buffer */ 359 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 360 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 361 362 void (*av_recv_mgmt)(struct ieee80211_node *, 363 struct mbuf *, int, int, int); 364 int (*av_newstate)(struct ieee80211vap *, 365 enum ieee80211_state, int); 366 void (*av_bmiss)(struct ieee80211vap *); 367}; 368#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 369 370struct taskqueue; 371struct ath_tx99; 372 373/* 374 * Whether to reset the TX/RX queue with or without 375 * a queue flush. 376 */ 377typedef enum { 378 ATH_RESET_DEFAULT = 0, 379 ATH_RESET_NOLOSS = 1, 380 ATH_RESET_FULL = 2, 381} ATH_RESET_TYPE; 382 383struct ath_rx_methods { 384 void (*recv_stop)(struct ath_softc *sc, int dodelay); 385 int (*recv_start)(struct ath_softc *sc); 386 void (*recv_flush)(struct ath_softc *sc); 387 void (*recv_tasklet)(void *arg, int npending); 388 int (*recv_rxbuf_init)(struct ath_softc *sc, 389 struct ath_buf *bf); 390 int (*recv_setup)(struct ath_softc *sc); 391 int (*recv_teardown)(struct ath_softc *sc); 392}; 393 394/* 395 * Represent the current state of the RX FIFO. 396 */ 397struct ath_rx_edma { 398 struct ath_buf **m_fifo; 399 int m_fifolen; 400 int m_fifo_head; 401 int m_fifo_tail; 402 int m_fifo_depth; 403 struct mbuf *m_rxpending; 404}; 405 406struct ath_tx_edma_fifo { 407 struct ath_buf **m_fifo; 408 int m_fifolen; 409 int m_fifo_head; 410 int m_fifo_tail; 411 int m_fifo_depth; 412}; 413 414struct ath_tx_methods { 415 int (*xmit_setup)(struct ath_softc *sc); 416 int (*xmit_teardown)(struct ath_softc *sc); 417 void (*xmit_attach_comp_func)(struct ath_softc *sc); 418 419 void (*xmit_dma_restart)(struct ath_softc *sc, 420 struct ath_txq *txq); 421 void (*xmit_handoff)(struct ath_softc *sc, 422 struct ath_txq *txq, struct ath_buf *bf); 423 void (*xmit_drain)(struct ath_softc *sc, 424 ATH_RESET_TYPE reset_type); 425}; 426 427struct ath_softc { 428 struct ifnet *sc_ifp; /* interface common */ 429 struct ath_stats sc_stats; /* interface statistics */ 430 struct ath_tx_aggr_stats sc_aggr_stats; 431 struct ath_intr_stats sc_intr_stats; 432 uint64_t sc_debug; 433 int sc_nvaps; /* # vaps */ 434 int sc_nstavaps; /* # station vaps */ 435 int sc_nmeshvaps; /* # mbss vaps */ 436 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 437 u_int8_t sc_nbssid0; /* # vap's using base mac */ 438 uint32_t sc_bssidmask; /* bssid mask */ 439 440 struct ath_rx_methods sc_rx; 441 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 442 struct ath_tx_methods sc_tx; 443 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 444 445 int sc_rx_statuslen; 446 int sc_tx_desclen; 447 int sc_tx_statuslen; 448 int sc_tx_nmaps; /* Number of TX maps */ 449 int sc_edma_bufsize; 450 451 void (*sc_node_cleanup)(struct ieee80211_node *); 452 void (*sc_node_free)(struct ieee80211_node *); 453 device_t sc_dev; 454 HAL_BUS_TAG sc_st; /* bus space tag */ 455 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 456 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 457 struct mtx sc_mtx; /* master lock (recursive) */ 458 struct mtx sc_pcu_mtx; /* PCU access mutex */ 459 char sc_pcu_mtx_name[32]; 460 struct mtx sc_rx_mtx; /* RX access mutex */ 461 char sc_rx_mtx_name[32]; 462 struct taskqueue *sc_tq; /* private task queue */ 463 struct ath_hal *sc_ah; /* Atheros HAL */ 464 struct ath_ratectrl *sc_rc; /* tx rate control support */ 465 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 466 void (*sc_setdefantenna)(struct ath_softc *, u_int); 467 unsigned int sc_invalid : 1,/* disable hardware accesses */ 468 sc_mrretry : 1,/* multi-rate retry support */ 469 sc_mrrprot : 1,/* MRR + protection support */ 470 sc_softled : 1,/* enable LED gpio status */ 471 sc_hardled : 1,/* enable MAC LED status */ 472 sc_splitmic : 1,/* split TKIP MIC keys */ 473 sc_needmib : 1,/* enable MIB stats intr */ 474 sc_diversity: 1,/* enable rx diversity */ 475 sc_hasveol : 1,/* tx VEOL support */ 476 sc_ledstate : 1,/* LED on/off state */ 477 sc_blinking : 1,/* LED blink operation active */ 478 sc_mcastkey : 1,/* mcast key cache search */ 479 sc_scanning : 1,/* scanning active */ 480 sc_syncbeacon:1,/* sync/resync beacon timers */ 481 sc_hasclrkey: 1,/* CLR key supported */ 482 sc_xchanmode: 1,/* extended channel mode */ 483 sc_outdoor : 1,/* outdoor operation */ 484 sc_dturbo : 1,/* dynamic turbo in use */ 485 sc_hasbmask : 1,/* bssid mask support */ 486 sc_hasbmatch: 1,/* bssid match disable support*/ 487 sc_hastsfadd: 1,/* tsf adjust support */ 488 sc_beacons : 1,/* beacons running */ 489 sc_swbmiss : 1,/* sta mode using sw bmiss */ 490 sc_stagbeacons:1,/* use staggered beacons */ 491 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 492 sc_resume_up: 1,/* on resume, start all vaps */ 493 sc_tdma : 1,/* TDMA in use */ 494 sc_setcca : 1,/* set/clr CCA with TDMA */ 495 sc_resetcal : 1,/* reset cal state next trip */ 496 sc_rxslink : 1,/* do self-linked final descriptor */ 497 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 498 sc_isedma : 1;/* supports EDMA */ 499 uint32_t sc_eerd; /* regdomain from EEPROM */ 500 uint32_t sc_eecc; /* country code from EEPROM */ 501 /* rate tables */ 502 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 503 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 504 enum ieee80211_phymode sc_curmode; /* current phy mode */ 505 HAL_OPMODE sc_opmode; /* current operating mode */ 506 u_int16_t sc_curtxpow; /* current tx power limit */ 507 u_int16_t sc_curaid; /* current association id */ 508 struct ieee80211_channel *sc_curchan; /* current installed channel */ 509 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 510 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 511 struct { 512 u_int8_t ieeerate; /* IEEE rate */ 513 u_int8_t rxflags; /* radiotap rx flags */ 514 u_int8_t txflags; /* radiotap tx flags */ 515 u_int16_t ledon; /* softled on time */ 516 u_int16_t ledoff; /* softled off time */ 517 } sc_hwmap[32]; /* h/w rate ix mappings */ 518 u_int8_t sc_protrix; /* protection rate index */ 519 u_int8_t sc_lastdatarix; /* last data frame rate index */ 520 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 521 u_int sc_fftxqmin; /* min frames before staging */ 522 u_int sc_fftxqmax; /* max frames before drop */ 523 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 524 525 HAL_INT sc_imask; /* interrupt mask copy */ 526 527 /* 528 * These are modified in the interrupt handler as well as 529 * the task queues and other contexts. Thus these must be 530 * protected by a mutex, or they could clash. 531 * 532 * For now, access to these is behind the ATH_LOCK, 533 * just to save time. 534 */ 535 uint32_t sc_txq_active; /* bitmap of active TXQs */ 536 uint32_t sc_kickpcu; /* whether to kick the PCU */ 537 uint32_t sc_rxproc_cnt; /* In RX processing */ 538 uint32_t sc_txproc_cnt; /* In TX processing */ 539 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 540 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 541 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 542 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 543 544 u_int sc_keymax; /* size of key cache */ 545 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 546 547 /* 548 * Software based LED blinking 549 */ 550 u_int sc_ledpin; /* GPIO pin for driving LED */ 551 u_int sc_ledon; /* pin setting for LED on */ 552 u_int sc_ledidle; /* idle polling interval */ 553 int sc_ledevent; /* time of last LED event */ 554 u_int8_t sc_txrix; /* current tx rate for LED */ 555 u_int16_t sc_ledoff; /* off time for current blink */ 556 struct callout sc_ledtimer; /* led off timer */ 557 558 /* 559 * Hardware based LED blinking 560 */ 561 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 562 int sc_led_net_pin; /* MAC network LED GPIO pin */ 563 564 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 565 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 566 567 struct ath_descdma sc_rxdma; /* RX descriptors */ 568 ath_bufhead sc_rxbuf; /* receive buffer */ 569 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 570 struct task sc_rxtask; /* rx int processing */ 571 u_int8_t sc_defant; /* current default antenna */ 572 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 573 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 574 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 575 struct ath_rx_radiotap_header sc_rx_th; 576 int sc_rx_th_len; 577 u_int sc_monpass; /* frames to pass in mon.mode */ 578 579 struct ath_descdma sc_txdma; /* TX descriptors */ 580 uint16_t sc_txbuf_descid; 581 ath_bufhead sc_txbuf; /* transmit buffer */ 582 int sc_txbuf_cnt; /* how many buffers avail */ 583 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 584 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 585 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 586 struct mtx sc_txbuflock; /* txbuf lock */ 587 char sc_txname[12]; /* e.g. "ath0_buf" */ 588 u_int sc_txqsetup; /* h/w queues setup */ 589 u_int sc_txintrperiod;/* tx interrupt batching */ 590 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 591 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 592 struct task sc_txtask; /* tx int processing */ 593 struct task sc_txqtask; /* tx proc processing */ 594 595 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 596 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 597 char sc_txcompname[12]; /* eg ath0_txcomp */ 598 599 int sc_wd_timer; /* count down for wd timer */ 600 struct callout sc_wd_ch; /* tx watchdog timer */ 601 struct ath_tx_radiotap_header sc_tx_th; 602 int sc_tx_th_len; 603 604 struct ath_descdma sc_bdma; /* beacon descriptors */ 605 ath_bufhead sc_bbuf; /* beacon buffers */ 606 u_int sc_bhalq; /* HAL q for outgoing beacons */ 607 u_int sc_bmisscount; /* missed beacon transmits */ 608 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 609 struct ath_txq *sc_cabq; /* tx q for cab frames */ 610 struct task sc_bmisstask; /* bmiss int processing */ 611 struct task sc_bstucktask; /* stuck beacon processing */ 612 struct task sc_resettask; /* interface reset task */ 613 struct task sc_fataltask; /* fatal task */ 614 enum { 615 OK, /* no change needed */ 616 UPDATE, /* update pending */ 617 COMMIT /* beacon sent, commit change */ 618 } sc_updateslot; /* slot time update fsm */ 619 int sc_slotupdate; /* slot to advance fsm */ 620 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 621 int sc_nbcnvaps; /* # vaps with beacons */ 622 623 struct callout sc_cal_ch; /* callout handle for cals */ 624 int sc_lastlongcal; /* last long cal completed */ 625 int sc_lastcalreset;/* last cal reset done */ 626 int sc_lastani; /* last ANI poll */ 627 int sc_lastshortcal; /* last short calibration */ 628 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 629 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 630 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 631 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 632 u_int sc_tdmaswba; /* TDMA SWBA counter */ 633 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 634 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 635 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 636 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 637 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 638 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 639 int sc_txchainmask; /* currently configured TX chainmask */ 640 int sc_rxchainmask; /* currently configured RX chainmask */ 641 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 642 643 /* Queue limits */ 644 645 /* 646 * To avoid queue starvation in congested conditions, 647 * these parameters tune the maximum number of frames 648 * queued to the data/mcastq before they're dropped. 649 * 650 * This is to prevent: 651 * + a single destination overwhelming everything, including 652 * management/multicast frames; 653 * + multicast frames overwhelming everything (when the 654 * air is sufficiently busy that cabq can't drain.) 655 * 656 * These implement: 657 * + data_minfree is the maximum number of free buffers 658 * overall to successfully allow a data frame. 659 * 660 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 661 */ 662 int sc_txq_data_minfree; 663 int sc_txq_mcastq_maxdepth; 664 665 /* 666 * Aggregation twiddles 667 * 668 * hwq_limit: how busy to keep the hardware queue - don't schedule 669 * further packets to the hardware, regardless of the TID 670 * tid_hwq_lo: how low the per-TID hwq count has to be before the 671 * TID will be scheduled again 672 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 673 * stops being scheduled. 674 */ 675 int sc_hwq_limit; 676 int sc_tid_hwq_lo; 677 int sc_tid_hwq_hi; 678 679 /* DFS related state */ 680 void *sc_dfs; /* Used by an optional DFS module */ 681 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 682 struct task sc_dfstask; /* DFS processing task */ 683 684 /* TX AMPDU handling */ 685 int (*sc_addba_request)(struct ieee80211_node *, 686 struct ieee80211_tx_ampdu *, int, int, int); 687 int (*sc_addba_response)(struct ieee80211_node *, 688 struct ieee80211_tx_ampdu *, int, int, int); 689 void (*sc_addba_stop)(struct ieee80211_node *, 690 struct ieee80211_tx_ampdu *); 691 void (*sc_addba_response_timeout) 692 (struct ieee80211_node *, 693 struct ieee80211_tx_ampdu *); 694 void (*sc_bar_response)(struct ieee80211_node *ni, 695 struct ieee80211_tx_ampdu *tap, 696 int status); 697}; 698 699#define ATH_LOCK_INIT(_sc) \ 700 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 701 NULL, MTX_DEF | MTX_RECURSE) 702#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 703#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 704#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 705#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 706#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 707 708/* 709 * The PCU lock is non-recursive and should be treated as a spinlock. 710 * Although currently the interrupt code is run in netisr context and 711 * doesn't require this, this may change in the future. 712 * Please keep this in mind when protecting certain code paths 713 * with the PCU lock. 714 * 715 * The PCU lock is used to serialise access to the PCU so things such 716 * as TX, RX, state change (eg channel change), channel reset and updates 717 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 718 * 719 * Although the current single-thread taskqueue mechanism protects the 720 * majority of these situations by simply serialising them, there are 721 * a few others which occur at the same time. These include the TX path 722 * (which only acquires ATH_LOCK when recycling buffers to the free list), 723 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 724 */ 725#define ATH_PCU_LOCK_INIT(_sc) do {\ 726 snprintf((_sc)->sc_pcu_mtx_name, \ 727 sizeof((_sc)->sc_pcu_mtx_name), \ 728 "%s PCU lock", \ 729 device_get_nameunit((_sc)->sc_dev)); \ 730 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 731 NULL, MTX_DEF); \ 732 } while (0) 733#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 734#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 735#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 736#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 737 MA_OWNED) 738#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 739 MA_NOTOWNED) 740 741/* 742 * The RX lock is primarily a(nother) workaround to ensure that the 743 * RX FIFO/list isn't modified by various execution paths. 744 * Even though RX occurs in a single context (the ath taskqueue), the 745 * RX path can be executed via various reset/channel change paths. 746 */ 747#define ATH_RX_LOCK_INIT(_sc) do {\ 748 snprintf((_sc)->sc_rx_mtx_name, \ 749 sizeof((_sc)->sc_rx_mtx_name), \ 750 "%s RX lock", \ 751 device_get_nameunit((_sc)->sc_dev)); \ 752 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 753 NULL, MTX_DEF); \ 754 } while (0) 755#define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 756#define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 757#define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 758#define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 759 MA_OWNED) 760#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 761 MA_NOTOWNED) 762 763#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 764 765#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 766 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 767 device_get_nameunit((_sc)->sc_dev)); \ 768 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 769} while (0) 770#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 771#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 772#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 773#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 774 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 775 776#define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 777 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 778 "%s_buf", \ 779 device_get_nameunit((_sc)->sc_dev)); \ 780 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 781 MTX_DEF); \ 782} while (0) 783#define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 784#define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 785#define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 786#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 787 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 788 789int ath_attach(u_int16_t, struct ath_softc *); 790int ath_detach(struct ath_softc *); 791void ath_resume(struct ath_softc *); 792void ath_suspend(struct ath_softc *); 793void ath_shutdown(struct ath_softc *); 794void ath_intr(void *); 795 796/* 797 * HAL definitions to comply with local coding convention. 798 */ 799#define ath_hal_detach(_ah) \ 800 ((*(_ah)->ah_detach)((_ah))) 801#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 802 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 803#define ath_hal_macversion(_ah) \ 804 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 805#define ath_hal_getratetable(_ah, _mode) \ 806 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 807#define ath_hal_getmac(_ah, _mac) \ 808 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 809#define ath_hal_setmac(_ah, _mac) \ 810 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 811#define ath_hal_getbssidmask(_ah, _mask) \ 812 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 813#define ath_hal_setbssidmask(_ah, _mask) \ 814 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 815#define ath_hal_intrset(_ah, _mask) \ 816 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 817#define ath_hal_intrget(_ah) \ 818 ((*(_ah)->ah_getInterrupts)((_ah))) 819#define ath_hal_intrpend(_ah) \ 820 ((*(_ah)->ah_isInterruptPending)((_ah))) 821#define ath_hal_getisr(_ah, _pmask) \ 822 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 823#define ath_hal_updatetxtriglevel(_ah, _inc) \ 824 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 825#define ath_hal_setpower(_ah, _mode) \ 826 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 827#define ath_hal_keycachesize(_ah) \ 828 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 829#define ath_hal_keyreset(_ah, _ix) \ 830 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 831#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 832 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 833#define ath_hal_keyisvalid(_ah, _ix) \ 834 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 835#define ath_hal_keysetmac(_ah, _ix, _mac) \ 836 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 837#define ath_hal_getrxfilter(_ah) \ 838 ((*(_ah)->ah_getRxFilter)((_ah))) 839#define ath_hal_setrxfilter(_ah, _filter) \ 840 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 841#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 842 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 843#define ath_hal_waitforbeacon(_ah, _bf) \ 844 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 845#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 846 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 847/* NB: common across all chips */ 848#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 849#define ath_hal_gettsf32(_ah) \ 850 OS_REG_READ(_ah, AR_TSF_L32) 851#define ath_hal_gettsf64(_ah) \ 852 ((*(_ah)->ah_getTsf64)((_ah))) 853#define ath_hal_resettsf(_ah) \ 854 ((*(_ah)->ah_resetTsf)((_ah))) 855#define ath_hal_rxena(_ah) \ 856 ((*(_ah)->ah_enableReceive)((_ah))) 857#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 858 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 859#define ath_hal_gettxbuf(_ah, _q) \ 860 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 861#define ath_hal_numtxpending(_ah, _q) \ 862 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 863#define ath_hal_getrxbuf(_ah, _rxq) \ 864 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 865#define ath_hal_txstart(_ah, _q) \ 866 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 867#define ath_hal_setchannel(_ah, _chan) \ 868 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 869#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 870 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 871#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 872 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 873#define ath_hal_calreset(_ah, _chan) \ 874 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 875#define ath_hal_setledstate(_ah, _state) \ 876 ((*(_ah)->ah_setLedState)((_ah), (_state))) 877#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 878 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 879#define ath_hal_beaconreset(_ah) \ 880 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 881#define ath_hal_beaconsettimers(_ah, _bt) \ 882 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 883#define ath_hal_beacontimers(_ah, _bs) \ 884 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 885#define ath_hal_getnexttbtt(_ah) \ 886 ((*(_ah)->ah_getNextTBTT)((_ah))) 887#define ath_hal_setassocid(_ah, _bss, _associd) \ 888 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 889#define ath_hal_phydisable(_ah) \ 890 ((*(_ah)->ah_phyDisable)((_ah))) 891#define ath_hal_setopmode(_ah) \ 892 ((*(_ah)->ah_setPCUConfig)((_ah))) 893#define ath_hal_stoptxdma(_ah, _qnum) \ 894 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 895#define ath_hal_stoppcurecv(_ah) \ 896 ((*(_ah)->ah_stopPcuReceive)((_ah))) 897#define ath_hal_startpcurecv(_ah) \ 898 ((*(_ah)->ah_startPcuReceive)((_ah))) 899#define ath_hal_stopdmarecv(_ah) \ 900 ((*(_ah)->ah_stopDmaReceive)((_ah))) 901#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 902 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 903 (_indata), (_insize), (_outdata), (_outsize))) 904#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 905 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 906#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 907 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 908#define ath_hal_resettxqueue(_ah, _q) \ 909 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 910#define ath_hal_releasetxqueue(_ah, _q) \ 911 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 912#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 913 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 914#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 915 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 916/* NB: common across all chips */ 917#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 918#define ath_hal_txqenabled(_ah, _qnum) \ 919 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 920#define ath_hal_getrfgain(_ah) \ 921 ((*(_ah)->ah_getRfGain)((_ah))) 922#define ath_hal_getdefantenna(_ah) \ 923 ((*(_ah)->ah_getDefAntenna)((_ah))) 924#define ath_hal_setdefantenna(_ah, _ant) \ 925 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 926#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 927 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 928#define ath_hal_ani_poll(_ah, _chan) \ 929 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 930#define ath_hal_mibevent(_ah, _stats) \ 931 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 932#define ath_hal_setslottime(_ah, _us) \ 933 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 934#define ath_hal_getslottime(_ah) \ 935 ((*(_ah)->ah_getSlotTime)((_ah))) 936#define ath_hal_setacktimeout(_ah, _us) \ 937 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 938#define ath_hal_getacktimeout(_ah) \ 939 ((*(_ah)->ah_getAckTimeout)((_ah))) 940#define ath_hal_setctstimeout(_ah, _us) \ 941 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 942#define ath_hal_getctstimeout(_ah) \ 943 ((*(_ah)->ah_getCTSTimeout)((_ah))) 944#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 945 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 946#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 947 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 948#define ath_hal_ciphersupported(_ah, _cipher) \ 949 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 950#define ath_hal_getregdomain(_ah, _prd) \ 951 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 952#define ath_hal_setregdomain(_ah, _rd) \ 953 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 954#define ath_hal_getcountrycode(_ah, _pcc) \ 955 (*(_pcc) = (_ah)->ah_countryCode) 956#define ath_hal_gettkipmic(_ah) \ 957 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 958#define ath_hal_settkipmic(_ah, _v) \ 959 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 960#define ath_hal_hastkipsplit(_ah) \ 961 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 962#define ath_hal_gettkipsplit(_ah) \ 963 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 964#define ath_hal_settkipsplit(_ah, _v) \ 965 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 966#define ath_hal_haswmetkipmic(_ah) \ 967 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 968#define ath_hal_hwphycounters(_ah) \ 969 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 970#define ath_hal_hasdiversity(_ah) \ 971 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 972#define ath_hal_getdiversity(_ah) \ 973 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 974#define ath_hal_setdiversity(_ah, _v) \ 975 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 976#define ath_hal_getantennaswitch(_ah) \ 977 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 978#define ath_hal_setantennaswitch(_ah, _v) \ 979 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 980#define ath_hal_getdiag(_ah, _pv) \ 981 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 982#define ath_hal_setdiag(_ah, _v) \ 983 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 984#define ath_hal_getnumtxqueues(_ah, _pv) \ 985 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 986#define ath_hal_hasveol(_ah) \ 987 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 988#define ath_hal_hastxpowlimit(_ah) \ 989 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 990#define ath_hal_settxpowlimit(_ah, _pow) \ 991 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 992#define ath_hal_gettxpowlimit(_ah, _ppow) \ 993 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 994#define ath_hal_getmaxtxpow(_ah, _ppow) \ 995 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 996#define ath_hal_gettpscale(_ah, _scale) \ 997 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 998#define ath_hal_settpscale(_ah, _v) \ 999 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1000#define ath_hal_hastpc(_ah) \ 1001 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1002#define ath_hal_gettpc(_ah) \ 1003 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1004#define ath_hal_settpc(_ah, _v) \ 1005 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1006#define ath_hal_hasbursting(_ah) \ 1007 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1008#define ath_hal_setmcastkeysearch(_ah, _v) \ 1009 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1010#define ath_hal_hasmcastkeysearch(_ah) \ 1011 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1012#define ath_hal_getmcastkeysearch(_ah) \ 1013 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1014#define ath_hal_hasfastframes(_ah) \ 1015 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1016#define ath_hal_hasbssidmask(_ah) \ 1017 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1018#define ath_hal_hasbssidmatch(_ah) \ 1019 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1020#define ath_hal_hastsfadjust(_ah) \ 1021 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1022#define ath_hal_gettsfadjust(_ah) \ 1023 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1024#define ath_hal_settsfadjust(_ah, _onoff) \ 1025 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1026#define ath_hal_hasrfsilent(_ah) \ 1027 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1028#define ath_hal_getrfkill(_ah) \ 1029 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1030#define ath_hal_setrfkill(_ah, _onoff) \ 1031 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1032#define ath_hal_getrfsilent(_ah, _prfsilent) \ 1033 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1034#define ath_hal_setrfsilent(_ah, _rfsilent) \ 1035 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1036#define ath_hal_gettpack(_ah, _ptpack) \ 1037 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1038#define ath_hal_settpack(_ah, _tpack) \ 1039 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1040#define ath_hal_gettpcts(_ah, _ptpcts) \ 1041 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1042#define ath_hal_settpcts(_ah, _tpcts) \ 1043 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1044#define ath_hal_hasintmit(_ah) \ 1045 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1046 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1047#define ath_hal_getintmit(_ah) \ 1048 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1049 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1050#define ath_hal_setintmit(_ah, _v) \ 1051 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1052 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1053 1054/* EDMA definitions */ 1055#define ath_hal_hasedma(_ah) \ 1056 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1057 0, NULL) == HAL_OK) 1058#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1059 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1060 == HAL_OK) 1061#define ath_hal_getntxmaps(_ah, _req) \ 1062 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1063 == HAL_OK) 1064#define ath_hal_gettxdesclen(_ah, _req) \ 1065 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1066 == HAL_OK) 1067#define ath_hal_gettxstatuslen(_ah, _req) \ 1068 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1069 == HAL_OK) 1070#define ath_hal_getrxstatuslen(_ah, _req) \ 1071 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1072 == HAL_OK) 1073#define ath_hal_setrxbufsize(_ah, _req) \ 1074 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1075 == HAL_OK) 1076 1077#define ath_hal_getchannoise(_ah, _c) \ 1078 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1079 1080/* 802.11n HAL methods */ 1081#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1082 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1083#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1084 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1085#define ath_hal_setrxchainmask(_ah, _rx) \ 1086 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1087#define ath_hal_settxchainmask(_ah, _tx) \ 1088 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1089#define ath_hal_split4ktrans(_ah) \ 1090 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1091 0, NULL) == HAL_OK) 1092#define ath_hal_self_linked_final_rxdesc(_ah) \ 1093 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1094 0, NULL) == HAL_OK) 1095#define ath_hal_gtxto_supported(_ah) \ 1096 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1097#define ath_hal_has_long_rxdesc_tsf(_ah) \ 1098 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1099 0, NULL) == HAL_OK) 1100#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1101 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1102#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1103 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1104#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1105 _txr0, _txtr0, _keyix, _ant, _flags, \ 1106 _rtsrate, _rtsdura) \ 1107 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1108 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1109 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1110#define ath_hal_setupxtxdesc(_ah, _ds, \ 1111 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1112 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1113 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1114#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1115 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1116 (_first), (_last), (_ds0))) 1117#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1118 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1119#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1120 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1121#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1122 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1123#define ath_hal_settxdesclink(_ah, _ds, _link) \ 1124 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1125#define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1126 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1127#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1128 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1129#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1130 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1131 (_size))) 1132 1133#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1134 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1135 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1136 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1137#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1138 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1139 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1140 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1141 (_first), (_last), (_lastaggr))) 1142#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1143 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1144 1145#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1146 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1147 (_series), (_ns), (_flags))) 1148 1149#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1150 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1151#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1152 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1153#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1154 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1155 1156#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1157 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1158#define ath_hal_clr11n_aggr(_ah, _ds) \ 1159 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1160 1161#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1162 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1163#define ath_hal_gpioset(_ah, _gpio, _b) \ 1164 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1165#define ath_hal_gpioget(_ah, _gpio) \ 1166 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1167#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1168 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1169 1170/* 1171 * PCIe suspend/resume/poweron/poweroff related macros 1172 */ 1173#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1174 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1175#define ath_hal_disablepcie(_ah) \ 1176 ((*(_ah)->ah_disablePCIE)((_ah))) 1177 1178/* 1179 * This is badly-named; you need to set the correct parameters 1180 * to begin to receive useful radar events; and even then 1181 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1182 * more information. 1183 */ 1184#define ath_hal_enabledfs(_ah, _param) \ 1185 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1186#define ath_hal_getdfsthresh(_ah, _param) \ 1187 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1188#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1189 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1190 (_buf), (_event))) 1191#define ath_hal_is_fast_clock_enabled(_ah) \ 1192 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1193#define ath_hal_radar_wait(_ah, _chan) \ 1194 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1195#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1196 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1197#define ath_hal_get_chan_ext_busy(_ah) \ 1198 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1199 1200#endif /* _DEV_ATH_ATHVAR_H */ 1201