if_athvar.h revision 238278
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 238278 2012-07-09 07:19:11Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * There is a separate TX ath_buf pool for management frames. 48 * This ensures that management frames such as probe responses 49 * and BAR frames can be transmitted during periods of high 50 * TX activity. 51 */ 52#define ATH_MGMT_TXBUF 32 53 54/* 55 * 802.11n requires more TX and RX buffers to do AMPDU. 56 */ 57#ifdef ATH_ENABLE_11N 58#define ATH_TXBUF 512 59#define ATH_RXBUF 512 60#endif 61 62#ifndef ATH_RXBUF 63#define ATH_RXBUF 40 /* number of RX buffers */ 64#endif 65#ifndef ATH_TXBUF 66#define ATH_TXBUF 200 /* number of TX buffers */ 67#endif 68#define ATH_BCBUF 4 /* number of beacon buffers */ 69 70#define ATH_TXDESC 10 /* number of descriptors per buffer */ 71#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74 75#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78 79/* 80 * The key cache is used for h/w cipher state and also for 81 * tracking station state such as the current tx antenna. 82 * We also setup a mapping table between key cache slot indices 83 * and station state to short-circuit node lookups on rx. 84 * Different parts have different size key caches. We handle 85 * up to ATH_KEYMAX entries (could dynamically allocate state). 86 */ 87#define ATH_KEYMAX 128 /* max key cache size we handle */ 88#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89 90struct taskqueue; 91struct kthread; 92struct ath_buf; 93 94#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95 96/* 97 * Per-TID state 98 * 99 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100 */ 101struct ath_tid { 102 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103 u_int axq_depth; /* SW queue depth */ 104 char axq_name[48]; /* lock name */ 105 struct ath_node *an; /* pointer to parent */ 106 int tid; /* tid */ 107 int ac; /* which AC gets this trafic */ 108 int hwq_depth; /* how many buffers are on HW */ 109 110 /* 111 * Entry on the ath_txq; when there's traffic 112 * to send 113 */ 114 TAILQ_ENTRY(ath_tid) axq_qelem; 115 int sched; 116 int paused; /* >0 if the TID has been paused */ 117 int addba_tx_pending; /* TX ADDBA pending */ 118 int bar_wait; /* waiting for BAR */ 119 int bar_tx; /* BAR TXed */ 120 121 /* 122 * Is the TID being cleaned up after a transition 123 * from aggregation to non-aggregation? 124 * When this is set to 1, this TID will be paused 125 * and no further traffic will be queued until all 126 * the hardware packets pending for this TID have been 127 * TXed/completed; at which point (non-aggregation) 128 * traffic will resume being TXed. 129 */ 130 int cleanup_inprogress; 131 /* 132 * How many hardware-queued packets are 133 * waiting to be cleaned up. 134 * This is only valid if cleanup_inprogress is 1. 135 */ 136 int incomp; 137 138 /* 139 * The following implements a ring representing 140 * the frames in the current BAW. 141 * To avoid copying the array content each time 142 * the BAW is moved, the baw_head/baw_tail point 143 * to the current BAW begin/end; when the BAW is 144 * shifted the head/tail of the array are also 145 * appropriately shifted. 146 */ 147 /* active tx buffers, beginning at current BAW */ 148 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 149 /* where the baw head is in the array */ 150 int baw_head; 151 /* where the BAW tail is in the array */ 152 int baw_tail; 153}; 154 155/* driver-specific node state */ 156struct ath_node { 157 struct ieee80211_node an_node; /* base class */ 158 u_int8_t an_mgmtrix; /* min h/w rate index */ 159 u_int8_t an_mcastrix; /* mcast h/w rate index */ 160 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 161 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 162 char an_name[32]; /* eg "wlan0_a1" */ 163 struct mtx an_mtx; /* protecting the ath_node state */ 164 /* variable-length rate control state follows */ 165}; 166#define ATH_NODE(ni) ((struct ath_node *)(ni)) 167#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 168 169#define ATH_RSSI_LPF_LEN 10 170#define ATH_RSSI_DUMMY_MARKER 0x127 171#define ATH_EP_MUL(x, mul) ((x) * (mul)) 172#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 173#define ATH_LPF_RSSI(x, y, len) \ 174 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 175#define ATH_RSSI_LPF(x, y) do { \ 176 if ((y) >= -20) \ 177 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 178} while (0) 179#define ATH_EP_RND(x,mul) \ 180 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 181#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 182 183typedef enum { 184 ATH_BUFTYPE_NORMAL = 0, 185 ATH_BUFTYPE_MGMT = 1, 186} ath_buf_type_t; 187 188struct ath_buf { 189 TAILQ_ENTRY(ath_buf) bf_list; 190 struct ath_buf * bf_next; /* next buffer in the aggregate */ 191 int bf_nseg; 192 uint16_t bf_flags; /* status flags (below) */ 193 struct ath_desc *bf_desc; /* virtual addr of desc */ 194 struct ath_desc_status bf_status; /* tx/rx status */ 195 bus_addr_t bf_daddr; /* physical addr of desc */ 196 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 197 struct mbuf *bf_m; /* mbuf for buf */ 198 struct ieee80211_node *bf_node; /* pointer to the node */ 199 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 200 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 201 bus_size_t bf_mapsize; 202#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 203 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 204 205 /* Completion function to call on TX complete (fail or not) */ 206 /* 207 * "fail" here is set to 1 if the queue entries were removed 208 * through a call to ath_tx_draintxq(). 209 */ 210 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 211 212 /* This state is kept to support software retries and aggregation */ 213 struct { 214 uint16_t bfs_seqno; /* sequence number of this packet */ 215 uint16_t bfs_ndelim; /* number of delims for padding */ 216 217 uint8_t bfs_retries; /* retry count */ 218 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 219 uint8_t bfs_nframes; /* number of frames in aggregate */ 220 uint8_t bfs_pri; /* packet AC priority */ 221 222 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 223 224 u_int32_t bfs_aggr:1, /* part of aggregate? */ 225 bfs_aggrburst:1, /* part of aggregate burst? */ 226 bfs_isretried:1, /* retried frame? */ 227 bfs_dobaw:1, /* actually check against BAW? */ 228 bfs_addedbaw:1, /* has been added to the BAW */ 229 bfs_shpream:1, /* use short preamble */ 230 bfs_istxfrag:1, /* is fragmented */ 231 bfs_ismrr:1, /* do multi-rate TX retry */ 232 bfs_doprot:1, /* do RTS/CTS based protection */ 233 bfs_doratelookup:1; /* do rate lookup before each TX */ 234 235 /* 236 * These fields are passed into the 237 * descriptor setup functions. 238 */ 239 240 /* Make this an 8 bit value? */ 241 HAL_PKT_TYPE bfs_atype; /* packet type */ 242 243 uint32_t bfs_pktlen; /* length of this packet */ 244 245 uint16_t bfs_hdrlen; /* length of this packet header */ 246 uint16_t bfs_al; /* length of aggregate */ 247 248 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 249 uint8_t bfs_txrate0; /* first TX rate */ 250 uint8_t bfs_try0; /* first try count */ 251 252 uint16_t bfs_txpower; /* tx power */ 253 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 254 uint8_t bfs_ctsrate; /* CTS rate */ 255 256 /* 16 bit? */ 257 int32_t bfs_keyix; /* crypto key index */ 258 int32_t bfs_txantenna; /* TX antenna config */ 259 260 /* Make this an 8 bit value? */ 261 enum ieee80211_protmode bfs_protmode; 262 263 /* 16 bit? */ 264 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 265 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 266 } bf_state; 267}; 268typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 269 270#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 271#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 272 273/* 274 * DMA state for tx/rx descriptors. 275 */ 276struct ath_descdma { 277 const char* dd_name; 278 struct ath_desc *dd_desc; /* descriptors */ 279 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 280 bus_size_t dd_desc_len; /* size of dd_desc */ 281 bus_dma_segment_t dd_dseg; 282 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 283 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 284 struct ath_buf *dd_bufptr; /* associated buffers */ 285}; 286 287/* 288 * Data transmit queue state. One of these exists for each 289 * hardware transmit queue. Packets sent to us from above 290 * are assigned to queues based on their priority. Not all 291 * devices support a complete set of hardware transmit queues. 292 * For those devices the array sc_ac2q will map multiple 293 * priorities to fewer hardware queues (typically all to one 294 * hardware queue). 295 */ 296struct ath_txq { 297 struct ath_softc *axq_softc; /* Needed for scheduling */ 298 u_int axq_qnum; /* hardware q number */ 299#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 300 u_int axq_ac; /* WME AC */ 301 u_int axq_flags; 302#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 303 u_int axq_depth; /* queue depth (stat only) */ 304 u_int axq_aggr_depth; /* how many aggregates are queued */ 305 u_int axq_intrcnt; /* interrupt count */ 306 u_int32_t *axq_link; /* link ptr in last TX desc */ 307 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 308 struct mtx axq_lock; /* lock on q and link */ 309 char axq_name[12]; /* e.g. "ath0_txq4" */ 310 311 /* Per-TID traffic queue for software -> hardware TX */ 312 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 313}; 314 315#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 316#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 317#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 318 319#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 320 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 321 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 322 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 323} while (0) 324#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 325#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 326#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 327#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 328#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 329 330#define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 331 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 332 333#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 334 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 335 (_tq)->axq_depth++; \ 336} while (0) 337#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 338 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 339 (_tq)->axq_depth++; \ 340} while (0) 341#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 342 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 343 (_tq)->axq_depth--; \ 344} while (0) 345#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 346 347struct ath_vap { 348 struct ieee80211vap av_vap; /* base class */ 349 int av_bslot; /* beacon slot index */ 350 struct ath_buf *av_bcbuf; /* beacon buffer */ 351 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 352 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 353 354 void (*av_recv_mgmt)(struct ieee80211_node *, 355 struct mbuf *, int, int, int); 356 int (*av_newstate)(struct ieee80211vap *, 357 enum ieee80211_state, int); 358 void (*av_bmiss)(struct ieee80211vap *); 359}; 360#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 361 362struct taskqueue; 363struct ath_tx99; 364 365/* 366 * Whether to reset the TX/RX queue with or without 367 * a queue flush. 368 */ 369typedef enum { 370 ATH_RESET_DEFAULT = 0, 371 ATH_RESET_NOLOSS = 1, 372 ATH_RESET_FULL = 2, 373} ATH_RESET_TYPE; 374 375struct ath_rx_methods { 376 void (*recv_stop)(struct ath_softc *sc, int dodelay); 377 int (*recv_start)(struct ath_softc *sc); 378 void (*recv_flush)(struct ath_softc *sc); 379 void (*recv_tasklet)(void *arg, int npending); 380 int (*recv_rxbuf_init)(struct ath_softc *sc, 381 struct ath_buf *bf); 382}; 383 384struct ath_softc { 385 struct ifnet *sc_ifp; /* interface common */ 386 struct ath_stats sc_stats; /* interface statistics */ 387 struct ath_tx_aggr_stats sc_aggr_stats; 388 struct ath_intr_stats sc_intr_stats; 389 uint64_t sc_debug; 390 int sc_nvaps; /* # vaps */ 391 int sc_nstavaps; /* # station vaps */ 392 int sc_nmeshvaps; /* # mbss vaps */ 393 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 394 u_int8_t sc_nbssid0; /* # vap's using base mac */ 395 uint32_t sc_bssidmask; /* bssid mask */ 396 397 struct ath_rx_methods sc_rx; 398 399 void (*sc_node_cleanup)(struct ieee80211_node *); 400 void (*sc_node_free)(struct ieee80211_node *); 401 device_t sc_dev; 402 HAL_BUS_TAG sc_st; /* bus space tag */ 403 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 404 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 405 struct mtx sc_mtx; /* master lock (recursive) */ 406 struct mtx sc_pcu_mtx; /* PCU access mutex */ 407 char sc_pcu_mtx_name[32]; 408 struct taskqueue *sc_tq; /* private task queue */ 409 struct ath_hal *sc_ah; /* Atheros HAL */ 410 struct ath_ratectrl *sc_rc; /* tx rate control support */ 411 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 412 void (*sc_setdefantenna)(struct ath_softc *, u_int); 413 unsigned int sc_invalid : 1,/* disable hardware accesses */ 414 sc_mrretry : 1,/* multi-rate retry support */ 415 sc_softled : 1,/* enable LED gpio status */ 416 sc_hardled : 1,/* enable MAC LED status */ 417 sc_splitmic : 1,/* split TKIP MIC keys */ 418 sc_needmib : 1,/* enable MIB stats intr */ 419 sc_diversity: 1,/* enable rx diversity */ 420 sc_hasveol : 1,/* tx VEOL support */ 421 sc_ledstate : 1,/* LED on/off state */ 422 sc_blinking : 1,/* LED blink operation active */ 423 sc_mcastkey : 1,/* mcast key cache search */ 424 sc_scanning : 1,/* scanning active */ 425 sc_syncbeacon:1,/* sync/resync beacon timers */ 426 sc_hasclrkey: 1,/* CLR key supported */ 427 sc_xchanmode: 1,/* extended channel mode */ 428 sc_outdoor : 1,/* outdoor operation */ 429 sc_dturbo : 1,/* dynamic turbo in use */ 430 sc_hasbmask : 1,/* bssid mask support */ 431 sc_hasbmatch: 1,/* bssid match disable support*/ 432 sc_hastsfadd: 1,/* tsf adjust support */ 433 sc_beacons : 1,/* beacons running */ 434 sc_swbmiss : 1,/* sta mode using sw bmiss */ 435 sc_stagbeacons:1,/* use staggered beacons */ 436 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 437 sc_resume_up: 1,/* on resume, start all vaps */ 438 sc_tdma : 1,/* TDMA in use */ 439 sc_setcca : 1,/* set/clr CCA with TDMA */ 440 sc_resetcal : 1,/* reset cal state next trip */ 441 sc_rxslink : 1,/* do self-linked final descriptor */ 442 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 443 uint32_t sc_eerd; /* regdomain from EEPROM */ 444 uint32_t sc_eecc; /* country code from EEPROM */ 445 /* rate tables */ 446 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 447 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 448 enum ieee80211_phymode sc_curmode; /* current phy mode */ 449 HAL_OPMODE sc_opmode; /* current operating mode */ 450 u_int16_t sc_curtxpow; /* current tx power limit */ 451 u_int16_t sc_curaid; /* current association id */ 452 struct ieee80211_channel *sc_curchan; /* current installed channel */ 453 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 454 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 455 struct { 456 u_int8_t ieeerate; /* IEEE rate */ 457 u_int8_t rxflags; /* radiotap rx flags */ 458 u_int8_t txflags; /* radiotap tx flags */ 459 u_int16_t ledon; /* softled on time */ 460 u_int16_t ledoff; /* softled off time */ 461 } sc_hwmap[32]; /* h/w rate ix mappings */ 462 u_int8_t sc_protrix; /* protection rate index */ 463 u_int8_t sc_lastdatarix; /* last data frame rate index */ 464 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 465 u_int sc_fftxqmin; /* min frames before staging */ 466 u_int sc_fftxqmax; /* max frames before drop */ 467 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 468 469 HAL_INT sc_imask; /* interrupt mask copy */ 470 471 /* 472 * These are modified in the interrupt handler as well as 473 * the task queues and other contexts. Thus these must be 474 * protected by a mutex, or they could clash. 475 * 476 * For now, access to these is behind the ATH_LOCK, 477 * just to save time. 478 */ 479 uint32_t sc_txq_active; /* bitmap of active TXQs */ 480 uint32_t sc_kickpcu; /* whether to kick the PCU */ 481 uint32_t sc_rxproc_cnt; /* In RX processing */ 482 uint32_t sc_txproc_cnt; /* In TX processing */ 483 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 484 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 485 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 486 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 487 488 u_int sc_keymax; /* size of key cache */ 489 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 490 491 /* 492 * Software based LED blinking 493 */ 494 u_int sc_ledpin; /* GPIO pin for driving LED */ 495 u_int sc_ledon; /* pin setting for LED on */ 496 u_int sc_ledidle; /* idle polling interval */ 497 int sc_ledevent; /* time of last LED event */ 498 u_int8_t sc_txrix; /* current tx rate for LED */ 499 u_int16_t sc_ledoff; /* off time for current blink */ 500 struct callout sc_ledtimer; /* led off timer */ 501 502 /* 503 * Hardware based LED blinking 504 */ 505 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 506 int sc_led_net_pin; /* MAC network LED GPIO pin */ 507 508 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 509 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 510 511 struct ath_descdma sc_rxdma; /* RX descriptors */ 512 ath_bufhead sc_rxbuf; /* receive buffer */ 513 struct mbuf *sc_rxpending; /* pending receive data */ 514 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 515 struct task sc_rxtask; /* rx int processing */ 516 u_int8_t sc_defant; /* current default antenna */ 517 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 518 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 519 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 520 struct ath_rx_radiotap_header sc_rx_th; 521 int sc_rx_th_len; 522 u_int sc_monpass; /* frames to pass in mon.mode */ 523 524 struct ath_descdma sc_txdma; /* TX descriptors */ 525 ath_bufhead sc_txbuf; /* transmit buffer */ 526 int sc_txbuf_cnt; /* how many buffers avail */ 527 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 528 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 529 struct mtx sc_txbuflock; /* txbuf lock */ 530 char sc_txname[12]; /* e.g. "ath0_buf" */ 531 u_int sc_txqsetup; /* h/w queues setup */ 532 u_int sc_txintrperiod;/* tx interrupt batching */ 533 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 534 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 535 struct task sc_txtask; /* tx int processing */ 536 struct task sc_txqtask; /* tx proc processing */ 537 int sc_wd_timer; /* count down for wd timer */ 538 struct callout sc_wd_ch; /* tx watchdog timer */ 539 struct ath_tx_radiotap_header sc_tx_th; 540 int sc_tx_th_len; 541 542 struct ath_descdma sc_bdma; /* beacon descriptors */ 543 ath_bufhead sc_bbuf; /* beacon buffers */ 544 u_int sc_bhalq; /* HAL q for outgoing beacons */ 545 u_int sc_bmisscount; /* missed beacon transmits */ 546 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 547 struct ath_txq *sc_cabq; /* tx q for cab frames */ 548 struct task sc_bmisstask; /* bmiss int processing */ 549 struct task sc_bstucktask; /* stuck beacon processing */ 550 struct task sc_resettask; /* interface reset task */ 551 struct task sc_fataltask; /* fatal task */ 552 enum { 553 OK, /* no change needed */ 554 UPDATE, /* update pending */ 555 COMMIT /* beacon sent, commit change */ 556 } sc_updateslot; /* slot time update fsm */ 557 int sc_slotupdate; /* slot to advance fsm */ 558 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 559 int sc_nbcnvaps; /* # vaps with beacons */ 560 561 struct callout sc_cal_ch; /* callout handle for cals */ 562 int sc_lastlongcal; /* last long cal completed */ 563 int sc_lastcalreset;/* last cal reset done */ 564 int sc_lastani; /* last ANI poll */ 565 int sc_lastshortcal; /* last short calibration */ 566 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 567 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 568 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 569 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 570 u_int sc_tdmaswba; /* TDMA SWBA counter */ 571 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 572 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 573 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 574 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 575 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 576 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 577 int sc_txchainmask; /* currently configured TX chainmask */ 578 int sc_rxchainmask; /* currently configured RX chainmask */ 579 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 580 581 /* Queue limits */ 582 583 /* 584 * To avoid queue starvation in congested conditions, 585 * these parameters tune the maximum number of frames 586 * queued to the data/mcastq before they're dropped. 587 * 588 * This is to prevent: 589 * + a single destination overwhelming everything, including 590 * management/multicast frames; 591 * + multicast frames overwhelming everything (when the 592 * air is sufficiently busy that cabq can't drain.) 593 * 594 * These implement: 595 * + data_minfree is the maximum number of free buffers 596 * overall to successfully allow a data frame. 597 * 598 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 599 */ 600 int sc_txq_data_minfree; 601 int sc_txq_mcastq_maxdepth; 602 603 /* 604 * Aggregation twiddles 605 * 606 * hwq_limit: how busy to keep the hardware queue - don't schedule 607 * further packets to the hardware, regardless of the TID 608 * tid_hwq_lo: how low the per-TID hwq count has to be before the 609 * TID will be scheduled again 610 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 611 * stops being scheduled. 612 */ 613 int sc_hwq_limit; 614 int sc_tid_hwq_lo; 615 int sc_tid_hwq_hi; 616 617 /* DFS related state */ 618 void *sc_dfs; /* Used by an optional DFS module */ 619 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 620 struct task sc_dfstask; /* DFS processing task */ 621 622 /* TX AMPDU handling */ 623 int (*sc_addba_request)(struct ieee80211_node *, 624 struct ieee80211_tx_ampdu *, int, int, int); 625 int (*sc_addba_response)(struct ieee80211_node *, 626 struct ieee80211_tx_ampdu *, int, int, int); 627 void (*sc_addba_stop)(struct ieee80211_node *, 628 struct ieee80211_tx_ampdu *); 629 void (*sc_addba_response_timeout) 630 (struct ieee80211_node *, 631 struct ieee80211_tx_ampdu *); 632 void (*sc_bar_response)(struct ieee80211_node *ni, 633 struct ieee80211_tx_ampdu *tap, 634 int status); 635}; 636 637#define ATH_LOCK_INIT(_sc) \ 638 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 639 NULL, MTX_DEF | MTX_RECURSE) 640#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 641#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 642#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 643#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 644#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 645 646/* 647 * The PCU lock is non-recursive and should be treated as a spinlock. 648 * Although currently the interrupt code is run in netisr context and 649 * doesn't require this, this may change in the future. 650 * Please keep this in mind when protecting certain code paths 651 * with the PCU lock. 652 * 653 * The PCU lock is used to serialise access to the PCU so things such 654 * as TX, RX, state change (eg channel change), channel reset and updates 655 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 656 * 657 * Although the current single-thread taskqueue mechanism protects the 658 * majority of these situations by simply serialising them, there are 659 * a few others which occur at the same time. These include the TX path 660 * (which only acquires ATH_LOCK when recycling buffers to the free list), 661 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 662 */ 663#define ATH_PCU_LOCK_INIT(_sc) do {\ 664 snprintf((_sc)->sc_pcu_mtx_name, \ 665 sizeof((_sc)->sc_pcu_mtx_name), \ 666 "%s PCU lock", \ 667 device_get_nameunit((_sc)->sc_dev)); \ 668 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 669 NULL, MTX_DEF); \ 670 } while (0) 671#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 672#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 673#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 674#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 675 MA_OWNED) 676#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 677 MA_NOTOWNED) 678 679#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 680 681#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 682 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 683 device_get_nameunit((_sc)->sc_dev)); \ 684 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 685} while (0) 686#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 687#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 688#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 689#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 690 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 691 692int ath_attach(u_int16_t, struct ath_softc *); 693int ath_detach(struct ath_softc *); 694void ath_resume(struct ath_softc *); 695void ath_suspend(struct ath_softc *); 696void ath_shutdown(struct ath_softc *); 697void ath_intr(void *); 698 699/* 700 * HAL definitions to comply with local coding convention. 701 */ 702#define ath_hal_detach(_ah) \ 703 ((*(_ah)->ah_detach)((_ah))) 704#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 705 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 706#define ath_hal_macversion(_ah) \ 707 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 708#define ath_hal_getratetable(_ah, _mode) \ 709 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 710#define ath_hal_getmac(_ah, _mac) \ 711 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 712#define ath_hal_setmac(_ah, _mac) \ 713 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 714#define ath_hal_getbssidmask(_ah, _mask) \ 715 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 716#define ath_hal_setbssidmask(_ah, _mask) \ 717 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 718#define ath_hal_intrset(_ah, _mask) \ 719 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 720#define ath_hal_intrget(_ah) \ 721 ((*(_ah)->ah_getInterrupts)((_ah))) 722#define ath_hal_intrpend(_ah) \ 723 ((*(_ah)->ah_isInterruptPending)((_ah))) 724#define ath_hal_getisr(_ah, _pmask) \ 725 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 726#define ath_hal_updatetxtriglevel(_ah, _inc) \ 727 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 728#define ath_hal_setpower(_ah, _mode) \ 729 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 730#define ath_hal_keycachesize(_ah) \ 731 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 732#define ath_hal_keyreset(_ah, _ix) \ 733 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 734#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 735 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 736#define ath_hal_keyisvalid(_ah, _ix) \ 737 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 738#define ath_hal_keysetmac(_ah, _ix, _mac) \ 739 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 740#define ath_hal_getrxfilter(_ah) \ 741 ((*(_ah)->ah_getRxFilter)((_ah))) 742#define ath_hal_setrxfilter(_ah, _filter) \ 743 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 744#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 745 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 746#define ath_hal_waitforbeacon(_ah, _bf) \ 747 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 748#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 749 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 750/* NB: common across all chips */ 751#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 752#define ath_hal_gettsf32(_ah) \ 753 OS_REG_READ(_ah, AR_TSF_L32) 754#define ath_hal_gettsf64(_ah) \ 755 ((*(_ah)->ah_getTsf64)((_ah))) 756#define ath_hal_resettsf(_ah) \ 757 ((*(_ah)->ah_resetTsf)((_ah))) 758#define ath_hal_rxena(_ah) \ 759 ((*(_ah)->ah_enableReceive)((_ah))) 760#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 761 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 762#define ath_hal_gettxbuf(_ah, _q) \ 763 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 764#define ath_hal_numtxpending(_ah, _q) \ 765 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 766#define ath_hal_getrxbuf(_ah, _rxq) \ 767 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 768#define ath_hal_txstart(_ah, _q) \ 769 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 770#define ath_hal_setchannel(_ah, _chan) \ 771 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 772#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 773 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 774#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 775 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 776#define ath_hal_calreset(_ah, _chan) \ 777 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 778#define ath_hal_setledstate(_ah, _state) \ 779 ((*(_ah)->ah_setLedState)((_ah), (_state))) 780#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 781 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 782#define ath_hal_beaconreset(_ah) \ 783 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 784#define ath_hal_beaconsettimers(_ah, _bt) \ 785 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 786#define ath_hal_beacontimers(_ah, _bs) \ 787 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 788#define ath_hal_getnexttbtt(_ah) \ 789 ((*(_ah)->ah_getNextTBTT)((_ah))) 790#define ath_hal_setassocid(_ah, _bss, _associd) \ 791 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 792#define ath_hal_phydisable(_ah) \ 793 ((*(_ah)->ah_phyDisable)((_ah))) 794#define ath_hal_setopmode(_ah) \ 795 ((*(_ah)->ah_setPCUConfig)((_ah))) 796#define ath_hal_stoptxdma(_ah, _qnum) \ 797 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 798#define ath_hal_stoppcurecv(_ah) \ 799 ((*(_ah)->ah_stopPcuReceive)((_ah))) 800#define ath_hal_startpcurecv(_ah) \ 801 ((*(_ah)->ah_startPcuReceive)((_ah))) 802#define ath_hal_stopdmarecv(_ah) \ 803 ((*(_ah)->ah_stopDmaReceive)((_ah))) 804#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 805 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 806 (_indata), (_insize), (_outdata), (_outsize))) 807#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 808 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 809#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 810 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 811#define ath_hal_resettxqueue(_ah, _q) \ 812 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 813#define ath_hal_releasetxqueue(_ah, _q) \ 814 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 815#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 816 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 817#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 818 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 819/* NB: common across all chips */ 820#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 821#define ath_hal_txqenabled(_ah, _qnum) \ 822 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 823#define ath_hal_getrfgain(_ah) \ 824 ((*(_ah)->ah_getRfGain)((_ah))) 825#define ath_hal_getdefantenna(_ah) \ 826 ((*(_ah)->ah_getDefAntenna)((_ah))) 827#define ath_hal_setdefantenna(_ah, _ant) \ 828 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 829#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 830 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 831#define ath_hal_ani_poll(_ah, _chan) \ 832 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 833#define ath_hal_mibevent(_ah, _stats) \ 834 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 835#define ath_hal_setslottime(_ah, _us) \ 836 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 837#define ath_hal_getslottime(_ah) \ 838 ((*(_ah)->ah_getSlotTime)((_ah))) 839#define ath_hal_setacktimeout(_ah, _us) \ 840 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 841#define ath_hal_getacktimeout(_ah) \ 842 ((*(_ah)->ah_getAckTimeout)((_ah))) 843#define ath_hal_setctstimeout(_ah, _us) \ 844 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 845#define ath_hal_getctstimeout(_ah) \ 846 ((*(_ah)->ah_getCTSTimeout)((_ah))) 847#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 848 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 849#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 850 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 851#define ath_hal_ciphersupported(_ah, _cipher) \ 852 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 853#define ath_hal_getregdomain(_ah, _prd) \ 854 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 855#define ath_hal_setregdomain(_ah, _rd) \ 856 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 857#define ath_hal_getcountrycode(_ah, _pcc) \ 858 (*(_pcc) = (_ah)->ah_countryCode) 859#define ath_hal_gettkipmic(_ah) \ 860 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 861#define ath_hal_settkipmic(_ah, _v) \ 862 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 863#define ath_hal_hastkipsplit(_ah) \ 864 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 865#define ath_hal_gettkipsplit(_ah) \ 866 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 867#define ath_hal_settkipsplit(_ah, _v) \ 868 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 869#define ath_hal_haswmetkipmic(_ah) \ 870 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 871#define ath_hal_hwphycounters(_ah) \ 872 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 873#define ath_hal_hasdiversity(_ah) \ 874 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 875#define ath_hal_getdiversity(_ah) \ 876 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 877#define ath_hal_setdiversity(_ah, _v) \ 878 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 879#define ath_hal_getantennaswitch(_ah) \ 880 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 881#define ath_hal_setantennaswitch(_ah, _v) \ 882 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 883#define ath_hal_getdiag(_ah, _pv) \ 884 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 885#define ath_hal_setdiag(_ah, _v) \ 886 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 887#define ath_hal_getnumtxqueues(_ah, _pv) \ 888 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 889#define ath_hal_hasveol(_ah) \ 890 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 891#define ath_hal_hastxpowlimit(_ah) \ 892 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 893#define ath_hal_settxpowlimit(_ah, _pow) \ 894 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 895#define ath_hal_gettxpowlimit(_ah, _ppow) \ 896 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 897#define ath_hal_getmaxtxpow(_ah, _ppow) \ 898 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 899#define ath_hal_gettpscale(_ah, _scale) \ 900 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 901#define ath_hal_settpscale(_ah, _v) \ 902 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 903#define ath_hal_hastpc(_ah) \ 904 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 905#define ath_hal_gettpc(_ah) \ 906 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 907#define ath_hal_settpc(_ah, _v) \ 908 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 909#define ath_hal_hasbursting(_ah) \ 910 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 911#define ath_hal_setmcastkeysearch(_ah, _v) \ 912 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 913#define ath_hal_hasmcastkeysearch(_ah) \ 914 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 915#define ath_hal_getmcastkeysearch(_ah) \ 916 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 917#define ath_hal_hasfastframes(_ah) \ 918 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 919#define ath_hal_hasbssidmask(_ah) \ 920 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 921#define ath_hal_hasbssidmatch(_ah) \ 922 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 923#define ath_hal_hastsfadjust(_ah) \ 924 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 925#define ath_hal_gettsfadjust(_ah) \ 926 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 927#define ath_hal_settsfadjust(_ah, _onoff) \ 928 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 929#define ath_hal_hasrfsilent(_ah) \ 930 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 931#define ath_hal_getrfkill(_ah) \ 932 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 933#define ath_hal_setrfkill(_ah, _onoff) \ 934 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 935#define ath_hal_getrfsilent(_ah, _prfsilent) \ 936 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 937#define ath_hal_setrfsilent(_ah, _rfsilent) \ 938 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 939#define ath_hal_gettpack(_ah, _ptpack) \ 940 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 941#define ath_hal_settpack(_ah, _tpack) \ 942 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 943#define ath_hal_gettpcts(_ah, _ptpcts) \ 944 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 945#define ath_hal_settpcts(_ah, _tpcts) \ 946 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 947#define ath_hal_hasintmit(_ah) \ 948 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 949 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 950#define ath_hal_getintmit(_ah) \ 951 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 952 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 953#define ath_hal_setintmit(_ah, _v) \ 954 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 955 HAL_CAP_INTMIT_ENABLE, _v, NULL) 956#define ath_hal_hasedma(_ah) \ 957 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 958 0, NULL) == HAL_OK) 959#define ath_hal_getchannoise(_ah, _c) \ 960 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 961#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 962 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 963#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 964 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 965#define ath_hal_setrxchainmask(_ah, _rx) \ 966 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 967#define ath_hal_settxchainmask(_ah, _tx) \ 968 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 969#define ath_hal_split4ktrans(_ah) \ 970 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 971 0, NULL) == HAL_OK) 972#define ath_hal_self_linked_final_rxdesc(_ah) \ 973 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 974 0, NULL) == HAL_OK) 975#define ath_hal_gtxto_supported(_ah) \ 976 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 977#define ath_hal_has_long_rxdesc_tsf(_ah) \ 978 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 979 0, NULL) == HAL_OK) 980#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 981 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 982#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 983 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 984#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 985 _txr0, _txtr0, _keyix, _ant, _flags, \ 986 _rtsrate, _rtsdura) \ 987 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 988 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 989 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 990#define ath_hal_setupxtxdesc(_ah, _ds, \ 991 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 992 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 993 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 994#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 995 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 996#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 997 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 998#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 999 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1000#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1001 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1002 1003#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1004 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1005 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1006 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1007#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 1008 _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 1009 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 1010 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 1011 (_first), (_last), (_lastaggr))) 1012#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1013 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1014 1015#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1016 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1017 (_series), (_ns), (_flags))) 1018 1019#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1020 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1021#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1022 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1023#define ath_hal_set11n_aggr_last(_ah, _ds) \ 1024 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1025 1026#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1027 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1028#define ath_hal_clr11n_aggr(_ah, _ds) \ 1029 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1030 1031#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1032 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1033#define ath_hal_gpioset(_ah, _gpio, _b) \ 1034 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1035#define ath_hal_gpioget(_ah, _gpio) \ 1036 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1037#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1038 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1039 1040/* 1041 * PCIe suspend/resume/poweron/poweroff related macros 1042 */ 1043#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1044 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1045#define ath_hal_disablepcie(_ah) \ 1046 ((*(_ah)->ah_disablePCIE)((_ah))) 1047 1048/* 1049 * This is badly-named; you need to set the correct parameters 1050 * to begin to receive useful radar events; and even then 1051 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1052 * more information. 1053 */ 1054#define ath_hal_enabledfs(_ah, _param) \ 1055 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1056#define ath_hal_getdfsthresh(_ah, _param) \ 1057 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1058#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1059 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1060 (_buf), (_event))) 1061#define ath_hal_is_fast_clock_enabled(_ah) \ 1062 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1063#define ath_hal_radar_wait(_ah, _chan) \ 1064 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1065#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1066 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1067#define ath_hal_get_chan_ext_busy(_ah) \ 1068 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1069 1070#endif /* _DEV_ATH_ATHVAR_H */ 1071