if_athvar.h revision 236872
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 236872 2012-06-11 06:59:28Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * 802.11n requires more TX and RX buffers to do AMPDU. 48 */ 49#ifdef ATH_ENABLE_11N 50#define ATH_TXBUF 512 51#define ATH_RXBUF 512 52#endif 53 54#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 200 /* number of TX buffers */ 59#endif 60#define ATH_BCBUF 4 /* number of beacon buffers */ 61 62#define ATH_TXDESC 10 /* number of descriptors per buffer */ 63#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66 67#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 68#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70 71/* 72 * The key cache is used for h/w cipher state and also for 73 * tracking station state such as the current tx antenna. 74 * We also setup a mapping table between key cache slot indices 75 * and station state to short-circuit node lookups on rx. 76 * Different parts have different size key caches. We handle 77 * up to ATH_KEYMAX entries (could dynamically allocate state). 78 */ 79#define ATH_KEYMAX 128 /* max key cache size we handle */ 80#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81 82struct taskqueue; 83struct kthread; 84struct ath_buf; 85 86#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 87 88/* 89 * Per-TID state 90 * 91 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 92 */ 93struct ath_tid { 94 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 95 u_int axq_depth; /* SW queue depth */ 96 char axq_name[48]; /* lock name */ 97 struct ath_node *an; /* pointer to parent */ 98 int tid; /* tid */ 99 int ac; /* which AC gets this trafic */ 100 int hwq_depth; /* how many buffers are on HW */ 101 102 /* 103 * Entry on the ath_txq; when there's traffic 104 * to send 105 */ 106 TAILQ_ENTRY(ath_tid) axq_qelem; 107 int sched; 108 int paused; /* >0 if the TID has been paused */ 109 int addba_tx_pending; /* TX ADDBA pending */ 110 int bar_wait; /* waiting for BAR */ 111 int bar_tx; /* BAR TXed */ 112 113 /* 114 * Is the TID being cleaned up after a transition 115 * from aggregation to non-aggregation? 116 * When this is set to 1, this TID will be paused 117 * and no further traffic will be queued until all 118 * the hardware packets pending for this TID have been 119 * TXed/completed; at which point (non-aggregation) 120 * traffic will resume being TXed. 121 */ 122 int cleanup_inprogress; 123 /* 124 * How many hardware-queued packets are 125 * waiting to be cleaned up. 126 * This is only valid if cleanup_inprogress is 1. 127 */ 128 int incomp; 129 130 /* 131 * The following implements a ring representing 132 * the frames in the current BAW. 133 * To avoid copying the array content each time 134 * the BAW is moved, the baw_head/baw_tail point 135 * to the current BAW begin/end; when the BAW is 136 * shifted the head/tail of the array are also 137 * appropriately shifted. 138 */ 139 /* active tx buffers, beginning at current BAW */ 140 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 141 /* where the baw head is in the array */ 142 int baw_head; 143 /* where the BAW tail is in the array */ 144 int baw_tail; 145}; 146 147/* driver-specific node state */ 148struct ath_node { 149 struct ieee80211_node an_node; /* base class */ 150 u_int8_t an_mgmtrix; /* min h/w rate index */ 151 u_int8_t an_mcastrix; /* mcast h/w rate index */ 152 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 153 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 154 char an_name[32]; /* eg "wlan0_a1" */ 155 struct mtx an_mtx; /* protecting the ath_node state */ 156 /* variable-length rate control state follows */ 157}; 158#define ATH_NODE(ni) ((struct ath_node *)(ni)) 159#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 160 161#define ATH_RSSI_LPF_LEN 10 162#define ATH_RSSI_DUMMY_MARKER 0x127 163#define ATH_EP_MUL(x, mul) ((x) * (mul)) 164#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 165#define ATH_LPF_RSSI(x, y, len) \ 166 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 167#define ATH_RSSI_LPF(x, y) do { \ 168 if ((y) >= -20) \ 169 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 170} while (0) 171#define ATH_EP_RND(x,mul) \ 172 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 173#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 174 175struct ath_buf { 176 TAILQ_ENTRY(ath_buf) bf_list; 177 struct ath_buf * bf_next; /* next buffer in the aggregate */ 178 int bf_nseg; 179 uint16_t bf_flags; /* status flags (below) */ 180 struct ath_desc *bf_desc; /* virtual addr of desc */ 181 struct ath_desc_status bf_status; /* tx/rx status */ 182 bus_addr_t bf_daddr; /* physical addr of desc */ 183 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 184 struct mbuf *bf_m; /* mbuf for buf */ 185 struct ieee80211_node *bf_node; /* pointer to the node */ 186 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 187 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 188 bus_size_t bf_mapsize; 189#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 190 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 191 192 /* Completion function to call on TX complete (fail or not) */ 193 /* 194 * "fail" here is set to 1 if the queue entries were removed 195 * through a call to ath_tx_draintxq(). 196 */ 197 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 198 199 /* This state is kept to support software retries and aggregation */ 200 struct { 201 int bfs_seqno; /* sequence number of this packet */ 202 int bfs_retries; /* retry count */ 203 uint16_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 204 uint16_t bfs_pri; /* packet AC priority */ 205 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 206 uint16_t bfs_pktdur; /* packet duration (at current rate?) */ 207 uint16_t bfs_nframes; /* number of frames in aggregate */ 208 uint16_t bfs_ndelim; /* number of delims for padding */ 209 210 u_int32_t bfs_aggr:1, /* part of aggregate? */ 211 bfs_aggrburst:1, /* part of aggregate burst? */ 212 bfs_isretried:1, /* retried frame? */ 213 bfs_dobaw:1, /* actually check against BAW? */ 214 bfs_addedbaw:1, /* has been added to the BAW */ 215 bfs_shpream:1, /* use short preamble */ 216 bfs_istxfrag:1, /* is fragmented */ 217 bfs_ismrr:1, /* do multi-rate TX retry */ 218 bfs_doprot:1, /* do RTS/CTS based protection */ 219 bfs_doratelookup:1; /* do rate lookup before each TX */ 220 221 int bfs_nfl; /* next fragment length */ 222 223 /* 224 * These fields are passed into the 225 * descriptor setup functions. 226 */ 227 HAL_PKT_TYPE bfs_atype; /* packet type */ 228 int bfs_pktlen; /* length of this packet */ 229 int bfs_hdrlen; /* length of this packet header */ 230 uint16_t bfs_al; /* length of aggregate */ 231 int bfs_txflags; /* HAL (tx) descriptor flags */ 232 int bfs_txrate0; /* first TX rate */ 233 int bfs_try0; /* first try count */ 234 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 235 int bfs_keyix; /* crypto key index */ 236 int bfs_txpower; /* tx power */ 237 int bfs_txantenna; /* TX antenna config */ 238 enum ieee80211_protmode bfs_protmode; 239 int bfs_ctsrate; /* CTS rate */ 240 int bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 241 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 242 } bf_state; 243}; 244typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 245 246#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 247 248/* 249 * DMA state for tx/rx descriptors. 250 */ 251struct ath_descdma { 252 const char* dd_name; 253 struct ath_desc *dd_desc; /* descriptors */ 254 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 255 bus_size_t dd_desc_len; /* size of dd_desc */ 256 bus_dma_segment_t dd_dseg; 257 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 258 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 259 struct ath_buf *dd_bufptr; /* associated buffers */ 260}; 261 262/* 263 * Data transmit queue state. One of these exists for each 264 * hardware transmit queue. Packets sent to us from above 265 * are assigned to queues based on their priority. Not all 266 * devices support a complete set of hardware transmit queues. 267 * For those devices the array sc_ac2q will map multiple 268 * priorities to fewer hardware queues (typically all to one 269 * hardware queue). 270 */ 271struct ath_txq { 272 struct ath_softc *axq_softc; /* Needed for scheduling */ 273 u_int axq_qnum; /* hardware q number */ 274#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 275 u_int axq_ac; /* WME AC */ 276 u_int axq_flags; 277#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 278 u_int axq_depth; /* queue depth (stat only) */ 279 u_int axq_aggr_depth; /* how many aggregates are queued */ 280 u_int axq_intrcnt; /* interrupt count */ 281 u_int32_t *axq_link; /* link ptr in last TX desc */ 282 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 283 struct mtx axq_lock; /* lock on q and link */ 284 char axq_name[12]; /* e.g. "ath0_txq4" */ 285 286 /* Per-TID traffic queue for software -> hardware TX */ 287 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 288}; 289 290#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 291#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 292#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 293 294#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 295 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 296 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 297 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 298} while (0) 299#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 300#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 301#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 302#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 303#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 304 305#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 306 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 307 (_tq)->axq_depth++; \ 308} while (0) 309#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 310 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 311 (_tq)->axq_depth++; \ 312} while (0) 313#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 314 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 315 (_tq)->axq_depth--; \ 316} while (0) 317#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 318 319struct ath_vap { 320 struct ieee80211vap av_vap; /* base class */ 321 int av_bslot; /* beacon slot index */ 322 struct ath_buf *av_bcbuf; /* beacon buffer */ 323 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 324 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 325 326 void (*av_recv_mgmt)(struct ieee80211_node *, 327 struct mbuf *, int, int, int); 328 int (*av_newstate)(struct ieee80211vap *, 329 enum ieee80211_state, int); 330 void (*av_bmiss)(struct ieee80211vap *); 331}; 332#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 333 334struct taskqueue; 335struct ath_tx99; 336 337/* 338 * Whether to reset the TX/RX queue with or without 339 * a queue flush. 340 */ 341typedef enum { 342 ATH_RESET_DEFAULT = 0, 343 ATH_RESET_NOLOSS = 1, 344 ATH_RESET_FULL = 2, 345} ATH_RESET_TYPE; 346 347struct ath_softc { 348 struct ifnet *sc_ifp; /* interface common */ 349 struct ath_stats sc_stats; /* interface statistics */ 350 struct ath_tx_aggr_stats sc_aggr_stats; 351 struct ath_intr_stats sc_intr_stats; 352 uint64_t sc_debug; 353 int sc_nvaps; /* # vaps */ 354 int sc_nstavaps; /* # station vaps */ 355 int sc_nmeshvaps; /* # mbss vaps */ 356 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 357 u_int8_t sc_nbssid0; /* # vap's using base mac */ 358 uint32_t sc_bssidmask; /* bssid mask */ 359 360 void (*sc_node_cleanup)(struct ieee80211_node *); 361 void (*sc_node_free)(struct ieee80211_node *); 362 device_t sc_dev; 363 HAL_BUS_TAG sc_st; /* bus space tag */ 364 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 365 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 366 struct mtx sc_mtx; /* master lock (recursive) */ 367 struct mtx sc_pcu_mtx; /* PCU access mutex */ 368 char sc_pcu_mtx_name[32]; 369 struct taskqueue *sc_tq; /* private task queue */ 370 struct ath_hal *sc_ah; /* Atheros HAL */ 371 struct ath_ratectrl *sc_rc; /* tx rate control support */ 372 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 373 void (*sc_setdefantenna)(struct ath_softc *, u_int); 374 unsigned int sc_invalid : 1,/* disable hardware accesses */ 375 sc_mrretry : 1,/* multi-rate retry support */ 376 sc_softled : 1,/* enable LED gpio status */ 377 sc_hardled : 1,/* enable MAC LED status */ 378 sc_splitmic : 1,/* split TKIP MIC keys */ 379 sc_needmib : 1,/* enable MIB stats intr */ 380 sc_diversity: 1,/* enable rx diversity */ 381 sc_hasveol : 1,/* tx VEOL support */ 382 sc_ledstate : 1,/* LED on/off state */ 383 sc_blinking : 1,/* LED blink operation active */ 384 sc_mcastkey : 1,/* mcast key cache search */ 385 sc_scanning : 1,/* scanning active */ 386 sc_syncbeacon:1,/* sync/resync beacon timers */ 387 sc_hasclrkey: 1,/* CLR key supported */ 388 sc_xchanmode: 1,/* extended channel mode */ 389 sc_outdoor : 1,/* outdoor operation */ 390 sc_dturbo : 1,/* dynamic turbo in use */ 391 sc_hasbmask : 1,/* bssid mask support */ 392 sc_hasbmatch: 1,/* bssid match disable support*/ 393 sc_hastsfadd: 1,/* tsf adjust support */ 394 sc_beacons : 1,/* beacons running */ 395 sc_swbmiss : 1,/* sta mode using sw bmiss */ 396 sc_stagbeacons:1,/* use staggered beacons */ 397 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 398 sc_resume_up: 1,/* on resume, start all vaps */ 399 sc_tdma : 1,/* TDMA in use */ 400 sc_setcca : 1,/* set/clr CCA with TDMA */ 401 sc_resetcal : 1,/* reset cal state next trip */ 402 sc_rxslink : 1,/* do self-linked final descriptor */ 403 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 404 uint32_t sc_eerd; /* regdomain from EEPROM */ 405 uint32_t sc_eecc; /* country code from EEPROM */ 406 /* rate tables */ 407 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 408 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 409 enum ieee80211_phymode sc_curmode; /* current phy mode */ 410 HAL_OPMODE sc_opmode; /* current operating mode */ 411 u_int16_t sc_curtxpow; /* current tx power limit */ 412 u_int16_t sc_curaid; /* current association id */ 413 struct ieee80211_channel *sc_curchan; /* current installed channel */ 414 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 415 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 416 struct { 417 u_int8_t ieeerate; /* IEEE rate */ 418 u_int8_t rxflags; /* radiotap rx flags */ 419 u_int8_t txflags; /* radiotap tx flags */ 420 u_int16_t ledon; /* softled on time */ 421 u_int16_t ledoff; /* softled off time */ 422 } sc_hwmap[32]; /* h/w rate ix mappings */ 423 u_int8_t sc_protrix; /* protection rate index */ 424 u_int8_t sc_lastdatarix; /* last data frame rate index */ 425 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 426 u_int sc_fftxqmin; /* min frames before staging */ 427 u_int sc_fftxqmax; /* max frames before drop */ 428 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 429 430 HAL_INT sc_imask; /* interrupt mask copy */ 431 432 /* 433 * These are modified in the interrupt handler as well as 434 * the task queues and other contexts. Thus these must be 435 * protected by a mutex, or they could clash. 436 * 437 * For now, access to these is behind the ATH_LOCK, 438 * just to save time. 439 */ 440 uint32_t sc_txq_active; /* bitmap of active TXQs */ 441 uint32_t sc_kickpcu; /* whether to kick the PCU */ 442 uint32_t sc_rxproc_cnt; /* In RX processing */ 443 uint32_t sc_txproc_cnt; /* In TX processing */ 444 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 445 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 446 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 447 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 448 449 u_int sc_keymax; /* size of key cache */ 450 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 451 452 /* 453 * Software based LED blinking 454 */ 455 u_int sc_ledpin; /* GPIO pin for driving LED */ 456 u_int sc_ledon; /* pin setting for LED on */ 457 u_int sc_ledidle; /* idle polling interval */ 458 int sc_ledevent; /* time of last LED event */ 459 u_int8_t sc_txrix; /* current tx rate for LED */ 460 u_int16_t sc_ledoff; /* off time for current blink */ 461 struct callout sc_ledtimer; /* led off timer */ 462 463 /* 464 * Hardware based LED blinking 465 */ 466 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 467 int sc_led_net_pin; /* MAC network LED GPIO pin */ 468 469 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 470 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 471 472 struct ath_descdma sc_rxdma; /* RX descriptors */ 473 ath_bufhead sc_rxbuf; /* receive buffer */ 474 struct mbuf *sc_rxpending; /* pending receive data */ 475 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 476 struct task sc_rxtask; /* rx int processing */ 477 u_int8_t sc_defant; /* current default antenna */ 478 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 479 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 480 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 481 struct ath_rx_radiotap_header sc_rx_th; 482 int sc_rx_th_len; 483 u_int sc_monpass; /* frames to pass in mon.mode */ 484 485 struct ath_descdma sc_txdma; /* TX descriptors */ 486 ath_bufhead sc_txbuf; /* transmit buffer */ 487 struct mtx sc_txbuflock; /* txbuf lock */ 488 char sc_txname[12]; /* e.g. "ath0_buf" */ 489 u_int sc_txqsetup; /* h/w queues setup */ 490 u_int sc_txintrperiod;/* tx interrupt batching */ 491 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 492 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 493 struct task sc_txtask; /* tx int processing */ 494 struct task sc_txqtask; /* tx proc processing */ 495 int sc_wd_timer; /* count down for wd timer */ 496 struct callout sc_wd_ch; /* tx watchdog timer */ 497 struct ath_tx_radiotap_header sc_tx_th; 498 int sc_tx_th_len; 499 500 struct ath_descdma sc_bdma; /* beacon descriptors */ 501 ath_bufhead sc_bbuf; /* beacon buffers */ 502 u_int sc_bhalq; /* HAL q for outgoing beacons */ 503 u_int sc_bmisscount; /* missed beacon transmits */ 504 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 505 struct ath_txq *sc_cabq; /* tx q for cab frames */ 506 struct task sc_bmisstask; /* bmiss int processing */ 507 struct task sc_bstucktask; /* stuck beacon processing */ 508 struct task sc_resettask; /* interface reset task */ 509 struct task sc_fataltask; /* fatal task */ 510 enum { 511 OK, /* no change needed */ 512 UPDATE, /* update pending */ 513 COMMIT /* beacon sent, commit change */ 514 } sc_updateslot; /* slot time update fsm */ 515 int sc_slotupdate; /* slot to advance fsm */ 516 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 517 int sc_nbcnvaps; /* # vaps with beacons */ 518 519 struct callout sc_cal_ch; /* callout handle for cals */ 520 int sc_lastlongcal; /* last long cal completed */ 521 int sc_lastcalreset;/* last cal reset done */ 522 int sc_lastani; /* last ANI poll */ 523 int sc_lastshortcal; /* last short calibration */ 524 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 525 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 526 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 527 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 528 u_int sc_tdmaswba; /* TDMA SWBA counter */ 529 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 530 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 531 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 532 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 533 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 534 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 535 int sc_txchainmask; /* currently configured TX chainmask */ 536 int sc_rxchainmask; /* currently configured RX chainmask */ 537 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 538 539 /* Queue limits */ 540 541 /* 542 * To avoid queue starvation in congested conditions, 543 * these parameters tune the maximum number of frames 544 * queued to the data/mcastq before they're dropped. 545 * 546 * This is to prevent: 547 * + a single destination overwhelming everything, including 548 * management/multicast frames; 549 * + multicast frames overwhelming everything (when the 550 * air is sufficiently busy that cabq can't drain.) 551 * 552 * These implement: 553 * + data_minfree is the maximum number of free buffers 554 * overall to successfully allow a data frame. 555 * 556 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 557 */ 558 int sc_txq_data_minfree; 559 int sc_txq_mcastq_maxdepth; 560 561 /* 562 * Aggregation twiddles 563 * 564 * hwq_limit: how busy to keep the hardware queue - don't schedule 565 * further packets to the hardware, regardless of the TID 566 * tid_hwq_lo: how low the per-TID hwq count has to be before the 567 * TID will be scheduled again 568 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 569 * stops being scheduled. 570 */ 571 int sc_hwq_limit; 572 int sc_tid_hwq_lo; 573 int sc_tid_hwq_hi; 574 575 /* DFS related state */ 576 void *sc_dfs; /* Used by an optional DFS module */ 577 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 578 struct task sc_dfstask; /* DFS processing task */ 579 580 /* TX AMPDU handling */ 581 int (*sc_addba_request)(struct ieee80211_node *, 582 struct ieee80211_tx_ampdu *, int, int, int); 583 int (*sc_addba_response)(struct ieee80211_node *, 584 struct ieee80211_tx_ampdu *, int, int, int); 585 void (*sc_addba_stop)(struct ieee80211_node *, 586 struct ieee80211_tx_ampdu *); 587 void (*sc_addba_response_timeout) 588 (struct ieee80211_node *, 589 struct ieee80211_tx_ampdu *); 590 void (*sc_bar_response)(struct ieee80211_node *ni, 591 struct ieee80211_tx_ampdu *tap, 592 int status); 593}; 594 595#define ATH_LOCK_INIT(_sc) \ 596 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 597 NULL, MTX_DEF | MTX_RECURSE) 598#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 599#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 600#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 601#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 602#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 603 604/* 605 * The PCU lock is non-recursive and should be treated as a spinlock. 606 * Although currently the interrupt code is run in netisr context and 607 * doesn't require this, this may change in the future. 608 * Please keep this in mind when protecting certain code paths 609 * with the PCU lock. 610 * 611 * The PCU lock is used to serialise access to the PCU so things such 612 * as TX, RX, state change (eg channel change), channel reset and updates 613 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 614 * 615 * Although the current single-thread taskqueue mechanism protects the 616 * majority of these situations by simply serialising them, there are 617 * a few others which occur at the same time. These include the TX path 618 * (which only acquires ATH_LOCK when recycling buffers to the free list), 619 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 620 */ 621#define ATH_PCU_LOCK_INIT(_sc) do {\ 622 snprintf((_sc)->sc_pcu_mtx_name, \ 623 sizeof((_sc)->sc_pcu_mtx_name), \ 624 "%s PCU lock", \ 625 device_get_nameunit((_sc)->sc_dev)); \ 626 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 627 NULL, MTX_DEF); \ 628 } while (0) 629#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 630#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 631#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 632#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 633 MA_OWNED) 634#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 635 MA_NOTOWNED) 636 637#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 638 639#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 640 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 641 device_get_nameunit((_sc)->sc_dev)); \ 642 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 643} while (0) 644#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 645#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 646#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 647#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 648 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 649 650int ath_attach(u_int16_t, struct ath_softc *); 651int ath_detach(struct ath_softc *); 652void ath_resume(struct ath_softc *); 653void ath_suspend(struct ath_softc *); 654void ath_shutdown(struct ath_softc *); 655void ath_intr(void *); 656 657/* 658 * HAL definitions to comply with local coding convention. 659 */ 660#define ath_hal_detach(_ah) \ 661 ((*(_ah)->ah_detach)((_ah))) 662#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 663 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 664#define ath_hal_macversion(_ah) \ 665 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 666#define ath_hal_getratetable(_ah, _mode) \ 667 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 668#define ath_hal_getmac(_ah, _mac) \ 669 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 670#define ath_hal_setmac(_ah, _mac) \ 671 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 672#define ath_hal_getbssidmask(_ah, _mask) \ 673 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 674#define ath_hal_setbssidmask(_ah, _mask) \ 675 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 676#define ath_hal_intrset(_ah, _mask) \ 677 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 678#define ath_hal_intrget(_ah) \ 679 ((*(_ah)->ah_getInterrupts)((_ah))) 680#define ath_hal_intrpend(_ah) \ 681 ((*(_ah)->ah_isInterruptPending)((_ah))) 682#define ath_hal_getisr(_ah, _pmask) \ 683 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 684#define ath_hal_updatetxtriglevel(_ah, _inc) \ 685 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 686#define ath_hal_setpower(_ah, _mode) \ 687 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 688#define ath_hal_keycachesize(_ah) \ 689 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 690#define ath_hal_keyreset(_ah, _ix) \ 691 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 692#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 693 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 694#define ath_hal_keyisvalid(_ah, _ix) \ 695 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 696#define ath_hal_keysetmac(_ah, _ix, _mac) \ 697 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 698#define ath_hal_getrxfilter(_ah) \ 699 ((*(_ah)->ah_getRxFilter)((_ah))) 700#define ath_hal_setrxfilter(_ah, _filter) \ 701 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 702#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 703 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 704#define ath_hal_waitforbeacon(_ah, _bf) \ 705 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 706#define ath_hal_putrxbuf(_ah, _bufaddr) \ 707 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 708/* NB: common across all chips */ 709#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 710#define ath_hal_gettsf32(_ah) \ 711 OS_REG_READ(_ah, AR_TSF_L32) 712#define ath_hal_gettsf64(_ah) \ 713 ((*(_ah)->ah_getTsf64)((_ah))) 714#define ath_hal_resettsf(_ah) \ 715 ((*(_ah)->ah_resetTsf)((_ah))) 716#define ath_hal_rxena(_ah) \ 717 ((*(_ah)->ah_enableReceive)((_ah))) 718#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 719 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 720#define ath_hal_gettxbuf(_ah, _q) \ 721 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 722#define ath_hal_numtxpending(_ah, _q) \ 723 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 724#define ath_hal_getrxbuf(_ah) \ 725 ((*(_ah)->ah_getRxDP)((_ah))) 726#define ath_hal_txstart(_ah, _q) \ 727 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 728#define ath_hal_setchannel(_ah, _chan) \ 729 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 730#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 731 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 732#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 733 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 734#define ath_hal_calreset(_ah, _chan) \ 735 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 736#define ath_hal_setledstate(_ah, _state) \ 737 ((*(_ah)->ah_setLedState)((_ah), (_state))) 738#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 739 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 740#define ath_hal_beaconreset(_ah) \ 741 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 742#define ath_hal_beaconsettimers(_ah, _bt) \ 743 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 744#define ath_hal_beacontimers(_ah, _bs) \ 745 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 746#define ath_hal_getnexttbtt(_ah) \ 747 ((*(_ah)->ah_getNextTBTT)((_ah))) 748#define ath_hal_setassocid(_ah, _bss, _associd) \ 749 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 750#define ath_hal_phydisable(_ah) \ 751 ((*(_ah)->ah_phyDisable)((_ah))) 752#define ath_hal_setopmode(_ah) \ 753 ((*(_ah)->ah_setPCUConfig)((_ah))) 754#define ath_hal_stoptxdma(_ah, _qnum) \ 755 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 756#define ath_hal_stoppcurecv(_ah) \ 757 ((*(_ah)->ah_stopPcuReceive)((_ah))) 758#define ath_hal_startpcurecv(_ah) \ 759 ((*(_ah)->ah_startPcuReceive)((_ah))) 760#define ath_hal_stopdmarecv(_ah) \ 761 ((*(_ah)->ah_stopDmaReceive)((_ah))) 762#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 763 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 764 (_indata), (_insize), (_outdata), (_outsize))) 765#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 766 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 767#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 768 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 769#define ath_hal_resettxqueue(_ah, _q) \ 770 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 771#define ath_hal_releasetxqueue(_ah, _q) \ 772 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 773#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 774 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 775#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 776 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 777/* NB: common across all chips */ 778#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 779#define ath_hal_txqenabled(_ah, _qnum) \ 780 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 781#define ath_hal_getrfgain(_ah) \ 782 ((*(_ah)->ah_getRfGain)((_ah))) 783#define ath_hal_getdefantenna(_ah) \ 784 ((*(_ah)->ah_getDefAntenna)((_ah))) 785#define ath_hal_setdefantenna(_ah, _ant) \ 786 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 787#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 788 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 789#define ath_hal_ani_poll(_ah, _chan) \ 790 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 791#define ath_hal_mibevent(_ah, _stats) \ 792 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 793#define ath_hal_setslottime(_ah, _us) \ 794 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 795#define ath_hal_getslottime(_ah) \ 796 ((*(_ah)->ah_getSlotTime)((_ah))) 797#define ath_hal_setacktimeout(_ah, _us) \ 798 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 799#define ath_hal_getacktimeout(_ah) \ 800 ((*(_ah)->ah_getAckTimeout)((_ah))) 801#define ath_hal_setctstimeout(_ah, _us) \ 802 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 803#define ath_hal_getctstimeout(_ah) \ 804 ((*(_ah)->ah_getCTSTimeout)((_ah))) 805#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 806 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 807#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 808 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 809#define ath_hal_ciphersupported(_ah, _cipher) \ 810 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 811#define ath_hal_getregdomain(_ah, _prd) \ 812 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 813#define ath_hal_setregdomain(_ah, _rd) \ 814 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 815#define ath_hal_getcountrycode(_ah, _pcc) \ 816 (*(_pcc) = (_ah)->ah_countryCode) 817#define ath_hal_gettkipmic(_ah) \ 818 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 819#define ath_hal_settkipmic(_ah, _v) \ 820 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 821#define ath_hal_hastkipsplit(_ah) \ 822 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 823#define ath_hal_gettkipsplit(_ah) \ 824 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 825#define ath_hal_settkipsplit(_ah, _v) \ 826 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 827#define ath_hal_haswmetkipmic(_ah) \ 828 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 829#define ath_hal_hwphycounters(_ah) \ 830 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 831#define ath_hal_hasdiversity(_ah) \ 832 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 833#define ath_hal_getdiversity(_ah) \ 834 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 835#define ath_hal_setdiversity(_ah, _v) \ 836 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 837#define ath_hal_getantennaswitch(_ah) \ 838 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 839#define ath_hal_setantennaswitch(_ah, _v) \ 840 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 841#define ath_hal_getdiag(_ah, _pv) \ 842 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 843#define ath_hal_setdiag(_ah, _v) \ 844 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 845#define ath_hal_getnumtxqueues(_ah, _pv) \ 846 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 847#define ath_hal_hasveol(_ah) \ 848 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 849#define ath_hal_hastxpowlimit(_ah) \ 850 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 851#define ath_hal_settxpowlimit(_ah, _pow) \ 852 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 853#define ath_hal_gettxpowlimit(_ah, _ppow) \ 854 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 855#define ath_hal_getmaxtxpow(_ah, _ppow) \ 856 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 857#define ath_hal_gettpscale(_ah, _scale) \ 858 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 859#define ath_hal_settpscale(_ah, _v) \ 860 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 861#define ath_hal_hastpc(_ah) \ 862 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 863#define ath_hal_gettpc(_ah) \ 864 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 865#define ath_hal_settpc(_ah, _v) \ 866 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 867#define ath_hal_hasbursting(_ah) \ 868 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 869#define ath_hal_setmcastkeysearch(_ah, _v) \ 870 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 871#define ath_hal_hasmcastkeysearch(_ah) \ 872 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 873#define ath_hal_getmcastkeysearch(_ah) \ 874 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 875#define ath_hal_hasfastframes(_ah) \ 876 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 877#define ath_hal_hasbssidmask(_ah) \ 878 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 879#define ath_hal_hasbssidmatch(_ah) \ 880 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 881#define ath_hal_hastsfadjust(_ah) \ 882 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 883#define ath_hal_gettsfadjust(_ah) \ 884 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 885#define ath_hal_settsfadjust(_ah, _onoff) \ 886 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 887#define ath_hal_hasrfsilent(_ah) \ 888 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 889#define ath_hal_getrfkill(_ah) \ 890 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 891#define ath_hal_setrfkill(_ah, _onoff) \ 892 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 893#define ath_hal_getrfsilent(_ah, _prfsilent) \ 894 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 895#define ath_hal_setrfsilent(_ah, _rfsilent) \ 896 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 897#define ath_hal_gettpack(_ah, _ptpack) \ 898 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 899#define ath_hal_settpack(_ah, _tpack) \ 900 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 901#define ath_hal_gettpcts(_ah, _ptpcts) \ 902 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 903#define ath_hal_settpcts(_ah, _tpcts) \ 904 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 905#define ath_hal_hasintmit(_ah) \ 906 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 907 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 908#define ath_hal_getintmit(_ah) \ 909 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 910 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 911#define ath_hal_setintmit(_ah, _v) \ 912 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 913 HAL_CAP_INTMIT_ENABLE, _v, NULL) 914#define ath_hal_getchannoise(_ah, _c) \ 915 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 916#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 917 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 918#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 919 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 920#define ath_hal_setrxchainmask(_ah, _rx) \ 921 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 922#define ath_hal_settxchainmask(_ah, _tx) \ 923 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 924#define ath_hal_split4ktrans(_ah) \ 925 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 926 0, NULL) == HAL_OK) 927#define ath_hal_self_linked_final_rxdesc(_ah) \ 928 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 929 0, NULL) == HAL_OK) 930#define ath_hal_gtxto_supported(_ah) \ 931 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 932#define ath_hal_has_long_rxdesc_tsf(_ah) \ 933 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 934 0, NULL) == HAL_OK) 935#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 936 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 937#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 938 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 939#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 940 _txr0, _txtr0, _keyix, _ant, _flags, \ 941 _rtsrate, _rtsdura) \ 942 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 943 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 944 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 945#define ath_hal_setupxtxdesc(_ah, _ds, \ 946 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 947 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 948 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 949#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 950 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 951#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 952 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 953#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 954 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 955#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 956 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 957 958#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 959 _txr0, _txtr0, _antm, _rcr, _rcd) \ 960 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 961 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 962#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 963 _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 964 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 965 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 966 (_first), (_last), (_lastaggr))) 967#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 968 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 969 970#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 971 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 972 (_series), (_ns), (_flags))) 973 974#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 975 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 976#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 977 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 978#define ath_hal_set11n_aggr_last(_ah, _ds) \ 979 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 980 981#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 982 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 983#define ath_hal_clr11n_aggr(_ah, _ds) \ 984 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 985 986#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 987 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 988#define ath_hal_gpioset(_ah, _gpio, _b) \ 989 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 990#define ath_hal_gpioget(_ah, _gpio) \ 991 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 992#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 993 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 994 995/* 996 * PCIe suspend/resume/poweron/poweroff related macros 997 */ 998#define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 999 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1000#define ath_hal_disablepcie(_ah) \ 1001 ((*(_ah)->ah_disablePCIE)((_ah))) 1002 1003/* 1004 * This is badly-named; you need to set the correct parameters 1005 * to begin to receive useful radar events; and even then 1006 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1007 * more information. 1008 */ 1009#define ath_hal_enabledfs(_ah, _param) \ 1010 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1011#define ath_hal_getdfsthresh(_ah, _param) \ 1012 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1013#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1014 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1015 (_buf), (_event))) 1016#define ath_hal_is_fast_clock_enabled(_ah) \ 1017 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1018#define ath_hal_radar_wait(_ah, _chan) \ 1019 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1020#define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1021 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1022#define ath_hal_get_chan_ext_busy(_ah) \ 1023 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1024 1025#endif /* _DEV_ATH_ATHVAR_H */ 1026