if_athvar.h revision 232794
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 232794 2012-03-10 19:58:23Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * 802.11n requires more TX and RX buffers to do AMPDU. 48 */ 49#ifdef ATH_ENABLE_11N 50#define ATH_TXBUF 512 51#define ATH_RXBUF 512 52#endif 53 54#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 200 /* number of TX buffers */ 59#endif 60#define ATH_BCBUF 4 /* number of beacon buffers */ 61 62#define ATH_TXDESC 10 /* number of descriptors per buffer */ 63#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66 67#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 68#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70 71/* 72 * The key cache is used for h/w cipher state and also for 73 * tracking station state such as the current tx antenna. 74 * We also setup a mapping table between key cache slot indices 75 * and station state to short-circuit node lookups on rx. 76 * Different parts have different size key caches. We handle 77 * up to ATH_KEYMAX entries (could dynamically allocate state). 78 */ 79#define ATH_KEYMAX 128 /* max key cache size we handle */ 80#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81 82struct taskqueue; 83struct kthread; 84struct ath_buf; 85 86#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 87 88/* 89 * Per-TID state 90 * 91 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 92 */ 93struct ath_tid { 94 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 95 u_int axq_depth; /* SW queue depth */ 96 char axq_name[48]; /* lock name */ 97 struct ath_node *an; /* pointer to parent */ 98 int tid; /* tid */ 99 int ac; /* which AC gets this trafic */ 100 int hwq_depth; /* how many buffers are on HW */ 101 102 /* 103 * Entry on the ath_txq; when there's traffic 104 * to send 105 */ 106 TAILQ_ENTRY(ath_tid) axq_qelem; 107 int sched; 108 int paused; /* >0 if the TID has been paused */ 109 110 /* 111 * Is the TID being cleaned up after a transition 112 * from aggregation to non-aggregation? 113 * When this is set to 1, this TID will be paused 114 * and no further traffic will be queued until all 115 * the hardware packets pending for this TID have been 116 * TXed/completed; at which point (non-aggregation) 117 * traffic will resume being TXed. 118 */ 119 int cleanup_inprogress; 120 /* 121 * How many hardware-queued packets are 122 * waiting to be cleaned up. 123 * This is only valid if cleanup_inprogress is 1. 124 */ 125 int incomp; 126 127 /* 128 * The following implements a ring representing 129 * the frames in the current BAW. 130 * To avoid copying the array content each time 131 * the BAW is moved, the baw_head/baw_tail point 132 * to the current BAW begin/end; when the BAW is 133 * shifted the head/tail of the array are also 134 * appropriately shifted. 135 */ 136 /* active tx buffers, beginning at current BAW */ 137 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 138 /* where the baw head is in the array */ 139 int baw_head; 140 /* where the BAW tail is in the array */ 141 int baw_tail; 142}; 143 144/* driver-specific node state */ 145struct ath_node { 146 struct ieee80211_node an_node; /* base class */ 147 u_int8_t an_mgmtrix; /* min h/w rate index */ 148 u_int8_t an_mcastrix; /* mcast h/w rate index */ 149 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 150 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 151 char an_name[32]; /* eg "wlan0_a1" */ 152 struct mtx an_mtx; /* protecting the ath_node state */ 153 /* variable-length rate control state follows */ 154}; 155#define ATH_NODE(ni) ((struct ath_node *)(ni)) 156#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 157 158#define ATH_RSSI_LPF_LEN 10 159#define ATH_RSSI_DUMMY_MARKER 0x127 160#define ATH_EP_MUL(x, mul) ((x) * (mul)) 161#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 162#define ATH_LPF_RSSI(x, y, len) \ 163 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 164#define ATH_RSSI_LPF(x, y) do { \ 165 if ((y) >= -20) \ 166 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 167} while (0) 168#define ATH_EP_RND(x,mul) \ 169 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 170#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 171 172struct ath_buf { 173 TAILQ_ENTRY(ath_buf) bf_list; 174 struct ath_buf * bf_next; /* next buffer in the aggregate */ 175 int bf_nseg; 176 uint16_t bf_txflags; /* tx descriptor flags */ 177 uint16_t bf_flags; /* status flags (below) */ 178 struct ath_desc *bf_desc; /* virtual addr of desc */ 179 struct ath_desc_status bf_status; /* tx/rx status */ 180 bus_addr_t bf_daddr; /* physical addr of desc */ 181 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 182 struct mbuf *bf_m; /* mbuf for buf */ 183 struct ieee80211_node *bf_node; /* pointer to the node */ 184 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 185 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 186 bus_size_t bf_mapsize; 187#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 188 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 189 190 /* Completion function to call on TX complete (fail or not) */ 191 /* 192 * "fail" here is set to 1 if the queue entries were removed 193 * through a call to ath_tx_draintxq(). 194 */ 195 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 196 197 /* This state is kept to support software retries and aggregation */ 198 struct { 199 int bfs_seqno; /* sequence number of this packet */ 200 int bfs_retries; /* retry count */ 201 uint16_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 202 uint16_t bfs_pri; /* packet AC priority */ 203 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 204 uint16_t bfs_pktdur; /* packet duration (at current rate?) */ 205 uint16_t bfs_nframes; /* number of frames in aggregate */ 206 uint16_t bfs_ndelim; /* number of delims for padding */ 207 208 int bfs_aggr:1; /* part of aggregate? */ 209 int bfs_aggrburst:1; /* part of aggregate burst? */ 210 int bfs_isretried:1; /* retried frame? */ 211 int bfs_dobaw:1; /* actually check against BAW? */ 212 int bfs_addedbaw:1; /* has been added to the BAW */ 213 int bfs_shpream:1; /* use short preamble */ 214 int bfs_istxfrag:1; /* is fragmented */ 215 int bfs_ismrr:1; /* do multi-rate TX retry */ 216 int bfs_doprot:1; /* do RTS/CTS based protection */ 217 int bfs_doratelookup:1; /* do rate lookup before each TX */ 218 int bfs_nfl; /* next fragment length */ 219 220 /* 221 * These fields are passed into the 222 * descriptor setup functions. 223 */ 224 HAL_PKT_TYPE bfs_atype; /* packet type */ 225 int bfs_pktlen; /* length of this packet */ 226 int bfs_hdrlen; /* length of this packet header */ 227 uint16_t bfs_al; /* length of aggregate */ 228 int bfs_flags; /* HAL descriptor flags */ 229 int bfs_txrate0; /* first TX rate */ 230 int bfs_try0; /* first try count */ 231 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 232 int bfs_keyix; /* crypto key index */ 233 int bfs_txpower; /* tx power */ 234 int bfs_txantenna; /* TX antenna config */ 235 enum ieee80211_protmode bfs_protmode; 236 HAL_11N_RATE_SERIES bfs_rc11n[ATH_RC_NUM]; /* 11n TX series */ 237 int bfs_ctsrate; /* CTS rate */ 238 int bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 239 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 240 } bf_state; 241}; 242typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 243 244#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 245 246/* 247 * DMA state for tx/rx descriptors. 248 */ 249struct ath_descdma { 250 const char* dd_name; 251 struct ath_desc *dd_desc; /* descriptors */ 252 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 253 bus_size_t dd_desc_len; /* size of dd_desc */ 254 bus_dma_segment_t dd_dseg; 255 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 256 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 257 struct ath_buf *dd_bufptr; /* associated buffers */ 258}; 259 260/* 261 * Data transmit queue state. One of these exists for each 262 * hardware transmit queue. Packets sent to us from above 263 * are assigned to queues based on their priority. Not all 264 * devices support a complete set of hardware transmit queues. 265 * For those devices the array sc_ac2q will map multiple 266 * priorities to fewer hardware queues (typically all to one 267 * hardware queue). 268 */ 269struct ath_txq { 270 struct ath_softc *axq_softc; /* Needed for scheduling */ 271 u_int axq_qnum; /* hardware q number */ 272#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 273 u_int axq_ac; /* WME AC */ 274 u_int axq_flags; 275#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 276 u_int axq_depth; /* queue depth (stat only) */ 277 u_int axq_aggr_depth; /* how many aggregates are queued */ 278 u_int axq_intrcnt; /* interrupt count */ 279 u_int32_t *axq_link; /* link ptr in last TX desc */ 280 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 281 struct mtx axq_lock; /* lock on q and link */ 282 char axq_name[12]; /* e.g. "ath0_txq4" */ 283 284 /* Per-TID traffic queue for software -> hardware TX */ 285 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 286}; 287 288#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 289#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 290#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 291 292#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 293 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 294 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 295 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 296} while (0) 297#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 298#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 299#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 300#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 301#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 302 303#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 304 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 305 (_tq)->axq_depth++; \ 306} while (0) 307#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 308 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 309 (_tq)->axq_depth++; \ 310} while (0) 311#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 312 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 313 (_tq)->axq_depth--; \ 314} while (0) 315#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 316 317struct ath_vap { 318 struct ieee80211vap av_vap; /* base class */ 319 int av_bslot; /* beacon slot index */ 320 struct ath_buf *av_bcbuf; /* beacon buffer */ 321 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 322 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 323 324 void (*av_recv_mgmt)(struct ieee80211_node *, 325 struct mbuf *, int, int, int); 326 int (*av_newstate)(struct ieee80211vap *, 327 enum ieee80211_state, int); 328 void (*av_bmiss)(struct ieee80211vap *); 329}; 330#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 331 332struct taskqueue; 333struct ath_tx99; 334 335/* 336 * Whether to reset the TX/RX queue with or without 337 * a queue flush. 338 */ 339typedef enum { 340 ATH_RESET_DEFAULT = 0, 341 ATH_RESET_NOLOSS = 1, 342 ATH_RESET_FULL = 2, 343} ATH_RESET_TYPE; 344 345struct ath_softc { 346 struct ifnet *sc_ifp; /* interface common */ 347 struct ath_stats sc_stats; /* interface statistics */ 348 struct ath_tx_aggr_stats sc_aggr_stats; 349 int sc_debug; 350 int sc_nvaps; /* # vaps */ 351 int sc_nstavaps; /* # station vaps */ 352 int sc_nmeshvaps; /* # mbss vaps */ 353 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 354 u_int8_t sc_nbssid0; /* # vap's using base mac */ 355 uint32_t sc_bssidmask; /* bssid mask */ 356 357 void (*sc_node_cleanup)(struct ieee80211_node *); 358 void (*sc_node_free)(struct ieee80211_node *); 359 device_t sc_dev; 360 HAL_BUS_TAG sc_st; /* bus space tag */ 361 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 362 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 363 struct mtx sc_mtx; /* master lock (recursive) */ 364 struct mtx sc_pcu_mtx; /* PCU access mutex */ 365 char sc_pcu_mtx_name[32]; 366 struct taskqueue *sc_tq; /* private task queue */ 367 struct ath_hal *sc_ah; /* Atheros HAL */ 368 struct ath_ratectrl *sc_rc; /* tx rate control support */ 369 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 370 void (*sc_setdefantenna)(struct ath_softc *, u_int); 371 unsigned int sc_invalid : 1,/* disable hardware accesses */ 372 sc_mrretry : 1,/* multi-rate retry support */ 373 sc_softled : 1,/* enable LED gpio status */ 374 sc_hardled : 1,/* enable MAC LED status */ 375 sc_splitmic : 1,/* split TKIP MIC keys */ 376 sc_needmib : 1,/* enable MIB stats intr */ 377 sc_diversity: 1,/* enable rx diversity */ 378 sc_hasveol : 1,/* tx VEOL support */ 379 sc_ledstate : 1,/* LED on/off state */ 380 sc_blinking : 1,/* LED blink operation active */ 381 sc_mcastkey : 1,/* mcast key cache search */ 382 sc_scanning : 1,/* scanning active */ 383 sc_syncbeacon:1,/* sync/resync beacon timers */ 384 sc_hasclrkey: 1,/* CLR key supported */ 385 sc_xchanmode: 1,/* extended channel mode */ 386 sc_outdoor : 1,/* outdoor operation */ 387 sc_dturbo : 1,/* dynamic turbo in use */ 388 sc_hasbmask : 1,/* bssid mask support */ 389 sc_hasbmatch: 1,/* bssid match disable support*/ 390 sc_hastsfadd: 1,/* tsf adjust support */ 391 sc_beacons : 1,/* beacons running */ 392 sc_swbmiss : 1,/* sta mode using sw bmiss */ 393 sc_stagbeacons:1,/* use staggered beacons */ 394 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 395 sc_resume_up: 1,/* on resume, start all vaps */ 396 sc_tdma : 1,/* TDMA in use */ 397 sc_setcca : 1,/* set/clr CCA with TDMA */ 398 sc_resetcal : 1,/* reset cal state next trip */ 399 sc_rxslink : 1,/* do self-linked final descriptor */ 400 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 401 uint32_t sc_eerd; /* regdomain from EEPROM */ 402 uint32_t sc_eecc; /* country code from EEPROM */ 403 /* rate tables */ 404 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 405 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 406 enum ieee80211_phymode sc_curmode; /* current phy mode */ 407 HAL_OPMODE sc_opmode; /* current operating mode */ 408 u_int16_t sc_curtxpow; /* current tx power limit */ 409 u_int16_t sc_curaid; /* current association id */ 410 struct ieee80211_channel *sc_curchan; /* current installed channel */ 411 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 412 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 413 struct { 414 u_int8_t ieeerate; /* IEEE rate */ 415 u_int8_t rxflags; /* radiotap rx flags */ 416 u_int8_t txflags; /* radiotap tx flags */ 417 u_int16_t ledon; /* softled on time */ 418 u_int16_t ledoff; /* softled off time */ 419 } sc_hwmap[32]; /* h/w rate ix mappings */ 420 u_int8_t sc_protrix; /* protection rate index */ 421 u_int8_t sc_lastdatarix; /* last data frame rate index */ 422 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 423 u_int sc_fftxqmin; /* min frames before staging */ 424 u_int sc_fftxqmax; /* max frames before drop */ 425 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 426 427 HAL_INT sc_imask; /* interrupt mask copy */ 428 429 /* 430 * These are modified in the interrupt handler as well as 431 * the task queues and other contexts. Thus these must be 432 * protected by a mutex, or they could clash. 433 * 434 * For now, access to these is behind the ATH_LOCK, 435 * just to save time. 436 */ 437 uint32_t sc_txq_active; /* bitmap of active TXQs */ 438 uint32_t sc_kickpcu; /* whether to kick the PCU */ 439 uint32_t sc_rxproc_cnt; /* In RX processing */ 440 uint32_t sc_txproc_cnt; /* In TX processing */ 441 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 442 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 443 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 444 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 445 446 u_int sc_keymax; /* size of key cache */ 447 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 448 449 /* 450 * Software based LED blinking 451 */ 452 u_int sc_ledpin; /* GPIO pin for driving LED */ 453 u_int sc_ledon; /* pin setting for LED on */ 454 u_int sc_ledidle; /* idle polling interval */ 455 int sc_ledevent; /* time of last LED event */ 456 u_int8_t sc_txrix; /* current tx rate for LED */ 457 u_int16_t sc_ledoff; /* off time for current blink */ 458 struct callout sc_ledtimer; /* led off timer */ 459 460 /* 461 * Hardware based LED blinking 462 */ 463 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 464 int sc_led_net_pin; /* MAC network LED GPIO pin */ 465 466 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 467 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 468 469 struct ath_descdma sc_rxdma; /* RX descriptors */ 470 ath_bufhead sc_rxbuf; /* receive buffer */ 471 struct mbuf *sc_rxpending; /* pending receive data */ 472 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 473 struct task sc_rxtask; /* rx int processing */ 474 u_int8_t sc_defant; /* current default antenna */ 475 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 476 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 477 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 478 struct ath_rx_radiotap_header sc_rx_th; 479 int sc_rx_th_len; 480 u_int sc_monpass; /* frames to pass in mon.mode */ 481 482 struct ath_descdma sc_txdma; /* TX descriptors */ 483 ath_bufhead sc_txbuf; /* transmit buffer */ 484 struct mtx sc_txbuflock; /* txbuf lock */ 485 char sc_txname[12]; /* e.g. "ath0_buf" */ 486 u_int sc_txqsetup; /* h/w queues setup */ 487 u_int sc_txintrperiod;/* tx interrupt batching */ 488 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 489 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 490 struct task sc_txtask; /* tx int processing */ 491 int sc_wd_timer; /* count down for wd timer */ 492 struct callout sc_wd_ch; /* tx watchdog timer */ 493 struct ath_tx_radiotap_header sc_tx_th; 494 int sc_tx_th_len; 495 496 struct ath_descdma sc_bdma; /* beacon descriptors */ 497 ath_bufhead sc_bbuf; /* beacon buffers */ 498 u_int sc_bhalq; /* HAL q for outgoing beacons */ 499 u_int sc_bmisscount; /* missed beacon transmits */ 500 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 501 struct ath_txq *sc_cabq; /* tx q for cab frames */ 502 struct task sc_bmisstask; /* bmiss int processing */ 503 struct task sc_bstucktask; /* stuck beacon processing */ 504 struct task sc_resettask; /* interface reset task */ 505 enum { 506 OK, /* no change needed */ 507 UPDATE, /* update pending */ 508 COMMIT /* beacon sent, commit change */ 509 } sc_updateslot; /* slot time update fsm */ 510 int sc_slotupdate; /* slot to advance fsm */ 511 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 512 int sc_nbcnvaps; /* # vaps with beacons */ 513 514 struct callout sc_cal_ch; /* callout handle for cals */ 515 int sc_lastlongcal; /* last long cal completed */ 516 int sc_lastcalreset;/* last cal reset done */ 517 int sc_lastani; /* last ANI poll */ 518 int sc_lastshortcal; /* last short calibration */ 519 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 520 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 521 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 522 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 523 u_int sc_tdmaswba; /* TDMA SWBA counter */ 524 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 525 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 526 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 527 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 528 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 529 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 530 int sc_txchainmask; /* currently configured TX chainmask */ 531 int sc_rxchainmask; /* currently configured RX chainmask */ 532 533 /* Queue limits */ 534 535 /* 536 * To avoid queue starvation in congested conditions, 537 * these parameters tune the maximum number of frames 538 * queued to the data/mcastq before they're dropped. 539 * 540 * This is to prevent: 541 * + a single destination overwhelming everything, including 542 * management/multicast frames; 543 * + multicast frames overwhelming everything (when the 544 * air is sufficiently busy that cabq can't drain.) 545 * 546 * These implement: 547 * + data_minfree is the maximum number of free buffers 548 * overall to successfully allow a data frame. 549 * 550 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 551 */ 552 int sc_txq_data_minfree; 553 int sc_txq_mcastq_maxdepth; 554 555 /* 556 * Aggregation twiddles 557 * 558 * hwq_limit: how busy to keep the hardware queue - don't schedule 559 * further packets to the hardware, regardless of the TID 560 * tid_hwq_lo: how low the per-TID hwq count has to be before the 561 * TID will be scheduled again 562 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 563 * stops being scheduled. 564 */ 565 int sc_hwq_limit; 566 int sc_tid_hwq_lo; 567 int sc_tid_hwq_hi; 568 569 /* DFS related state */ 570 void *sc_dfs; /* Used by an optional DFS module */ 571 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 572 struct task sc_dfstask; /* DFS processing task */ 573 574 /* TX AMPDU handling */ 575 int (*sc_addba_request)(struct ieee80211_node *, 576 struct ieee80211_tx_ampdu *, int, int, int); 577 int (*sc_addba_response)(struct ieee80211_node *, 578 struct ieee80211_tx_ampdu *, int, int, int); 579 void (*sc_addba_stop)(struct ieee80211_node *, 580 struct ieee80211_tx_ampdu *); 581 void (*sc_addba_response_timeout) 582 (struct ieee80211_node *, 583 struct ieee80211_tx_ampdu *); 584 void (*sc_bar_response)(struct ieee80211_node *ni, 585 struct ieee80211_tx_ampdu *tap, 586 int status); 587}; 588 589#define ATH_LOCK_INIT(_sc) \ 590 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 591 NULL, MTX_DEF | MTX_RECURSE) 592#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 593#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 594#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 595#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 596#define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 597 598/* 599 * The PCU lock is non-recursive and should be treated as a spinlock. 600 * Although currently the interrupt code is run in netisr context and 601 * doesn't require this, this may change in the future. 602 * Please keep this in mind when protecting certain code paths 603 * with the PCU lock. 604 * 605 * The PCU lock is used to serialise access to the PCU so things such 606 * as TX, RX, state change (eg channel change), channel reset and updates 607 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 608 * 609 * Although the current single-thread taskqueue mechanism protects the 610 * majority of these situations by simply serialising them, there are 611 * a few others which occur at the same time. These include the TX path 612 * (which only acquires ATH_LOCK when recycling buffers to the free list), 613 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 614 */ 615#define ATH_PCU_LOCK_INIT(_sc) do {\ 616 snprintf((_sc)->sc_pcu_mtx_name, \ 617 sizeof((_sc)->sc_pcu_mtx_name), \ 618 "%s PCU lock", \ 619 device_get_nameunit((_sc)->sc_dev)); \ 620 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 621 NULL, MTX_DEF); \ 622 } while (0) 623#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 624#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 625#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 626#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 627 MA_OWNED) 628#define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 629 MA_NOTOWNED) 630 631#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 632 633#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 634 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 635 device_get_nameunit((_sc)->sc_dev)); \ 636 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 637} while (0) 638#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 639#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 640#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 641#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 642 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 643 644int ath_attach(u_int16_t, struct ath_softc *); 645int ath_detach(struct ath_softc *); 646void ath_resume(struct ath_softc *); 647void ath_suspend(struct ath_softc *); 648void ath_shutdown(struct ath_softc *); 649void ath_intr(void *); 650 651/* 652 * HAL definitions to comply with local coding convention. 653 */ 654#define ath_hal_detach(_ah) \ 655 ((*(_ah)->ah_detach)((_ah))) 656#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 657 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 658#define ath_hal_macversion(_ah) \ 659 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 660#define ath_hal_getratetable(_ah, _mode) \ 661 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 662#define ath_hal_getmac(_ah, _mac) \ 663 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 664#define ath_hal_setmac(_ah, _mac) \ 665 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 666#define ath_hal_getbssidmask(_ah, _mask) \ 667 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 668#define ath_hal_setbssidmask(_ah, _mask) \ 669 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 670#define ath_hal_intrset(_ah, _mask) \ 671 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 672#define ath_hal_intrget(_ah) \ 673 ((*(_ah)->ah_getInterrupts)((_ah))) 674#define ath_hal_intrpend(_ah) \ 675 ((*(_ah)->ah_isInterruptPending)((_ah))) 676#define ath_hal_getisr(_ah, _pmask) \ 677 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 678#define ath_hal_updatetxtriglevel(_ah, _inc) \ 679 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 680#define ath_hal_setpower(_ah, _mode) \ 681 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 682#define ath_hal_keycachesize(_ah) \ 683 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 684#define ath_hal_keyreset(_ah, _ix) \ 685 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 686#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 687 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 688#define ath_hal_keyisvalid(_ah, _ix) \ 689 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 690#define ath_hal_keysetmac(_ah, _ix, _mac) \ 691 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 692#define ath_hal_getrxfilter(_ah) \ 693 ((*(_ah)->ah_getRxFilter)((_ah))) 694#define ath_hal_setrxfilter(_ah, _filter) \ 695 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 696#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 697 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 698#define ath_hal_waitforbeacon(_ah, _bf) \ 699 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 700#define ath_hal_putrxbuf(_ah, _bufaddr) \ 701 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 702/* NB: common across all chips */ 703#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 704#define ath_hal_gettsf32(_ah) \ 705 OS_REG_READ(_ah, AR_TSF_L32) 706#define ath_hal_gettsf64(_ah) \ 707 ((*(_ah)->ah_getTsf64)((_ah))) 708#define ath_hal_resettsf(_ah) \ 709 ((*(_ah)->ah_resetTsf)((_ah))) 710#define ath_hal_rxena(_ah) \ 711 ((*(_ah)->ah_enableReceive)((_ah))) 712#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 713 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 714#define ath_hal_gettxbuf(_ah, _q) \ 715 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 716#define ath_hal_numtxpending(_ah, _q) \ 717 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 718#define ath_hal_getrxbuf(_ah) \ 719 ((*(_ah)->ah_getRxDP)((_ah))) 720#define ath_hal_txstart(_ah, _q) \ 721 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 722#define ath_hal_setchannel(_ah, _chan) \ 723 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 724#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 725 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 726#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 727 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 728#define ath_hal_calreset(_ah, _chan) \ 729 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 730#define ath_hal_setledstate(_ah, _state) \ 731 ((*(_ah)->ah_setLedState)((_ah), (_state))) 732#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 733 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 734#define ath_hal_beaconreset(_ah) \ 735 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 736#define ath_hal_beaconsettimers(_ah, _bt) \ 737 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 738#define ath_hal_beacontimers(_ah, _bs) \ 739 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 740#define ath_hal_getnexttbtt(_ah) \ 741 ((*(_ah)->ah_getNextTBTT)((_ah))) 742#define ath_hal_setassocid(_ah, _bss, _associd) \ 743 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 744#define ath_hal_phydisable(_ah) \ 745 ((*(_ah)->ah_phyDisable)((_ah))) 746#define ath_hal_setopmode(_ah) \ 747 ((*(_ah)->ah_setPCUConfig)((_ah))) 748#define ath_hal_stoptxdma(_ah, _qnum) \ 749 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 750#define ath_hal_stoppcurecv(_ah) \ 751 ((*(_ah)->ah_stopPcuReceive)((_ah))) 752#define ath_hal_startpcurecv(_ah) \ 753 ((*(_ah)->ah_startPcuReceive)((_ah))) 754#define ath_hal_stopdmarecv(_ah) \ 755 ((*(_ah)->ah_stopDmaReceive)((_ah))) 756#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 757 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 758 (_indata), (_insize), (_outdata), (_outsize))) 759#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 760 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 761#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 762 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 763#define ath_hal_resettxqueue(_ah, _q) \ 764 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 765#define ath_hal_releasetxqueue(_ah, _q) \ 766 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 767#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 768 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 769#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 770 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 771/* NB: common across all chips */ 772#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 773#define ath_hal_txqenabled(_ah, _qnum) \ 774 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 775#define ath_hal_getrfgain(_ah) \ 776 ((*(_ah)->ah_getRfGain)((_ah))) 777#define ath_hal_getdefantenna(_ah) \ 778 ((*(_ah)->ah_getDefAntenna)((_ah))) 779#define ath_hal_setdefantenna(_ah, _ant) \ 780 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 781#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 782 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 783#define ath_hal_ani_poll(_ah, _chan) \ 784 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 785#define ath_hal_mibevent(_ah, _stats) \ 786 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 787#define ath_hal_setslottime(_ah, _us) \ 788 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 789#define ath_hal_getslottime(_ah) \ 790 ((*(_ah)->ah_getSlotTime)((_ah))) 791#define ath_hal_setacktimeout(_ah, _us) \ 792 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 793#define ath_hal_getacktimeout(_ah) \ 794 ((*(_ah)->ah_getAckTimeout)((_ah))) 795#define ath_hal_setctstimeout(_ah, _us) \ 796 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 797#define ath_hal_getctstimeout(_ah) \ 798 ((*(_ah)->ah_getCTSTimeout)((_ah))) 799#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 800 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 801#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 802 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 803#define ath_hal_ciphersupported(_ah, _cipher) \ 804 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 805#define ath_hal_getregdomain(_ah, _prd) \ 806 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 807#define ath_hal_setregdomain(_ah, _rd) \ 808 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 809#define ath_hal_getcountrycode(_ah, _pcc) \ 810 (*(_pcc) = (_ah)->ah_countryCode) 811#define ath_hal_gettkipmic(_ah) \ 812 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 813#define ath_hal_settkipmic(_ah, _v) \ 814 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 815#define ath_hal_hastkipsplit(_ah) \ 816 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 817#define ath_hal_gettkipsplit(_ah) \ 818 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 819#define ath_hal_settkipsplit(_ah, _v) \ 820 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 821#define ath_hal_haswmetkipmic(_ah) \ 822 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 823#define ath_hal_hwphycounters(_ah) \ 824 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 825#define ath_hal_hasdiversity(_ah) \ 826 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 827#define ath_hal_getdiversity(_ah) \ 828 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 829#define ath_hal_setdiversity(_ah, _v) \ 830 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 831#define ath_hal_getantennaswitch(_ah) \ 832 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 833#define ath_hal_setantennaswitch(_ah, _v) \ 834 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 835#define ath_hal_getdiag(_ah, _pv) \ 836 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 837#define ath_hal_setdiag(_ah, _v) \ 838 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 839#define ath_hal_getnumtxqueues(_ah, _pv) \ 840 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 841#define ath_hal_hasveol(_ah) \ 842 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 843#define ath_hal_hastxpowlimit(_ah) \ 844 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 845#define ath_hal_settxpowlimit(_ah, _pow) \ 846 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 847#define ath_hal_gettxpowlimit(_ah, _ppow) \ 848 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 849#define ath_hal_getmaxtxpow(_ah, _ppow) \ 850 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 851#define ath_hal_gettpscale(_ah, _scale) \ 852 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 853#define ath_hal_settpscale(_ah, _v) \ 854 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 855#define ath_hal_hastpc(_ah) \ 856 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 857#define ath_hal_gettpc(_ah) \ 858 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 859#define ath_hal_settpc(_ah, _v) \ 860 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 861#define ath_hal_hasbursting(_ah) \ 862 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 863#define ath_hal_setmcastkeysearch(_ah, _v) \ 864 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 865#define ath_hal_hasmcastkeysearch(_ah) \ 866 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 867#define ath_hal_getmcastkeysearch(_ah) \ 868 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 869#define ath_hal_hasfastframes(_ah) \ 870 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 871#define ath_hal_hasbssidmask(_ah) \ 872 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 873#define ath_hal_hasbssidmatch(_ah) \ 874 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 875#define ath_hal_hastsfadjust(_ah) \ 876 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 877#define ath_hal_gettsfadjust(_ah) \ 878 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 879#define ath_hal_settsfadjust(_ah, _onoff) \ 880 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 881#define ath_hal_hasrfsilent(_ah) \ 882 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 883#define ath_hal_getrfkill(_ah) \ 884 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 885#define ath_hal_setrfkill(_ah, _onoff) \ 886 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 887#define ath_hal_getrfsilent(_ah, _prfsilent) \ 888 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 889#define ath_hal_setrfsilent(_ah, _rfsilent) \ 890 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 891#define ath_hal_gettpack(_ah, _ptpack) \ 892 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 893#define ath_hal_settpack(_ah, _tpack) \ 894 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 895#define ath_hal_gettpcts(_ah, _ptpcts) \ 896 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 897#define ath_hal_settpcts(_ah, _tpcts) \ 898 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 899#define ath_hal_hasintmit(_ah) \ 900 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 901 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 902#define ath_hal_getintmit(_ah) \ 903 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 904 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 905#define ath_hal_setintmit(_ah, _v) \ 906 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 907 HAL_CAP_INTMIT_ENABLE, _v, NULL) 908#define ath_hal_getchannoise(_ah, _c) \ 909 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 910#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 911 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 912#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 913 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 914#define ath_hal_setrxchainmask(_ah, _rx) \ 915 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 916#define ath_hal_settxchainmask(_ah, _tx) \ 917 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 918#define ath_hal_split4ktrans(_ah) \ 919 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 920 0, NULL) == HAL_OK) 921#define ath_hal_self_linked_final_rxdesc(_ah) \ 922 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 923 0, NULL) == HAL_OK) 924#define ath_hal_gtxto_supported(_ah) \ 925 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 926#define ath_hal_has_long_rxdesc_tsf(_ah) \ 927 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 928 0, NULL) == HAL_OK) 929#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 930 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 931#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 932 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 933#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 934 _txr0, _txtr0, _keyix, _ant, _flags, \ 935 _rtsrate, _rtsdura) \ 936 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 937 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 938 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 939#define ath_hal_setupxtxdesc(_ah, _ds, \ 940 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 941 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 942 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 943#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 944 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 945#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 946 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 947#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 948 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 949#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 950 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 951 952#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 953 _txr0, _txtr0, _antm, _rcr, _rcd) \ 954 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 955 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 956#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 957 _cipher, _delims, _seglen, _first, _last) \ 958 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 959 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 960 (_first), (_last))) 961#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 962 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 963 964#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 965 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 966 (_series), (_ns), (_flags))) 967 968#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 969 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 970#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 971 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 972#define ath_hal_set11n_aggr_last(_ah, _ds) \ 973 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 974 975#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 976 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 977#define ath_hal_clr11n_aggr(_ah, _ds) \ 978 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 979 980#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 981 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 982#define ath_hal_gpioset(_ah, _gpio, _b) \ 983 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 984#define ath_hal_gpioget(_ah, _gpio) \ 985 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 986#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 987 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 988 989/* 990 * This is badly-named; you need to set the correct parameters 991 * to begin to receive useful radar events; and even then 992 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 993 * more information. 994 */ 995#define ath_hal_enabledfs(_ah, _param) \ 996 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 997#define ath_hal_getdfsthresh(_ah, _param) \ 998 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 999#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1000 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1001 (_buf), (_event))) 1002#define ath_hal_is_fast_clock_enabled(_ah) \ 1003 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1004#define ath_hal_radar_wait(_ah, _chan) \ 1005 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1006#define ath_hal_get_chan_ext_busy(_ah) \ 1007 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1008 1009#endif /* _DEV_ATH_ATHVAR_H */ 1010