if_athvar.h revision 227344
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 227344 2011-11-08 17:08:12Z adrian $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <dev/ath/ath_hal/ah.h> 39#include <dev/ath/ath_hal/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46/* 47 * 802.11n requires more TX and RX buffers to do AMPDU. 48 */ 49#ifdef ATH_ENABLE_11N 50#define ATH_TXBUF 512 51#define ATH_RXBUF 512 52#endif 53 54#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 200 /* number of TX buffers */ 59#endif 60#define ATH_BCBUF 4 /* number of beacon buffers */ 61 62#define ATH_TXDESC 10 /* number of descriptors per buffer */ 63#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66 67#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 68#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70 71/* 72 * The key cache is used for h/w cipher state and also for 73 * tracking station state such as the current tx antenna. 74 * We also setup a mapping table between key cache slot indices 75 * and station state to short-circuit node lookups on rx. 76 * Different parts have different size key caches. We handle 77 * up to ATH_KEYMAX entries (could dynamically allocate state). 78 */ 79#define ATH_KEYMAX 128 /* max key cache size we handle */ 80#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81 82struct taskqueue; 83struct kthread; 84struct ath_buf; 85 86#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 87 88/* 89 * Per-TID state 90 * 91 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 92 */ 93struct ath_tid { 94 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 95 u_int axq_depth; /* SW queue depth */ 96 char axq_name[48]; /* lock name */ 97 struct ath_node *an; /* pointer to parent */ 98 int tid; /* tid */ 99 int ac; /* which AC gets this trafic */ 100 int hwq_depth; /* how many buffers are on HW */ 101 102 /* 103 * Entry on the ath_txq; when there's traffic 104 * to send 105 */ 106 TAILQ_ENTRY(ath_tid) axq_qelem; 107 int sched; 108 int paused; /* >0 if the TID has been paused */ 109 110 /* 111 * Is the TID being cleaned up after a transition 112 * from aggregation to non-aggregation? 113 * When this is set to 1, this TID will be paused 114 * and no further traffic will be queued until all 115 * the hardware packets pending for this TID have been 116 * TXed/completed; at which point (non-aggregation) 117 * traffic will resume being TXed. 118 */ 119 int cleanup_inprogress; 120 /* 121 * How many hardware-queued packets are 122 * waiting to be cleaned up. 123 * This is only valid if cleanup_inprogress is 1. 124 */ 125 int incomp; 126 127 /* 128 * The following implements a ring representing 129 * the frames in the current BAW. 130 * To avoid copying the array content each time 131 * the BAW is moved, the baw_head/baw_tail point 132 * to the current BAW begin/end; when the BAW is 133 * shifted the head/tail of the array are also 134 * appropriately shifted. 135 */ 136 /* active tx buffers, beginning at current BAW */ 137 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 138 /* where the baw head is in the array */ 139 int baw_head; 140 /* where the BAW tail is in the array */ 141 int baw_tail; 142}; 143 144/* driver-specific node state */ 145struct ath_node { 146 struct ieee80211_node an_node; /* base class */ 147 u_int8_t an_mgmtrix; /* min h/w rate index */ 148 u_int8_t an_mcastrix; /* mcast h/w rate index */ 149 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 150 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 151 char an_name[32]; /* eg "wlan0_a1" */ 152 struct mtx an_mtx; /* protecting the ath_node state */ 153 /* variable-length rate control state follows */ 154}; 155#define ATH_NODE(ni) ((struct ath_node *)(ni)) 156#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 157 158#define ATH_RSSI_LPF_LEN 10 159#define ATH_RSSI_DUMMY_MARKER 0x127 160#define ATH_EP_MUL(x, mul) ((x) * (mul)) 161#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 162#define ATH_LPF_RSSI(x, y, len) \ 163 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 164#define ATH_RSSI_LPF(x, y) do { \ 165 if ((y) >= -20) \ 166 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 167} while (0) 168#define ATH_EP_RND(x,mul) \ 169 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 170#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 171 172struct ath_buf { 173 TAILQ_ENTRY(ath_buf) bf_list; 174 struct ath_buf * bf_next; /* next buffer in the aggregate */ 175 int bf_nseg; 176 uint16_t bf_txflags; /* tx descriptor flags */ 177 uint16_t bf_flags; /* status flags (below) */ 178 struct ath_desc *bf_desc; /* virtual addr of desc */ 179 struct ath_desc_status bf_status; /* tx/rx status */ 180 bus_addr_t bf_daddr; /* physical addr of desc */ 181 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 182 struct mbuf *bf_m; /* mbuf for buf */ 183 struct ieee80211_node *bf_node; /* pointer to the node */ 184 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 185 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 186 bus_size_t bf_mapsize; 187#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 188 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 189 190 /* Completion function to call on TX complete (fail or not) */ 191 /* 192 * "fail" here is set to 1 if the queue entries were removed 193 * through a call to ath_tx_draintxq(). 194 */ 195 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 196 197 /* This state is kept to support software retries and aggregation */ 198 struct { 199 int bfs_seqno; /* sequence number of this packet */ 200 int bfs_retries; /* retry count */ 201 uint16_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 202 uint16_t bfs_pri; /* packet AC priority */ 203 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 204 uint16_t bfs_pktdur; /* packet duration (at current rate?) */ 205 uint16_t bfs_nframes; /* number of frames in aggregate */ 206 uint16_t bfs_ndelim; /* number of delims for padding */ 207 208 int bfs_aggr:1; /* part of aggregate? */ 209 int bfs_aggrburst:1; /* part of aggregate burst? */ 210 int bfs_isretried:1; /* retried frame? */ 211 int bfs_dobaw:1; /* actually check against BAW? */ 212 int bfs_addedbaw:1; /* has been added to the BAW */ 213 int bfs_shpream:1; /* use short preamble */ 214 int bfs_istxfrag:1; /* is fragmented */ 215 int bfs_ismrr:1; /* do multi-rate TX retry */ 216 int bfs_doprot:1; /* do RTS/CTS based protection */ 217 int bfs_doratelookup:1; /* do rate lookup before each TX */ 218 int bfs_nfl; /* next fragment length */ 219 220 /* 221 * These fields are passed into the 222 * descriptor setup functions. 223 */ 224 HAL_PKT_TYPE bfs_atype; /* packet type */ 225 int bfs_pktlen; /* length of this packet */ 226 int bfs_hdrlen; /* length of this packet header */ 227 uint16_t bfs_al; /* length of aggregate */ 228 int bfs_flags; /* HAL descriptor flags */ 229 int bfs_txrate0; /* first TX rate */ 230 int bfs_try0; /* first try count */ 231 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 232 int bfs_keyix; /* crypto key index */ 233 int bfs_txpower; /* tx power */ 234 int bfs_txantenna; /* TX antenna config */ 235 enum ieee80211_protmode bfs_protmode; 236 HAL_11N_RATE_SERIES bfs_rc11n[ATH_RC_NUM]; /* 11n TX series */ 237 int bfs_ctsrate; /* CTS rate */ 238 int bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 239 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 240 } bf_state; 241}; 242typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 243 244#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 245 246/* 247 * DMA state for tx/rx descriptors. 248 */ 249struct ath_descdma { 250 const char* dd_name; 251 struct ath_desc *dd_desc; /* descriptors */ 252 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 253 bus_size_t dd_desc_len; /* size of dd_desc */ 254 bus_dma_segment_t dd_dseg; 255 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 256 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 257 struct ath_buf *dd_bufptr; /* associated buffers */ 258}; 259 260/* 261 * Data transmit queue state. One of these exists for each 262 * hardware transmit queue. Packets sent to us from above 263 * are assigned to queues based on their priority. Not all 264 * devices support a complete set of hardware transmit queues. 265 * For those devices the array sc_ac2q will map multiple 266 * priorities to fewer hardware queues (typically all to one 267 * hardware queue). 268 */ 269struct ath_txq { 270 struct ath_softc *axq_softc; /* Needed for scheduling */ 271 u_int axq_qnum; /* hardware q number */ 272#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 273 u_int axq_ac; /* WME AC */ 274 u_int axq_flags; 275#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 276 u_int axq_depth; /* queue depth (stat only) */ 277 u_int axq_aggr_depth; /* how many aggregates are queued */ 278 u_int axq_intrcnt; /* interrupt count */ 279 u_int32_t *axq_link; /* link ptr in last TX desc */ 280 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 281 struct mtx axq_lock; /* lock on q and link */ 282 char axq_name[12]; /* e.g. "ath0_txq4" */ 283 284 /* Per-TID traffic queue for software -> hardware TX */ 285 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 286}; 287 288#define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 289#define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 290#define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 291 292#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 293 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 294 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 295 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 296} while (0) 297#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 298#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 299#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 300#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 301#define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 302 303#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 304 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 305 (_tq)->axq_depth++; \ 306} while (0) 307#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 308 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 309 (_tq)->axq_depth++; \ 310} while (0) 311#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 312 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 313 (_tq)->axq_depth--; \ 314} while (0) 315/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 316#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 317 318struct ath_vap { 319 struct ieee80211vap av_vap; /* base class */ 320 int av_bslot; /* beacon slot index */ 321 struct ath_buf *av_bcbuf; /* beacon buffer */ 322 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 323 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 324 325 void (*av_recv_mgmt)(struct ieee80211_node *, 326 struct mbuf *, int, int, int); 327 int (*av_newstate)(struct ieee80211vap *, 328 enum ieee80211_state, int); 329 void (*av_bmiss)(struct ieee80211vap *); 330}; 331#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 332 333struct taskqueue; 334struct ath_tx99; 335 336/* 337 * Whether to reset the TX/RX queue with or without 338 * a queue flush. 339 */ 340typedef enum { 341 ATH_RESET_DEFAULT = 0, 342 ATH_RESET_NOLOSS = 1, 343 ATH_RESET_FULL = 2, 344} ATH_RESET_TYPE; 345 346struct ath_softc { 347 struct ifnet *sc_ifp; /* interface common */ 348 struct ath_stats sc_stats; /* interface statistics */ 349 struct ath_tx_aggr_stats sc_aggr_stats; 350 int sc_debug; 351 int sc_nvaps; /* # vaps */ 352 int sc_nstavaps; /* # station vaps */ 353 int sc_nmeshvaps; /* # mbss vaps */ 354 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 355 u_int8_t sc_nbssid0; /* # vap's using base mac */ 356 uint32_t sc_bssidmask; /* bssid mask */ 357 358 void (*sc_node_cleanup)(struct ieee80211_node *); 359 void (*sc_node_free)(struct ieee80211_node *); 360 device_t sc_dev; 361 HAL_BUS_TAG sc_st; /* bus space tag */ 362 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 363 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 364 struct mtx sc_mtx; /* master lock (recursive) */ 365 struct mtx sc_pcu_mtx; /* PCU access mutex */ 366 char sc_pcu_mtx_name[32]; 367 struct taskqueue *sc_tq; /* private task queue */ 368 struct ath_hal *sc_ah; /* Atheros HAL */ 369 struct ath_ratectrl *sc_rc; /* tx rate control support */ 370 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 371 void (*sc_setdefantenna)(struct ath_softc *, u_int); 372 unsigned int sc_invalid : 1,/* disable hardware accesses */ 373 sc_mrretry : 1,/* multi-rate retry support */ 374 sc_softled : 1,/* enable LED gpio status */ 375 sc_splitmic : 1,/* split TKIP MIC keys */ 376 sc_needmib : 1,/* enable MIB stats intr */ 377 sc_diversity: 1,/* enable rx diversity */ 378 sc_hasveol : 1,/* tx VEOL support */ 379 sc_ledstate : 1,/* LED on/off state */ 380 sc_blinking : 1,/* LED blink operation active */ 381 sc_mcastkey : 1,/* mcast key cache search */ 382 sc_scanning : 1,/* scanning active */ 383 sc_syncbeacon:1,/* sync/resync beacon timers */ 384 sc_hasclrkey: 1,/* CLR key supported */ 385 sc_xchanmode: 1,/* extended channel mode */ 386 sc_outdoor : 1,/* outdoor operation */ 387 sc_dturbo : 1,/* dynamic turbo in use */ 388 sc_hasbmask : 1,/* bssid mask support */ 389 sc_hasbmatch: 1,/* bssid match disable support*/ 390 sc_hastsfadd: 1,/* tsf adjust support */ 391 sc_beacons : 1,/* beacons running */ 392 sc_swbmiss : 1,/* sta mode using sw bmiss */ 393 sc_stagbeacons:1,/* use staggered beacons */ 394 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 395 sc_resume_up: 1,/* on resume, start all vaps */ 396 sc_tdma : 1,/* TDMA in use */ 397 sc_setcca : 1,/* set/clr CCA with TDMA */ 398 sc_resetcal : 1,/* reset cal state next trip */ 399 sc_rxslink : 1,/* do self-linked final descriptor */ 400 sc_kickpcu : 1,/* kick PCU RX on next RX proc */ 401 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 402 uint32_t sc_eerd; /* regdomain from EEPROM */ 403 uint32_t sc_eecc; /* country code from EEPROM */ 404 /* rate tables */ 405 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 406 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 407 enum ieee80211_phymode sc_curmode; /* current phy mode */ 408 HAL_OPMODE sc_opmode; /* current operating mode */ 409 u_int16_t sc_curtxpow; /* current tx power limit */ 410 u_int16_t sc_curaid; /* current association id */ 411 struct ieee80211_channel *sc_curchan; /* current installed channel */ 412 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 413 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 414 struct { 415 u_int8_t ieeerate; /* IEEE rate */ 416 u_int8_t rxflags; /* radiotap rx flags */ 417 u_int8_t txflags; /* radiotap tx flags */ 418 u_int16_t ledon; /* softled on time */ 419 u_int16_t ledoff; /* softled off time */ 420 } sc_hwmap[32]; /* h/w rate ix mappings */ 421 u_int8_t sc_protrix; /* protection rate index */ 422 u_int8_t sc_lastdatarix; /* last data frame rate index */ 423 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 424 u_int sc_fftxqmin; /* min frames before staging */ 425 u_int sc_fftxqmax; /* max frames before drop */ 426 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 427 HAL_INT sc_imask; /* interrupt mask copy */ 428 u_int sc_keymax; /* size of key cache */ 429 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 430 431 u_int sc_ledpin; /* GPIO pin for driving LED */ 432 u_int sc_ledon; /* pin setting for LED on */ 433 u_int sc_ledidle; /* idle polling interval */ 434 int sc_ledevent; /* time of last LED event */ 435 u_int8_t sc_txrix; /* current tx rate for LED */ 436 u_int16_t sc_ledoff; /* off time for current blink */ 437 struct callout sc_ledtimer; /* led off timer */ 438 439 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 440 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 441 442 struct ath_descdma sc_rxdma; /* RX descriptors */ 443 ath_bufhead sc_rxbuf; /* receive buffer */ 444 struct mbuf *sc_rxpending; /* pending receive data */ 445 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 446 struct task sc_rxtask; /* rx int processing */ 447 u_int8_t sc_defant; /* current default antenna */ 448 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 449 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 450 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 451 struct ath_rx_radiotap_header sc_rx_th; 452 int sc_rx_th_len; 453 u_int sc_monpass; /* frames to pass in mon.mode */ 454 455 struct ath_descdma sc_txdma; /* TX descriptors */ 456 ath_bufhead sc_txbuf; /* transmit buffer */ 457 struct mtx sc_txbuflock; /* txbuf lock */ 458 char sc_txname[12]; /* e.g. "ath0_buf" */ 459 u_int sc_txqsetup; /* h/w queues setup */ 460 u_int sc_txintrperiod;/* tx interrupt batching */ 461 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 462 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 463 struct task sc_txtask; /* tx int processing */ 464 int sc_wd_timer; /* count down for wd timer */ 465 struct callout sc_wd_ch; /* tx watchdog timer */ 466 struct ath_tx_radiotap_header sc_tx_th; 467 int sc_tx_th_len; 468 469 struct ath_descdma sc_bdma; /* beacon descriptors */ 470 ath_bufhead sc_bbuf; /* beacon buffers */ 471 u_int sc_bhalq; /* HAL q for outgoing beacons */ 472 u_int sc_bmisscount; /* missed beacon transmits */ 473 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 474 struct ath_txq *sc_cabq; /* tx q for cab frames */ 475 struct task sc_bmisstask; /* bmiss int processing */ 476 struct task sc_bstucktask; /* stuck beacon processing */ 477 enum { 478 OK, /* no change needed */ 479 UPDATE, /* update pending */ 480 COMMIT /* beacon sent, commit change */ 481 } sc_updateslot; /* slot time update fsm */ 482 int sc_slotupdate; /* slot to advance fsm */ 483 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 484 int sc_nbcnvaps; /* # vaps with beacons */ 485 486 struct callout sc_cal_ch; /* callout handle for cals */ 487 int sc_lastlongcal; /* last long cal completed */ 488 int sc_lastcalreset;/* last cal reset done */ 489 int sc_lastani; /* last ANI poll */ 490 int sc_lastshortcal; /* last short calibration */ 491 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 492 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 493 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 494 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 495 u_int sc_tdmaswba; /* TDMA SWBA counter */ 496 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 497 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 498 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 499 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 500 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 501 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 502 int sc_txchainmask; /* currently configured TX chainmask */ 503 int sc_rxchainmask; /* currently configured RX chainmask */ 504 505 /* 506 * Aggregation twiddles 507 * 508 * hwq_limit: how busy to keep the hardware queue - don't schedule 509 * further packets to the hardware, regardless of the TID 510 * tid_hwq_lo: how low the per-TID hwq count has to be before the 511 * TID will be scheduled again 512 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 513 * stops being scheduled. 514 */ 515 int sc_hwq_limit; 516 int sc_tid_hwq_lo; 517 int sc_tid_hwq_hi; 518 519 /* DFS related state */ 520 void *sc_dfs; /* Used by an optional DFS module */ 521 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 522 struct task sc_dfstask; /* DFS processing task */ 523 524 /* TX AMPDU handling */ 525 int (*sc_addba_request)(struct ieee80211_node *, 526 struct ieee80211_tx_ampdu *, int, int, int); 527 int (*sc_addba_response)(struct ieee80211_node *, 528 struct ieee80211_tx_ampdu *, int, int, int); 529 void (*sc_addba_stop)(struct ieee80211_node *, 530 struct ieee80211_tx_ampdu *); 531 void (*sc_addba_response_timeout) 532 (struct ieee80211_node *, 533 struct ieee80211_tx_ampdu *); 534 void (*sc_bar_response)(struct ieee80211_node *ni, 535 struct ieee80211_tx_ampdu *tap, 536 int status); 537}; 538 539#define ATH_LOCK_INIT(_sc) \ 540 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 541 NULL, MTX_DEF | MTX_RECURSE) 542#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 543#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 544#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 545#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 546 547/* 548 * The PCU lock is non-recursive and should be treated as a spinlock. 549 * Although currently the interrupt code is run in netisr context and 550 * doesn't require this, this may change in the future. 551 * Please keep this in mind when protecting certain code paths 552 * with the PCU lock. 553 * 554 * The PCU lock is used to serialise access to the PCU so things such 555 * as TX, RX, state change (eg channel change), channel reset and updates 556 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 557 * 558 * Although the current single-thread taskqueue mechanism protects the 559 * majority of these situations by simply serialising them, there are 560 * a few others which occur at the same time. These include the TX path 561 * (which only acquires ATH_LOCK when recycling buffers to the free list), 562 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 563 */ 564#define ATH_PCU_LOCK_INIT(_sc) do {\ 565 snprintf((_sc)->sc_pcu_mtx_name, \ 566 sizeof((_sc)->sc_pcu_mtx_name), \ 567 "%s PCU lock", \ 568 device_get_nameunit((_sc)->sc_dev)); \ 569 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 570 NULL, MTX_DEF); \ 571 } while (0) 572#define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 573#define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 574#define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 575#define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 576 MA_OWNED) 577 578#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 579 580#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 581 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 582 device_get_nameunit((_sc)->sc_dev)); \ 583 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 584} while (0) 585#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 586#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 587#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 588#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 589 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 590 591int ath_attach(u_int16_t, struct ath_softc *); 592int ath_detach(struct ath_softc *); 593void ath_resume(struct ath_softc *); 594void ath_suspend(struct ath_softc *); 595void ath_shutdown(struct ath_softc *); 596void ath_intr(void *); 597 598/* 599 * HAL definitions to comply with local coding convention. 600 */ 601#define ath_hal_detach(_ah) \ 602 ((*(_ah)->ah_detach)((_ah))) 603#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 604 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 605#define ath_hal_macversion(_ah) \ 606 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 607#define ath_hal_getratetable(_ah, _mode) \ 608 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 609#define ath_hal_getmac(_ah, _mac) \ 610 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 611#define ath_hal_setmac(_ah, _mac) \ 612 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 613#define ath_hal_getbssidmask(_ah, _mask) \ 614 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 615#define ath_hal_setbssidmask(_ah, _mask) \ 616 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 617#define ath_hal_intrset(_ah, _mask) \ 618 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 619#define ath_hal_intrget(_ah) \ 620 ((*(_ah)->ah_getInterrupts)((_ah))) 621#define ath_hal_intrpend(_ah) \ 622 ((*(_ah)->ah_isInterruptPending)((_ah))) 623#define ath_hal_getisr(_ah, _pmask) \ 624 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 625#define ath_hal_updatetxtriglevel(_ah, _inc) \ 626 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 627#define ath_hal_setpower(_ah, _mode) \ 628 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 629#define ath_hal_keycachesize(_ah) \ 630 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 631#define ath_hal_keyreset(_ah, _ix) \ 632 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 633#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 634 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 635#define ath_hal_keyisvalid(_ah, _ix) \ 636 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 637#define ath_hal_keysetmac(_ah, _ix, _mac) \ 638 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 639#define ath_hal_getrxfilter(_ah) \ 640 ((*(_ah)->ah_getRxFilter)((_ah))) 641#define ath_hal_setrxfilter(_ah, _filter) \ 642 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 643#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 644 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 645#define ath_hal_waitforbeacon(_ah, _bf) \ 646 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 647#define ath_hal_putrxbuf(_ah, _bufaddr) \ 648 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 649/* NB: common across all chips */ 650#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 651#define ath_hal_gettsf32(_ah) \ 652 OS_REG_READ(_ah, AR_TSF_L32) 653#define ath_hal_gettsf64(_ah) \ 654 ((*(_ah)->ah_getTsf64)((_ah))) 655#define ath_hal_resettsf(_ah) \ 656 ((*(_ah)->ah_resetTsf)((_ah))) 657#define ath_hal_rxena(_ah) \ 658 ((*(_ah)->ah_enableReceive)((_ah))) 659#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 660 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 661#define ath_hal_gettxbuf(_ah, _q) \ 662 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 663#define ath_hal_numtxpending(_ah, _q) \ 664 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 665#define ath_hal_getrxbuf(_ah) \ 666 ((*(_ah)->ah_getRxDP)((_ah))) 667#define ath_hal_txstart(_ah, _q) \ 668 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 669#define ath_hal_setchannel(_ah, _chan) \ 670 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 671#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 672 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 673#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 674 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 675#define ath_hal_calreset(_ah, _chan) \ 676 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 677#define ath_hal_setledstate(_ah, _state) \ 678 ((*(_ah)->ah_setLedState)((_ah), (_state))) 679#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 680 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 681#define ath_hal_beaconreset(_ah) \ 682 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 683#define ath_hal_beaconsettimers(_ah, _bt) \ 684 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 685#define ath_hal_beacontimers(_ah, _bs) \ 686 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 687#define ath_hal_getnexttbtt(_ah) \ 688 ((*(_ah)->ah_getNextTBTT)((_ah))) 689#define ath_hal_setassocid(_ah, _bss, _associd) \ 690 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 691#define ath_hal_phydisable(_ah) \ 692 ((*(_ah)->ah_phyDisable)((_ah))) 693#define ath_hal_setopmode(_ah) \ 694 ((*(_ah)->ah_setPCUConfig)((_ah))) 695#define ath_hal_stoptxdma(_ah, _qnum) \ 696 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 697#define ath_hal_stoppcurecv(_ah) \ 698 ((*(_ah)->ah_stopPcuReceive)((_ah))) 699#define ath_hal_startpcurecv(_ah) \ 700 ((*(_ah)->ah_startPcuReceive)((_ah))) 701#define ath_hal_stopdmarecv(_ah) \ 702 ((*(_ah)->ah_stopDmaReceive)((_ah))) 703#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 704 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 705 (_indata), (_insize), (_outdata), (_outsize))) 706#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 707 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 708#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 709 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 710#define ath_hal_resettxqueue(_ah, _q) \ 711 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 712#define ath_hal_releasetxqueue(_ah, _q) \ 713 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 714#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 715 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 716#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 717 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 718/* NB: common across all chips */ 719#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 720#define ath_hal_txqenabled(_ah, _qnum) \ 721 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 722#define ath_hal_getrfgain(_ah) \ 723 ((*(_ah)->ah_getRfGain)((_ah))) 724#define ath_hal_getdefantenna(_ah) \ 725 ((*(_ah)->ah_getDefAntenna)((_ah))) 726#define ath_hal_setdefantenna(_ah, _ant) \ 727 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 728#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 729 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 730#define ath_hal_ani_poll(_ah, _chan) \ 731 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 732#define ath_hal_mibevent(_ah, _stats) \ 733 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 734#define ath_hal_setslottime(_ah, _us) \ 735 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 736#define ath_hal_getslottime(_ah) \ 737 ((*(_ah)->ah_getSlotTime)((_ah))) 738#define ath_hal_setacktimeout(_ah, _us) \ 739 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 740#define ath_hal_getacktimeout(_ah) \ 741 ((*(_ah)->ah_getAckTimeout)((_ah))) 742#define ath_hal_setctstimeout(_ah, _us) \ 743 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 744#define ath_hal_getctstimeout(_ah) \ 745 ((*(_ah)->ah_getCTSTimeout)((_ah))) 746#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 747 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 748#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 749 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 750#define ath_hal_ciphersupported(_ah, _cipher) \ 751 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 752#define ath_hal_getregdomain(_ah, _prd) \ 753 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 754#define ath_hal_setregdomain(_ah, _rd) \ 755 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 756#define ath_hal_getcountrycode(_ah, _pcc) \ 757 (*(_pcc) = (_ah)->ah_countryCode) 758#define ath_hal_gettkipmic(_ah) \ 759 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 760#define ath_hal_settkipmic(_ah, _v) \ 761 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 762#define ath_hal_hastkipsplit(_ah) \ 763 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 764#define ath_hal_gettkipsplit(_ah) \ 765 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 766#define ath_hal_settkipsplit(_ah, _v) \ 767 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 768#define ath_hal_haswmetkipmic(_ah) \ 769 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 770#define ath_hal_hwphycounters(_ah) \ 771 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 772#define ath_hal_hasdiversity(_ah) \ 773 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 774#define ath_hal_getdiversity(_ah) \ 775 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 776#define ath_hal_setdiversity(_ah, _v) \ 777 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 778#define ath_hal_getantennaswitch(_ah) \ 779 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 780#define ath_hal_setantennaswitch(_ah, _v) \ 781 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 782#define ath_hal_getdiag(_ah, _pv) \ 783 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 784#define ath_hal_setdiag(_ah, _v) \ 785 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 786#define ath_hal_getnumtxqueues(_ah, _pv) \ 787 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 788#define ath_hal_hasveol(_ah) \ 789 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 790#define ath_hal_hastxpowlimit(_ah) \ 791 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 792#define ath_hal_settxpowlimit(_ah, _pow) \ 793 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 794#define ath_hal_gettxpowlimit(_ah, _ppow) \ 795 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 796#define ath_hal_getmaxtxpow(_ah, _ppow) \ 797 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 798#define ath_hal_gettpscale(_ah, _scale) \ 799 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 800#define ath_hal_settpscale(_ah, _v) \ 801 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 802#define ath_hal_hastpc(_ah) \ 803 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 804#define ath_hal_gettpc(_ah) \ 805 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 806#define ath_hal_settpc(_ah, _v) \ 807 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 808#define ath_hal_hasbursting(_ah) \ 809 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 810#define ath_hal_setmcastkeysearch(_ah, _v) \ 811 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 812#define ath_hal_hasmcastkeysearch(_ah) \ 813 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 814#define ath_hal_getmcastkeysearch(_ah) \ 815 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 816#define ath_hal_hasfastframes(_ah) \ 817 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 818#define ath_hal_hasbssidmask(_ah) \ 819 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 820#define ath_hal_hasbssidmatch(_ah) \ 821 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 822#define ath_hal_hastsfadjust(_ah) \ 823 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 824#define ath_hal_gettsfadjust(_ah) \ 825 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 826#define ath_hal_settsfadjust(_ah, _onoff) \ 827 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 828#define ath_hal_hasrfsilent(_ah) \ 829 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 830#define ath_hal_getrfkill(_ah) \ 831 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 832#define ath_hal_setrfkill(_ah, _onoff) \ 833 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 834#define ath_hal_getrfsilent(_ah, _prfsilent) \ 835 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 836#define ath_hal_setrfsilent(_ah, _rfsilent) \ 837 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 838#define ath_hal_gettpack(_ah, _ptpack) \ 839 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 840#define ath_hal_settpack(_ah, _tpack) \ 841 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 842#define ath_hal_gettpcts(_ah, _ptpcts) \ 843 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 844#define ath_hal_settpcts(_ah, _tpcts) \ 845 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 846#define ath_hal_hasintmit(_ah) \ 847 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 848#define ath_hal_getintmit(_ah) \ 849 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 850#define ath_hal_setintmit(_ah, _v) \ 851 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, _v, NULL) 852#define ath_hal_getchannoise(_ah, _c) \ 853 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 854#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 855 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 856#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 857 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 858#define ath_hal_split4ktrans(_ah) \ 859 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, 0, NULL) == HAL_OK) 860#define ath_hal_self_linked_final_rxdesc(_ah) \ 861 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, 0, NULL) == HAL_OK) 862#define ath_hal_gtxto_supported(_ah) \ 863 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 864#define ath_hal_has_long_rxdesc_tsf(_ah) \ 865 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, 0, NULL) == HAL_OK) 866 867#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 868 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 869#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 870 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 871#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 872 _txr0, _txtr0, _keyix, _ant, _flags, \ 873 _rtsrate, _rtsdura) \ 874 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 875 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 876 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 877#define ath_hal_setupxtxdesc(_ah, _ds, \ 878 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 879 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 880 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 881#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 882 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 883#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 884 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 885#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 886 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 887#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 888 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 889 890#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 891 _txr0, _txtr0, _antm, _rcr, _rcd) \ 892 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 893 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 894#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 895 _cipher, _delims, _seglen, _first, _last) \ 896 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 897 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 898 (_first), (_last))) 899#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 900 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 901 902#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 903 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 904 (_series), (_ns), (_flags))) 905 906#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 907 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 908#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 909 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 910#define ath_hal_set11n_aggr_last(_ah, _ds) \ 911 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 912 913#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 914 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 915#define ath_hal_clr11n_aggr(_ah, _ds) \ 916 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 917 918/* 919 * This is badly-named; you need to set the correct parameters 920 * to begin to receive useful radar events; and even then 921 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 922 * more information. 923 */ 924#define ath_hal_enabledfs(_ah, _param) \ 925 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 926#define ath_hal_getdfsthresh(_ah, _param) \ 927 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 928#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 929 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), (_buf), (_event))) 930#define ath_hal_is_fast_clock_enabled(_ah) \ 931 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 932 933#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 934 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 935#define ath_hal_gpioset(_ah, _gpio, _b) \ 936 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 937#define ath_hal_gpioget(_ah, _gpio) \ 938 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 939#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 940 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 941 942#define ath_hal_radar_wait(_ah, _chan) \ 943 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 944 945#endif /* _DEV_ATH_ATHVAR_H */ 946