if_athvar.h revision 182893
1/*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_athvar.h 182893 2008-09-09 16:21:25Z rpaulo $ 30 */ 31 32/* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35#ifndef _DEV_ATH_ATHVAR_H 36#define _DEV_ATH_ATHVAR_H 37 38#include <contrib/dev/ath/ah.h> 39#include <contrib/dev/ath/ah_desc.h> 40#include <net80211/ieee80211_radiotap.h> 41#include <dev/ath/if_athioctl.h> 42#include <dev/ath/if_athrate.h> 43 44#define ATH_TIMEOUT 1000 45 46#ifndef ATH_RXBUF 47#define ATH_RXBUF 40 /* number of RX buffers */ 48#endif 49#ifndef ATH_TXBUF 50#define ATH_TXBUF 200 /* number of TX buffers */ 51#endif 52#define ATH_BCBUF 4 /* number of beacon buffers */ 53 54#define ATH_TXDESC 10 /* number of descriptors per buffer */ 55#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 56#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 57#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 58 59#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 60#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 61#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 62 63/* 64 * The key cache is used for h/w cipher state and also for 65 * tracking station state such as the current tx antenna. 66 * We also setup a mapping table between key cache slot indices 67 * and station state to short-circuit node lookups on rx. 68 * Different parts have different size key caches. We handle 69 * up to ATH_KEYMAX entries (could dynamically allocate state). 70 */ 71#define ATH_KEYMAX 128 /* max key cache size we handle */ 72#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 73 74#define ATH_FF_TXQMIN 2 /* min txq depth for staging */ 75#define ATH_FF_TXQMAX 50 /* maximum # of queued frames allowed */ 76#define ATH_FF_STAGEMAX 5 /* max waiting period for staged frame*/ 77 78struct taskqueue; 79struct kthread; 80struct ath_buf; 81 82/* driver-specific node state */ 83struct ath_node { 84 struct ieee80211_node an_node; /* base class */ 85 const struct ieee80211_txparam *an_tp; 86 u_int8_t an_mgmtrix; /* min h/w rate index */ 87 u_int8_t an_mcastrix; /* mcast h/w rate index */ 88 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 89 /* variable-length rate control state follows */ 90}; 91#define ATH_NODE(ni) ((struct ath_node *)(ni)) 92#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 93 94#define ATH_RSSI_LPF_LEN 10 95#define ATH_RSSI_DUMMY_MARKER 0x127 96#define ATH_EP_MUL(x, mul) ((x) * (mul)) 97#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 98#define ATH_LPF_RSSI(x, y, len) \ 99 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 100#define ATH_RSSI_LPF(x, y) do { \ 101 if ((y) >= -20) \ 102 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 103} while (0) 104 105struct ath_buf { 106 STAILQ_ENTRY(ath_buf) bf_list; 107 TAILQ_ENTRY(ath_buf) bf_stagelist; /* stage queue list */ 108 u_int32_t bf_age; /* age when placed on stageq */ 109 int bf_nseg; 110 int bf_flags; /* tx descriptor flags */ 111 struct ath_desc *bf_desc; /* virtual addr of desc */ 112 struct ath_desc_status bf_status; /* tx/rx status */ 113 bus_addr_t bf_daddr; /* physical addr of desc */ 114 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 115 struct mbuf *bf_m; /* mbuf for buf */ 116 struct ieee80211_node *bf_node; /* pointer to the node */ 117 bus_size_t bf_mapsize; 118#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 119 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 120}; 121typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 122 123/* 124 * DMA state for tx/rx descriptors. 125 */ 126struct ath_descdma { 127 const char* dd_name; 128 struct ath_desc *dd_desc; /* descriptors */ 129 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 130 bus_size_t dd_desc_len; /* size of dd_desc */ 131 bus_dma_segment_t dd_dseg; 132 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 133 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 134 struct ath_buf *dd_bufptr; /* associated buffers */ 135}; 136 137/* 138 * Data transmit queue state. One of these exists for each 139 * hardware transmit queue. Packets sent to us from above 140 * are assigned to queues based on their priority. Not all 141 * devices support a complete set of hardware transmit queues. 142 * For those devices the array sc_ac2q will map multiple 143 * priorities to fewer hardware queues (typically all to one 144 * hardware queue). 145 */ 146struct ath_txq { 147 u_int axq_qnum; /* hardware q number */ 148#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 149 u_int axq_depth; /* queue depth (stat only) */ 150 u_int axq_intrcnt; /* interrupt count */ 151 u_int32_t *axq_link; /* link ptr in last TX desc */ 152 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 153 struct mtx axq_lock; /* lock on q and link */ 154 char axq_name[12]; /* e.g. "ath0_txq4" */ 155 /* 156 * Fast-frame state. The staging queue holds awaiting 157 * a fast-frame pairing. Buffers on this queue are 158 * assigned an ``age'' and flushed when they wait too long. 159 */ 160 TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq; 161 u_int32_t axq_curage; /* queue age */ 162}; 163 164#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 165 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 166 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 167 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 168} while (0) 169#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 170#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 171#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 172#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 173 174#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 175 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 176 (_tq)->axq_depth++; \ 177 (_tq)->axq_curage++; \ 178} while (0) 179#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 180 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 181 (_tq)->axq_depth--; \ 182} while (0) 183/* NB: this does not do the "head empty check" that STAILQ_LAST does */ 184#define ATH_TXQ_LAST(_tq) \ 185 ((struct ath_buf *)(void *) \ 186 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 187 188struct ath_vap { 189 struct ieee80211vap av_vap; /* base class */ 190 int av_bslot; /* beacon slot index */ 191 struct ath_buf *av_bcbuf; /* beacon buffer */ 192 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 193 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 194 195 void (*av_recv_mgmt)(struct ieee80211_node *, 196 struct mbuf *, int, int, int, u_int32_t); 197 int (*av_newstate)(struct ieee80211vap *, 198 enum ieee80211_state, int); 199 void (*av_bmiss)(struct ieee80211vap *); 200}; 201#define ATH_VAP(vap) ((struct ath_vap *)(vap)) 202 203struct taskqueue; 204struct ath_tx99; 205 206struct ath_softc { 207 struct ifnet *sc_ifp; /* interface common */ 208 struct ath_stats sc_stats; /* interface statistics */ 209 int sc_debug; 210 int sc_nvaps; /* # vaps */ 211 int sc_nstavaps; /* # station vaps */ 212 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 213 u_int8_t sc_nbssid0; /* # vap's using base mac */ 214 uint32_t sc_bssidmask; /* bssid mask */ 215 216 void (*sc_node_free)(struct ieee80211_node *); 217 device_t sc_dev; 218 HAL_BUS_TAG sc_st; /* bus space tag */ 219 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 struct mtx sc_mtx; /* master lock (recursive) */ 222 struct taskqueue *sc_tq; /* private task queue */ 223 struct ath_hal *sc_ah; /* Atheros HAL */ 224 struct ath_ratectrl *sc_rc; /* tx rate control support */ 225 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 226 void (*sc_setdefantenna)(struct ath_softc *, u_int); 227 unsigned int sc_invalid : 1,/* disable hardware accesses */ 228 sc_mrretry : 1,/* multi-rate retry support */ 229 sc_softled : 1,/* enable LED gpio status */ 230 sc_splitmic : 1,/* split TKIP MIC keys */ 231 sc_needmib : 1,/* enable MIB stats intr */ 232 sc_diversity: 1,/* enable rx diversity */ 233 sc_hasveol : 1,/* tx VEOL support */ 234 sc_ledstate : 1,/* LED on/off state */ 235 sc_blinking : 1,/* LED blink operation active */ 236 sc_mcastkey : 1,/* mcast key cache search */ 237 sc_scanning : 1,/* scanning active */ 238 sc_syncbeacon:1,/* sync/resync beacon timers */ 239 sc_hasclrkey: 1,/* CLR key supported */ 240 sc_xchanmode: 1,/* extended channel mode */ 241 sc_outdoor : 1,/* outdoor operation */ 242 sc_dturbo : 1,/* dynamic turbo in use */ 243 sc_hasbmask : 1,/* bssid mask support */ 244 sc_hastsfadd: 1,/* tsf adjust support */ 245 sc_beacons : 1,/* beacons running */ 246 sc_swbmiss : 1,/* sta mode using sw bmiss */ 247 sc_stagbeacons:1,/* use staggered beacons */ 248 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 249 sc_resume_up: 1;/* on resume, start all vaps */ 250 uint32_t sc_eerd; /* regdomain from EEPROM */ 251 uint32_t sc_eecc; /* country code from EEPROM */ 252 /* rate tables */ 253#define IEEE80211_MODE_HALF (IEEE80211_MODE_MAX+0) 254#define IEEE80211_MODE_QUARTER (IEEE80211_MODE_MAX+1) 255 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX+2]; 256 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 257 enum ieee80211_phymode sc_curmode; /* current phy mode */ 258 HAL_OPMODE sc_opmode; /* current operating mode */ 259 u_int16_t sc_curtxpow; /* current tx power limit */ 260 u_int16_t sc_curaid; /* current association id */ 261 HAL_CHANNEL sc_curchan; /* current h/w channel */ 262 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 263 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 264 struct { 265 u_int8_t ieeerate; /* IEEE rate */ 266 u_int8_t rxflags; /* radiotap rx flags */ 267 u_int8_t txflags; /* radiotap tx flags */ 268 u_int16_t ledon; /* softled on time */ 269 u_int16_t ledoff; /* softled off time */ 270 } sc_hwmap[32]; /* h/w rate ix mappings */ 271 u_int8_t sc_protrix; /* protection rate index */ 272 u_int8_t sc_lastdatarix; /* last data frame rate index */ 273 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 274 u_int sc_fftxqmin; /* min frames before staging */ 275 u_int sc_fftxqmax; /* max frames before drop */ 276 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 277 HAL_INT sc_imask; /* interrupt mask copy */ 278 u_int sc_keymax; /* size of key cache */ 279 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 280 281 u_int sc_ledpin; /* GPIO pin for driving LED */ 282 u_int sc_ledon; /* pin setting for LED on */ 283 u_int sc_ledidle; /* idle polling interval */ 284 int sc_ledevent; /* time of last LED event */ 285 u_int8_t sc_rxrate; /* current rx rate for LED */ 286 u_int8_t sc_txrate; /* current tx rate for LED */ 287 u_int16_t sc_ledoff; /* off time for current blink */ 288 struct callout sc_ledtimer; /* led off timer */ 289 290 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 291 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 292 293 struct ath_tx_radiotap_header sc_tx_th; 294 int sc_tx_th_len; 295 struct ath_rx_radiotap_header sc_rx_th; 296 int sc_rx_th_len; 297 u_int sc_monpass; /* frames to pass in mon.mode */ 298 299 struct ath_descdma sc_rxdma; /* RX descriptors */ 300 ath_bufhead sc_rxbuf; /* receive buffer */ 301 struct mbuf *sc_rxpending; /* pending receive data */ 302 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 303 struct task sc_rxtask; /* rx int processing */ 304 struct task sc_rxorntask; /* rxorn int processing */ 305 u_int8_t sc_defant; /* current default antenna */ 306 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 307 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 308 309 struct ath_descdma sc_txdma; /* TX descriptors */ 310 ath_bufhead sc_txbuf; /* transmit buffer */ 311 struct mtx sc_txbuflock; /* txbuf lock */ 312 char sc_txname[12]; /* e.g. "ath0_buf" */ 313 u_int sc_txqsetup; /* h/w queues setup */ 314 u_int sc_txintrperiod;/* tx interrupt batching */ 315 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 316 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 317 struct task sc_txtask; /* tx int processing */ 318 319 struct ath_descdma sc_bdma; /* beacon descriptors */ 320 ath_bufhead sc_bbuf; /* beacon buffers */ 321 u_int sc_bhalq; /* HAL q for outgoing beacons */ 322 u_int sc_bmisscount; /* missed beacon transmits */ 323 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 324 struct ath_txq *sc_cabq; /* tx q for cab frames */ 325 struct task sc_bmisstask; /* bmiss int processing */ 326 struct task sc_bstucktask; /* stuck beacon processing */ 327 enum { 328 OK, /* no change needed */ 329 UPDATE, /* update pending */ 330 COMMIT /* beacon sent, commit change */ 331 } sc_updateslot; /* slot time update fsm */ 332 int sc_slotupdate; /* slot to advance fsm */ 333 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 334 int sc_nbcnvaps; /* # vaps with beacons */ 335 336 struct callout sc_cal_ch; /* callout handle for cals */ 337 int sc_calinterval; /* current polling interval */ 338 int sc_caltries; /* cals at current interval */ 339 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 340}; 341 342#define ATH_LOCK_INIT(_sc) \ 343 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 344 NULL, MTX_DEF | MTX_RECURSE) 345#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 346#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 347#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 348#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 349 350#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 351 352#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 353 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 354 device_get_nameunit((_sc)->sc_dev)); \ 355 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 356} while (0) 357#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 358#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 359#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 360#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 361 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 362 363int ath_attach(u_int16_t, struct ath_softc *); 364int ath_detach(struct ath_softc *); 365void ath_resume(struct ath_softc *); 366void ath_suspend(struct ath_softc *); 367void ath_shutdown(struct ath_softc *); 368void ath_intr(void *); 369 370/* 371 * HAL definitions to comply with local coding convention. 372 */ 373#define ath_hal_detach(_ah) \ 374 ((*(_ah)->ah_detach)((_ah))) 375#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 376 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 377#define ath_hal_getratetable(_ah, _mode) \ 378 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 379#define ath_hal_getmac(_ah, _mac) \ 380 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 381#define ath_hal_setmac(_ah, _mac) \ 382 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 383#define ath_hal_getbssidmask(_ah, _mask) \ 384 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 385#define ath_hal_setbssidmask(_ah, _mask) \ 386 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 387#define ath_hal_intrset(_ah, _mask) \ 388 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 389#define ath_hal_intrget(_ah) \ 390 ((*(_ah)->ah_getInterrupts)((_ah))) 391#define ath_hal_intrpend(_ah) \ 392 ((*(_ah)->ah_isInterruptPending)((_ah))) 393#define ath_hal_getisr(_ah, _pmask) \ 394 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 395#define ath_hal_updatetxtriglevel(_ah, _inc) \ 396 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 397#define ath_hal_setpower(_ah, _mode) \ 398 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 399#define ath_hal_keycachesize(_ah) \ 400 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 401#define ath_hal_keyreset(_ah, _ix) \ 402 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 403#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 404 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 405#define ath_hal_keyisvalid(_ah, _ix) \ 406 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 407#define ath_hal_keysetmac(_ah, _ix, _mac) \ 408 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 409#define ath_hal_getrxfilter(_ah) \ 410 ((*(_ah)->ah_getRxFilter)((_ah))) 411#define ath_hal_setrxfilter(_ah, _filter) \ 412 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 413#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 414 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 415#define ath_hal_waitforbeacon(_ah, _bf) \ 416 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 417#define ath_hal_putrxbuf(_ah, _bufaddr) \ 418 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 419#define ath_hal_gettsf32(_ah) \ 420 ((*(_ah)->ah_getTsf32)((_ah))) 421#define ath_hal_gettsf64(_ah) \ 422 ((*(_ah)->ah_getTsf64)((_ah))) 423#define ath_hal_resettsf(_ah) \ 424 ((*(_ah)->ah_resetTsf)((_ah))) 425#define ath_hal_rxena(_ah) \ 426 ((*(_ah)->ah_enableReceive)((_ah))) 427#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 428 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 429#define ath_hal_gettxbuf(_ah, _q) \ 430 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 431#define ath_hal_numtxpending(_ah, _q) \ 432 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 433#define ath_hal_getrxbuf(_ah) \ 434 ((*(_ah)->ah_getRxDP)((_ah))) 435#define ath_hal_txstart(_ah, _q) \ 436 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 437#define ath_hal_setchannel(_ah, _chan) \ 438 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 439#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 440 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 441#define ath_hal_setledstate(_ah, _state) \ 442 ((*(_ah)->ah_setLedState)((_ah), (_state))) 443#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 444 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 445#define ath_hal_beaconreset(_ah) \ 446 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 447#define ath_hal_beacontimers(_ah, _bs) \ 448 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 449#define ath_hal_setassocid(_ah, _bss, _associd) \ 450 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 451#define ath_hal_phydisable(_ah) \ 452 ((*(_ah)->ah_phyDisable)((_ah))) 453#define ath_hal_setopmode(_ah) \ 454 ((*(_ah)->ah_setPCUConfig)((_ah))) 455#define ath_hal_stoptxdma(_ah, _qnum) \ 456 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 457#define ath_hal_stoppcurecv(_ah) \ 458 ((*(_ah)->ah_stopPcuReceive)((_ah))) 459#define ath_hal_startpcurecv(_ah) \ 460 ((*(_ah)->ah_startPcuReceive)((_ah))) 461#define ath_hal_stopdmarecv(_ah) \ 462 ((*(_ah)->ah_stopDmaReceive)((_ah))) 463#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 464 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 465 (_indata), (_insize), (_outdata), (_outsize))) 466#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 467 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 468#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 469 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 470#define ath_hal_resettxqueue(_ah, _q) \ 471 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 472#define ath_hal_releasetxqueue(_ah, _q) \ 473 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 474#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 475 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 476#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 477 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 478#define ath_hal_getrfgain(_ah) \ 479 ((*(_ah)->ah_getRfGain)((_ah))) 480#define ath_hal_getdefantenna(_ah) \ 481 ((*(_ah)->ah_getDefAntenna)((_ah))) 482#define ath_hal_setdefantenna(_ah, _ant) \ 483 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 484#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 485 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 486#define ath_hal_mibevent(_ah, _stats) \ 487 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 488#define ath_hal_setslottime(_ah, _us) \ 489 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 490#define ath_hal_getslottime(_ah) \ 491 ((*(_ah)->ah_getSlotTime)((_ah))) 492#define ath_hal_setacktimeout(_ah, _us) \ 493 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 494#define ath_hal_getacktimeout(_ah) \ 495 ((*(_ah)->ah_getAckTimeout)((_ah))) 496#define ath_hal_setctstimeout(_ah, _us) \ 497 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 498#define ath_hal_getctstimeout(_ah) \ 499 ((*(_ah)->ah_getCTSTimeout)((_ah))) 500#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 501 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 502#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 503 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 504#define ath_hal_ciphersupported(_ah, _cipher) \ 505 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 506#define ath_hal_getregdomain(_ah, _prd) \ 507 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 508#define ath_hal_setregdomain(_ah, _rd) \ 509 (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 128) = (_rd)) 510#define ath_hal_getcountrycode(_ah, _pcc) \ 511 (*(_pcc) = (_ah)->ah_countryCode) 512#define ath_hal_gettkipmic(_ah) \ 513 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 514#define ath_hal_settkipmic(_ah, _v) \ 515 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 516#define ath_hal_hastkipsplit(_ah) \ 517 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 518#define ath_hal_gettkipsplit(_ah) \ 519 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 520#define ath_hal_settkipsplit(_ah, _v) \ 521 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 522#define ath_hal_haswmetkipmic(_ah) \ 523 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 524#define ath_hal_hwphycounters(_ah) \ 525 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 526#define ath_hal_hasdiversity(_ah) \ 527 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 528#define ath_hal_getdiversity(_ah) \ 529 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 530#define ath_hal_setdiversity(_ah, _v) \ 531 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 532#define ath_hal_getantennaswitch(_ah) \ 533 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 534#define ath_hal_setantennaswitch(_ah, _v) \ 535 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 536#define ath_hal_getdiag(_ah, _pv) \ 537 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 538#define ath_hal_setdiag(_ah, _v) \ 539 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 540#define ath_hal_getnumtxqueues(_ah, _pv) \ 541 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 542#define ath_hal_hasveol(_ah) \ 543 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 544#define ath_hal_hastxpowlimit(_ah) \ 545 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 546#define ath_hal_settxpowlimit(_ah, _pow) \ 547 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 548#define ath_hal_gettxpowlimit(_ah, _ppow) \ 549 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 550#define ath_hal_getmaxtxpow(_ah, _ppow) \ 551 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 552#define ath_hal_gettpscale(_ah, _scale) \ 553 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 554#define ath_hal_settpscale(_ah, _v) \ 555 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 556#define ath_hal_hastpc(_ah) \ 557 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 558#define ath_hal_gettpc(_ah) \ 559 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 560#define ath_hal_settpc(_ah, _v) \ 561 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 562#define ath_hal_hasbursting(_ah) \ 563 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 564#ifdef notyet 565#define ath_hal_hasmcastkeysearch(_ah) \ 566 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 567#define ath_hal_getmcastkeysearch(_ah) \ 568 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 569#else 570#define ath_hal_getmcastkeysearch(_ah) 0 571#endif 572#define ath_hal_hasfastframes(_ah) \ 573 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 574#define ath_hal_hasbssidmask(_ah) \ 575 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 576#define ath_hal_hastsfadjust(_ah) \ 577 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 578#define ath_hal_gettsfadjust(_ah) \ 579 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 580#define ath_hal_settsfadjust(_ah, _onoff) \ 581 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 582#define ath_hal_hasrfsilent(_ah) \ 583 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 584#define ath_hal_getrfkill(_ah) \ 585 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 586#define ath_hal_setrfkill(_ah, _onoff) \ 587 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 588#define ath_hal_getrfsilent(_ah, _prfsilent) \ 589 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 590#define ath_hal_setrfsilent(_ah, _rfsilent) \ 591 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 592#define ath_hal_gettpack(_ah, _ptpack) \ 593 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 594#define ath_hal_settpack(_ah, _tpack) \ 595 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 596#define ath_hal_gettpcts(_ah, _ptpcts) \ 597 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 598#define ath_hal_settpcts(_ah, _tpcts) \ 599 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 600#define ath_hal_getchannoise(_ah, _c) \ 601 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 602#if HAL_ABI_VERSION < 0x05122200 603#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 604#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 605#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 606#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 607#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 608#endif 609#if HAL_ABI_VERSION < 0x06102501 610#define ath_hal_ispublicsafetysku(ah) \ 611 (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \ 612 (ah)->ah_regdomain == 0x12) 613#endif 614#if HAL_ABI_VERSION < 0x06122400 615/* XXX yech, can't get to regdomain so just hack a compat shim */ 616#define ath_hal_isgsmsku(ah) \ 617 ((ah)->ah_countryCode == 843) 618#endif 619#if HAL_ABI_VERSION < 0x07050400 620/* compat shims so code compilers--it won't work though */ 621#define CHANNEL_HT20 0x10000 622#define CHANNEL_HT40PLUS 0x20000 623#define CHANNEL_HT40MINUS 0x40000 624#define HAL_MODE_11NG_HT20 0x008000 625#define HAL_MODE_11NA_HT20 0x010000 626#endif 627 628#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 629 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 630#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 631 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 632#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 633 _txr0, _txtr0, _keyix, _ant, _flags, \ 634 _rtsrate, _rtsdura) \ 635 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 636 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 637 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 638#define ath_hal_setupxtxdesc(_ah, _ds, \ 639 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 640 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 641 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 642#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 643 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 644#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 645 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 646#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 647 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 648 649#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 650 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 651#define ath_hal_gpioset(_ah, _gpio, _b) \ 652 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 653#define ath_hal_gpioget(_ah, _gpio) \ 654 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 655#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 656 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 657 658#define ath_hal_radar_wait(_ah, _chan) \ 659 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 660 661#endif /* _DEV_ATH_ATHVAR_H */ 662