if_athvar.h revision 155991
1/*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD: head/sys/dev/ath/if_athvar.h 155991 2006-02-24 23:10:08Z sam $ 37 */ 38 39/* 40 * Defintions for the Atheros Wireless LAN controller driver. 41 */ 42#ifndef _DEV_ATH_ATHVAR_H 43#define _DEV_ATH_ATHVAR_H 44 45#include <sys/taskqueue.h> 46 47#include <contrib/dev/ath/ah.h> 48#include <net80211/ieee80211_radiotap.h> 49#include <dev/ath/if_athioctl.h> 50#include <dev/ath/if_athrate.h> 51 52#define ATH_TIMEOUT 1000 53 54#ifndef ATH_RXBUF 55#define ATH_RXBUF 40 /* number of RX buffers */ 56#endif 57#ifndef ATH_TXBUF 58#define ATH_TXBUF 100 /* number of TX buffers */ 59#endif 60#define ATH_TXDESC 10 /* number of descriptors per buffer */ 61#define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 62#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 63#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 64 65#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 66#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 67#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 68 69/* 70 * The key cache is used for h/w cipher state and also for 71 * tracking station state such as the current tx antenna. 72 * We also setup a mapping table between key cache slot indices 73 * and station state to short-circuit node lookups on rx. 74 * Different parts have different size key caches. We handle 75 * up to ATH_KEYMAX entries (could dynamically allocate state). 76 */ 77#define ATH_KEYMAX 128 /* max key cache size we handle */ 78#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 79 80/* driver-specific node state */ 81struct ath_node { 82 struct ieee80211_node an_node; /* base class */ 83 u_int32_t an_avgrssi; /* average rssi over all rx frames */ 84 /* variable-length rate control state follows */ 85}; 86#define ATH_NODE(ni) ((struct ath_node *)(ni)) 87#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 88 89#define ATH_RSSI_LPF_LEN 10 90#define ATH_RSSI_DUMMY_MARKER 0x127 91#define ATH_EP_MUL(x, mul) ((x) * (mul)) 92#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 93#define ATH_LPF_RSSI(x, y, len) \ 94 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 95#define ATH_RSSI_LPF(x, y) do { \ 96 if ((y) >= -20) \ 97 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 98} while (0) 99 100struct ath_buf { 101 STAILQ_ENTRY(ath_buf) bf_list; 102 int bf_nseg; 103 u_int16_t bf_txflags; /* tx descriptor flags */ 104 u_int16_t bf_flags; /* see below */ 105 struct ath_desc *bf_desc; /* virtual addr of desc */ 106 bus_addr_t bf_daddr; /* physical addr of desc */ 107 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 108 struct mbuf *bf_m; /* mbuf for buf */ 109 struct ieee80211_node *bf_node; /* pointer to the node */ 110 bus_size_t bf_mapsize; 111#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 112 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 113}; 114typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 115 116#define ATH_FLAG_BUSY 0x0001 /* tx descriptor owned by h/w */ 117 118/* 119 * DMA state for tx/rx descriptors. 120 */ 121struct ath_descdma { 122 const char* dd_name; 123 struct ath_desc *dd_desc; /* descriptors */ 124 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 125 bus_addr_t dd_desc_len; /* size of dd_desc */ 126 bus_dma_segment_t dd_dseg; 127 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 128 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 129 struct ath_buf *dd_bufptr; /* associated buffers */ 130}; 131 132/* 133 * Data transmit queue state. One of these exists for each 134 * hardware transmit queue. Packets sent to us from above 135 * are assigned to queues based on their priority. Not all 136 * devices support a complete set of hardware transmit queues. 137 * For those devices the array sc_ac2q will map multiple 138 * priorities to fewer hardware queues (typically all to one 139 * hardware queue). 140 */ 141struct ath_txq { 142 u_int axq_qnum; /* hardware q number */ 143 int axq_depth; /* queue depth (stat only) */ 144 u_int axq_intrcnt; /* interrupt count */ 145 u_int32_t *axq_link; /* link ptr in last TX desc */ 146 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 147 struct mtx axq_lock; /* lock on q and link */ 148 char axq_name[12]; /* e.g. "ath0_txq4" */ 149}; 150 151#define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 152 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 153 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 154 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, "ath_txq", MTX_DEF); \ 155} while (0); 156#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 157#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 158#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 159#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 160 161#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 162 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 163 (_tq)->axq_depth++; \ 164} while (0) 165#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 166 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 167 (_tq)->axq_depth--; \ 168} while (0) 169 170struct taskqueue; 171struct ath_tx99; 172 173struct ath_softc { 174 struct ifnet *sc_ifp; /* interface common */ 175 struct ath_stats sc_stats; /* interface statistics */ 176 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 177 int sc_countrycode; 178 int sc_debug; 179 void (*sc_recv_mgmt)(struct ieee80211com *, 180 struct mbuf *, 181 struct ieee80211_node *, 182 int, int, u_int32_t); 183 int (*sc_newstate)(struct ieee80211com *, 184 enum ieee80211_state, int); 185 void (*sc_node_free)(struct ieee80211_node *); 186 device_t sc_dev; 187 bus_space_tag_t sc_st; /* bus space tag */ 188 bus_space_handle_t sc_sh; /* bus space handle */ 189 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 190 struct mtx sc_mtx; /* master lock (recursive) */ 191 struct taskqueue *sc_tq; /* private task queue */ 192 struct ath_hal *sc_ah; /* Atheros HAL */ 193 struct ath_ratectrl *sc_rc; /* tx rate control support */ 194 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 195 void (*sc_setdefantenna)(struct ath_softc *, u_int); 196 unsigned int sc_invalid : 1, /* disable hardware accesses */ 197 sc_mrretry : 1, /* multi-rate retry support */ 198 sc_softled : 1, /* enable LED gpio status */ 199 sc_splitmic: 1, /* split TKIP MIC keys */ 200 sc_needmib : 1, /* enable MIB stats intr */ 201 sc_diversity : 1,/* enable rx diversity */ 202 sc_hasveol : 1, /* tx VEOL support */ 203 sc_ledstate: 1, /* LED on/off state */ 204 sc_blinking: 1, /* LED blink operation active */ 205 sc_mcastkey: 1, /* mcast key cache search */ 206 sc_syncbeacon:1,/* sync/resync beacon timers */ 207 sc_hasclrkey:1; /* CLR key supported */ 208 /* rate tables */ 209 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 210 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 211 enum ieee80211_phymode sc_curmode; /* current phy mode */ 212 HAL_OPMODE sc_opmode; /* current operating mode */ 213 u_int16_t sc_curtxpow; /* current tx power limit */ 214 HAL_CHANNEL sc_curchan; /* current h/w channel */ 215 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 216 struct { 217 u_int8_t ieeerate; /* IEEE rate */ 218 u_int8_t rxflags; /* radiotap rx flags */ 219 u_int8_t txflags; /* radiotap tx flags */ 220 u_int16_t ledon; /* softled on time */ 221 u_int16_t ledoff; /* softled off time */ 222 } sc_hwmap[32]; /* h/w rate ix mappings */ 223 u_int8_t sc_minrateix; /* min h/w rate index */ 224 u_int8_t sc_mcastrix; /* mcast h/w rate index */ 225 u_int8_t sc_protrix; /* protection rate index */ 226 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 227 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 228 HAL_INT sc_imask; /* interrupt mask copy */ 229 u_int sc_keymax; /* size of key cache */ 230 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 231 232 u_int sc_ledpin; /* GPIO pin for driving LED */ 233 u_int sc_ledon; /* pin setting for LED on */ 234 u_int sc_ledidle; /* idle polling interval */ 235 int sc_ledevent; /* time of last LED event */ 236 u_int8_t sc_rxrate; /* current rx rate for LED */ 237 u_int8_t sc_txrate; /* current tx rate for LED */ 238 u_int16_t sc_ledoff; /* off time for current blink */ 239 struct callout sc_ledtimer; /* led off timer */ 240 241 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 242 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 243 244 struct bpf_if *sc_drvbpf; 245 union { 246 struct ath_tx_radiotap_header th; 247 u_int8_t pad[64]; 248 } u_tx_rt; 249 int sc_tx_th_len; 250 union { 251 struct ath_rx_radiotap_header th; 252 u_int8_t pad[64]; 253 } u_rx_rt; 254 int sc_rx_th_len; 255 u_int sc_monpass; /* frames to pass in mon.mode */ 256 257 struct ath_descdma sc_rxdma; /* RX descriptos */ 258 ath_bufhead sc_rxbuf; /* receive buffer */ 259 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 260 struct task sc_rxtask; /* rx int processing */ 261 struct task sc_rxorntask; /* rxorn int processing */ 262 struct task sc_radartask; /* radar processing */ 263 u_int8_t sc_defant; /* current default antenna */ 264 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 265 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 266 267 struct ath_descdma sc_txdma; /* TX descriptors */ 268 ath_bufhead sc_txbuf; /* transmit buffer */ 269 struct mtx sc_txbuflock; /* txbuf lock */ 270 char sc_txname[12]; /* e.g. "ath0_buf" */ 271 int sc_tx_timer; /* transmit timeout */ 272 u_int sc_txqsetup; /* h/w queues setup */ 273 u_int sc_txintrperiod;/* tx interrupt batching */ 274 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 275 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 276 struct task sc_txtask; /* tx int processing */ 277 278 struct ath_descdma sc_bdma; /* beacon descriptors */ 279 ath_bufhead sc_bbuf; /* beacon buffers */ 280 u_int sc_bhalq; /* HAL q for outgoing beacons */ 281 u_int sc_bmisscount; /* missed beacon transmits */ 282 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 283 struct ath_txq *sc_cabq; /* tx q for cab frames */ 284 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 285 struct task sc_bmisstask; /* bmiss int processing */ 286 struct task sc_bstucktask; /* stuck beacon processing */ 287 enum { 288 OK, /* no change needed */ 289 UPDATE, /* update pending */ 290 COMMIT /* beacon sent, commit change */ 291 } sc_updateslot; /* slot time update fsm */ 292 293 struct callout sc_cal_ch; /* callout handle for cals */ 294 int sc_calinterval; /* current polling interval */ 295 int sc_caltries; /* cals at current interval */ 296 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 297 struct callout sc_scan_ch; /* callout handle for scan */ 298 struct callout sc_dfs_ch; /* callout handle for dfs */ 299}; 300#define sc_tx_th u_tx_rt.th 301#define sc_rx_th u_rx_rt.th 302 303#define ATH_LOCK_INIT(_sc) \ 304 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 305 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 306#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 307#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 308#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 309#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 310 311#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 312 313#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 314 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 315 device_get_nameunit((_sc)->sc_dev)); \ 316 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, "ath_buf", MTX_DEF); \ 317} while (0) 318#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 319#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 320#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 321#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 322 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 323 324int ath_attach(u_int16_t, struct ath_softc *); 325int ath_detach(struct ath_softc *); 326void ath_resume(struct ath_softc *); 327void ath_suspend(struct ath_softc *); 328void ath_shutdown(struct ath_softc *); 329void ath_intr(void *); 330 331/* 332 * HAL definitions to comply with local coding convention. 333 */ 334#define ath_hal_detach(_ah) \ 335 ((*(_ah)->ah_detach)((_ah))) 336#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 337 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 338#define ath_hal_getratetable(_ah, _mode) \ 339 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 340#define ath_hal_getmac(_ah, _mac) \ 341 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 342#define ath_hal_setmac(_ah, _mac) \ 343 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 344#define ath_hal_intrset(_ah, _mask) \ 345 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 346#define ath_hal_intrget(_ah) \ 347 ((*(_ah)->ah_getInterrupts)((_ah))) 348#define ath_hal_intrpend(_ah) \ 349 ((*(_ah)->ah_isInterruptPending)((_ah))) 350#define ath_hal_getisr(_ah, _pmask) \ 351 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 352#define ath_hal_updatetxtriglevel(_ah, _inc) \ 353 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 354#define ath_hal_setpower(_ah, _mode) \ 355 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 356#define ath_hal_keycachesize(_ah) \ 357 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 358#define ath_hal_keyreset(_ah, _ix) \ 359 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 360#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 361 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 362#define ath_hal_keyisvalid(_ah, _ix) \ 363 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 364#define ath_hal_keysetmac(_ah, _ix, _mac) \ 365 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 366#define ath_hal_getrxfilter(_ah) \ 367 ((*(_ah)->ah_getRxFilter)((_ah))) 368#define ath_hal_setrxfilter(_ah, _filter) \ 369 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 370#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 371 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 372#define ath_hal_waitforbeacon(_ah, _bf) \ 373 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 374#define ath_hal_putrxbuf(_ah, _bufaddr) \ 375 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 376#define ath_hal_gettsf32(_ah) \ 377 ((*(_ah)->ah_getTsf32)((_ah))) 378#define ath_hal_gettsf64(_ah) \ 379 ((*(_ah)->ah_getTsf64)((_ah))) 380#define ath_hal_resettsf(_ah) \ 381 ((*(_ah)->ah_resetTsf)((_ah))) 382#define ath_hal_rxena(_ah) \ 383 ((*(_ah)->ah_enableReceive)((_ah))) 384#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 385 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 386#define ath_hal_gettxbuf(_ah, _q) \ 387 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 388#define ath_hal_numtxpending(_ah, _q) \ 389 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 390#define ath_hal_getrxbuf(_ah) \ 391 ((*(_ah)->ah_getRxDP)((_ah))) 392#define ath_hal_txstart(_ah, _q) \ 393 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 394#define ath_hal_setchannel(_ah, _chan) \ 395 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 396#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 397 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 398#define ath_hal_setledstate(_ah, _state) \ 399 ((*(_ah)->ah_setLedState)((_ah), (_state))) 400#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 401 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 402#define ath_hal_beaconreset(_ah) \ 403 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 404#define ath_hal_beacontimers(_ah, _bs) \ 405 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 406#define ath_hal_setassocid(_ah, _bss, _associd) \ 407 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 408#define ath_hal_phydisable(_ah) \ 409 ((*(_ah)->ah_phyDisable)((_ah))) 410#define ath_hal_setopmode(_ah) \ 411 ((*(_ah)->ah_setPCUConfig)((_ah))) 412#define ath_hal_stoptxdma(_ah, _qnum) \ 413 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 414#define ath_hal_stoppcurecv(_ah) \ 415 ((*(_ah)->ah_stopPcuReceive)((_ah))) 416#define ath_hal_startpcurecv(_ah) \ 417 ((*(_ah)->ah_startPcuReceive)((_ah))) 418#define ath_hal_stopdmarecv(_ah) \ 419 ((*(_ah)->ah_stopDmaReceive)((_ah))) 420#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 421 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 422 (_indata), (_insize), (_outdata), (_outsize))) 423#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 424 ath_hal_getdiagstate(_ah, 27, NULL, 0, (void **)(_outdata), _outsize) 425#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 426 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 427#define ath_hal_resettxqueue(_ah, _q) \ 428 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 429#define ath_hal_releasetxqueue(_ah, _q) \ 430 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 431#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 432 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 433#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 434 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 435#define ath_hal_getrfgain(_ah) \ 436 ((*(_ah)->ah_getRfGain)((_ah))) 437#define ath_hal_getdefantenna(_ah) \ 438 ((*(_ah)->ah_getDefAntenna)((_ah))) 439#define ath_hal_setdefantenna(_ah, _ant) \ 440 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 441#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 442 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 443#define ath_hal_mibevent(_ah, _stats) \ 444 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 445#define ath_hal_setslottime(_ah, _us) \ 446 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 447#define ath_hal_getslottime(_ah) \ 448 ((*(_ah)->ah_getSlotTime)((_ah))) 449#define ath_hal_setacktimeout(_ah, _us) \ 450 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 451#define ath_hal_getacktimeout(_ah) \ 452 ((*(_ah)->ah_getAckTimeout)((_ah))) 453#define ath_hal_setctstimeout(_ah, _us) \ 454 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 455#define ath_hal_getctstimeout(_ah) \ 456 ((*(_ah)->ah_getCTSTimeout)((_ah))) 457#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 458 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 459#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 460 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 461#define ath_hal_ciphersupported(_ah, _cipher) \ 462 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 463#define ath_hal_getregdomain(_ah, _prd) \ 464 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 465#define ath_hal_setregdomain(_ah, _rd) \ 466 ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL)) 467#define ath_hal_getcountrycode(_ah, _pcc) \ 468 (*(_pcc) = (_ah)->ah_countryCode) 469#define ath_hal_tkipsplit(_ah) \ 470 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 471#define ath_hal_hwphycounters(_ah) \ 472 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 473#define ath_hal_hasdiversity(_ah) \ 474 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 475#define ath_hal_getdiversity(_ah) \ 476 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 477#define ath_hal_setdiversity(_ah, _v) \ 478 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 479#define ath_hal_getdiag(_ah, _pv) \ 480 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 481#define ath_hal_setdiag(_ah, _v) \ 482 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 483#define ath_hal_getnumtxqueues(_ah, _pv) \ 484 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 485#define ath_hal_hasveol(_ah) \ 486 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 487#define ath_hal_hastxpowlimit(_ah) \ 488 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 489#define ath_hal_settxpowlimit(_ah, _pow) \ 490 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 491#define ath_hal_gettxpowlimit(_ah, _ppow) \ 492 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 493#define ath_hal_getmaxtxpow(_ah, _ppow) \ 494 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 495#define ath_hal_gettpscale(_ah, _scale) \ 496 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 497#define ath_hal_settpscale(_ah, _v) \ 498 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 499#define ath_hal_hastpc(_ah) \ 500 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 501#define ath_hal_gettpc(_ah) \ 502 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 503#define ath_hal_settpc(_ah, _v) \ 504 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 505#define ath_hal_hasbursting(_ah) \ 506 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 507#ifdef notyet 508#define ath_hal_hasmcastkeysearch(_ah) \ 509 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 510#define ath_hal_getmcastkeysearch(_ah) \ 511 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 512#else 513#define ath_hal_getmcastkeysearch(_ah) 0 514#endif 515#define ath_hal_hasrfsilent(_ah) \ 516 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 517#define ath_hal_getrfkill(_ah) \ 518 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 519#define ath_hal_setrfkill(_ah, _onoff) \ 520 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 521#define ath_hal_getrfsilent(_ah, _prfsilent) \ 522 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 523#define ath_hal_setrfsilent(_ah, _rfsilent) \ 524 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 525#define ath_hal_gettpack(_ah, _ptpack) \ 526 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 527#define ath_hal_settpack(_ah, _tpack) \ 528 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 529#define ath_hal_gettpcts(_ah, _ptpcts) \ 530 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 531#define ath_hal_settpcts(_ah, _tpcts) \ 532 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 533#if HAL_ABI_VERSION < 0x05120700 534#define ath_hal_process_noisefloor(_ah) 535#define ath_hal_getchannoise(_ah, _c) (-96) 536#define HAL_CAP_TPC_ACK 100 537#define HAL_CAP_TPC_CTS 101 538#else 539#define ath_hal_getchannoise(_ah, _c) \ 540 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 541#endif 542#if HAL_ABI_VERSION < 0x05122200 543#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 544#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 545#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 546#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 547#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 548#endif 549 550#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 551 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 552#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 553 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0)) 554#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 555 _txr0, _txtr0, _keyix, _ant, _flags, \ 556 _rtsrate, _rtsdura) \ 557 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 558 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 559 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 560#define ath_hal_setupxtxdesc(_ah, _ds, \ 561 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 562 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 563 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 564#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 565 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 566#define ath_hal_txprocdesc(_ah, _ds) \ 567 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 568#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 569 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 570 571#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 572 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 573#define ath_hal_gpioset(_ah, _gpio, _b) \ 574 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 575#define ath_hal_gpioget(_ah, _gpio) \ 576 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 577#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 578 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 579 580#define ath_hal_radar_event(_ah) \ 581 ((*(_ah)->ah_radarHaveEvent)((_ah))) 582#define ath_hal_procdfs(_ah, _chan) \ 583 ((*(_ah)->ah_processDfs)((_ah), (_chan))) 584#define ath_hal_checknol(_ah, _chan, _nchans) \ 585 ((*(_ah)->ah_dfsNolCheck)((_ah), (_chan), (_nchans))) 586#define ath_hal_radar_wait(_ah, _chan) \ 587 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 588 589#endif /* _DEV_ATH_ATHVAR_H */ 590