if_athvar.h revision 127780
1/*- 2 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD: head/sys/dev/ath/if_athvar.h 127780 2004-04-02 23:57:10Z sam $ 37 */ 38 39/* 40 * Defintions for the Atheros Wireless LAN controller driver. 41 */ 42#ifndef _DEV_ATH_ATHVAR_H 43#define _DEV_ATH_ATHVAR_H 44 45#include <sys/taskqueue.h> 46 47#include <contrib/dev/ath/ah.h> 48#include <net80211/ieee80211_radiotap.h> 49#include <dev/ath/if_athioctl.h> 50 51#define ATH_TIMEOUT 1000 52 53#define ATH_RXBUF 40 /* number of RX buffers */ 54#define ATH_TXBUF 60 /* number of TX buffers */ 55#define ATH_TXDESC 8 /* number of descriptors per buffer */ 56 57struct ath_recv_hist { 58 int arh_ticks; /* sample time by system clock */ 59 u_int8_t arh_rssi; /* rssi */ 60 u_int8_t arh_antenna; /* antenna */ 61}; 62#define ATH_RHIST_SIZE 16 /* number of samples */ 63#define ATH_RHIST_NOTIME (~0) 64 65/* driver-specific node */ 66struct ath_node { 67 struct ieee80211_node an_node; /* base class */ 68 u_int an_tx_ok; /* tx ok pkt */ 69 u_int an_tx_err; /* tx !ok pkt */ 70 u_int an_tx_retr; /* tx retry count */ 71 int an_tx_upper; /* tx upper rate req cnt */ 72 u_int an_tx_antenna; /* antenna for last good frame */ 73 u_int an_rx_antenna; /* antenna for last rcvd frame */ 74 struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE]; 75 u_int an_rx_hist_next;/* index of next ``free entry'' */ 76}; 77#define ATH_NODE(_n) ((struct ath_node *)(_n)) 78 79struct ath_buf { 80 TAILQ_ENTRY(ath_buf) bf_list; 81 int bf_nseg; 82 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 83 struct ath_desc *bf_desc; /* virtual addr of desc */ 84 bus_addr_t bf_daddr; /* physical addr of desc */ 85 struct mbuf *bf_m; /* mbuf for buf */ 86 struct ieee80211_node *bf_node; /* pointer to the node */ 87 bus_size_t bf_mapsize; 88#define ATH_MAX_SCATTER 64 89 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 90}; 91 92struct ath_softc { 93 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 94 int (*sc_newstate)(struct ieee80211com *, 95 enum ieee80211_state, int); 96 device_t sc_dev; 97 bus_space_tag_t sc_st; /* bus space tag */ 98 bus_space_handle_t sc_sh; /* bus space handle */ 99 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 100 struct mtx sc_mtx; /* master lock (recursive) */ 101 struct ath_hal *sc_ah; /* Atheros HAL */ 102 unsigned int sc_invalid : 1,/* disable hardware accesses */ 103 sc_doani : 1,/* dynamic noise immunity */ 104 sc_probing : 1;/* probing AP on beacon miss */ 105 /* rate tables */ 106 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 107 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 108 enum ieee80211_phymode sc_curmode; /* current phy mode */ 109 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 110 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 111 HAL_INT sc_imask; /* interrupt mask copy */ 112 113 struct bpf_if *sc_drvbpf; 114 union { 115 struct ath_tx_radiotap_header th; 116 u_int8_t pad[64]; 117 } u_tx_rt; 118 int sc_tx_th_len; 119 union { 120 struct ath_rx_radiotap_header th; 121 u_int8_t pad[64]; 122 } u_rx_rt; 123 int sc_rx_th_len; 124 125 struct ath_desc *sc_desc; /* TX/RX descriptors */ 126 bus_dma_segment_t sc_dseg; 127 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 128 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 129 bus_addr_t sc_desc_len; /* size of sc_desc */ 130 131 struct task sc_fataltask; /* fatal int processing */ 132 struct task sc_rxorntask; /* rxorn int processing */ 133 134 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 135 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 136 struct task sc_rxtask; /* rx int processing */ 137 138 u_int sc_txhalq; /* HAL q for outgoing frames */ 139 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 140 int sc_tx_timer; /* transmit timeout */ 141 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 142 struct mtx sc_txbuflock; /* txbuf lock */ 143 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 144 struct mtx sc_txqlock; /* lock on txq and txlink */ 145 struct task sc_txtask; /* tx int processing */ 146 147 u_int sc_bhalq; /* HAL q for outgoing beacons */ 148 struct ath_buf *sc_bcbuf; /* beacon buffer */ 149 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 150 struct task sc_swbatask; /* swba int processing */ 151 struct task sc_bmisstask; /* bmiss int processing */ 152 153 struct callout sc_cal_ch; /* callout handle for cals */ 154 struct callout sc_scan_ch; /* callout handle for scan */ 155 struct ath_stats sc_stats; /* interface statistics */ 156}; 157#define sc_tx_th u_tx_rt.th 158#define sc_rx_th u_rx_rt.th 159 160#define ATH_LOCK_INIT(_sc) \ 161 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 162 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 163#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 164#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 165#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 166#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 167 168#define ATH_TXBUF_LOCK_INIT(_sc) \ 169 mtx_init(&(_sc)->sc_txbuflock, \ 170 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 171#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 172#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 173#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 174#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 175 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 176 177#define ATH_TXQ_LOCK_INIT(_sc) \ 178 mtx_init(&(_sc)->sc_txqlock, \ 179 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 180#define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) 181#define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) 182#define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) 183#define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) 184 185int ath_attach(u_int16_t, struct ath_softc *); 186int ath_detach(struct ath_softc *); 187void ath_resume(struct ath_softc *); 188void ath_suspend(struct ath_softc *); 189void ath_shutdown(struct ath_softc *); 190void ath_intr(void *); 191 192/* 193 * HAL definitions to comply with local coding convention. 194 */ 195#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 196 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 197#define ath_hal_getratetable(_ah, _mode) \ 198 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 199#define ath_hal_getregdomain(_ah) \ 200 ((*(_ah)->ah_getRegDomain)((_ah))) 201#define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 202#define ath_hal_getmac(_ah, _mac) \ 203 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 204#define ath_hal_detach(_ah) \ 205 ((*(_ah)->ah_detach)((_ah))) 206#define ath_hal_intrset(_ah, _mask) \ 207 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 208#define ath_hal_intrget(_ah) \ 209 ((*(_ah)->ah_getInterrupts)((_ah))) 210#define ath_hal_intrpend(_ah) \ 211 ((*(_ah)->ah_isInterruptPending)((_ah))) 212#define ath_hal_getisr(_ah, _pmask) \ 213 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 214#define ath_hal_updatetxtriglevel(_ah, _inc) \ 215 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 216#define ath_hal_setpower(_ah, _mode, _sleepduration) \ 217 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 218#define ath_hal_keyreset(_ah, _ix) \ 219 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 220#define ath_hal_keyset(_ah, _ix, _pk) \ 221 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 222#define ath_hal_keyisvalid(_ah, _ix) \ 223 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 224#define ath_hal_keysetmac(_ah, _ix, _mac) \ 225 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 226#define ath_hal_getrxfilter(_ah) \ 227 ((*(_ah)->ah_getRxFilter)((_ah))) 228#define ath_hal_setrxfilter(_ah, _filter) \ 229 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 230#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 231 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 232#define ath_hal_waitforbeacon(_ah, _bf) \ 233 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 234#define ath_hal_putrxbuf(_ah, _bufaddr) \ 235 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 236#define ath_hal_gettsf32(_ah) \ 237 ((*(_ah)->ah_getTsf32)((_ah))) 238#define ath_hal_gettsf64(_ah) \ 239 ((*(_ah)->ah_getTsf64)((_ah))) 240#define ath_hal_resettsf(_ah) \ 241 ((*(_ah)->ah_resetTsf)((_ah))) 242#define ath_hal_rxena(_ah) \ 243 ((*(_ah)->ah_enableReceive)((_ah))) 244#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 245 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 246#define ath_hal_gettxbuf(_ah, _q) \ 247 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 248#define ath_hal_getrxbuf(_ah) \ 249 ((*(_ah)->ah_getRxDP)((_ah))) 250#define ath_hal_txstart(_ah, _q) \ 251 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 252#define ath_hal_setchannel(_ah, _chan) \ 253 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 254#define ath_hal_calibrate(_ah, _chan) \ 255 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 256#define ath_hal_setledstate(_ah, _state) \ 257 ((*(_ah)->ah_setLedState)((_ah), (_state))) 258#define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \ 259 ((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod))) 260#define ath_hal_beaconreset(_ah) \ 261 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 262#define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 263 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 264 (_dc), (_cc))) 265#define ath_hal_setassocid(_ah, _bss, _associd) \ 266 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 267#define ath_hal_setopmode(_ah, _opmode) \ 268 ((*(_ah)->ah_setPCUConfig)((_ah), (_opmode))) 269#define ath_hal_stoptxdma(_ah, _qnum) \ 270 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 271#define ath_hal_stoppcurecv(_ah) \ 272 ((*(_ah)->ah_stopPcuReceive)((_ah))) 273#define ath_hal_startpcurecv(_ah) \ 274 ((*(_ah)->ah_startPcuReceive)((_ah))) 275#define ath_hal_stopdmarecv(_ah) \ 276 ((*(_ah)->ah_stopDmaReceive)((_ah))) 277#define ath_hal_dumpstate(_ah) \ 278 ((*(_ah)->ah_dumpState)((_ah))) 279#define ath_hal_getdiagstate(_ah, _id, _data, _size) \ 280 ((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size))) 281#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 282 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 283#define ath_hal_resettxqueue(_ah, _q) \ 284 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 285#define ath_hal_releasetxqueue(_ah, _q) \ 286 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 287#define ath_hal_hasveol(_ah) \ 288 ((*(_ah)->ah_hasVEOL)((_ah))) 289#define ath_hal_getrfgain(_ah) \ 290 ((*(_ah)->ah_getRfGain)((_ah))) 291#define ath_hal_rxmonitor(_ah) \ 292 ((*(_ah)->ah_rxMonitor)((_ah))) 293 294#define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 295 _rate, _antmode) \ 296 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 297 (_flen), (_hlen), (_rate), (_antmode))) 298#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 299 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 300#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \ 301 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext))) 302#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 303 _txr0, _txtr0, _keyix, _ant, _flags, \ 304 _rtsrate, _rtsdura) \ 305 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 306 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 307 (_flags), (_rtsrate), (_rtsdura))) 308#define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 309 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 310 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 311 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 312#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 313 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 314#define ath_hal_txprocdesc(_ah, _ds) \ 315 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 316 317#endif /* _DEV_ATH_ATHVAR_H */ 318